A PCIe Switch exchange matrix device based on shared cache

Abstract

The present invention relates to the field of chip technology, and provides a PCIe Switch exchange matrix device based on shared cache. The device includes M Matrix modules; in each Matrix module, there is a multi-port shared cache area, and each Matrix module has M internal output terminals, M internal input terminals, N external input terminals and N external output terminals; the internal output terminal of each Matrix module is connected to the internal input terminal of each Matrix module to merge the M Matrix modules into one large-scale Matrix module; the external input terminal of each Matrix module is used to receive external input messages; the external output terminal of each Matrix module is used to fan out the messages in the shared cache. The present invention uses a shared cache area to improve cache utilization, and the interconnection of multiple matrices reduces the difficulty of realizing a super-large matrix, while also improving the freedom of chip layout, and supporting the needs of multi-port burst large-bandwidth switching.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a PCIe Switch exchange matrix device based on shared cache. Background Art

[0002] High-end high-speed serial computer expansion bus standard Peripheral Component Interconnect express (PCIe) Switch chips often need to support multiple virtual channels (VC), multi-port phase arbitration, multicast and peer to peer (p2p), and have a large number of ports. This requires the design of a high-performance switch matrix with high bandwidth, low latency, no blocking, and meeting the requirements of the PCIe protocol, and meeting the performance, area and timing requirements.

[0003] The cache size increases linearly with the number of ports, but not all ports are enabled, and the strategy of allocating cache to each port individually will greatly waste memory.

[0004] Multicast is an important function of PCIe and is increasingly used. The later the fan-out, the higher the memory utilization efficiency. Adding a write and delete management strategy for multicast messages to the switch matrix is ​​of great significance to PCIe switches.

[0005] PCIe stipulates that each port supports up to 8 VCs and supports message routing from all ports to this port. In actual applications, existing PCIe switch chips only support up to 2 VCs.

[0006] The switching matrix requires low forwarding delay, but the rates between multiple ports are not matched. This requires the switching matrix to calculate the stored message depth when the slow port is sent to the fast port, and start the output after the forwarding conditions are met to ensure that the input is not reverse pressured and the fast port output is continuous. This is called flow control. Because the output of the switching matrix will be given to the controller, and the controller will output to the physical layer (PHY for short), when the PHY sends data, a single message must be sent continuously, so the switching matrix output must be continuous, otherwise the subsequent processing still needs to be cached, which increases the design complexity and area.

[0007] In view of this, overcoming the defects of the prior art is an urgent problem to be solved in the field of this technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 It is a schematic diagram of the architecture of a PCIe Switch exchange matrix device based on shared cache provided by an embodiment of the present invention;

[0010] Figure 2 It is a schematic diagram of the architecture of a matrix module in a PCIe Switch exchange matrix device based on shared cache provided by an embodiment of the present invention;

[0011] Figure 3 It is a schematic diagram of external input terminal scheduling in a PCIe Switch switching matrix device based on a shared cache provided by an embodiment of the present invention;

[0012] Figure 4 It is a schematic diagram of writing a message into a shared cache in a PCIe Switch switching matrix device based on a shared cache provided by an embodiment of the present invention;

[0013] Figure 5 It is a schematic diagram of unicast message fan-out in a PCIe Switch switching matrix device based on shared cache provided by an embodiment of the present invention;

[0014] Figure 6 The present invention is a schematic diagram of a multicast message fan-out in a PCIe Switch switching matrix device based on a shared cache provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0016] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "multiple" means two or more.

[0017] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0018] The embodiment of the present invention provides a PCIe Switch switching matrix device based on shared cache, such as Figure 1 As shown, it includes M Matrix modules; in each Matrix module, there is a multi-port shared cache area (also called shared cache), and each Matrix module is provided with M internal output ports, M internal input ports, N external input ports and N external output ports.

[0019] The internal output of each Matrix module is connected to the internal input of each Matrix module to merge the M Matrix modules into one large-scale Matrix module, that is, to merge multiple matrices into one large matrix. In actual use, the M buffers can be set inside one Matrix module as a shared buffer.

[0020] The external input end of each Matrix module serves as the input end of the PCIe Switch switching matrix device, and is used to receive external input messages, so that the Matrix module stores the messages in the shared cache.

[0021] The external output end of each Matrix module serves as the output end of the PCIe Switch switching matrix device, and is used to fan out the messages in the shared cache.

[0022] in, Figure 1 M=4, N=4, that is, it includes 4 Matrix modules, each of which is provided with 4 external input terminals ( Figure 1 port input) and 4 external output ports ( Figure 1 In addition, each Matrix module has 4 internal input ports ( Figure 1 The group input) and 4 internal outputs ( Figure 1 ), with Figure 1 Taking the Matrix module M1 in the example, the internal output ends of each Matrix module are connected to the internal input ends of each Matrix module, which is manifested as: the four internal output ends of M1 are respectively connected to an internal input end of M1, an internal input end of M2, an internal input end of M3 and an internal input end of M4, thereby forming a channel for data transmission between M1 and each Matrix module, and realizing cache sharing between each Matrix module.

[0023] This embodiment connects M Matrix modules, thereby using a small-sized chip to implement a PCIe Switch exchange matrix device (i.e., PCIe Switch chip) based on shared cache for multiple VCs, that is, using a shared cache area to improve cache utilization, and multiple Matrix interconnection reduces the difficulty of implementing a super-large matrix. Among them, since each Matrix module is interconnected, each Matrix module can be freely and flexibly arranged on the board, thereby improving the freedom of chip layout, and multiple Matrix modules can also read and write at the same time, which is more efficient than a single Matrix module, and supports the needs of multi-port burst large bandwidth switching.

[0024] In specific application scenarios, such as Figure 2 As shown, the Matrix module includes a routing module, M write modules, N arbitration modules and 1 read module; wherein the source of each write module corresponds to a Matrix module (i.e., one Matrix module corresponds to one write module, and the write module is used to process all messages that need to be fanned out from each external output end of the Matrix module), and each arbitration module corresponds to one external output end.

[0025] The N input ends of the routing module serve as the N external input ends of the Matrix module, and the output ends of the routing module are respectively connected to the input ends of the writing modules; the output ends of the writing modules are connected to the input ends of the arbitration modules and the input ends of the shared cache of the corresponding Matrix modules. It can be understood that: the output end of the writing module has two exits, one exit is connected to the input end of the arbitration module, and the other exit is connected to the input end of the shared cache; the output end of each arbitration module is connected to the input end of the reading module.

[0026] The routing module is used to receive external input messages and transmit the messages to the corresponding writing modules according to the routing information in the messages; wherein the routing information is used to represent the external output end to which the message needs to be fanned out, the first message is transmitted to the first writing module, the first message is the message to be fanned out from the first external output end, and the first writing module is the writing module corresponding to the Matrix module where the first external output end is located.

[0027] The write module is used to write the message into the shared cache, generate cache information of the message, and send the cache information to the arbitration module; wherein, the cache information of the first message is sent to the first arbitration module, and the first arbitration module is the arbitration module corresponding to the first external output terminal; wherein, the transmission of the message to the corresponding write module is actually to send the data of the message in the corresponding beat to the write module, and the write module writes the beat data into the shared cache. Since the present embodiment writes data according to beats, multiple beats of data of a message may be written into different cache areas, or the cache addresses written in the cache area are not continuous, so the cache information is used to ensure that the message can be read continuously.

[0028] The arbitration module is used for performing port arbitration and VC arbitration, and determines the output order of multiple source port messages to the same output port, that is, determines the messages to be output at the external output port at the corresponding time.

[0029] The readout module is used to read the cache information corresponding to the message to be output from the arbitration module, read the message to be output from the shared cache according to the cache information, and fan out the message to be output.

[0030] In actual use, there is also a scheduling module, the output end of the writing module is connected to the scheduling module, and each output end of the scheduling module is connected to the internal input end of each Matrix module as the internal output end of the Matrix module.

[0031] The scheduling module is used to perform cache management on the cache area, including: reclaiming the cache address corresponding to the fanned-out message, and the writing module is used to write the message into the shared cache, specifically: the writing module transmits the message to the scheduling module, and the scheduling module writes the message into the shared cache.

[0032] The readout module is also provided with a data input terminal, and the data input terminal is connected to the internal output terminal of each Matrix module as the internal input terminal of the Matrix module.

[0033] The VC arbitration and port arbitration are often completed based on a well-known protocol, and this embodiment does not limit the specific implementation of the VC arbitration and port arbitration.

[0034] The determining of the messages to be outputted at the external output terminal is to determine which message should be scheduled first when one external output terminal corresponds to multiple messages waiting to be outputted.

[0035] Among them, the rate of the routing module is greater than or equal to the sum of the rates of the external input terminals of the Matrix module where it is located; the rate of the readout module is greater than or equal to the sum of the rates of the external output terminals of the Matrix module where it is located, in order to ensure non-blocking routing. This ensures that the various inputs and outputs of the Matrix module can be carried out concurrently.

[0036] In actual use, since the rates of the external input terminals are often different, port scheduling conflicts may occur. In order to solve this problem, this embodiment provides a preferred implementation method, that is, the external input message is received and scheduled according to the rate of each external input terminal, specifically including:

[0037] A plurality of scheduling cycles are divided, and the scheduling times of each external input terminal in the scheduling cycle are determined according to the ratio of the rates of each external input terminal, so as to schedule the external input terminal according to the scheduling times.

[0038] like Figure 3 As shown, assuming that the rates of the four external input ports of M1 are 64Gbps, 64Gbps, 128Gbps, and 0Gbps (equivalent to disabled), the forwarding bandwidth needs to be their sum of 256Gbps. When the data bit width remains unchanged, the main frequency of the switching matrix (i.e., M1) needs to be increased to 4 times that of the 64Gbps port. The clock domain can be crossed before the N port input or in the routing module. This embodiment takes the example before the routing module input, so the scheduling cycle can be set to 4 beats, where a 128Gbps port is scheduled once every 2 beats and a 64Gbps port is scheduled once every 4 beats, so that the scheduling of the three ports will never conflict.

[0039] In a preferred implementation, writing the message into the shared cache specifically includes:

[0040] Pair each cache area with each enabled external input terminal in descending order of the remaining storage space of each cache area; wherein, a plurality of judgment cycles may be divided by a technician in this field, and a pairing is performed once in each judgment cycle, and an enabled external input terminal refers to an external input terminal with data input in the current judgment cycle. In addition, each external input terminal has a preset priority order, which is obtained by a technician in this field based on demand analysis, and a high-priority enabled external input terminal is preferentially paired with a cache area with a large remaining storage space.

[0041] According to the pairing result, the message content from the corresponding external input terminal is written into the corresponding buffer area. The message content refers to one or more beats of data in the message received in the current judgment cycle.

[0042] like Figure 4As shown, assume that a Matrix module has 8 external input terminals, which are W[0], W[1], W[2], W[3], W[4], W[5], W[6], and W[7] in the order of preset priority. Correspondingly, M=8, that is, there are 8 Matrix modules to form a shared cache with 8 cache areas. These 8 cache areas are ram[0], ram[1], ram[2], ram[3], ram[4], ram[5], ram[6], and ram[7]. The size of the remaining storage space in each cache area is shown as follows: Figure 4 As shown, if the remaining storage space size of ram[0] is 9, and there is data input to W[2], W[4] and W[6] during the corresponding judgment cycle, then these three external input ports are enabled. First, arrange the M write enables from valid (enabled) to invalid (disabled). If the conditions are the same, they are arranged by index size (i.e. priority). For example, if W[6], W[4] and W[2] have written data, they are sorted by index size, with the smaller index in the front, i.e. W[6] = 2, W[4] = 1, and W[2] = 0. The remaining ports are similar, and a write enable sorting list [3, 4, 0, 5, 1, 6, 2, 7] is obtained. Similarly, the remaining cache space is arranged from most to least, and the conditions are the same. Arrange by index size. ram[7] has 37 spaces remaining, and the largest row is 0. According to this rule, the cache sorting list [6, 5, 4, 7, 3, 2, 1, 0] is obtained. Pair the two tables to find the write enable sequence number that is the same as that in the cache sorting table. For example, ram[7] is ranked 0, and W[2]=0 in the write enable table, then W[2] will be written into ram[7].

[0043] In a specific application scenario, the cache information may be a queue storing cache addresses of data in a message. However, in actual use, since the length of each message may be inconsistent, using a queue as cache information may easily lead to inconsistent length of cache information, making it difficult to perform unified scheduling. To solve this problem, this embodiment provides a preferred implementation, that is, generating cache information of a message and sending the cache information to an arbitration module, specifically includes:

[0044] Generate first cache information and second cache information, and send the first cache information to the arbitration module; wherein, the first cache information of the message is generated using the first data address of the message, the fan-out times of the message, the external input end of the message, and the end mark of the message.

[0045] A corresponding address storage location is set for each data in the cache area, and the cache address of the next data in the message is written into the address storage location of the previous data to form a cache address linked list, and the cache address linked list is used as the second cache information.

[0046] Correspondingly, Figure 5 As shown, the reading of the to-be-output message from the shared cache according to the cache information specifically includes:

[0047] According to the first cache information, the first beat data address of the message to be output is obtained. That is, the message is scheduled by beat, and the first beat data address is the address of the first data in each beat of the message to be output.

[0048] According to the first-shot data address, the first data and the second cache information of the message to be output are read, that is, the cache address in the address storage position of the first data is first read, the second data is read according to the cache address, and then the third data is read according to the cache address in the address storage position of the second data, and so on.

[0049] According to each cache address in the second cache information, subsequent data of the message to be output is read in sequence.

[0050] In actual use, when the last data of the message is stored in the buffer area, there is no next data at this time, and a preset end mark is stored in the address storage location corresponding to the data, such as Figure 5 In X (which is 1 in actual use), and when the corresponding data is the last beat data of the message, a preset tail beat identifier (ie, the end identifier of the above message) is stored in the first cache information corresponding to the data.

[0051] Since the capabilities of the external input end and the external output end may be inconsistent, when the input rate of the external input end cannot keep up with the output rate of the external output end, the message output will be discontinuous. In order to solve this problem, this embodiment also provides a preferred implementation, that is, sending the first cache information to the arbitration module specifically includes:

[0052] The buffer length of the message is calculated according to the first formula, and when the buffer length of the message received from the external input end reaches the buffer length, the first buffer information is sent to the arbitration module.

[0053] Among them, the first formula is: taking the ratio between the input capacity of the external input end of the message source and the output capacity of the external output end required to fan out the message as the first reference value, subtracting the first reference value from 1 to obtain the second reference value, and multiplying the second reference value by the packet length of the message to obtain the cache length.

[0054] The buffer length of the message is expressed in the form of a mathematical formula: Among them, In is the input capacity of the external input end, Out is the output capacity of the external output end, and Len is the packet length of the message.

[0055] In order to support the multicast function, this embodiment also provides a preferred implementation method:

[0056] like Figure 5 and Figure 6 As shown, the cache information also includes a preset fan-out number (ie, the fan-out number of the above-mentioned message).

[0057] The first message is transmitted to all first writing modules pointed to by the routing information, and each first writing module writes the first message into the cache area respectively, and generates its own cache information; wherein the number of first external output terminals in each Matrix module is used as the preset fan-out number in the corresponding cache information.

[0058] When the fan-out times of the corresponding message to be output are less than the preset fan-out times, the message to be output is continuously stored until the fan-out times of the message to be output reach the preset fan-out times, and the cache space of the message to be output is reclaimed. Thus, each first external output terminal can fan out the message to be output. Among them, the external output terminal required to fan out of the message is obtained from the routing information, and the routing information can be M×N bits in the specific implementation, that is, the routing information is M×N bits, each bit represents an external output terminal, and when the value of the corresponding bit is the preset value (such as 1), it means that the message carrying the routing information needs to be fanned out from the external output terminal corresponding to the bit. Thus, single message input and multiple message output are realized, that is, the multicast function of the message is realized.

[0059] Among them, the recovery of cache space is implemented by the scheduling module.

[0060] This embodiment will be based on the method described above, combined with specific application scenarios, and will use technical descriptions in related scenarios to illustrate the implementation process of the present invention in the characteristic scenarios.

[0061] First, in order to solve the problem of large bandwidth writing, the present invention provides a PCIe Switch structure (i.e., a PCIe Switch switching matrix device based on shared cache) with M groups (i.e., Matrix modules), each group has N ports (i.e., N external input ports and N internal input ports), the N ports are merged into one write module, and then connected to all groups, and the write module is frequency-increased so that the write module bandwidth is the sum of the write bandwidths of the N ports. M cache areas are set inside each group corresponding to M write modules, allowing M×N ports to burst write to this group. This embodiment reduces the write module frequency by increasing the number of shared caches, thereby making it easier to implement the circuit. And because a single switching matrix is ​​split into several small group matrices (i.e., Matrix modules), the small matrix is ​​set with multiple caches to allow groups to read and write to each other simultaneously.

[0062] The write module schedules the N ports in a fixed polling manner according to the capacity of the N ports. The period of fixed polling ports is inversely proportional to the port capacity. The greater the capacity, the shorter the polling period. Fixed polling scheduling ensures that the input of the N ports is continuous.

[0063] And the N ports in the same group can be written to any cache, and the strategy of giving priority to writing to the cache with the largest remaining space is adopted for write balancing, so that the group write data is first written to the cache with the largest remaining space. The specific implementation is made by using the M remaining address first-in first-out queue (First Input First Output, referred to as: FIFO) and the maximum sorting pairing method of the write module. As a result, the message of a single port will be scattered and written to any cache. In order to realize the continuous output of the message, the next hop address is recorded in the linked list cache corresponding to the current address, and an additional flag is set to indicate the tail address (that is, the preset tail beat mark and the preset end mark). Only the first address is needed to continuously read the data until the tail, so that the linked list address can be used to make the data scattered and written to different caches read out in order again.

[0064] The write module writes the first beat data address and source port of the message, the fan-out number (preset fan-out number), the end bit (preset tail beat identifier) ​​and other information into a select queue (abbreviated as: sq, i.e. the first cache information) and writes it to the arbitration module. Each port first performs VC arbitration on sq, then port arbitration, and finally passes sq to the read module. The arbitration method using single beat sq greatly reduces the complexity of arbitration based on unequal length packets.

[0065] In addition, the routing information carried in the message is used to query the capacity ratio of the sending and receiving ends. When the amount of data written to the source port (i.e., the external input port) reaches the cache length, writing sq to the arbitration module is allowed. This flow control method ensures the data continuity of the output port. This embodiment uses the capability ratio of the sending end and the receiving end and the packet length to calculate the amount of data that needs to be cached to obtain the condition for writing sq, thereby ensuring the continuity of the output port data.

[0066] The readout module polls the sq of each port, takes out the first address from sq, takes out the next hop address from the linked list cache, uses the fanout cache to record the fanout times of the multicast message, and compares it with the fanout field in sq to determine whether the fanout ends. When the data address is invalid, it is written back to FIFO to complete the address recovery. Among them, the read bandwidth of the readout module is the sum of the output bandwidths of N ports. According to the capacity of the output port, a fixed polling arbitration read cache is used to ensure that the output is continuous.

[0067] For the sake of convenience, this embodiment uses an abstract form to describe the PCIe Switch exchange matrix device based on shared cache, that is, the PCIe Switch exchange matrix device based on shared cache and the Matrix module are abstracted as a matrix. Figure 1 As shown in the figure, all ports are divided into M groups, each group has N ports (i.e., N external input ports and N external output ports). After the N port data input, it is merged into 1 data path and routed to all groups at the same time. Each group has M caches corresponding to each group input, which can handle the burst write of all ports to a certain port. Among them, the full cross matrix of N ports must increase the write frequency to N times the input rate to realize the output queuing mode, so that N data can be written to the output cache in one cycle and wait for the queue output of a single port. This is a necessary condition for achieving non-blocking. Each group reads data from the shared cache and outputs it to N external output ports.

[0068] The core idea of ​​the present invention is to split a large matrix into small matrices, and implement a shared cache similar to multi-port simultaneous writing and single-port reading inside the small matrix. Multi-port simultaneous writing improves the write bandwidth, thereby realizing non-blocking forwarding.

[0069] The schematic diagram of data storage and forwarding of a single packet in the switching matrix (i.e., a PCIe Switch switching matrix device based on a shared cache) is shown in FIG. Figure 2 As shown in the figure, after the data of N ports are input, the first routing is performed, mainly to complete the packet routing and the first multicast fan-out. The routing information (M×N bits) in the message is judged in the Route module (i.e., the routing module). When a bit is 1, it indicates which port the data is going to. When multiple bits are 1 at the same time, it means that this is a multicast message. After judging whether all destination packets are writable (i.e., judging whether the arbitration module sq fifo is not full and whether the shared cache is not full), the data is written to all packets at the same time. This is the first fan-out of multicast data and it is indivisible.

[0070] The data is routed to the writer modules (i.e., writing modules) of all packets through the route module. The writer module obtains the free cache address of the recycling address FIFO through sch (i.e., scheduling module), writes the message to the data cache, writes the address of the next message to the linked list address (i.e., the second cache information), and writes the sq information (i.e., the first cache information) to the arbitration module of all destination ports after flow control processing. The arbitration module outputs sq representing a single message to the Reader module (i.e., readout module) after VC arbitration and port arbitration. The readout module obtains the data head address from sq, and at the same time obtains the next hop address in the linked list cache from the data address, until the linked list cache address or sq itself indicates that the data message has been read to the end, and then switches to a new sq. After the number of fan-outs reaches the number of times specified by sq (i.e., the preset number of fan-outs), the data cache address is written back to the FIFO and waits for the next scheduling.

[0071] The Route module performs fixed-cycle polling arbitration based on the capabilities of the N ports, such as Figure 3 As shown. If the rates of the N ports are 64Gbps, 64Gbps, 128Gbps, and 0Gbps (equivalent to disabled), the forwarding bandwidth needs to be their sum of 256Gbps. When the data bit width remains unchanged, the main frequency of the switching matrix needs to be increased to 4 times that of the 64Gbps port. The clock domain crossing can be before the N port input or in the Route module. The present invention will default to before the Route module input. Then the fixed arbitration is to schedule the 128Gbps port every 2 beats and the 64Gbps port every 4 beats. Figure 3 It can be seen that the scheduling of the three ports will never conflict. In the specific implementation, when a port has no data, the fixed period of the port can be allocated to other ports with data, thereby improving the forwarding efficiency. The fixed arbitration strategy ensures that the input data can be input continuously. When the shared cache or sq fifo is saturated, the writer module can reverse the pressure in the first beat of the packet. Once the first beat of the message is written to the shared cache, the entire link is not allowed to have back pressure.

[0072] The write module obtains the free shared cache address from the sch module, writes the data to the RAM, and is responsible for writing the linked list cache. The write module is also responsible for calculating the flow control and determining the destination port of the packet to decide when to write the sq information to the arbitration module, that is, to calculate the cache length according to the first formula. When the data length of the received message reaches the cache length, the sq information is written to the arbitration module. Writing sq information to the arbitration module of multiple ports can be understood as the second fan-out of the multicast message. This is a splittable fan-out, that is, the multicast data message will only be stored in a shared cache for N output ports to read and use, that is, the fan-out function of writing only one copy of the data and being able to read multiple times is realized by writing multiple sq at the same time. The fan-out cache is used to record the number of fan-outs to decide when to recycle the address. When the linked list reading of the last sq is completed, the cache address of the multicast message is allowed to be recycled. When a multicast data message needs to be fanned out from the external output terminals of multiple Matrix modules, multiple copies of the multicast data message are stored in the shared cache. For example, when it needs to be fanned out from the external output terminals of two Matrix modules, two copies are stored. In actual use, sq and the linked list address include but are not limited to recording only one address, thereby achieving a balance between area and timing.

[0073] In each cycle, there are 0 to M valid writes corresponding to M caches. The writes need to be balanced to ensure that the remaining space of each cache is not much different, and that the burst of M valid writes can be handled when the cache is not full. The specific implementation is as follows Figure 3 As shown, first arrange the M write enables from valid to invalid. If the conditions are the same, they are suitable to be arranged by index size. For example, W[6], W[4], and W[2] have written data. They are sorted by index size, with the smaller index in front, that is, W[6] = 2, W[4] = 1, and W[2] = 0. The remaining ports are similar, and a write enable sorting list [3, 4, 0, 5, 1, 6, 2, 7] is obtained. Similarly, the remaining cache space is arranged from most to least. If the conditions are the same, they are arranged by index size. ram[7] has 37 spaces remaining, and the largest space is 0. According to this rule, the cache sorting list [6, 5, 4, 7, 3, 2, 1, 0] is obtained. Pair the two tables and find the write enable sequence number that is the same as the cache sorting table. For example, ram[7] is ranked 0, and W[2] = 0 in the write enable table, so W[2] will be written to ram[7].

[0074] Figure 5 This shows how four unicast messages written to the same port are stored in the shared cache and read out. Assuming that each group has four ports and the rate is X1, it is necessary to first cross the clock domain to the switching clock domain of X4, and after the fixed cycle arbitration of the routing module, write the data a1 of port 1 first, according to Figure 4According to the pairing strategy, the remaining number of all RAMs is the same at this time, and ram[0] is written first. The write module takes out the pre-written address 000 from the address FIFO corresponding to ram[0] and writes a1 to the address 000. Since this is the first data, there is no need to write the linked list cache. When the next beat b1 data is written, ram[1] has the largest remaining space and the smallest index, so b1 will be written to the address 100. When writing a2 to address 300, it is also necessary to write the address 300 to the linked list cache corresponding to the address of the previous beat a1 data, and attach a flag bit to indicate whether a2 is the last beat. Since the destination port rate is also x1, according to the flow control calculation formula (i.e. the first formula), 1 data can be cached to write sq to the arbitration module. Therefore, when writing a1, b1, c1, and d1 data, the first address, fan-out times, source port, and sq data of whether it is the last beat are written to the sq fifo of the destination port. The source port only represents a type of useful information and can be used for maintenance and testing. VC arbitration and port arbitration are specified by the PCIe protocol, and the specific implementation is not considered in the present invention. When the first SQ0 is valid, the Reader module obtains the first address 000 and the fan-out number 0, and the tail indication tail is 0, indicating that the first address data is not the tail beat. It is necessary to read the linked list cache 000 address at the same time when reading the data cache 000 address to get the next hop address 300 and the tail flag 0. The tail flag 0 indicates that the data of 300 is not the tail beat either. According to this rule, the data of 000, 300, 301, and 302 are read in sequence. When reading the address 301, the linked list data read at the address 301 is 302, and the tail flag 1 indicates that 302 is the last data. There is no need to read the linked list address when reading the data 302, and sq0 is removed after reading 302, indicating that the message of a1-a4 has been read out completely. And the fan-out number of SQ is 0, and each address read will be immediately recycled to the FIFO.

[0075] Figure 6 This shows how a multicast message is fanned out. Assume that a 4-beat multicast packet is sent from an X1 port to port 0 and port 1. The data writing process is the same as Figure 5The difference is that the multicast packet needs to write the same sq to the sq fifo of port 0 and port 1 at the same time when writing the tail beat. The fan-out count of sq is indicated as 1, indicating that the data of this sq needs to be fanned out twice. In short, the address of the linked list indicated by this sq needs to be read twice before it is allowed to be recycled. Assuming that the sq of port 0 is arbitrated in the first beat, first take out the data from the first address 000 of sq and send it to port 0. Because the fan-out count is not 0, the fan-out count is read from the 000 address of the fanout cache. The value is 0. Because 0 is less than sq.fanout, the read value 0+1 needs to be written back to the 000 address of the fanout cache. Because the fan-out is not over, the 000 address of the shared cache is not allowed to be recycled. The reader module is a fixed-cycle arbitration module. In the next cycle, port 1 will be arbitrated. The first address of sq is still 000. Data will continue to be read from the shared cache address 000 and sent to port 1. Because sq.fanout = 1 is not 0, the address 000 of the fanout cache needs to be read. However, since port 0 has been filled with plus 1 when fanning out, the read value at this time is 1, the same as sq.fanout, indicating that the number of fanouts has been reached. The address 000 of the shared cache is allowed to be recycled, and 0 needs to be written to the address 000 of the fanout cache to restore it and wait for the next fanout. Eventually, the following will occur: Figure 5 The readout process is shown.

[0076] In actual use, in order to obtain better timing, the address width of sq can be expanded to place two addresses corresponding to two end flags. Similarly, two address data are also stored in the linked list address. In this way, the reader module can read the linked list address once to obtain two data link addresses, and the linked list can be read at intervals of two cycles to improve the timing.

Claims

1. A PCIe Switch exchange matrix device based on shared cache, characterized in that: Includes M Matrix modules; In each Matrix module, there is a multi-port shared buffer area, and each Matrix module is provided with M internal output ports, M internal input ports, N external input ports and N external output ports; The internal output end of each Matrix module is connected to the internal input end of each Matrix module, so as to merge the M Matrix modules into one large-scale Matrix module; The external input end of each Matrix module serves as the input end of the PCIe Switch switching matrix device, and is used to receive external input messages, so that the Matrix module can store the messages in the shared cache; The external output end of each Matrix module serves as the output end of the PCIe Switch switching matrix device, and is used to fan out the messages in the shared cache.

2. The PCIe Switch exchange matrix device based on shared cache according to claim 1, characterized in that: The Matrix module includes a routing module, M write modules, N arbitration modules and 1 read module; wherein the source of each write module corresponds to a Matrix module, and each arbitration module corresponds to an external output terminal; The N input terminals of the routing module serve as the N external input terminals of the Matrix module, and the output terminals of the routing module are respectively connected to the input terminals of the writing modules; the output terminals of the writing modules are connected to the input terminals of the arbitration modules and the input terminals of the shared cache of the corresponding Matrix modules; the output terminals of the arbitration modules are connected to the input terminals of the reading modules; The routing module is used to receive external input messages and transmit the messages to the corresponding writing modules according to the routing information in the messages; wherein the routing information is used to represent the external output terminal to which the message needs to be fanned out, the first message is transmitted to the first writing module, the first message is the message to be fanned out from the first external output terminal, and the first writing module is the writing module corresponding to the Matrix module where the first external output terminal is located; The writing module is used to write the message into the shared cache, generate cache information of the message, and send the cache information to the arbitration module; wherein the cache information of the first message is sent to the first arbitration module, and the first arbitration module is the arbitration module corresponding to the first external output terminal; The arbitration module is used to perform port arbitration and VC arbitration to determine the output order of multiple source port messages to the same output port; The readout module is used to read the cache information corresponding to the message to be output from the arbitration module, read the message to be output from the shared cache according to the cache information, and fan out the message to be output.

3. The PCIe Switch exchange matrix device based on shared cache according to claim 2, characterized in that: The receiving of the external input message is implemented by scheduling according to the rate of each external input end, including: According to the ratio of the rates of the external input terminals, the scheduling times and scheduling times of the external input terminals within the scheduling period are determined, and the external input terminals are scheduled according to the fixed scheduling method.

4. The PCIe Switch exchange matrix device based on shared cache according to claim 2, characterized in that: Writing the message into the shared cache includes: Pair each cache area with each write module output according to the order of remaining storage space of each cache area from large to small and whether each write module is write enabled; According to the pairing result, the message content of the external input terminal to be written is written into the buffer area with the most remaining storage space.

5. The PCIe Switch exchange matrix device based on shared cache according to claim 2, characterized in that: The generating cache information of the message and sending the cache information to the arbitration module comprises: Generate first cache information and second cache information, and send the first cache information to the arbitration module; wherein the first cache information of the message is generated using the first data address of the message, the fan-out number of the message, the external input terminal number of the message, and the end mark of the message; A corresponding address storage location is set for each data in the cache area, and the cache address of the next data in the message is written into the address storage location of the previous data to form a cache address linked list, and the cache address linked list is used as the second cache information.

6. The PCIe Switch exchange matrix device based on shared cache according to claim 5, characterized in that: The sending the first cache information to the arbitration module includes: Calculating the cache length of the message according to the first formula, and sending the first cache information to the arbitration module when the cache length of the message received from the external input end reaches the cache length; Among them, the first formula is: taking the ratio between the input capacity of the external input end of the message source and the output capacity of the external output end required to fan out the message as the first reference value, subtracting the first reference value from 1 to obtain the second reference value, and multiplying the second reference value by the packet length of the message to obtain the cache length.

7. The PCIe Switch exchange matrix device based on shared cache according to claim 5, characterized in that: The step of reading the to-be-output message from the shared cache according to the cache information includes: According to the first cache information, the first data address of the message to be output is obtained; Reading the first data and the second cache information of the message to be output according to the first-shot data address; According to each cache address in the second cache information, subsequent data of the message to be output is read in sequence.

8. The PCIe Switch exchange matrix device based on shared cache according to claim 2, characterized in that: The cache information also includes a preset fan-out number; The first message is transmitted to all the first writing modules pointed to by the routing information, and each of the first writing modules writes the first message into the cache area respectively, and generates respective cache information; wherein the number of the first external output terminals in each Matrix module is used as the preset fan-out number in the corresponding cache information; When the fan-out number of the corresponding message to be output is less than the preset fan-out number, the message to be output is continuously stored until the fan-out number of the message to be output reaches the preset fan-out number, and the cache space of the message to be output is reclaimed.

9. The PCIe Switch exchange matrix device based on shared cache according to claim 2, characterized in that: The rate of the routing module is greater than or equal to the sum of the rates of the external input terminals of the Matrix module in which it is located; The rate of the readout module is greater than or equal to the sum of the rates of the external output terminals of the Matrix module in which it is located.

10. The PCIe Switch exchange matrix device based on shared cache according to claim 2, characterized in that: The routing information is M×N bits, each bit represents an external output end, and when the value of the corresponding bit is a preset value, it means that the message carrying the routing information needs to be fanned out from the external output end corresponding to the bit.

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