Multi-layer electrode connection structure, on-chip capacitor, and multi-layer electrode connection method

Abstract

The present invention relates to the field of semiconductor devices, and provides a multi-layer electrode connection structure, an on-chip capacitor, and a multi-layer electrode connection method. The multi-layer electrode connection structure is applied inside an on-chip capacitor and includes: a substrate for providing an attachment surface for an electrode layer located at the bottom layer; an electrode layer provided with etching grooves for providing a first conductive region and a second conductive region; the profiles of the etching grooves adjacent to each other in the N-layer electrode layer do not intersect in the stacking direction, where N is a positive integer greater than 2; and a dielectric layer located between adjacent electrode layers for providing an insulating dielectric. This structure is used to reduce the step difference in the multi-layer electrodes to ensure the performance of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a multi-layer electrode connection structure, an on-chip capacitor, and a multi-layer electrode connection method. Background Art

[0002] Silicon-based capacitors usually improve the capacitance value by depositing dielectric materials and electrode materials on a silicon substrate to form a multi-layer structure. As the number of layers increases, it becomes increasingly difficult to connect the electrodes of each layer in a staggered manner, especially at the nanoscale.

[0003] In the current market products, after forming a multi-layer structure with alternating electrodes and dielectric layers, it is necessary to etch a fixed depth to separately lead out the positive and negative electrodes to separate the positive and negative electrode plates. The process difficulty and cost increase with the increase in the number of layers. When the number of layers is large, the position etched for leading out the electrodes will collapse, generating a step difference. The step difference will not only affect the deposition of subsequent dielectric layers and electrode layers, but also introduce additional electric field non-uniformity between the electrode layers, which may cause the local electric field intensity to be too high, thereby increasing the leakage current, reducing the insulation performance of the dielectric layer, and even causing breakdown, affecting the performance of the capacitor. Therefore, there is an urgent need for a multi-layer electrode connection structure, an on-chip capacitor, and a multi-layer electrode connection method to improve the above problems. Summary of the Invention

[0004] The purpose of the present invention is to provide a multi-layer electrode connection structure, an on-chip capacitor, and a multi-layer electrode connection method, which are used to reduce the step difference in the multi-layer electrodes to ensure the performance of the capacitor.

[0005] In a first aspect, the present invention provides a multi-layer electrode connection structure, which is applied inside an on-chip capacitor and includes: a substrate for providing an attachment surface for the electrode layer located at the bottom layer; an electrode layer provided with an etching groove for providing a first conductive region and a second conductive region; the contours of the etching grooves adjacent to each other in the N-layer electrode layer do not intersect in the stacking direction, where N is a positive integer greater than 2; a dielectric layer located between adjacent electrode layers for providing an insulating dielectric.

[0006] Optionally, the electrode layer is set to M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etching grooves in the N-layer electrode layer do not intersect in the stacking direction.

[0007] Optionally, when M is greater than N, the contours of the etching grooves in the electrode layers within N layers and the electrode layers outside N layers partially intersect.

[0008] Optionally, the electrode layer has opposite first and second edges, and the etching grooves in adjacent two electrode layers are respectively close to the first edge and the second edge, so that the first regions and the second regions in adjacent electrode layers alternately overlap.

[0009] Optionally, the substrate is provided with grooves; the width of the grooves is greater than the width of the etching grooves.

[0010] Optionally, a plurality of the grooves are distributed in a self-similar patterned array on the surface of the substrate; the shapes of the grooves include at least one of strip, rectangular, and circular.

[0011] In a second aspect, the present invention provides a chip capacitor, including: the multi-layer electrode connection structure according to any one of the first aspects, and: a first conductive sealing end for connecting a first region in each electrode layer; a second conductive sealing end for connecting a second region in each electrode layer; the first conductive sealing end and the second conductive sealing end are isolated from each other.

[0012] In a third aspect, the present invention provides a multi-layer electrode connection method for forming the multi-layer electrode connection structure according to any one of the first aspects, including: S1, providing a substrate and forming an electrode layer on its upper surface; S2, performing an etching process on the electrode layer located on the surface so that the electrode layer is divided into a first region and a second region by the etching grooves; S3, forming a dielectric layer on the surface of the electrode layer; forming an electrode layer on the upper surface of the dielectric layer; S4, repeating S2-S3 several times and then performing S2 once; the profiles of the adjacent etching grooves in the N-layer electrode layers do not intersect in the stacking direction, where N is a positive integer greater than 2.

[0013] Optionally, S4 further includes: cutting or grinding the edges of the stacked electrode layers so that the first region and the second region of the electrode layer are exposed.

[0014] Optionally, it further includes S5, forming a first conductive sealing end for connecting the first regions in each electrode layer and forming a second conductive sealing end for connecting the second regions in each electrode layer.

[0015] Optionally, the electrode layer and the dielectric layer are respectively formed by at least one of atomic layer deposition or chemical vapor deposition processes; the first conductive sealing end and the second conductive sealing end are formed by an electroplating process.

[0016] The beneficial effects of the present invention are as follows: By ensuring that the profiles of the adjacent etching grooves in the N-layer electrode layers do not intersect in the stacking direction, it is possible to avoid the accumulation of height differences of the etching grooves in the multi-layer electrode layers to form steps, which can increase the actual effective capacitance area, keep the electric field between the electrode layers uniform, avoid too high local electric field intensity, thereby reducing leakage current, improving the insulation performance of the dielectric layer, avoiding breakdown, and being beneficial to improving the performance of the capacitor. Description of the Drawings

[0017] Figure 1 It is a schematic diagram of a multi-layer electrode connection structure provided by the present invention;

[0018] Figure 2 Schematic diagram of a structure with grooves on a substrate provided by the present invention;

[0019] Figure 3 Schematic diagram of a rectangular array distribution of several rectangular grooves on a substrate provided by the present invention;

[0020] Figure 4 Schematic diagram of a linear arrangement of several strip grooves on a substrate provided by the present invention;

[0021] Figure 5 Schematic diagram of a structure of an on-chip capacitor provided by the present invention;

[0022] Figure 6 Schematic diagram of a process flow of a method for connecting multi-layer electrodes provided by the present invention;

[0023] Figure 7 Schematic diagram of a structure in which an odd-numbered first electrode layer is formed on a substrate provided by the present invention;

[0024] Figure 8 Schematic diagram of a structure in which an etching groove of an odd-numbered first electrode layer is formed in the odd-numbered first electrode layer provided by the present invention;

[0025] Figure 9 Schematic diagram of a structure in which a first dielectric layer is formed on the odd-numbered first electrode layer provided by the present invention;

[0026] Figure 10 Schematic diagram of a structure in which an odd-numbered second electrode layer is formed on the first dielectric layer provided by the present invention;

[0027] Figure 11 Schematic diagram of a structure in which an etching groove of an odd-numbered second electrode layer is formed in the odd-numbered second electrode layer provided by the present invention;

[0028] Figure 12 Schematic diagram of a structure in which a second dielectric layer is formed on the odd-numbered second electrode layer provided by the present invention.

[0029] Explanation of reference numerals in the figure:

[0030] 1. Substrate; 5. Conductive seal end;

[0031] 11. Groove; 21. Odd-numbered first electrode layer; 22. Even-numbered first electrode layer; 31. Odd-numbered second electrode layer; 32. Even-numbered second electrode layer; 41. First dielectric layer; 42. Second dielectric layer; 43. Third dielectric layer; 51. First conductive seal end; 52. Second conductive seal end;

[0032] 201. Etching groove of the first electrode layer at odd positions; 202. Etching groove of the first electrode layer at even positions; 211. Positive electrode region of the first electrode layer at odd positions; 212. Negative electrode region of the first electrode layer at odd positions; 221. Positive electrode region of the first electrode layer at even positions; 222. Negative electrode region of the first electrode layer at even positions;

[0033] 301. Etching groove of the second electrode layer at odd positions; 302. Etching groove of the second electrode layer at even positions; 311. Positive electrode region of the second electrode layer at odd positions; 312. Negative electrode region of the second electrode layer at odd positions; 321. Positive electrode region of the second electrode layer at even positions; 322. Negative electrode region of the second electrode layer at even positions. Detailed implementation manners

[0034] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art in the field to which the present invention pertains. The words such as "including" used herein mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects.

[0035] Regarding the problems existing in the prior art, such as Figure 1 As shown, the first embodiment of the present invention provides a multi-layer electrode connection structure, which is applied inside a chip capacitor and includes: a substrate 1 for providing an attachment surface for the electrode layer located at the bottom layer; an electrode layer provided with etching grooves for providing a conductive first region and a second region; the contours of the adjacent etching grooves in the N-layer electrode layer do not intersect in the stacking direction, where N is a positive integer greater than 2; a dielectric layer located between adjacent electrode layers for providing an insulating dielectric. In this embodiment, since the contours of the adjacent etching grooves in the N-layer electrode layer do not intersect in the stacking direction, the accumulation of height differences of the etching grooves provided in the multi-layer electrode layers is avoided, the actual effective capacitance area can be increased, the electric field between the electrode layers can be kept uniform, the local electric field strength can be prevented from being too high, thereby reducing the leakage current, improving the insulation performance of the dielectric layer, avoiding breakdown, and being beneficial to improving the performance of the capacitor.

[0036] In some other specific embodiments, the stacking direction of the N-layer electrode layer is along the vertical direction Z, and the extending directions of the substrate 1, the electrode layer and the dielectric layer are along the horizontal plane. The etching grooves are configured to gradually penetrate into the electrode layer along the vertical direction Z until they contact the substrate 1 or the dielectric layer.

[0037] In some other specific embodiments, the substrate 1 is made of silicon, silicon oxide, zirconium oxide, hafnium oxide, germanium, silicon nitride, aluminum oxide, or gallium oxide materials. The electrode layer is provided as a conductive material. The dielectric layer is provided as an insulating material. The dielectric layer is further configured to fill the etching grooves of the underlying electrode layer, such that the first region and the second region are separated by the insulating material.

[0038] In some embodiments, the electrode layer is provided as the M layer, where M is greater than or equal to N; when M equals N, the profiles of the etching grooves in the N layers of the electrode layer do not intersect in the stacking direction.

[0039] In some specific embodiments, M = N = 4, and an odd-numbered first electrode layer 21 is connected to the attachment surface provided by the substrate 1. A first dielectric layer 41 is connected to the odd-numbered first electrode layer 21. An odd-numbered second electrode layer 31 is connected to the first dielectric layer 41. A second dielectric layer 42 is connected to the odd-numbered second electrode layer 31. An even-numbered first electrode layer 22 is connected to the second dielectric layer 42. A third dielectric layer 43 is connected to the even-numbered first electrode layer 22. An even-numbered second electrode layer 32 is connected to the third dielectric layer 43. In this embodiment, by setting the etching grooves in the N layers of the electrode layer not to intersect in the Z direction, the accumulation of the height difference of the etching grooves is avoided, and the step difference can be fundamentally eliminated. The actual effective capacitance area of the capacitor is increased, the electric field between the electrode layers is kept uniform, the local electric field intensity is prevented from being too high, thereby reducing the leakage current, improving the insulation performance of the dielectric layer, avoiding breakdown, and being beneficial to improving the performance of the capacitor.

[0040] In some examples, the odd-numbered first electrode layer 21 is provided with an odd-numbered first electrode layer etching groove 201 near the opposite direction of X, and the even-numbered first electrode layer 22 is provided with an even-numbered first electrode layer etching groove 202 near the opposite direction of X. The odd-numbered first electrode layer etching groove 201 and the even-numbered first electrode layer etching groove 202 are adjacent etching grooves, and their profiles in the Z direction do not intersect.

[0041] In some other examples, the odd-numbered second electrode layer 31 is provided with an odd-numbered second electrode layer etching groove 301 near the X direction, and the even-numbered second electrode layer 32 is provided with an even-numbered second electrode layer etching groove 302 near the X direction. The odd-numbered second electrode layer etching groove 301 and the even-numbered second electrode layer etching groove 302 are adjacent etching grooves, and their profiles in the Z direction do not intersect.

[0042] It should be noted that the Micro-displacement Fine Trench Patterning (MDFTP) is adopted to define the positions of the etching grooves of adjacent electrode layers. It can achieve a positioning accuracy at the sub-micron or even nano-scale, which is beneficial to improving the integration degree of integrated circuits.

[0043] In some embodiments, when M is greater than N, the contour parts of the etching grooves in the electrode layers within the N layers intersect with those in the electrode layers outside the N layers.

[0044] In some specific embodiments, M = 20, N = 10. The 20 electrode layers and 20 dielectric layers are stacked on the substrate 1 along the Z direction. The contour of the etching groove in the electrode layer located at the first layer intersects with that in the electrode layer located at the 401st layer in the Z direction; the contour of the etching groove in the electrode layer located at the second layer intersects with that in the electrode layer located at the 402nd layer in the Z direction; the contour of the etching groove in the electrode layer located at the 10th layer intersects with that in the electrode layer located at the 20th layer in the Z direction. In this embodiment, by reusing the positions of the etching grooves after every N electrode layers, the local accumulation of the height difference of the etching grooves can be minimized as much as possible, enabling the multi-layer electrode connection structure to reach a higher number of layers to meet the design of large-capacity on-chip capacitors. On the other hand, in this embodiment, by increasing the number of electrode layers to M layers, the effective surface area of the electrodes can be further increased, thereby improving the capacitance density.

[0045] In some embodiments, the electrode layer has opposite first and second edges, and the etching grooves in two adjacent electrode layers are respectively close to the first edge and the second edge, so that the first region and the second region in the adjacent electrode layers overlap alternately.

[0046] In some specific embodiments, the first edge is in the negative X direction, and the second edge is in the X direction. In some examples, the negative electrode regions 212 of the odd-numbered first electrode layers, the positive electrode regions 311 of the odd-numbered second electrode layers, the negative electrode regions 222 of the even-numbered first electrode layers, and the positive electrode regions 321 of the even-numbered second electrode layers overlap alternately from bottom to top. In some other specific embodiments, the first edge is in the X direction, and the second edge is in the negative X direction. In this embodiment, by making the etching grooves in two adjacent electrode layers close to the first edge and the second edge respectively, the space can be better utilized, the effective electrode area can be further increased, and thus the capacitance density can be improved.

[0047] Such as Figure 2As shown, in some embodiments, the substrate 1 is provided with a groove 11; the width of the groove 11 is greater than the width of the etching groove. In some specific embodiments, the groove 11 is formed on the surface of the substrate 1 by an etching process. In some examples, the silicon substrate 1 is etched by a Reactive Ion Etching (RIE) process, and the aspect ratio of the groove 11 formed ranges from 1:100 to 100:1. The width range of the groove 11 is 0.5 - 100 microns. The direction of the width is along the horizontal direction X, and the direction of the depth is along the vertical direction Z.

[0048] In some examples, the aspect ratio of the groove 11 is set to 1:100. The width of the groove 11 is set to 100 microns. In some other examples, the aspect ratio of the groove 11 is set to 100:1. The width of the groove 11 is set to 0.5 microns. In still some other examples, the aspect ratio of the groove 11 is set to 1:1. The width of the groove 11 is set to 50.25 microns.

[0049] In this embodiment, by controlling the size of the groove 11, the electrical signal path can be optimized and signal distortion can be reduced. In some examples, the cross-section of the groove 11 perpendicular to the Y direction is rectangular. In some other examples, the cross-section of the groove 11 perpendicular to the Y direction is trapezoidal. In still some other examples, the cross-section of the groove 11 perpendicular to the Y direction is bow-shaped. The curved side of the bow can be set as a parabola, an ellipse or a hyperbola. The horizontally set X direction, the horizontally set Y direction and the vertically set Z direction are perpendicular to each other in pairs.

[0050] In some embodiments, a plurality of the grooves 11 are distributed on the surface of the substrate 1 in a self-similar patterned array; the shape of the groove 11 includes at least one of a strip shape, a rectangular shape, and a circular shape.

[0051] As Figure 3 shown, in some specific embodiments, a single groove 11 is configured as a rectangle, and a plurality of grooves 11 are arranged in a rectangular array, and the outer contour of the rectangular array is a similar rectangle to the single groove 11.

[0052] In some other specific embodiments, a single groove 11 is configured as a circle, and a plurality of grooves 11 are arranged in a circular array, and the outer contour of the circular array is a similar circle to the single groove 11.

[0053] As Figure 4 shown, in still some other specific embodiments, a single groove 11 is configured as a strip, and a plurality of grooves 11 are linearly arranged. In some examples, the extending direction of a single strip-shaped groove 11 is along the Y direction, and the linear arrangement direction is along the X direction. In some other examples, both the extending direction of a single strip-shaped groove 11 and the linear arrangement direction are along the Y direction.

[0054] In this embodiment, by providing grooves 11 distributed in a self-similar patterned array on the surface of the substrate 1, the electric field distribution between the electrode layers can be made uniform, which is convenient for large-scale design.

[0055] It should be noted that the etching grooves extend along the Y direction and the opposite direction of Y to the edge of the electrode layer. The groove 11 does not need to extend to the edge of the substrate 1.

[0056] As Figure 5 shown, the second embodiment provides a chip capacitor, including: the multi-layer electrode connection structure described in any one of the above embodiments, and: a first conductive sealing end 51 for connecting the first regions in each electrode layer; a second conductive sealing end 52 for connecting the second regions in each electrode layer; the first conductive sealing end 51 and the second conductive sealing end 52 are isolated from each other.

[0057] In some specific embodiments, the first conductive sealing end 51 is used to connect the positive electrode, and the second conductive sealing end 52 is used to connect the negative electrode. When there is a potential difference between the positive and negative electrodes, an electric field is formed between the first region and the second region. In some other specific embodiments, the first conductive sealing end 51 is used to connect the negative electrode, and the second conductive sealing end 52 is used to connect the positive electrode. It should be noted that in this embodiment, by providing the mutually isolated first conductive sealing end 51 and second conductive sealing end 52, adjacent electrode layers are connected in parallel, which is beneficial to improving the capacitance of the capacitor.

[0058] In some examples, the number of electrode layers is even, and charges are stored through alternating insulating layers and electrode layers. In some other examples, the number of electrode layers is odd, and the top electrode layer is not connected to the first conductive sealing end 51 and the second conductive sealing end 52, which is used for shielding. This design can reduce the electromagnetic interference between the capacitor and other components, especially in high-frequency applications. The shielding effect of the top electrode layer helps to maintain the stable performance of the capacitor and reduce the electromagnetic interference to the outside.

[0059] The third embodiment provides a multi-layer electrode connection method for forming the multi-layer electrode connection structure described in any one of the above embodiments, including: S1, providing a substrate 1 and forming an electrode layer on its upper surface; S2, performing an etching process on the electrode layer located on the surface so that the electrode layer is divided into a first region and a second region by the etching groove; S3, forming a dielectric layer on the surface of the electrode layer; forming an electrode layer on the upper surface of the dielectric layer; S4, after repeating S2 - S3 several times, then performing S2 once again; the contours of the adjacent etching grooves in the N-layer electrode layer do not intersect in the stacking direction, where N is a positive integer greater than 2.

[0060] As Figure 7As shown, in some specific embodiments, S1 further includes: providing a substrate 1 with grooves 11 on its upper surface, and the electrode layer uniformly covers the inner wall of the grooves 11 and the surface of the original substrate surrounding the grooves 11. The surface of the original substrate connects to the side wall of the grooves 11 and protrudes from the bottom wall of the grooves 11.

[0061] In some embodiments, the etching groove is provided on the surface of the original substrate surrounding the grooves 11. In other embodiments, the etching groove is provided inside the grooves 11, and the etching direction of the etching groove is along the vertical Z direction. In still other embodiments, the etching groove is provided inside the grooves 11, and the etching direction of the etching groove is along the horizontal X direction or the reverse X direction.

[0062] It should be noted that the electrode layer and the dielectric layer are respectively formed by at least one of the processes of Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). In this embodiment, by repeatedly executing steps S2 and S3, and depositing a new layer on the basis of the previous layer of electrode and dielectric layer each time, the layer-by-layer accumulation of the multi-layer electrode structure is realized. This process demonstrates a high degree of repeatability and control accuracy, and supports the large-scale industrial production of complex multi-layer structures.

[0063] In the first example, a silicon substrate 1 with a size of 1 cm * 1 cm is patterned and etched by a reactive ion etching process to form grooves 11 with a width of 50 microns and a depth of 40 microns. S1 includes: depositing 20 nm of titanium nitride (TiN) on the surface of the silicon wafer by an atomic layer deposition process as the first electrode layer 21 of odd digits.

[0064] As Figure 8 shown, when S2 is executed for the first time, it further includes: etching the first electrode layer 21 of odd digits at the first edge in the reverse X direction to form an etching groove 201 for the first electrode layer of odd digits, and dividing the first electrode layer 21 of odd digits into a positive electrode region 211 and a negative electrode region 212 of the first electrode layer of odd digits.

[0065] As Figure 9 shown, when S3 is executed for the first time, it further includes: S31, depositing 50 nm of zirconia or hafnium oxide on the surface of the first electrode layer 21 of odd digits by an atomic layer deposition process as the first dielectric layer 41. As Figure 10 shown, 50 nm of titanium nitride is deposited on the first dielectric layer 41 by an atomic layer deposition process as the second electrode layer 31 of odd digits.

[0066] As Figure 11As shown, when S2 is executed for the second time, it further includes: S41, etching the odd-numbered second electrode layer 31 at the second edge in the X direction to form an odd-numbered second electrode layer etching groove 301, and dividing the odd-numbered second electrode layer 31 into an odd-numbered second electrode layer positive region 311 and an odd-numbered second electrode layer negative region 312.

[0067] As Figure 12 shown, when S3 is executed for the second time, it further includes: S42, depositing 10 nm of zirconia or hafnium oxide on the surface of the odd-numbered second electrode layer 31 using chemical vapor deposition as the second dielectric layer 42. Depositing 20 nm of titanium nitride on the second dielectric layer 42 using atomic layer deposition as the even-numbered first electrode layer 22.

[0068] When S2 is executed for the third time, it further includes: S43, etching the even-numbered first electrode layer 22 at the first edge in the X direction to form an even-numbered first electrode layer etching groove 202, and dividing the even-numbered first electrode layer 22 into an even-numbered first electrode layer positive region 221 and an even-numbered first electrode layer negative region 222.

[0069] When S3 is executed for the third time, it further includes: S44, depositing 50 nm of zirconia or hafnium oxide on the surface of the even-numbered first electrode layer 22 using atomic layer deposition as the third dielectric layer 43. Depositing 50 nm of titanium nitride on the third dielectric layer 43 using atomic layer deposition as the even-numbered second electrode layer 32.

[0070] When S2 is executed for the fourth time, it further includes: S45, etching the even-numbered second electrode layer 32 at the second edge in the X direction to form an even-numbered second electrode layer etching groove 302, and dividing the even-numbered second electrode layer 32 into an even-numbered second electrode layer positive region 321 and an even-numbered second electrode layer negative region 322.

[0071] When S3 is executed for the fourth time, it further includes: S46, depositing 50 nm of zirconia or hafnium oxide on the surface of the even-numbered second electrode layer 32 using chemical vapor deposition as the fourth dielectric layer.

[0072] Using the fourth dielectric layer as the substrate 1, the above S1 - S46 are repeatedly executed 10 times to form the silicon-based multi-layer electrode connection structure in the first example. In this example, by combining atomic layer deposition and chemical vapor deposition, the thickness and quality of the dielectric layer (such as zirconia, hafnium oxide) are precisely controlled, ensuring the effective utilization of high-k materials, thereby improving the energy density and efficiency of the capacitor. Selecting titanium nitride as the electrode material, due to its excellent electrical conductivity and thermal stability, in combination with high-k materials, significantly improves the capacitance performance and thermal stability of the device, meeting the requirements of high-performance electronic devices.

[0073] In the second example, a reactive ion etching process is used to pattern etch a silicon substrate 1 with a size of 1 cm * 1 cm to form a trench 11 with a width of 60 microns and a depth of 80 microns. An atomic layer deposition process is used to deposit 200 nanometers of metallic tungsten on the silicon wafer surface as the first electrode layer 21 for odd digits.

[0074] As Figure 8 shown, when S2 is executed for the first time, it also includes: etching the first electrode layer 21 for odd digits at the first edge located in the opposite direction of X to form an etched groove 201 of the first electrode layer for odd digits, and dividing the first electrode layer 21 for odd digits into a positive electrode region 211 of the first electrode layer for odd digits and a negative electrode region 212 of the first electrode layer for odd digits.

[0075] As Figure 9 shown, when S3 is executed for the first time, it also includes: S31, depositing 20 nm of silicon oxide on the surface of the first electrode layer 21 for odd digits using a chemical vapor deposition process as the first dielectric layer 41. As Figure 10 shown, 300 nm of metallic tungsten is deposited on the first dielectric layer 41 using a chemical vapor deposition process as the second electrode layer 31 for odd digits.

[0076] As Figure 11 shown, when S2 is executed for the second time, it also includes: S41, etching the second electrode layer 31 for odd digits at the second edge located in the X direction to form an etched groove 301 of the second electrode layer for odd digits, and dividing the second electrode layer 31 for odd digits into a positive electrode region 311 of the second electrode layer for odd digits and a negative electrode region 312 of the second electrode layer for odd digits.

[0077] As Figure 12 shown, when S3 is executed for the second time, it also includes: S42, depositing 100 nm of silicon oxide on the surface of the second electrode layer 31 for odd digits using a chemical vapor deposition process as the second dielectric layer 42. 200 nm of metallic tungsten is deposited on the second dielectric layer 42 as the first electrode layer 22 for even digits.

[0078] When S2 is executed for the third time, it also includes: S43, etching the first electrode layer 22 for even digits at the first edge located in the X direction to form an etched groove 202 of the first electrode layer for even digits, and dividing the first electrode layer 22 for even digits into a positive electrode region 221 of the first electrode layer for even digits and a negative electrode region 222 of the first electrode layer for even digits.

[0079] When S3 is executed for the third time, it also includes: S44, depositing 20 nm of silicon oxide on the surface of the first electrode layer 22 for even digits using a chemical vapor deposition process as the third dielectric layer 43. 300 nm of titanium nitride is deposited on the third dielectric layer 43 using a chemical vapor deposition process as the second electrode layer 32 for even digits.

[0080] When performing S2 for the fourth time, it further includes: S45, etching the even - numbered second electrode layer 32 at the second edge in the X direction to form an etched groove 302 for the even - numbered second electrode layer, and dividing the even - numbered second electrode layer 32 into a positive - region 321 and a negative - region 322 of the even - numbered second electrode layer.

[0081] When performing S3 for the fourth time, it further includes: S46, depositing 100 nm of zirconia or hafnium oxide on the surface of the even - numbered second electrode layer 32 using chemical vapor deposition as the fourth dielectric layer.

[0082] Taking the fourth dielectric layer as the substrate 1, the above S1 - S46 are repeatedly executed 15 times to form the silicon - based multi - layer electrode connection structure in the second example. Compared with other metals and alloys, tungsten metal has higher conductivity and better corrosion resistance, which not only enhances the conductivity of the electrode but also may improve the overall stability and service life of the device. Depositing 20 nm of silicon oxide as the first dielectric layer 41 for the first time in S3 and the change in the thickness of subsequent dielectric layers (such as 100 nm of silicon oxide for the second dielectric layer 42) can adjust different dielectric materials and thicknesses to optimize capacitance characteristics and leakage current to achieve the goal of higher energy density or lower leakage.

[0083] In some embodiments, S4 further includes: cutting or grinding the edges of the stacked electrode layers to expose the first region and the second region of the electrode layer.

[0084] In some specific embodiments, first cut the edges of the stacked electrode layers and then grind the edges so that a flat cut surface is exposed at the first edge on the X - reverse - direction side of the first region of the electrode layer, and at the same time, a flat cut surface is exposed at the second edge on the X - direction side of the second region of the electrode layer. In this embodiment, by cutting and subsequent grinding of the edges of the stacked electrode layers, it is ensured that the edges of the first region and the second region present flat cut surfaces on the X - reverse - direction side and the X - direction side. This treatment method improves the edge neatness of the electrode structure, reduces the risk of electric - field concentration or short - circuit caused by rough edges, and enhances the reliability and electrical performance of the device.

[0085] In some embodiments, it further includes S5, forming a first conductive sealing end portion 51 for connecting the first regions in each electrode layer and forming a second conductive sealing end portion 52 for connecting the second regions in each electrode layer.

[0086] In some specific embodiments, the first conductive sealing end portion 51 and the second conductive sealing end portion 52 are formed by electroplating with a graphite paste. In this embodiment, the conductive sealing end portion 5 formed by electroplating with the graphite paste can significantly enhance the conductivity of the electrical connection between electrode layers, ensure efficient current transmission, reduce resistance loss, which is particularly crucial for improving the overall electrical performance of the capacitor. The graphite material has good conductivity and stability, and the formed sealing end portion can effectively resist the influence of environmental factors on the electrical connection part, increasing the long-term stability and durability of the device. Depositing the conductive sealing end portion by electroplating process can precisely control the thickness and uniformity of the deposited layer, is suitable for mass production, can simplify the manufacturing process of the conductive sealing end portion, improve production efficiency and reduce costs.

[0087] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A multi-layer electrode connection structure, applied to an on-chip capacitor, characterized in that: include: A substrate for providing an attachment surface for the electrode layer located at the bottom layer; N electrode layers having etching grooves, N being a positive integer greater than 2; The electrode layer is divided into a first region and a second region for conducting electricity by etching grooves; Along the stacking direction, the N-layer electrode layer includes an odd-numbered first electrode layer, an even-numbered first electrode layer, an odd-numbered second electrode layer, and an even-numbered second electrode layer; The odd-numbered first electrode layer is provided with an odd-numbered first electrode layer etching groove, and the even-numbered first electrode layer is provided with an even-numbered first electrode layer etching groove; the contours of the odd-numbered first electrode layer etching groove and the even-numbered first electrode layer etching groove in the stacking direction do not intersect each other; The odd-numbered second electrode layer is provided with an odd-numbered second electrode layer etching groove, and the even-numbered second electrode layer is provided with an even-numbered second electrode layer etching groove; the contours of the odd-numbered second electrode layer etching groove and the even-numbered second electrode layer etching groove in the stacking direction do not intersect each other; The dielectric layer is located between adjacent electrode layers and is used to provide an insulating dielectric.

2. The multi-layer electrode connection structure according to claim 1, characterized in that: The electrode layer is set to be M layers, where M is greater than or equal to N; when M is equal to N, the contours of the etched grooves in the N-layer electrode layer do not intersect each other in the stacking direction.

3. The multi-layer electrode connection structure according to claim 2, characterized in that: When M is greater than N, the contours of the etched grooves in the electrode layer within the N layer intersect with the contours of the etched grooves in the electrode layer outside the N layer.

4. The multi-layer electrode connection structure according to claim 1, characterized in that: The electrode layer has a first edge and a second edge opposite to each other. The odd-numbered first electrode layer etching grooves and the even-numbered first electrode layer etching grooves are close to the first edge, and the odd-numbered second electrode layer etching grooves and the even-numbered second electrode layer etching grooves are close to the second edge.

5. The multi-layer electrode connection structure according to claim 4, characterized in that: The substrate is provided with a groove; the width of the groove is greater than the width of the etching groove.

6. The multi-layer electrode connection structure according to claim 5, characterized in that: A plurality of the grooves are distributed on the substrate surface in a self-similar patterned array; the shape of the grooves includes at least one of a strip, a rectangle, and a circle.

7. An on-chip capacitor, characterized in that: include: The multilayer electrode connection structure according to any one of claims 1 to 6, and: A first conductive sealing end portion, used to connect the first region in each electrode layer; The second conductive sealing end portion is used to connect the second region in each electrode layer; the first conductive sealing end portion and the second conductive sealing end portion are isolated from each other.

8. A multi-layer electrode connection method for forming a multi-layer electrode connection structure according to any one of claims 1 to 6, characterized in that: include: S1, providing a substrate and forming an electrode layer on the upper surface thereof; S2, performing an etching process on the electrode layer located on the surface, so that the electrode layer is divided into a first area and a second area by the etching grooves; S3, forming a dielectric layer on the surface of the electrode layer; forming an electrode layer on the upper surface of the dielectric layer; S4, after repeating S2-S3 several times, execute S2 again; the contours of the odd-numbered first electrode layer etching grooves and the even-numbered first electrode layer etching grooves in the N-layer electrode layer do not intersect each other in the stacking direction, and the contours of the odd-numbered second electrode layer etching grooves and the even-numbered second electrode layer etching grooves in the stacking direction do not intersect each other, and N is a positive integer greater than 2.

9. The multi-layer electrode connection method according to claim 8, characterized in that: S4 further includes: cutting or grinding edges of the stacked electrode layers to expose the first region and the second region of the electrode layers.

10. The multi-layer electrode connection method according to claim 9, characterized in that: The method further includes S5, forming a first conductive sealing end portion for connecting the first region in each electrode layer, and forming a second conductive sealing end portion for connecting the second region in each electrode layer.

11. The multi-layer electrode connection method according to claim 10, characterized in that: The electrode layer and the dielectric layer are respectively formed by at least one of atomic layer deposition and chemical vapor deposition processes; the first conductive sealing end portion and the second conductive sealing end portion are formed by an electroplating process.

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