Method for manufacturing a transistor device and transistor device

Abstract

The present disclosure relates to a method for manufacturing a transistor device, the method comprising: forming gate electrodes (21) such that each gate electrode (21) is arranged in a respective one of gate trenches (120) extending from a first surface (101) of a semiconductor body (100) into the semiconductor body (100), and each gate electrode is dielectrically insulated from the semiconductor body (100) by a respective one of the gate dielectrics (22); forming an insulating layer (221) over the first surface (101) of the semiconductor body and the gate electrode (21); forming at least one contact opening (222) in the insulating layer (221) over each gate electrode; forming contact fingers (32) wherein each contact finger (32) is connected to a respective gate electrode (21) in a respective contact opening; and forming a connector (31) connecting the contact fingers (32) to each other. The invention also relates to a transistor device.

Description

Technical Field

[0001] The present disclosure generally relates to a method of manufacturing a transistor device, and more particularly to a method of manufacturing a gate arrangement structure of a transistor device. Summary of the invention

[0002] One example relates to a method. The method includes forming gate electrodes such that each gate electrode is arranged in a corresponding one of gate trenches, the gate trenches extending from a first surface of a semiconductor body into the semiconductor body, and the gate electrodes are dielectrically insulated from the semiconductor body by a corresponding one of gate dielectrics, forming an insulating layer over the first surface of the semiconductor body and the gate electrodes, forming at least one contact opening in the insulating layer over each gate electrode, forming contact fingers, wherein each contact finger is connected to a corresponding gate electrode in a corresponding contact opening, and forming connectors connecting the contact fingers to each other.

[0003] Another example relates to a transistor device. The transistor device includes a gate arrangement structure. The gate arrangement structure includes: a gate electrode, each gate electrode is arranged in a corresponding one of the gate trenches, the gate trenches extending from the first surface of the semiconductor body into the semiconductor body, and the gate electrode is dielectrically insulated from the semiconductor body by a corresponding one of the gate dielectrics; an insulating layer above the first surface of the semiconductor body and the gate electrode; at least one contact opening in the insulating layer above each gate electrode; a contact finger, wherein each contact finger is connected to a corresponding gate electrode in a corresponding contact opening; and a connector connecting the contact fingers to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The examples will be explained below with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles and therefore only show aspects necessary for understanding these principles. The accompanying drawings are not drawn to scale. In the accompanying drawings, the same reference numerals represent the same features.

[0005] Figures 1A-1D and 2A-2D illustrate an example of a method of forming a gate arrangement structure of a transistor device, wherein the gate arrangement structure comprises a gate electrode in a trench of a semiconductor body, a contact finger, and a connector;

[0006] Figure 3 schematically shows a top view of a portion of a gate arrangement;

[0007] Figure 4 shows an example of a contact opening in an insulating layer according to an example;

[0008] Figures 5A-5C 6A-6C illustrate an example of a method of forming a gate dielectric and a gate electrode of a gate arrangement in a gate trench of a semiconductor body;

[0009] Figure 7A-7B and 8A-8B show one example of a method of forming contact fingers and connectors;

[0010] Fig. 9 shows a portion of a gate arrangement structure according to another example;

[0011] Figures 10A-10B shows a top view of a transistor device according to various examples;

[0012] Fig.11 schematically illustrates a transistor cell of a transistor device according to an example; and

[0013] Fig.12 Schematically shows Fig.11 Detail of a transistor cell of the type shown in . DETAILED DESCRIPTION

[0014] In the following detailed description, reference will be made to the accompanying drawings, which form part of the description and are used to illustrate examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless explicitly stated otherwise.

[0015] Figures 1A-1D 2A-2D show an example of a method of forming a gate arrangement structure of a transistor device. The gate arrangement structure comprises a plurality of gate trenches 120, each gate trench 120 extending from a first surface 101 of the semiconductor body 100 into the semiconductor body 100. According to an example, the gate trenches 120 are substantially parallel to each other.

[0016] Figures 1A-1D A vertical cross-sectional view of a portion of the semiconductor body 100 in a first section AA is shown, which is substantially perpendicular to the longitudinal direction of the gate trench 120 . Figures 2A-2D A vertical cross-sectional view of a portion of the semiconductor body 100 in a second cross-sectional area BB is shown, which crosses a portion of one of the gate trenches 120 and is substantially perpendicular to the first cross-sectional area AA.

[0017] The gate trenches 120 are spaced apart from each other in a first lateral direction x of the semiconductor body 100. A longitudinal direction of the gate trenches 120 corresponds to a second lateral direction y of the semiconductor body 100. Each gate trench 120 includes a first longitudinal end and a second longitudinal end spaced apart from the first longitudinal end in the longitudinal direction. Figures 2A-2D A first longitudinal end 121 and adjoining trench portions of one gate trench 120 are each shown. Figures 2A-2D The second longitudinal end is not shown.

[0018] Reference Figures 2A-2D, the first longitudinal end 121 is spaced apart from the sidewall 103 of the semiconductor body 100. It should be noted that the processes explained below are processes that can be performed on a wafer level. That is, these processes are applied to a wafer comprising a plurality of semiconductor bodies (semiconductor bare chips) that are separated from each other at the end of the manufacturing process. Figures 1A-1D 2A-2D, the sidewall 103 may not have been formed. Therefore, reference numeral 103 indicates the sidewall of the semiconductor body 100 or indicates the position of the sidewall of the semiconductor body 100 in the wafer.

[0019] The semiconductor body 100 includes a single-crystalline semiconductor material, such as silicon (Si) or silicon carbide (SiC).

[0020] Reference Figure 1A and 2A The method includes forming a plurality of gate electrodes 21 such that each gate electrode 21 is arranged in a corresponding one of the gate trenches 120 and is dielectrically insulated from the semiconductor material of the semiconductor body 100 by a gate dielectric 22. As shown, the gate dielectric 22 may be formed by a gate dielectric layer that covers the bottom and sidewalls of the gate trenches 120 and also covers the first surface 101 of the semiconductor body 100.

[0021] According to one example, the gate dielectric 22 includes an oxide, such as silicon oxide (SiO2). The gate electrode 21 is conductive and includes a conductive material. Examples of conductive materials include doped polycrystalline semiconductor materials (such as polysilicon), metals (such as aluminum, copper, titanium or tungsten), or silicides.

[0022] Reference Figure 1B and 2B The method further comprises forming an insulating layer 221 above the first surface 101 of the semiconductor body 100 and above the gate electrode 21 formed in the gate trench 120. The insulating layer 221 is an electrically insulating layer and comprises, for example, an oxide, a nitride, or a combination thereof. For example, according to one example, the insulating layer 221 is a homogeneous layer comprising only one electrically insulating material. According to another example, the insulating layer 221 comprises two or more electrically insulating sublayers, which are formed one above the other. The insulating layer 221 is formed, for example, using a deposition process.

[0023] According to one example, the insulating layer 221 is thicker than the dielectric layer forming the gate dielectric 22. According to one example, the thickness of the insulating layer 221 is between 2 and 5 times the thickness of the dielectric layer forming the gate dielectric 22. According to one example, the thickness of the gate dielectric is, for example, between 60 nanometers (nm) and 150 nm, and the thickness of the insulating layer 221 is between 150 nm and 500 nm.

[0024] exist Figure 1B and 2B In the example shown, the dielectric layer forming the gate dielectric 22 remains on top of the first surface 101 before forming the insulating layer 221. However, this is merely an example. According to another example, before forming the insulating layer 221, the dielectric layer is removed from the first surface 101, or the thickness of the dielectric layer on top of the first surface 101 is reduced before forming the insulating layer 221.

[0025] Reference Figure 1C and 2C The method further includes forming a contact opening 222 in the insulating layer 221 above the gate electrode 21, so that at least one contact opening 222 is formed in the insulating layer 221 above each gate electrode 21. Forming the contact opening 222 may include an etching process using an etching mask (not shown), such as an anisotropic etching process.

[0026] according to Figure 2C In one example shown, the contact opening 222 is spaced apart from the longitudinal end 121 of the gate trench 120. According to one example, the contact opening is close to the longitudinal end 121. This may include that the distance between the contact opening 222 and the longitudinal end 121 is, for example, between 0.5 micrometers and 10 micrometers.

[0027] According to one example, two contact openings are formed in the insulating layer 221 above each gate electrode 21, the first contact opening being close to the first longitudinal end 121 and the second contact opening being close to the second longitudinal end ( Figures 2A-2D According to another example, only one contact opening is formed in the insulating layer 221 above each gate electrode 21 near the first longitudinal end 121. According to another example, two contact openings are formed in the insulating layer 221 above the gate electrodes 21 of the first group of gate electrodes, and only one contact opening is formed in the insulating layer 221 above the gate electrodes 21 of the second group of gate electrodes different from the first group.

[0028] Reference Figure 1D and 2D , and refer to Figure 3 , which shows Figure 1D and 2D , the method further comprises forming a connector 31 and a gate contact finger 32 above the insulating layer 221. Each contact finger 32 is connected to a corresponding gate electrode 21 through a corresponding contact opening 222 in the insulating layer 221. The connector 31 connects the contact fingers 32 to each other. Each contact finger 32 and the connector 31 include a conductive material, such as doped polysilicon or metal. According to an example, the contact finger 32 and the connector 31 are formed by the same process. An example of such a process will be further explained below.

[0029] The connector 31 connecting the gate contact fingers 32 to each other can act as a field electrode (field plate) in the finished transistor device and can therefore also be referred to as a field electrode. In addition, the connector 31 can also be referred to as a gate runner, wherein in addition to the connector 31, another gate runner can also be formed, as further explained below.

[0030] Figure 4 A contact opening 222 in the insulating layer 221 above a gate electrode 21 is shown in more detail. According to an example, the contact opening is substantially rectangular and has a width w222 in a first lateral direction x of the semiconductor body 100 and a length l222 in a second lateral direction y of the semiconductor body 100. According to an example, the length l222 is greater than the width w222. Furthermore, according to an example, the width w222 of the contact opening 222 is less than the width w21 of the gate electrode 21. According to an example, the width w21 of the gate electrode 21 is, for example, selected from between 0.5 micrometers and 2 micrometers.

[0031] According to one example, the width w222 of the contact opening 222 is selected between 0.3 micrometers (300 nanometers, nm) and 0.8 micrometers (800 nm), and the length l222 of the contact opening 222 is selected between 0.5 micrometers (500 nm) and 10 micrometers. As further explained below, the connector 31 connects the gate electrode 21 to the gate pad of the transistor device through the contact finger 32.

[0032] The resistance between the gate electrode 21 and the connector 31 depends on various parameters, such as the size of the corresponding contact opening 222 (given by the length l222 multiplied by the width w222); the conductivity of the material of the corresponding contact finger 32; and the length and cross-sectional area of ​​the corresponding gate contact finger 32. The “cross-sectional area” of the gate contact finger 32 is determined by the width w32 (see Figure 3 ) is multiplied by the thickness of the conductive material forming the gate contact finger 32.

[0033] As further described in detail below, each gate electrode 21 is part of one or more transistor cells in the transistor device. Each of these transistor cells can operate in an on state (conductive state) or an off state (blocking state). Basically, the transistor device is turned on or off according to a drive signal applied to the gate pad (as further described below), wherein the transistor device is turned on when the drive signal has an on level, or the transistor device is turned off when the drive signal has an off level. There may be a delay time between the point in time when the drive signal changes from the off level to the on level (or vice versa) and the point in time when the individual transistor cells are turned on (or turned off). The delay time depends in particular on the resistance of the gate contact finger. In accordance with Figure 1D , 2DIn the gate arrangement structure of , 3, the resistance of the contact finger can be adjusted in various ways to achieve that each transistor unit is turned on after the same delay time or after different delay times.

[0034] The resistance between the gate electrode 21 and the connector 31 depends on various parameters, such as the size of the corresponding contact opening 222 (given by the length l222 multiplied by the width w222); the conductivity of the material of the corresponding contact finger 32; and the length and cross-sectional area of ​​the corresponding gate contact finger 32. The “cross-sectional area” of the gate contact finger 32 is determined by the width w32 (see Figure 3 ) is multiplied by the thickness of the conductive material forming the gate contact finger 32.

[0035] According to one example, the gate contact finger comprises doped polysilicon. In this example, the conductivity of each gate contact finger 32 depends on the doping concentration of the polysilicon forming the corresponding gate contact finger 32. According to one example, a doped polysilicon layer is deposited, and the contact fingers and connectors 31 are formed based on the deposited polysilicon layer. In this example, the polysilicon layer has substantially the same conductivity at each location. According to another example, an intrinsic (non-doped) polysilicon layer is deposited, and the polysilicon layer is doped by implanting dopant atoms into the polysilicon layer. In this example, different contact fingers 32 can be doped differently, thereby obtaining contact fingers 32 with different conductivity.

[0036] Figures 5A-5C 6A-6C illustrate one example of a method of forming a gate electrode 21 and a gate dielectric 22 in a gate trench 120 of a semiconductor body 100 . Figures 5A-5C shows a vertical cross-sectional view of a portion of a semiconductor body 100 in a first section, Figures 6A-6C A vertical cross-sectional view of a portion of the semiconductor body 100 in a second section BB is shown.

[0037] Reference Figure 5A and 6A , the method includes forming a gate trench 120 in a first surface 101 of a semiconductor body 100. Forming the gate trench 120 may include an etching process, such as an anisotropic etching process. The etching process includes forming an etching mask 401 on top of the first surface 101 and etching the gate trench 120 into a portion of the first surface 101 not covered by the etching mask 401. According to an example, the gate trench 120 is etched to have a depth between 0.5 micrometers and 5 micrometers, in particular between 1 micrometer and 3 micrometers.

[0038] Reference Figure 5B and 6BThe method further includes forming a gate dielectric layer, which forms a gate dielectric 22 in the gate trench 120. According to an example, forming the gate dielectric layer includes a thermal oxidation process after removing the etching mask 401. In this example, the gate dielectric layer includes a semiconductor oxide, such as silicon oxide.

[0039] Reference Figure 5C and 6C The method further includes forming a gate electrode layer 210 that fills the gate trench 120 and may cover those portions of the gate dielectric layer that are formed above the first surface 101. Forming the gate electrode layer 210 includes, for example, depositing the gate electrode layer 210. In order to achieve Figure 1A and 2A According to an embodiment of the present invention, the method further comprises removing the gate electrode layer 210 from at least above the first surface 101 of the semiconductor body 100. According to an example, this comprises an etching process, which selectively etches the material of the gate electrode layer 210 relative to the gate dielectric layer 22. According to an example, the etching process is performed such that the gate electrode layer 210 is not only removed from above the first surface 101, but also a part of the gate electrode layer 210 is removed from the upper part of the gate trench 120, so that the gate electrode 21 is spaced apart from the first surface 101 in a vertical direction z of the semiconductor body 100. The “vertical direction z” is substantially perpendicular to the first surface 101 of the semiconductor body 100.

[0040] Figure 7A-7B 8A-8B show one example of a method of forming the contact fingers 32 and the connector 31 . Figure 7A-7B shows a vertical cross-sectional view of a portion of a semiconductor body 100 in a first section, Figures 8A-8B A vertical cross-sectional view of a portion of the semiconductor body 100 in a second section BB is shown.

[0041] Reference Fig. 7A and 8A The method includes forming a conductive layer over the insulating layer 221 and in the contact opening 222. Figure 7B and 8B The method further includes patterning the conductive layer 310 to form the contact fingers 32 and the connectors 31. Patterning the conductive layer 310 may include an etching process, such as an anisotropic etching process using an etching mask 402 formed over the conductive layer 310, wherein the conductive layer 310 is removed from those portions of the insulating layer 221 that are not covered by the etching mask 402. By appropriately selecting the etching mask 402, the width of the contact fingers 32 may be adjusted, thereby adjusting the resistance of the contact fingers 32.

[0042] Referring to the above, the conductive layer 310 may be a doped polysilicon layer. According to one example, the doped polysilicon layer is deposited in a deposition process. According to another example, an intrinsic (non-conductive) polysilicon layer is deposited, and the intrinsic polysilicon layer is doped using an implantation process to obtain a doped polysilicon layer. The doping process may be performed before or after patterning the polysilicon layer. Referring to the above, different regions of the polysilicon layer may be doped differently to adjust the resistance of the gate contact finger 32 formed based on the polysilicon layer.

[0043] Fig. 9 A portion of a gate arrangement structure based on the above gate arrangement structure is shown. The gate arrangement structure further includes another insulating layer 223 formed over the gate contact finger 32 and the connector 31, and a gate runner 41 arranged over the another insulating layer 223 and electrically connected to the connector 31. The connector 31 may also be referred to as a first gate runner, and the gate runner 41 may also be referred to as a second gate runner.

[0044] Hereinafter, the insulating layer 221 is also referred to as a first insulating layer, and the other insulating layer 223 is also referred to as a second insulating layer.

[0045] According to one example, the connector 31 is electrically connected to the gate runner 41 by a conductive via 51 extending through the second insulating layer 223 .

[0046] The gate runner 41 includes a conductive material, such as aluminum (Al), copper (Cu) or aluminum-copper alloy (AlCu). The conductive via 51 includes, for example, tungsten (W), titanium (Ti), aluminum (Al) or copper (Cu). The gate runner 41 can be formed by depositing a conductive layer on top of the second insulating layer 223 and patterning the conductive layer in an etching process to obtain the gate runner 41.

[0047] Figures 10A-10B Schematically shows a top view of a transistor device according to two different examples. Figures 10A-10B , each transistor device includes a gate runner 41, a gate pad 42 connected to the gate runner 41, and a source electrode (source metallization) 43. The gate runner 41 surrounds the source electrode 43 in the horizontal direction. The gate pad 42 and the lower source electrode 43 may include the same material as the gate runner 41 and may be formed by the same process as the gate runner 41. The gate pad 42 may be adjacent to the gate runner 41 (as shown). According to another example (not shown), the gate pad is spaced apart from the gate runner 41, and a resistor (gate resistor) is formed between the gate runner 41 and the gate pad 42.

[0048] The gate electrode 21 is Figures 10A-10B The transistor device may include two of the multiple gate electrodes located at positions relative to the source electrode 43 and the gate channel 41. Figures 10A-10B Each of these gate electrodes 21 is connected by a corresponding contact finger 32 (in Fig. 10A and 10B (also not visible in the figure) is connected to connector 31.

[0049] exist Fig. 10A In the example shown, the gate pad 42 is arranged substantially in the middle between two opposite side walls 103, 104 of the semiconductor body 100. Fig. 10B In the examples of , the gate pad 42 is arranged near a corner formed by two adjacent sidewalls 104, 105 of the semiconductor body 100. In each of these examples, the transistor device may include two types of gate electrodes 21, namely a first type of gate electrode and a second type of gate electrode. Fig. 10A and 10B In the figure, reference numeral 211 denotes a first type of gate electrode, and reference numeral 212 denotes a second type of gate electrode. The first type gate electrode 21 has a first longitudinal end 121 and a second longitudinal end 122 connected to a connector 31 (in Fig. 10A and 10B The second type gate electrode has only one longitudinal end (eg, the first longitudinal end 121 connected to the connector 31) and the gate runner 41.

[0050] The gate pad 42 forms a gate node of the transistor device, and the source electrode 43 forms a source node of the transistor device. The source electrode 43 is spaced apart from each of the gate runner 41 and the gate pad 42. Fig. 10A and 10B 4 (not visible in the figure) is arranged below the gate flow channel 41. Like the gate flow channel 41, the connector 31 forms a closed loop in the horizontal plane where the connector 31 is arranged.

[0051] The semiconductor body 100 may include an inner region and an edge region. The inner region (also referred to as an active region) includes transistor cells and is essentially a region of the semiconductor body 100 arranged below the source electrode 43. The edge region is arranged between the inner region and the sidewalls 103-106 of the semiconductor body 100. According to an example, the connector 31, the gate runner 41 and the gate pad 42 are arranged above the edge region of the semiconductor body 100. According to an example, the gate contact finger 32 is also arranged in the edge region of the semiconductor body 100.

[0052] The inner region of the semiconductor body may include a plurality of transistor cells, wherein each transistor cell includes one of the gate electrodes 21 or a portion of one of the gate electrodes 21 . Fig.11 A transistor cell 10 according to an example is shown. Fig.11 Shows Figures 10A-10B A vertical cross-sectional view of a transistor device in vertical section CC shown in FIG.

[0053] Reference Fig.11 , each transistor cell 10 includes a source region 11 of a first doping type, a body region 12 of a second doping type complementary to the first doping type, a drain region 13 of the first doping type, and a drift region 14 of the first doping type. The body region 12 is adjacent to the source region 12, so that a PN junction is formed between the source region 11 and the body region 12. In addition, each of the source region 11 and the body region 12 is connected to the source electrode 41. The source region 11 and the body region 12 can be connected to the source electrode 41 through a conductive via 42. According to an example, each of the source region 11 and the body region 12 is ohmically connected to the conductive via 42. In order to achieve an ohmic contact between the via 42 and the body region 12, a contact region 17 of the second doping type can be arranged between the body region 12 and the via 42, wherein the contact region 17 has a higher doping concentration than the body region 12.

[0054] Reference Fig.11 , the source electrode 41 is formed on top of the insulating layer 5, and the insulating layer 5 separates the source electrode 41 from the semiconductor body 100. The insulating layer 5 may include the first and second insulating layers 221, 223 and / or other electrical insulating layers explained above. For example, the conductive via 42 extends through the insulating layer 5 into the source region 11 and the body region 12.

[0055] Reference Fig.11 , the drift region 14 is adjacent to the body region 12, thereby forming another PN junction between the body region 12 and the drift region 14. The drift region 14 may be adjacent to the drain region 13. Optionally, a buffer region 16 of the first doping type is arranged between the drift region 14 and the drain region 13. The doping concentration of the buffer region 16 may be lower than the doping concentration of the drain region 13 and higher than the doping concentration of the drift region 14.

[0056] exist Fig.11 In the example shown, the transistor device is a vertical transistor device. In this example, the drain region 13 is spaced apart from the body region 12 in the vertical direction z of the semiconductor body 100 .

[0057] from Fig.11 It can be seen that the same gate electrode can form the gate electrodes 21 of two adjacent transistor cells 10 and the body regions of two (other) adjacent transistor cells can be formed by a continuous doped semiconductor region. The transistor cells can have a common drift region 11 , a common drain region 13 and optionally a common buffer region 16 .

[0058] According to an example, the transistor device is a super junction transistor device. In this example, each transistor cell further comprises a compensation region 15 of the second doping type, the compensation region 15 being adjacent to the drift region 14 and connected to the source electrode 41. Fig.11 In the example shown, the compensation region 15 adjoins the body region 12 , so that the compensation region 15 is connected to the source electrode 41 via the body region 12 , the contact region 17 and the conductive via 42 .

[0059] By applying the gate pad 42 ( Fig.11 By applying a driving voltage between the gate dielectric 22 (not shown) and the source electrode 43, the transistor device can be operated in a conventional manner. When the driving voltage causes a conductive channel to be generated in the body region 12 along the gate dielectric 22 between the source region 11 and the drift region 14, the transistor device is in an on state (conductive state). When the conductive channel is interrupted, the transistor device is in an off state (blocking state). The transistor device can be implemented as an N-type transistor device or a P-type transistor device. For example, when the driving voltage is higher than a predefined positive threshold voltage, the N-type transistor device is in an on state, and when the driving voltage is lower than the threshold voltage, the N-type transistor device is in an off state.

[0060] In an N-type transistor device, the doped region of the first doping type is an N-type region, and the doped region of the second doping type is a P-type region; in a P-type transistor device, the doped region of the first doping type is a P-type region, and the doped region of the second doping type is an N-type region.

[0061] In N-type transistor devices, the doping concentration of the active device region is selected from the following ranges, e.g.

[0062] Source region 11: 5E19cm -3 –5E20cm -3

[0063] Main body area 12: 3E19cm -3 –3E20cm -3

[0064] Drain region 13: 5E18cm -3 –5E20cm -3

[0065] Drift zone 14: 7E15cm -3 –7E16cm -3

[0066] Compensation zone 15: 7E15cm -3 –7E16cm -3

[0067] Buffer 16: 5E15cm -3 –5E16cm-3

[0068] Body contact area 17: 1E20cm -3 –1E21cm -3

[0069] Reference Fig.11 , each of the source region 11 and the body region 12 is adjacent to the corresponding gate dielectric 22. In the longitudinal direction of the gate trench, the source region 11 may end before the longitudinal end of the gate trench. Fig.12 It is shown in Fig.12 1 shows a horizontal cross-sectional view of a portion of the gate arrangement in a region close to the first longitudinal end 121 along a section through the source region 11. Fig.12 It can be seen that the source region 11 does not extend to the longitudinal end 121 of the gate trench 120 , wherein the body region 12 surrounds the longitudinal end 121 of the gate trench 120 .

[0070] In the previously explained gate arrangement, the insulating layer 221 is manufactured independently of the gate dielectric 22, and the thickness of the insulating layer 221 can be adjusted independently of the thickness of the gate dielectric 22. This allows the gate dielectric 22 to be realized with a desired thinness to achieve the desired electrical properties of the transistor cell 10, and the insulating layer 221 to be realized with a desired thickness to ensure sufficient electrical insulation between the gate contact finger 32 and the (first) connector 31 on one side, and the region of the semiconductor body 100 on the other side that has the same potential as the source electrode 43. In particular along the first surface 101, in the corners between the first surface 101 and the sidewalls of the gate trench 120, particularly high electric fields may occur, which are absorbed by the insulating layer 221.

[0071] Furthermore, by appropriately adjusting the size of the contact opening 222 , the resistance between the gate electrode 21 and the connector 31 can be easily adjusted.

Claims

1. A method for manufacturing a transistor device, the method comprising: forming gate electrodes (21) such that each gate electrode (21) is arranged in a corresponding gate trench (120), the gate trench extending from a first surface (101) of the semiconductor body (100) into the semiconductor body (100), and each gate electrode is dielectrically insulated from the semiconductor body (100) by a corresponding gate dielectric (22); forming an insulating layer (221) above the first surface (101) of the semiconductor body and the gate electrode (21); forming at least one contact opening (222) in the insulating layer (221) above each gate electrode; forming contact fingers (32), wherein each contact finger (32) is connected to a corresponding gate electrode (21) in a corresponding contact opening; as well as A connector (31) is formed which connects the contact fingers (32) to each other.

2. The method according to claim 1, wherein: The contact fingers (32) and the connector (31) are formed by the same process.

3. The method according to claim 2, wherein: Forming the contact finger (32) and the connector (31) comprises: forming a conductive layer (310) above the first insulating layer (221); and The conductive layer (310) is patterned.

4. The method according to any one of the preceding claims, in, The gate trenches (120) are parallel to each other.

5. The method according to any one of the preceding claims, The method also includes forming the gate dielectric (22) and the gate electrode (21).

6. The method according to claim 5, in, Forming the gate dielectric (22) includes a thermal oxidation process, wherein a gate dielectric layer is formed along the sidewalls and bottom of the gate trench (120) and on the first surface (101) of the semiconductor body (100).

7. The method according to claim 6, in, Before forming the insulating layer (221), the gate dielectric layer is removed from at least part of the first surface (101).

8. The method according to claim 6, in, The gate dielectric layer remains on the first surface (101), so that the first insulating layer (221) is formed above the gate dielectric layer.

9. The method according to any one of the preceding claims, in, The insulating layer (221) is a first insulating layer, and The method further comprises: forming a second insulating layer (223) over the gate contact finger (32), the connector (31) and the first insulating layer (221); and A gate flow channel (41) connected to the connector (31) is formed above the second insulating layer (223).

10. The method according to any one of the preceding claims, in, The insulating layer (221) is thicker than the gate dielectric (22).

11. A transistor device comprising a gate arrangement structure, wherein: The gate arrangement structure comprises: Gate electrodes (21), each gate electrode being arranged in a corresponding gate trench (120), the gate trench extending from the first surface (101) of the semiconductor body (100) into the semiconductor body (100), and each gate electrode being dielectrically insulated from the semiconductor body (100) by a corresponding gate dielectric (22); An insulating layer (221) located above the first surface (101) of the semiconductor body and the gate electrode (21); at least one contact opening (222) located in the insulating layer (221) above each gate electrode; contact fingers (32), wherein each contact finger (32) is connected to a corresponding gate electrode (21) in a corresponding contact opening; and A connector (31) connects the contact fingers (32) to each other.

12. The transistor device according to claim 10, in, The insulating layer (221) is a first insulating layer, and The gate arrangement structure further comprises: A second insulating layer (223) formed over the gate contact finger (32), the connector (31) and the first insulating layer (221); and A gate runner (41) is formed above the second insulating layer (223) and is electrically connected to the connector (31).

13. The transistor device according to claim 12, further comprising: A plurality of transistor units (10), each transistor unit (10) comprising a source region (11) and at least a portion of a corresponding gate electrode (21); as well as a source electrode (43) connected to the source region (11) of each transistor cell (10), The gate channel (41) surrounds the source electrode (43) in a horizontal plane.

14. The transistor device according to any one of claims 11 to 13, further comprising: A gate pad (42) is connected to the gate flow channel (41).

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