A method for preparing an enhanced GaN HEMT device with a heterojunction gate
By oxidizing the method of forming heterogeneous p/n junctions on the surface of the p-type layer, the problem of too small gate breakdown voltage of Schottky pGaN HEMT devices is solved, and a GaN HEMT device with high threshold voltage and high breakdown electric field capability is realized.
Patent Information
- Application Number
- CN202411931530.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-04-04
AI Technical Summary
The gate breakdown voltage of existing Schottky-type pGaN HEMT devices is too small, which affects its application in the field of high power.
By using the preparation method of a heterojunction gate, an oxide layer is formed by oxidizing on the surface of the p-type layer to form a heterogeneous p/n junction between the n-type oxide layer and the p-type layer, thereby reducing holes in the gate metal injection and improving the reverse biasing capability.
It effectively improves the threshold voltage and gate breakdown voltage of the device, reduces gate leakage, and realizes a GaN HEMT device with high breakdown electric field capability.
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Figure CN119767720A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductors, and in particular to a method for preparing an enhanced-mode GaN HEMT device with a heterojunction gate. Background Art
[0002] As a representative of wide bandgap power semiconductor devices, GaN HEMT has outstanding advantages in the application of high-frequency and high-power devices. GaN materials have higher electron mobility, saturated electron velocity and breakdown electric field than Si and SiC. Considering the requirements of practical applications for reliability, design cost and energy consumption, enhancement-mode GaN HEMT devices have more significant advantages than traditional depletion-mode GaN HEMT devices. At present, the solutions for realizing enhancement-mode GaN HEMT devices include p-GaN gate technology, recessed gate structure, cascode structure, fluorine ion treatment method, etc. p-GaN gate technology can obtain enhancement-mode devices with stable threshold voltage, high reliability, strong process controllability and good repeatability, which are suitable for large-scale production and commercial use. Therefore, it has become the most widely used enhancement-mode GaN HEMT device preparation method.
[0003] The gate preparation method of conventional p GaN gate technology is to deposit metal on the pGaN cap layer to form a Schottky contact, whose structure includes a Schottky diode formed by metal and p GaN. When a forward voltage is applied to the gate metal, the Schottky diode is in a reverse cutoff state, and the vertical gate leakage is limited by the Schottky diode. However, the turn-on voltage of the Schottky contact is low. When the forward voltage applied to the gate is greater than the critical value, the Schottky diode is turned on and the gate leakage increases significantly. Gate leakage will increase switching losses, affect conversion efficiency, and even cause the gate of the device to breakdown, which is not conducive to high-voltage applications. At present, the gate breakdown voltage of traditional Schottky-type p GaN HEMT devices is mostly below 10V, and the gate breakdown voltage is only about 6V when working for a long time. Its too small gate voltage swing seriously affects the application of pGaN HEMT devices in the high-power field. Summary of the invention
[0004] Based on this, the present invention provides a method for preparing an enhanced-mode GaN HEMT device with a heterojunction gate. The device prepared by the method realizes an enhanced-mode GaN HEMT device while making the device have a larger threshold voltage and a larger gate breakdown voltage, thereby overcoming the deficiencies in the prior art.
[0005] The invention provides the following technical solution: a method for preparing an enhanced-mode GaN HEMT device with a heterojunction gate, comprising the following steps:
[0006] Step S1: providing a substrate layer, and sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure;
[0007] Step S2: oxidizing the surface of the p-type layer to form an oxide layer;
[0008] Step S3: removing the oxide layer and the p-type layer outside the gate region;
[0009] Step S4: performing mesa etching extending downward from a portion of the barrier layer to the buffer layer, thereby forming a mesa on the surface of the buffer layer;
[0010] Step S5: depositing a source electrode and a drain electrode on the upper surface of the barrier layer, thereby preparing a source ohmic contact electrode and a drain ohmic contact electrode on the barrier layer;
[0011] Step S6: depositing a gate electrode on the upper surface of the oxide layer to obtain an enhanced-mode GaN HEMT device with the heterojunction gate.
[0012] Furthermore, the step S1: providing a substrate, and sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure; wherein the thin film structure is grown by a metal organic chemical vapor deposition (MOCVD) method.
[0013] Furthermore, the step S1: provides a substrate, and sequentially grows a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure; wherein the substrate layer is made of silicon or sapphire or silicon carbide or gallium nitride or diamond; the nucleation layer is made of AlN superlattice, and the buffer layer is made of GaN or AlGaN; the channel layer is made of GaN or GaAs; the barrier layer is made of AlGaN or InAlN or AlN or InGaN; the p-type layer is made of any one or more combinations of GaN, AlGaN and InGaN.
[0014] Furthermore, the step S1: provides a substrate, and sequentially grows a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure; wherein the thickness of the substrate layer is 0.5 mm to 2 mm, the thickness of the nucleation layer is 0.2 um to 1 um, the thickness of the buffer layer is 0.5 um to 2.5 um, the thickness of the channel layer is 100 nm to 300 nm, the thickness of the barrier layer is 10 nm to 30 nm, and the thickness of the p-type layer is 50 nm to 120 nm.
[0015] Furthermore, the step S2: oxidizing the surface of the p-type layer to form an oxide layer; wherein the surface of the p-type layer is subjected to oxygen-based plasma treatment using an inductively coupled plasma device to form the oxide layer.
[0016] Furthermore, the step S2: oxidizing the surface of the p-type layer to form an oxide layer; wherein the material of the oxide layer is gallium oxide or a mixture of gallium oxide and aluminum oxide or a mixture of gallium oxide and indium oxide; the thickness of the oxide layer is 5nm to 200nm.
[0017] Furthermore, the step S4: extends downward from a portion of the barrier layer to the buffer layer for etching and removal, thereby forming a mesa on the surface of the buffer layer; wherein a patterned device mesa is obtained by a photolithography process and the mesa is etched, and the etching depth extends downward from a portion of the barrier layer to the buffer layer, thereby forming a mesa on the surface of the buffer layer.
[0018] Furthermore, the step S5: depositing a source electrode and a drain electrode on the upper surface of the barrier layer, thereby preparing a source ohmic contact electrode and a drain ohmic contact electrode; wherein the patterned source electrode and the drain electrode are obtained by a photolithography process, and the source electrode and the drain electrode are deposited on the upper surface of the barrier layer and annealed, thereby preparing the source ohmic contact electrode and the drain ohmic contact electrode on the barrier layer.
[0019] Furthermore, the step S6: depositing a gate electrode on the upper surface of the oxide layer to obtain an enhanced-mode GaN HEMT device with a heterojunction gate; wherein a patterned gate electrode pattern is obtained by a photolithography process, and then the gate electrode is deposited on the upper surface of the oxide layer to obtain an enhanced-mode GaN HEMT device with a heterojunction gate.
[0020] The beneficial effects of the invention are as follows: by oxidizing the surface of the p-type layer to form an oxide layer, under normal circumstances, undoped gallium oxide and indium oxide are an n-type semiconductor, forming an n-type oxide layer, and then the n-type oxide layer and the p-type layer form a heterogeneous p / n junction gate; when the depletion region extends to the p-side and the n-side, the pn junction can reduce the holes injected from the gate metal, and the pn junction reverse structure can withstand a larger reverse bias, so the heterogeneous p / n junction prepared by the method of the present invention can suppress the leakage path of the current from the gate to a greater extent compared with the Schottky junction formed by metal / p-GaN, effectively reduce the gate leakage of the device, and increase the gate breakdown voltage, thereby realizing a lateral GaN HEMT device with a high breakdown electric field capability; and the gallium oxide layer can play a voltage divider role, further increasing the threshold voltage of the GaN HEMT device; and compared with the device preparation method of the conventional metal dielectric layer pGaN structure, the method of the present invention uses the p-type layer to oxidize to form the n-type oxide layer, and there is no need to deposit a dielectric layer on the p-type cap layer again, thereby simplifying the process flow. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a schematic diagram corresponding to step S1 of the method for preparing an enhanced-mode GaN HEMT device of the present invention.
[0022] Figure 2 It is a schematic diagram corresponding to step S2 of the method for preparing an enhanced-mode GaN HEMT device of the present invention.
[0023] Figure 3 It is a schematic diagram corresponding to step S3 of the method for preparing an enhanced-mode GaN HEMT device of the present invention.
[0024] Figure 4 It is a schematic diagram corresponding to step S4 of the method for preparing an enhanced-mode GaN HEMT device of the present invention.
[0025] Figure 5 It is a schematic diagram corresponding to step S5 of the method for preparing an enhancement-mode GaN HEMT device of the present invention.
[0026] Figure 6 It is a schematic diagram corresponding to step S6 of the method for preparing an enhancement-mode GaN HEMT device of the present invention.
[0027] The markings in the accompanying drawings are: 101 - substrate layer, 102 - nucleation layer, 103 - buffer layer, 104 - channel layer, 105 - barrier layer, 106 - p-type layer, 107 - gallium oxide layer, 201 - source ohmic contact electrode, 202 - drain ohmic contact electrode, 203 - gate electrode. DETAILED DESCRIPTION
[0028] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.
[0029] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0031] The solution proposed by the present invention is suitable for the design and manufacture of enhanced GaN HEMT devices.
[0032] GaN HEMT is a high electron mobility transistor based on gallium nitride (GaN), which is an advanced power semiconductor device. Its structure includes GaN substrate, AlGaN buffer layer, GaN channel layer, AlGaN electron blocking layer and metal gate. Among them, the GaN channel layer is the channel for carrier flow, while the AlGaN buffer layer helps to reduce the electric field strength inside the transistor and improve the reliability and performance of the transistor.
[0033] The biggest advantage of GaN HEMT is its high electron mobility, which means that electrons move faster in the channel, which can support higher operating frequencies and faster switching speeds. In addition, GaN materials have a large bandgap width and high breakdown field strength, which enables GaN HEMT to withstand higher voltages and current densities, thereby achieving higher power density. This feature gives GaN HEMT a significant advantage in applications that require high power output, such as power electronic converters, radar systems, etc.
[0034] In practical applications, GaN HEMT has demonstrated its great potential. For example, in wireless charging devices, GaN HEMT can provide faster switching speeds and lower transmission losses, thereby significantly improving charging efficiency. In the field of automotive electronics, the high power density and low on-resistance of GaN HEMT make the motor smaller and lighter while maintaining the same output power as traditional motors. In addition, GaN HEMT also has fast switching capabilities and supports high-frequency operations of 200kHz and above, which gives it significant advantages in applications such as high-frequency motor drives and RF power amplifiers in wireless communication systems.
[0035] Embodiment 1:
[0036] This embodiment provides a method for preparing an enhanced-mode GaN HEMT device with a heterojunction gate, comprising the following steps:
[0037] Please refer to Figure 1 , step S1: providing a substrate layer 101, and sequentially growing a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105 and a p-type layer 106 on the substrate layer 101 to form a thin film structure;
[0038] It can be understood that a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105 and a p-type layer 106 are sequentially grown on a substrate using a metal organic chemical vapor deposition (MOCVD) method, wherein the p-type layer 106 is a p-GaN layer, thereby forming a thin film structure;
[0039] Among them, the thickness of the substrate layer 101 is 0.5mm to 2mm, the thickness of the nucleation layer 102 is 0.2um to 1um, the thickness of the buffer layer 103 is 0.5um to 2.5um, the thickness of the channel layer 104 is 100nm to 300nm, and the thickness of the barrier layer 105 is 10nm to 30nm; the thickness of the p-type layer 106 is 50nm to 120nm; the material of the substrate layer 101 is silicon or sapphire or silicon carbide or gallium nitride or diamond; the material of the nucleation layer 102 is AlN superlattice; the material of the buffer layer 103 is GaN or AlGaN; the material of the channel layer 104 is GaN or GaAs; the material of the barrier layer 105 is AlGaN or InAlN or AlN or InGaN; the material of the p-type layer 106 is any one or more combinations of GaN, AlGaN and InGaN.
[0040] In this embodiment, the thickness of the substrate layer 101 is 1150um and the material is preferably silicon, the thickness of the nucleation layer 102 is 500nm and the material is preferably AlN superlattice, the thickness of the buffer layer 103 is 2um and the material is preferably GaN, the thickness of the channel layer 104 is 250nm and the material is preferably GaN, the thickness of the barrier layer 105 is 20nm and the material is preferably AlGaN, and the thickness of the p-type layer 106 is 90nm.
[0041] Please refer to Figure 2 , step S2: oxidizing the surface of the p-type layer 106 to form an oxide layer;
[0042] Specifically, an inductively coupled plasma device is used to perform oxygen-based plasma treatment on the surface of the p-type layer 106, the upper electrode power is 20W to 800W, the lower electrode power is 0W to 100W, the O2 gas flow rate is 10sccm to 200sccm, the chamber pressure is 0.1mTorr to 50mTorr, the temperature is 300°C to 500°C, and the treatment time is 0.5min to 60min. The material of the oxide layer is one of gallium oxide, a mixture of gallium oxide and aluminum oxide, and a mixture of gallium oxide and indium oxide, and the thickness of the oxide layer is 5nm to 200nm.
[0043] In this embodiment, an inductively coupled plasma device is used to perform oxygen plasma treatment on the surface of the p-type layer 106, the upper electrode power is 60W, the lower electrode power is 2W, the O2 gas flow rate is 100sccm, the chamber pressure is 10mTorr, the temperature is 350°C, and the treatment time is 4min, and the 20nm thick surface gallium nitride of the p-type layer 106 is oxidized into gallium oxide to form an oxide layer with a thickness of 20nm;
[0044] Please refer to Figure 3 , step S3: removing the oxide layer and the p-type layer 106 outside the gate region;
[0045] Specifically, an inductively coupled plasma etcher is used to etch away the oxide layer and the p-type layer 106 in the non-gate region to expose the barrier layer 105;
[0046] Please refer to Figure 4 Step S4: performing mesa etching from a portion of the barrier layer 105 downward to the buffer layer 103 , thereby forming a mesa on the surface of the buffer layer 103 ;
[0047] Understandable, see Figure 4, a patterned device mesa is obtained by photolithography and the mesa is isolated. The isolation method is to etch the mesa, and then an inductively coupled plasma etcher is used to etch the thin film structure. Specifically, the mesa is etched from both sides of the barrier layer 105 downward to the buffer layer 103, thereby forming a mesa on the surface of the buffer layer 103;
[0048] Please refer to Figure 5 , step S5: depositing a source electrode and a drain electrode on the upper surface of the barrier layer 105 , thereby preparing a source ohmic contact electrode 201 and a drain ohmic contact electrode 202 on the barrier layer 105 ;
[0049] For details, see Figure 5 , obtaining the patterned source electrode and the drain electrode by photolithography, depositing the source electrode and the drain electrode on the upper surface of the barrier layer 105 and annealing, thereby preparing the source ohmic contact electrode 201 and the drain ohmic contact electrode 202 on the barrier layer 105;
[0050] The source electrode and the drain electrode are made of Ti / Al / Ni / Au.
[0051] Please refer to Figure 6 , step S6: depositing a gate electrode 203 on the upper surface of the oxide layer to obtain an enhancement-mode GaN HEMT device with the heterojunction gate.
[0052] Specifically, a patterned gate electrode 203 pattern is obtained by a photolithography process, and then the gate electrode 203 is deposited on the upper surface of the gallium oxide to obtain an enhanced GaN HEMT device with a heterojunction gate;
[0053] The gate electrode 203 is made of Ni / Au.
[0054] Embodiment 2:
[0055] This embodiment also provides a method for preparing an enhanced-mode GaN HEMT device with a heterojunction gate. This embodiment is substantially the same as the first embodiment, except that: in step S1 of this embodiment, the thickness of the p-type layer 106 is 110 nm; in step S2 of this embodiment: an oxygen-based plasma treatment is performed on the surface of the p-type layer 106 using an inductively coupled plasma device for 10 min, and the surface of the p-type layer 106 is oxidized into a mixture of indium oxide and gallium oxide to form an oxide layer, and the oxide layer has a thickness of 40 nm;
[0056] This embodiment specifically includes the following steps:
[0057] Please refer to Figure 1, step S1: providing a substrate layer 101, and sequentially growing a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105 and a p-type layer 106 on the substrate layer 101 to form a thin film structure;
[0058] It can be understood that a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105 and a p-type layer 106 are sequentially grown on a substrate using a metal organic chemical vapor deposition (MOCVD) method, wherein the p-type layer 106 is a p-GaN layer, thereby forming a thin film structure;
[0059] In this embodiment, the thickness of the substrate layer 101 is 1150um and the material is preferably silicon, the thickness of the nucleation layer 102 is 500nm and the material is preferably AlN superlattice, the thickness of the buffer layer 103 is 2um and the material is preferably GaN, the thickness of the channel layer 104 is 250nm and the material is preferably GaN, the thickness of the barrier layer 105 is 20nm and the material is preferably AlGaN, and the thickness of the p-type layer 106 is 110nm.
[0060] Please refer to Figure 2 , step S2: oxidizing the surface of the p-type layer 106 to form an oxide layer;
[0061] Specifically, in this embodiment, an inductively coupled plasma device is used to perform oxygen-based plasma treatment on the surface of the p-type layer 106. The upper electrode power is 60 W, the lower electrode power is 2 W, the O2 gas flow rate is 100 sccm, the chamber pressure is 10 mTorr, the temperature is 350°C, and the treatment time is 10 min. The p-type layer 106 is oxidized into a mixture of indium oxide and gallium oxide to form an oxide layer with a thickness of 40 nm.
[0062] Please refer to Figure 3 , step S3: removing the oxide layer and the p-type layer 106 outside the gate region;
[0063] Specifically, an inductively coupled plasma etcher is used to etch away the oxide layer and the p-type layer 106 in the non-gate region to expose the barrier layer 105;
[0064] Please refer to Figure 4 Step S4: performing mesa etching from a portion of the barrier layer 105 downward to the buffer layer 103 , thereby forming a mesa on the surface of the buffer layer 103 ;
[0065] It can be understood that a patterned device mesa is obtained by a photolithography process and the mesa is isolated. The isolation method adopts etching mesa isolation, and then an inductively coupled plasma etcher is used to perform mesa etching on the thin film structure. Specifically, the mesa etching is performed from both sides of the barrier layer 105 downward to the buffer layer 103, thereby forming a mesa on the surface of the buffer layer 103;
[0066] Please refer to Figure 5 , step S5: depositing a source electrode and a drain electrode on the upper surface of the barrier layer 105 , thereby preparing a source ohmic contact electrode 201 and a drain ohmic contact electrode 202 on the barrier layer 105 ;
[0067] Specifically, the patterned source electrode and the drain electrode are obtained by photolithography, and the source electrode and the drain electrode are deposited on the upper surface of the barrier layer 105 and annealed, thereby preparing the source ohmic contact electrode 201 and the drain ohmic contact electrode 202 on the barrier layer 105;
[0068] The source electrode and the drain electrode are made of Ti / Al / Ni / Au.
[0069] Please refer to Figure 6 , step S6: depositing a gate electrode 203 on the upper surface of the oxide layer to obtain an enhancement-mode GaN HEMT device with the heterojunction gate.
[0070] Specifically, a patterned gate electrode 203 pattern is obtained by a photolithography process, and then the gate electrode 203 is deposited on the upper surface of the gallium oxide to obtain an enhanced GaN HEMT device with a heterojunction gate;
[0071] The gate electrode 203 is made of Ni / Au.
[0072] In summary, by oxidizing the surface of the p-type layer 106 to form an oxide layer, under normal circumstances, undoped gallium oxide and indium oxide are an n-type semiconductor, forming an n-type oxide layer, and then the n-type oxide layer and the p-type layer 106 form a heterogeneous p / n junction gate; when the depletion region extends to the p-side and the n-side, the pn junction can reduce the holes injected from the gate metal, and the pn junction reverse structure can withstand a larger reverse bias, so the heterogeneous p / n junction prepared by the method of the present invention can suppress the leakage path of the current from the gate to a greater extent compared with the Schottky junction formed by metal / p-GaN, effectively reduce the gate leakage of the device, and improve the gate breakdown voltage, thereby realizing a lateral GaN HEMT device with a high breakdown electric field capability; and the gallium oxide layer 107 can play a voltage divider role, further improving the threshold voltage of the GaN HEMT device.
[0073] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0074] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for preparing an enhanced-mode GaN HEMT device with a heterojunction gate, characterized in that: The following steps are involved: Step S1: providing a substrate layer, and sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure; Step S2: oxidizing the surface of the p-type layer to form an oxide layer; Step S3: removing the oxide layer and the p-type layer outside the gate region; Step S4: performing mesa etching extending downward from a portion of the barrier layer to the buffer layer, thereby forming a mesa on the surface of the buffer layer; Step S5: depositing a source electrode and a drain electrode on the upper surface of the barrier layer, thereby preparing a source ohmic contact electrode and a drain ohmic contact electrode on the barrier layer; Step S6: depositing a gate electrode on the upper surface of the oxide layer to obtain an enhancement-mode GaN HEMT device with the heterojunction gate.
2. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The step S1: providing a substrate, and sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure; wherein the thin film structure is grown by a metal organic chemical vapor deposition (MOCVD) method.
3. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The step S1: providing a substrate, and sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure; wherein the substrate layer is made of silicon or sapphire or silicon carbide or gallium nitride or diamond; the nucleation layer is made of AlN superlattice, the buffer layer is made of GaN or AlGaN; the channel layer is made of GaN or GaAs; the barrier layer is made of AlGaN or InAlN or AlN or InGaN; the p-type layer is made of any one or more combinations of GaN, AlGaN and InGaN.
4. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The step S1: providing a substrate, and sequentially growing a nucleation layer, a buffer layer, a channel layer, a barrier layer and a p-type layer on the substrate layer to form a thin film structure; wherein the thickness of the substrate layer is 0.5 mm to 2 mm, the thickness of the nucleation layer is 0.2 um to 1 um, the thickness of the buffer layer is 0.5 um to 2.5 um, the thickness of the channel layer is 100 nm to 300 nm, the thickness of the barrier layer is 10 nm to 30 nm, and the thickness of the p-type layer is 50 nm to 120 nm.
5. The method for preparing an enhanced GaN HEMT device according to claim 1, characterized in that: The step S2: oxidizing the surface of the p-type layer to form an oxide layer; wherein the surface of the p-type layer is subjected to oxygen-based plasma treatment using an inductively coupled plasma device to form the oxide layer.
6. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The step S2: oxidizing the surface of the p-type layer to form an oxide layer; wherein the oxide layer is made of gallium oxide or a mixture of gallium oxide and aluminum oxide or a mixture of gallium oxide and indium oxide; and the thickness of the oxide layer is 5 nm to 200 nm.
7. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The step S4: etching and removing from a portion of the barrier layer downward to the buffer layer, thereby forming a mesa on the surface of the buffer layer; wherein a patterned device mesa is obtained by a photolithography process and the mesa is etched, and the etching depth extends from a portion of the barrier layer downward to the buffer layer, thereby forming a mesa on the surface of the buffer layer.
8. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The step S5: depositing a source electrode and a drain electrode on the upper surface of the barrier layer, thereby preparing a source ohmic contact electrode and a drain ohmic contact electrode; wherein the patterned source electrode and the drain electrode are obtained by a photolithography process, and the source electrode and the drain electrode are deposited on the upper surface of the barrier layer and annealed, thereby preparing the source ohmic contact electrode and the drain ohmic contact electrode on the barrier layer.
9. The method for preparing an enhanced-mode GaN HEMT device according to claim 1, characterized in that: The step S6: depositing a gate electrode on the upper surface of the oxide layer to obtain the enhancement-mode GaN HEMT device with the heterojunction gate; wherein a patterned gate electrode pattern is obtained by a photolithography process, and then the gate electrode is deposited on the upper surface of the oxide layer to obtain the enhancement-mode GaN HEMT device with the heterojunction gate.