Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the semiconductor device. The present disclosure relates, inter alia, to MOSFET transistors. The semiconductor device according to the present disclosure comprises: a first conductivity type substrate; the first conductive type epitaxial layer comprises a JFET (Junction Field Effect Transistor) region and a second conductive type shielding region; two well regions, wherein the two well regions comprise two source electrode regions; a gate oxide including a gate electrode; the first conductive type substrate is adjacent to the first conductive type epitaxial layer, the two well regions are adjacent to the first conductive type epitaxial layer, the JFET region is located between the two well regions, the first conductive type substrate is adjacent to the first conductive type epitaxial layer, and the first conductive type substrate is adjacent to the first conductive type epitaxial layer. Wherein the source contact region is the outermost layer and is adjacent to the two source regions, and wherein the gate oxide is adjacent to the two well regions, the two source regions, and the JFET region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing semiconductor devices. In particular, the present disclosure relates to MOSFET transistors. Background Art

[0002] Transistors with gate oxides, such as metal oxide semiconductor field effect transistors (MOSFETs), may face the problem of electric field rise at the oxide. This is especially true for power MOSFETs that operate at high voltages, such as those made of silicon carbide. Under normal operating conditions, a high potential difference is created between the gate and drain terminals. If the electric field at the gate interface is too large, degradation or destruction of the oxide layer can occur, especially if there are defects in the oxide or the interface material. In such cases, the MOSFET may become useless because it cannot perform any switching action.

[0003] Document US9685550B2 discloses a device that may include a silicon carbide (SiC) device that may include a gate dielectric, a first doped region having a first conductivity type, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region has a first portion disposed between the first doped region and the body region, and the second doped region has a second portion disposed between the first doped region and the gate dielectric.

[0004] Document US9530844B2 discloses a transistor device with a reduced electric field at the gate oxide interface. In one embodiment, the transistor device includes a gate, a source and a drain, wherein the gate is at least partially in contact with the gate oxide. The transistor device has a P+ region in the JFET region of the transistor device to reduce the electric field on the gate oxide.

[0005] Document JP6338134B2 discloses a vertical MOSFET and a method for manufacturing the same, and more specifically, relates to a structure of a vertical MOSFET that achieves both improvement in device breakdown voltage and reduction in on-resistance and a method for manufacturing the same. Even when the impurity concentration of the drift layer of the silicon carbide vertical MOSFET increases, by generating a depletion layer at the junction surface between the drift layer as an n-type withstand voltage region and a high-concentration p-type layer, both improvement in element withstand voltage and reduction in on-resistance can be achieved simultaneously.

[0006] Document US9093493B2 discloses a wide bandgap insulated gate semiconductor device, which includes: a semiconductor substrate made of a semiconductor having a wider bandgap than silicon; an n-drift layer on the semiconductor substrate; a p-channel region selectively disposed on the drift layer; an n+ semiconductor region selectively disposed in a corresponding surface in the channel region; a plurality of p+ base regions in contact with the bottom of the corresponding channel region; a protruding drift layer portion, The protruding drift layer portion is an n-type region between a p-channel region and a p+ base region thereunder; a gate electrode formed on the protruding drift layer portion and on a corresponding surface of the p-channel region through a gate insulating film; a source electrode in contact with an n+ semiconductor region in the channel region; and a p+ floating region having side surfaces within the protruding drift layer portion that respectively face the side surfaces of the second conductive type base region, wherein a corresponding gap between the p+ base region and the p+ floating region defined by the corresponding side surfaces has a wide portion and a narrow portion.

[0007] In the prior art, a shielding region, also called a JFET region, is implanted between the wells of a transistor, either at the gate-insulator interface, or at the center or lower end of the region between the wells, but always at the same vertical space as the vertical space of the wells. In this invention, the shielding region is located below the wells in the vertical direction, but is still between the wells from a horizontal perspective. In other words, the shielding region is located below the JFET region.

[0008] Therefore, it is an object of the present disclosure to provide an improved MOSFET transistor in which the electric field near the gate oxide interface is reduced by creating a shielding region below the JFET region located between the well regions. In order to fully utilize the shielding potential, the shielding region should be connected to the source terminal at the depth of the semiconductor. The oxide is susceptible to electric fields, and the reduction / avoidance of electric fields in the oxide does not affect the JFET. Summary of the invention

[0009] According to a first example of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first conductive type substrate; a first conductive type epitaxial layer, the first conductive type epitaxial layer includes a JFET region and a second conductive type shielding region; two well regions, the two well regions include two source regions; a gate oxide, the gate oxide includes a gate; a drain, the drain is adjacent to the first conductive type substrate. The first conductive type substrate is adjacent to the first conductive type epitaxial layer. The two well regions are adjacent to the first conductive type epitaxial layer. The JFET region is located between the two well regions. The source contact region is adjacent to the two source regions. The gate oxide is adjacent to the two well regions, the two source regions, and the JFET region.

[0010] Preferably, the second conductivity type shielding region is located at a deeper depth than or at the same depth as a lower edge of the well region, and at least a portion of the second conductivity type shielding region overlaps the JFET region.

[0011] Preferably, the distance from the second conductive type shielding region to each of the two well regions is the same.

[0012] Preferably, the first conductivity type epitaxial layer includes a second first conductivity type layer such that at least the JFET region, and preferably the second conductivity type shielding region, is located within the second first conductivity type layer. The second first conductivity type layer has a higher dopant concentration than the first conductivity type epitaxial layer.

[0013] Preferably, the second conductivity type shielding region includes two types of dopants.

[0014] Preferably, the second conductivity type shielding region is doped to the same doping concentration as the well region.

[0015] Preferably, the second conductivity type shielding region is doped such that it has a higher doping concentration than the well region.

[0016] Preferably, the edge of the second conductivity type shielding area is rounded.

[0017] Preferably, at least one end of the second conductivity type shielding region is connected to the well region. Even more preferably, both ends of the second conductivity type shielding region are connected to the well region.

[0018] According to a second example of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes the steps of: a) depositing a first conductive type epitaxial layer on top of a first conductive type substrate, b) depositing a scattering oxide layer on top of the first conductive type epitaxial layer, c) creating a first mask on top of the scattering oxide layer, d) creating a second conductive type shielding region in the first conductive type epitaxial layer by first implantation of a second conductive type dopant through the first mask, e) removing the first mask, f) creating a second mask above the second conductive type shielding region, g) creating a well region by second implantation of a second conductive type dopant through the second mask, h) creating a third mask wider than the second mask, i) creating a source region by second implantation of a first conductive type dopant through the third mask.

[0019] Preferably, after step b), a second first conductivity type layer is created by a first implantation of a first conductivity type dopant on the first conductivity type epitaxial layer.

[0020] Preferably, during step h), a third mask is created by adding spacers to the second mask.

[0021] Preferably, after step g), a fourth mask is placed over the well region and a third implantation of a second conductivity type dopant is performed such that a connection is created between the well region and the second conductivity type shielding region. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present disclosure will now be discussed with reference to the accompanying drawings, which show:

[0023] Figure 1 shows a cross section of a semiconductor device before applying a first mask,

[0024] Figure 2 shows a cross section of a semiconductor device with a first mask applied,

[0025] Figure 3 shows a cross section of a semiconductor device during creation of a shielding region,

[0026] Figure 4 shows a cross section of a semiconductor device with a second mask applied,

[0027] Figure 5 A cross section of a semiconductor device is shown during creation of a well region.

[0028] Figure 6 shows a top view of a semiconductor device,

[0029] Figure 7a , Figure 7b , Figure 7cshows a cross section of a semiconductor device - in different variants such as Figure 6 The cross section A shown,

[0030] Figure 8a , Figure 8b , Figure 8c shows a cross section of a semiconductor device - in different variants such as Figure 6 The cross section B shown,

[0031] Figure 8d It shows that Figure 8b and Figure 8c The method for manufacturing the semiconductor device shown,

[0032] Fig. 9 shows a cross section of a semiconductor device with a third mask applied,

[0033] Fig.10 shows a cross section of a semiconductor device during creation of a source region,

[0034] Fig.11 A cross section of a finished semiconductor device is shown. DETAILED DESCRIPTION

[0035] For proper understanding of the present disclosure, in the following detailed description, corresponding elements or portions of the present disclosure will be denoted by the same reference numerals in the accompanying drawings.

[0036] As briefly described, the method for manufacturing a semiconductor device according to the present invention will include the following steps, which will be described in more detail below. The method includes the steps of:

[0037] a) depositing a first conductivity type epitaxial layer 2 on top of a first conductivity type substrate 1,

[0038] b) depositing a scattering oxide layer 4 on top of the first conductivity type epitaxial layer 2,

[0039] c) creating a first mask 6 on top of the scattering oxide layer 4,

[0040] d) creating a second conductivity type shielding region 7 in the first conductivity type epitaxial layer 2 by a first implantation 14 of a first conductivity type dopant via a first mask 6,

[0041] e) removing the first mask 6,

[0042] f) creating a second mask 8 over the second conductivity type shielding region 7,

[0043] g) creating a well region 10 by a second implantation 9 of a dopant of a second conductivity type via a second mask 8,

[0044] h) creating a third mask 12 wider than the second mask 8,

[0045] i) Creating source regions 15 by a second implantation 13 of a dopant of the first conductivity type through a third mask 12 .

[0046] The first step of manufacturing a semiconductor device according to the present invention is not shown in the figure because these steps are the same as those in the prior art method. A first conductive type substrate 1 is used as a substrate, and a first conductive type epitaxial layer 2 is deposited on the substrate, which layer is used as a drift layer of the semiconductor device. Next, a scattering oxide layer 4 is deposited on top of the first conductive type epitaxial layer 2 to improve the subsequent injection method. It should be noted that the scattering oxide layer 4 is only necessary for the manufacturing method. The final structure will not have a scattering oxide layer 4.

[0047] It should be noted that throughout the entire description, the terms "first conductivity type" and "second conductivity type" will be used. Because the semiconductor device will have regions made of a semiconductor (usually silicon or germanium) doped with impurities for the purpose of adjusting the properties of the semiconductor. Since the impurities mentioned provide electrons (the impurities are donors) or holes (the impurities are acceptors), these regions are often referred to as n-type regions or p-type regions. In this description, it should be understood that where the first conductivity type may mean p-type, the second conductivity type will be n-type. The present invention will also work in the opposite manner. The applicant does not wish to focus on the exact type of region, but rather on the overall idea behind the present invention.

[0048] exist Figure 1 In the figure, an additional step of a surface-wide first implantation 5 of a first conductivity type is shown, which forms a second first conductivity type layer 3 within the first conductivity type epitaxial layer 2, which will modify the JFET region 11. The first implantation 5 can be shallower or deeper than the subsequent second implantation 9 of a second conductivity type dopant, which will form the well region 10. In the following illustrations, a deeper variant is shown.

[0049] exist Figure 2 In FIG. 5 , the final effect of the next step is shown, which forms the first mask 6. It should be noted that there are gaps between the first masks 6. It should also be noted that in practice there may be gaps such as Figure 6 A single first mask 6 is shown, and throughout the description, the plural form will be used when referring to other figures.

[0050] exist Figure 3In the figure, a first implantation 14 of a second conductivity type dopant is shown. Through a first mask 6, an implantation of a second conductivity type shielding region 7 is performed, effectively creating a deep region of the second conductivity type. To this end, the doping concentration created by the first implantation 14 of a second conductivity type dopant must overcome the doping concentration of the background doping of the first conductivity type epitaxial layer 2. If a surface-wide first implantation 5 has been performed, the doping concentration by the first implantation 14 of a second conductivity type dopant must overcome the doping concentration of the surface-wide first implantation 5.

[0051] The purpose of the second conductivity type shielding region 7 is that it will reduce the electric field at the gate insulator interface at the finished transistor. The deeply implanted region below the gate, here the second conductivity type shielding region 7, shields the gate from elevated electric fields that could potentially cause its degradation or destruction.

[0052] exist Figure 4 , the final effect of the next step is shown, which forms a second mask 8. After removing the first mask 6 on the scattering oxide layer 4, the second mask 8 is created. The second mask 8 is located above the previously implanted second conductivity type screening areas 7.

[0053] exist Figure 5 , a second implantation 9 of a second conductivity type dopant is shown. After this step, well regions 10 will be formed. The second conductivity type well regions 10 are implanted in such a way that they are not as deep as the second conductivity type shielding regions 7. The area between the well regions 10 is called a JFET region 11. Any portion below the bottom of the second conductivity type well region 10 is no longer a JFET region 11.

[0054] exist Figure 6 , a top view of the semiconductor device after a second implantation 9 of a second conductivity type dopant is shown. The two cross sections A and B are respectively Figure 7a , Figure 7b , Figure 7c and Figure 8a , Figure 7b , Figure 7c In order to fully utilize the shielding potential of the second conductive type shielding region 7, it should not be kept floating, but should be electrically connected to the source potential. To this end, the second conductive type shielding region 7 can be connected to the well region 10 at the depth of the semiconductor. One or both ends of the second conductive type shielding region 7 can be connected to the well region 10. It should be noted that different variations of the shielding region 7 can be used - in Figure 7a and Figure 7b In FIG. 1 , there is a shielding region 7 that is narrower than the JFET region 11 , wherein the top edge of the shielding region 7 is at a similar depth to the lower edge of the well region 10 . Figure 7a and Figure 7bIn the figure, the position of the shielding area 7 is Figure 7a and 7b It should be noted that the well region 10 must be deeper than before so that the well region 10 can connect to the shielding region 7. Figure 7c and Figure 8c In the shielded area 7 and Figure 7b and Figure 7c However, it is now longer than the JFET region 11. Figure 8d In the figure, it is shown that Figure 8b and Figure 8c . An additional mask, namely a fourth mask 19, is placed on the well region 10. At the desired location for the contact, in this example in the B cross section, a third implantation 20 of a second conductivity type dopant is performed so that both the well region 10 and the shielding region 7 are connected. After this step, the fourth mask 19 is removed.

[0055] exist Fig. 9 , the final effect of the next step is shown, which forms the third mask 12. It should be noted that preferably the third mask 12 is created by adding more spacers to the second mask 8, effectively resulting in a wider mask than the second mask 8.

[0056] exist Fig.10 In FIG. 1 , a second implantation 13 of a dopant of the first conductivity type is shown. This step results in the creation of a source region 15 .

[0057] The gate oxide, the terminal contacts at the gate / drain / source, the interlayer dielectric, metallization and passivation are then fabricated to complete the device, which is usually performed during the standard manufacturing process. These steps are not critical features of the device and are therefore not described in more detail, as those skilled in the art will know how to complete the product as described in this application.

[0058] During the above process, a semi-finished semiconductor device is manufactured, which includes: a first conductive type substrate 1; a first conductive type epitaxial layer 2, the first conductive type epitaxial layer including a JFET region 11 and a second conductive type shielding region 7; two well regions 10, the two well regions including two source regions 15; and a scattering oxide layer 4. The first conductive type substrate 1 is adjacent to the first conductive type epitaxial layer 2. The two well regions 10 are adjacent to the first conductive type epitaxial layer 2. The JFET region 11 is adjacent to the two well regions 10. The scattering oxide layer 4 is the outermost layer and is adjacent to the two source regions 15, the two well regions 10, and the JFET region 11.

[0059] The semiconductor device as a finished product includes: a first conductive type substrate 1; a first conductive type epitaxial layer 2, the first conductive type epitaxial layer including a JFET region 11 and a second conductive type shielding region 7; two well regions 10, the two well regions including two source regions 15; a gate oxide 17, the gate oxide including a gate 16; a drain 18, the drain being adjacent to the first conductive type substrate 1. The first conductive type substrate 1 is adjacent to the first conductive type epitaxial layer 2. The two well regions 10 are adjacent to the first conductive type epitaxial layer 2, and the JFET region 11 is located between the two well regions 10. The source contact region is adjacent to the two source regions 15. The gate oxide 17 is adjacent to the two well regions 10, the two source regions 15, and the JFET region 11.

[0060] In another embodiment, the second conductivity type shielding region 7 is narrower than the JFET region 11 .

[0061] The second conductive type shielding region 7 is located at a depth deeper than or at the same depth as the lower edge of the well region 10 , and at least a portion of the second conductive type shielding region 7 overlaps the JFET region 11 .

[0062] In yet another embodiment, the distance of the second conductivity type shielding region 7 to each of the two well regions 10 is the same.

[0063] As mentioned above, the first conductivity type epitaxial layer 2 may include a second first conductivity type layer 3 such that at least the JFET region 11 , and preferably the second conductivity type shielding region 7 is located within the second first conductivity type layer 3 , wherein the second first conductivity type layer 3 has a higher dopant concentration than the first conductivity type epitaxial layer 2 .

[0064] The semiconductor device manufactured as described above will have a second conductivity type shielding region 7 containing two types of dopants. However, it should be noted that other manufacturing steps can be taken and such a structure with two dopant types may not exist. Preferably, the second conductivity type shielding region 7 is doped to at least the same doping concentration as the well region 10, and even more preferably, the second conductivity type shielding region 7 is doped so that it has a higher doping concentration than the well region 10.

[0065] In another embodiment, the edges of the second conductivity type shielding area 7 are rounded - sharp edges would result in high electric fields which should be avoided.

[0066] If the second conductivity type shielding region 7 is too small, there may be no shielding effect (because the shielding range is smaller); and if it is too large, this may restrict current flow, which may be beneficial in certain kinds of protection elements, such as electrical fuses.

[0067] List of reference symbols used

[0068] 1 First conductivity type substrate

[0069] 2. First conductivity type epitaxial layer

[0070] 3 Second first conductivity type layer

[0071] 4 Scattering oxide layer

[0072] 5. First implantation of first conductivity type dopant

[0073] 6 First Mask

[0074] 7 Second conductivity type shielding area

[0075] 8 Second Mask

[0076] 9. Second implantation of second conductivity type dopant

[0077] 10-well area

[0078] 11JFET region

[0079] 12 The third mask

[0080] 13 Second implantation of first conductivity type dopant

[0081] 14 First implantation of second conductivity type dopant

[0082] 15 Source region

[0083] 16 Gate

[0084] 17 Gate Oxide

[0085] 18 Drain

[0086] 19 The Fourth Mask

[0087] 20 Third implantation of second conductivity type dopant

Claims

1. A semiconductor device, comprising: a first conductive type substrate (1), A first conductivity type epitaxial layer (2), the first conductivity type epitaxial layer comprising a JFET region (11) and a second conductivity type shielding region (7), two well regions (10), the two well regions including two source regions (15), a gate oxide (17), the gate oxide comprising a gate (16), a drain electrode (18), the drain electrode being adjacent to the first conductive type substrate (1), The first conductive type substrate (1) is adjacent to the first conductive type epitaxial layer (2), The two well regions (10) are adjacent to the first conductivity type epitaxial layer (2), wherein the JFET region (11) is located between the two well regions (10), wherein the source contact region is adjacent to the two source regions (15), The gate oxide (17) is adjacent to the two well regions (10), the two source regions (15) and the JFET region (11).

2. A semiconductor device according to claim 1, wherein the second conductive type shielding region (7) is located at a depth deeper than the lower edge of the well region (10) or at the same depth as the lower edge of the well region (10), and at least a portion of the second conductive type shielding region (7) overlaps with the JFET region (11).

3. The semiconductor device according to claim 1 or 2, wherein the distance from the second conductivity type shielding region (7) to each of the two well regions (10) is the same.

4. A semiconductor device according to any one of the preceding claims, wherein the first conductivity type epitaxial layer (2) includes a second first conductivity type layer (3), so that at least the JFET region (11), and preferably the second conductivity type shielding region (7), is located within the second first conductivity type layer (3), wherein the second first conductivity type layer (3) has a higher dopant concentration than the first conductivity type epitaxial layer (2).

5. The semiconductor device according to any of the preceding claims, wherein the second conductivity type screening region (7) comprises two types of dopants.

6. A semiconductor device according to any one of the preceding claims, wherein the second conductivity type shielding region (7) is doped to the same doping concentration as the well region (10).

7. The semiconductor device according to any one of claims 1 to 6, wherein the second conductivity type shielding region (7) is doped such that it has a higher doping concentration than the well region (10).

8. The semiconductor device according to any of the preceding claims, wherein the edges of the second conductivity type shielding region (7) are rounded.

9. A semiconductor device according to any one of the preceding claims, wherein at least one end of the second conductive type shielding region (7) is connected to the well region (10), and preferably both ends of the second conductive type shielding region (7) are connected to the well region (10).

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, comprising the steps of: a) depositing a first conductivity type epitaxial layer (2) on top of a first conductivity type substrate (1), b) depositing a scattering oxide layer (4) on top of the first conductivity type epitaxial layer (2), c) creating a first mask (6) on top of said scattering oxide layer (4), d) creating a second conductivity type shielding region (7) in the first conductivity type epitaxial layer (2) by a first implantation (5) of a second conductivity type dopant via the first mask (6), e) removing the first mask (6), f) creating a second mask (8) above the second conductivity type shielding area (7), g) creating a well region (10) by a second implantation (9) of a dopant of a second conductivity type through said second mask (8), h) creating a third mask (12) wider than said second mask (8), i) Creating a source region (15) by a second implantation (13) of a dopant of the first conductivity type through said third mask (15).

11. The method according to claim 10, wherein after step b), a second first conductivity type layer (3) is created by a first implantation (5) of a first conductivity type dopant on the first conductivity type epitaxial layer (2).

12. Method according to claim 10 or 11, wherein during step h) the third mask (12) is created by adding spacers to the second mask (8).

13. A method according to any one of claims 10-12, wherein after step g), a fourth mask (19) is placed on the well region (10) and a third implantation (20) of a second conductive type dopant is performed to create a connection between the well region (10) and the second conductive type shielding region (7).

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