Enhanced GaN-based HEMT (High Electron Mobility Transistor) device with oxygen-rich vacancy gate dielectric matched with fluorine ion implantation and

Abstract

The invention discloses an enhanced GaN-based HEMT (High Electron Mobility Transistor) device with oxygen-rich vacancy gate dielectric matched with fluorine ion implantation and a preparation method thereof. The device comprises an AlGaN / GaN heterojunction epitaxial layer, a source electrode, a drain electrode, an oxygen-vacancy-rich gate dielectric passivation layer and a gate electrode. The barrier layer of the device is provided with a gate region with a certain etching depth, thereby promoting the realization of enhanced performance. The gate dielectric passivation layer is located on the barrier layer, and fluorine ions are injected into the gate dielectric passivation layer and do not appear in the barrier layer. According to the invention, the thickness of the gate dielectric passivation layer can be effectively reduced, and the negative drift of the threshold voltage caused by the reverse polarization effect brought by the thick gate dielectric passivation layer is reduced; oxygen vacancies and fluorine ions can be better combined, the positions of the fluorine ions are limited, the influence of fluorine ion electromigration is reduced, and the stability of the device is improved; the introduction of fluorine ions can reduce dangling bonds in the gate dielectric, repair a leakage channel in the gate dielectric, and further improve the reliability of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to an enhanced GaN-based HEMT device with oxygen-vacancy-rich gate dielectric combined with fluorine ion implantation and a preparation method thereof. Background Art

[0002] Due to its unique lateral structure and polarization effect, GaN-based HEMT can form a layer of high-concentration, high-mobility two-dimensional electron gas on the barrier layer side of its channel layer, allowing HEMT devices to be used in high-current situations. With the development of electronic circuits, enhanced (normally closed) HEMTs have become a development trend. The number of devices controlling the switch at the front end has been reduced, and a single enhanced HEMT device switch can be controlled simply by changing the voltage applied to the gate. The circuit has been greatly simplified and the manufacturing cost can be further reduced. At present, gate groove devices are the mainstream of enhanced devices. However, in order to achieve a higher threshold voltage, the barrier layer under the gate needs to be etched to a greater depth, which greatly weakens the polarization effect and damages the conductive channel. While the device obtains a higher threshold voltage, the on-current drops severely, affecting the use of the device in the circuit.

[0003] In order to reduce the damage to the barrier layer, a solution of injecting fluorine ions into the gate dielectric on the barrier layer has been proposed to solve the problem of severe on-current drop. However, the introduction of fluorine ions brings new problems. In order to increase the threshold voltage, the fluorine ion concentration in the gate dielectric needs to be increased, but too many fluorine ions will diffuse into the barrier layer, aggravating the phonon scattering effect and weakening the on-current. Therefore, the gate dielectric needs to be thicker to prevent the diffusion of fluorine ions. Currently, SiNx is the mainstream gate dielectric passivation layer material. This material will exert tensile stress on the barrier layer and increase the polarization effect. As the thickness increases, the threshold voltage also drifts negatively, which is not conducive to the preparation of enhanced devices (S.Dinara, et al,"Enhancement oftwo dimensionalelectron gas concentrations due to Si3N4 passivation on Al 0.3 Ga 0.7 N / GaN heterostructure: strain and interface capacitance analysis,"AIPAdv.,APR2015,). In addition, fluorine ions are unstable in the gate dielectric and will migrate with the switching of the device and the application of voltage, causing the threshold voltage to change, hindering the application of the device in the circuit. Therefore, a suitable thin gate dielectric passivation layer is required to have a large number of positions to capture fluorine ions, while increasing the fluorine ion concentration and increasing the confinement of fluorine ions to improve the stability of the device. Summary of the invention

[0004] Based on this, the present invention proposes an enhanced GaN-based HEMT device with oxygen-rich vacancy gate dielectric and fluorine ion implantation. By selecting an optimized oxygen-rich vacancy gate dielectric and implanting fluorine ions after appropriate annealing, high-concentration fluorine ions are effectively captured without increasing the polarization effect and degrading the threshold voltage, thereby realizing an enhanced GaN-based HEMT device with high on-current.

[0005] The purpose of the present invention is achieved by at least one of the following technical solutions.

[0006] An enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation, comprising a substrate, a buffer layer, a channel layer, a barrier layer and a gate dielectric passivation layer from bottom to top;

[0007] The barrier layer below the gate is provided with an etching region of a certain depth. The gate dielectric passivation layer is an oxide layer rich in oxygen vacancies, and the fluorine ion implantation region is in the gate dielectric passivation layer below the gate.

[0008] Furthermore, the gate dielectric passivation layer is an oxide rich in oxygen vacancies, including but not limited to Hf x Zr 1-x One or more oxides such as O2, Al2O3, SrTiO3, BiFeO3, etc.

[0009] Furthermore, the enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation is characterized in that the gate dielectric passivation layer is a single-layer or multi-layer structure with a total thickness of 5-20 nm.

[0010] Furthermore, the oxygen vacancy rich gate dielectric passivation layer needs to be annealed after deposition, with the annealing temperature being 300° C.-500° C. and the time being 30 s-20 min.

[0011] Furthermore, reactive ion etching (RIE) equipment is used to perform fluorine ion implantation, with a radio frequency power greater than 90 W and a processing time greater than 90 seconds.

[0012] Furthermore, the fluorine ion implantation gas used is one or both of CF4 and CH3F, and the flow rate is greater than 20 sccm.

[0013] Furthermore, the substrate (101) is silicon; and the buffer layer (102) is C- or Fe-doped GaN.

[0014] Furthermore, the channel layer (103) is GaN, and the barrier layer (104) is AlGaN or AlN. The thickness of the barrier layer is 12-30 nm, and the depth of the etching area under the gate is less than half of the thickness of the barrier layer.

[0015] The present invention can effectively reduce the thickness of the gate dielectric passivation layer, reduce the reverse polarization effect caused by the thick gate dielectric passivation layer to cause the threshold voltage to drift negatively; oxygen vacancies and fluorine ions can be better combined, the position of fluorine ions is restricted, the influence of fluorine ion electromigration is reduced, and the stability of the device is improved; the introduction of fluorine ions can reduce dangling bonds in the gate dielectric, repair the leakage channel in the gate dielectric, and further improve the reliability of the device.

[0016] The method of an enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation comprises the following steps:

[0017] S1. Using etching isolation to remove the barrier layer (104) and the channel layer (103) in the heterojunction to form an independent active area, wherein the etching depth is greater than the thickness of the barrier layer and the channel layer.

[0018] S2, removing part of the barrier layer (104) below the gate by etching, wherein the depth of the etching area is less than half of the thickness of the barrier layer;

[0019] S3, defining the metal position and pattern of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 500°C-800°C in a vacuum or nitrogen atmosphere to form ohmic contacts between the source and drain electrodes and the barrier layer;

[0020] S4, depositing a gate dielectric passivation layer (105) rich in oxygen vacancies by electron beam evaporation or magnetron sputtering, and annealing at 300° C.-500° C. in a nitrogen atmosphere to rearrange the oxygen vacancies in the material to facilitate the combination with the implanted fluorine ions;

[0021] S5, using a reactive ion etching (RIE) device to perform fluorine ion implantation, wherein the implantation region is the gate dielectric passivation layer at the gate etching location;

[0022] S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

[0023] Compared with the prior art, the present invention has the following beneficial effects and advantages:

[0024] The present invention adopts a method of combining an oxygen vacancy-rich gate dielectric with fluorine ion implantation to realize the preparation of an enhanced GaN-based HEMT device, uses an oxygen vacancy-rich gate dielectric passivation layer to replace conventional SiNx, allows fluorine ions to combine with a large number of oxygen vacancies in the gate dielectric, and can achieve high-concentration fluorine ion implantation in a relatively thin gate dielectric, greatly enhancing the threshold voltage and maintaining a high on-current; at the same time, the fluorine ions are more stable after combining with the oxygen vacancies, inhibiting the migration effect of the fluorine ions under the action of voltage and reducing the threshold voltage variation; furthermore, the preparation instrument involved in the present invention is a conventionally used instrument with strong applicability, and the thinning of the gate dielectric can reduce material and time costs at the same time, thereby enhancing the practicality of the enhanced device in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of an enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation provided in an embodiment;

[0026] Figure 2 These are experimental test transfer curves of enhanced-mode GaN-based HEMT devices corresponding to the control group, Example 1 and Example 2 with oxygen-vacancy-rich gate dielectrics combined with fluorine ion implantation.

[0027] Figure 3 It is an experimental continuous test threshold voltage diagram of the enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation corresponding to the control group, Example 1 and Example 2. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0029] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0030] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0031] Embodiment 1:

[0032] In this embodiment, an enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation includes, from bottom to top, a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104 and a gate dielectric passivation layer 105, wherein the barrier layer has a thickness of 25 nm and the channel layer has a thickness of 200 nm;

[0033] The barrier layer below the gate is provided with an etching region of a certain depth. The gate dielectric passivation layer 105 is an oxide layer rich in oxygen vacancies, and the fluorine ion implantation region is in the gate dielectric passivation layer 105 below the gate.

[0034] S1. The barrier layer 104 and the channel layer 103 in the heterojunction are removed by etching isolation to form an independent active region. The etching depth is 400 nm, which is greater than the thickness of the barrier layer and the channel layer.

[0035] S2, removing part of the barrier layer 104 below the gate by etching, the depth of the etching area is 10 nm, which is less than half of the thickness of the barrier layer;

[0036] S3, defining the metal positions and patterns of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 550° C. in a nitrogen atmosphere to form ohmic contacts between the source and drain electrodes and the barrier layer;

[0037] S4. Deposition of Hf with oxygen vacancies by electron beam evaporation or magnetron sputtering 0.75 Zr 0.25 O216nm is used as the gate dielectric passivation layer 105, and annealed at 400°C for 1 minute in a nitrogen atmosphere to rearrange the oxygen vacancies in the material, which is conducive to the combination with the implantation of fluorine ions;

[0038] S5, using reactive ion etching equipment (RIE) to perform fluorine ion implantation, the implantation area is the gate dielectric passivation layer at the gate etching location, the RF power is 110 W, the processing time is 100 s, and the processing gas is CF4;

[0039] S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

[0040] Embodiment 2:

[0041] In this embodiment, an enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation includes, from bottom to top, a substrate 101, a buffer layer 102, a channel layer 103, a barrier layer 104 and a gate dielectric passivation layer 105, wherein the barrier layer has a thickness of 25 nm and the channel layer has a thickness of 200 nm;

[0042] The barrier layer below the gate is provided with an etching region of a certain depth. The gate dielectric passivation layer 105 is an oxide layer rich in oxygen vacancies, and the fluorine ion implantation region is in the gate dielectric passivation layer 105 below the gate.

[0043] S1. The barrier layer 104 and the channel layer 103 in the heterojunction are removed by etching isolation to form an independent active region. The etching depth is 400 nm, which is greater than the thickness of the barrier layer and the channel layer.

[0044] S2, removing part of the barrier layer 104 below the gate by etching, the depth of the etching area is 10 nm, which is less than half of the thickness of the barrier layer;

[0045] S3, defining the metal positions and patterns of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 550° C. in a nitrogen atmosphere to form ohmic contacts between the source and drain electrodes and the barrier layer;

[0046] S4. Deposition of Hf with oxygen vacancies by electron beam evaporation or magnetron sputtering 0.75 Zr 0.25 O216nm is used as the gate dielectric passivation layer 105, and annealed at 500°C for 1 minute in a nitrogen atmosphere to rearrange the oxygen vacancies in the material, which is conducive to the combination with the implantation of fluorine ions;

[0047] S5. Perform fluorine ion implantation using a reactive ion etching device (RIE), the implantation area is the gate dielectric passivation layer at the gate etching location, the RF power is 110 W, the processing time is 100 s, and the processing gas is CF4;

[0048] S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

[0049] Figure 2, which are experimental test transfer curves corresponding to the control group, Example 1 and Example 2, wherein the control group uses a gate dielectric passivation layer without fluorine ion implantation and annealing, and all other processes are consistent with the processes in Example 1 and Example 2, and the thickness of the gate dielectric passivation layer is also consistent; there is no other difference between Example 1 and Example 2 except that the annealing temperature of the gate dielectric passivation layer is different; Figure 2 It can be seen that compared with the control group, the threshold voltages of Examples 1 and 2 are both positively shifted, the current does not drop sharply, and the threshold voltage of Example 2 is larger than that of Example 1. This shows that the increase in annealing temperature can effectively increase the oxygen vacancies in the gate dielectric, making it easier to capture more fluorine ions, thereby increasing the threshold voltage. And with the injection of fluorine ions, the device changes from a near-enhancement device to a true enhancement device, and the threshold voltage is much greater than zero.

[0050] Figure 3 3 is an experimental continuous test threshold voltage diagram of an enhanced GaN-based HEMT device with oxygen-rich vacancy gate dielectric and fluorine ion implantation corresponding to the control group, Example 1 and Example 2, wherein the control group uses a gate dielectric passivation layer without fluorine ion implantation and annealing, and all other processes are consistent with those in Example 1 and Example 2, and the thickness of the gate dielectric passivation layer is also consistent; there is no other difference between Example 1 and Example 2 except that the annealing temperature of the gate dielectric passivation layer is different; from Figure 3 It can be seen that compared with the control group, the threshold voltage after fluoride ion injection in Example 1 and Example 2 can remain equally stable, which means that the fluoride ions can be effectively confined in the oxygen-rich vacancy gate dielectric, and the device performance does not deteriorate with the increase in the number of device switching times. The device has strong stability and the circuit is highly practical.

[0051] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should be included in the scope of the claims of the present invention.

Claims

1. An enhanced GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation, comprising, from bottom to top, a substrate (101), a buffer layer (102), a channel layer (103), a barrier layer (104) and a gate dielectric passivation layer (105); in, An etching region is provided in the barrier layer below the gate; the gate dielectric passivation layer (105) is an oxide layer rich in oxygen vacancies, and the fluorine ion implantation region is in the gate dielectric passivation layer (105) below the gate.

2. The enhanced-mode GaN-based HEMT device with oxygen-vacancy-rich gate dielectric and fluorine ion implantation according to claim 1, characterized in that: The gate dielectric passivation layer is an oxide rich in oxygen vacancies, including but not limited to Hf x Zr 1-x One or more of O2, Al2O3, SrTiO3, and BiFeO3 oxides.

3. The enhanced-mode GaN-based HEMT device with oxygen-vacancy-rich gate dielectric and fluorine ion implantation according to claim 2, characterized in that: The gate dielectric passivation layer is a single-layer or multi-layer structure with a total thickness of 5-20nm.

4. The enhanced-mode GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation according to claim 2, characterized in that: The oxygen vacancy rich gate dielectric passivation layer needs to be annealed after deposition, with the annealing temperature being 300° C.-500° C. and the time being 30s-20min.

5. The enhanced-mode GaN-based HEMT device with oxygen-vacancy-rich gate dielectric and fluorine ion implantation according to claim 1, characterized in that: Fluoride ion implantation is performed using reactive ion etching equipment, with a radio frequency power greater than 90 W and a processing time greater than 90 seconds.

6. The enhanced-mode GaN-based HEMT device with oxygen-vacancy-rich gate dielectric and fluorine ion implantation according to claim 5, characterized in that: The fluorine ion implantation gas used is one or both of CF4 and CH3F, and the flow rate is greater than 20 sccm.

7. The enhanced-mode GaN-based HEMT device with oxygen-vacancy-rich gate dielectric and fluorine ion implantation according to claim 1, characterized in that: The substrate (101) is silicon; the buffer layer (102) is C- or Fe-doped GaN.

8. The enhanced-mode GaN-based HEMT device with oxygen-vacancy-rich gate dielectric and fluorine ion implantation according to claim 1, characterized in that: The channel layer (103) is GaN; the barrier layer (104) is AlGaN or AlN.

9. The enhanced-mode GaN-based HEMT device with oxygen vacancy-rich gate dielectric and fluorine ion implantation according to claim 1, characterized in that: The thickness of the barrier layer is 12-30 nm, and the depth of the etching area under the gate is less than half of the thickness of the barrier layer.

10. A method for preparing an enhanced-mode GaN-based HEMT device with oxygen-vacancy-rich gate dielectric combined with fluorine ion implantation as claimed in any one of claims 1 to 9, characterized in that: The steps include: S1, using etching isolation to remove the barrier layer (104) and the channel layer (103) in the heterojunction to form an independent active area, wherein the etching depth is greater than the thickness of the barrier layer and the channel layer; S2, removing part of the barrier layer (104) below the gate by etching, wherein the depth of the etching area is less than half of the thickness of the barrier layer; S3, defining the metal position and pattern of the source and drain electrodes on the active area by photolithography, and depositing the source and drain electrode films by electron beam evaporation or magnetron sputtering; performing rapid metal annealing at a temperature of 500°C-800°C in a vacuum or nitrogen atmosphere to form ohmic contacts between the source and drain electrodes and the barrier layer; S4, depositing a gate dielectric passivation layer (105) rich in oxygen vacancies by electron beam evaporation or magnetron sputtering, and annealing at 300° C.-500° C. in a nitrogen atmosphere to rearrange the oxygen vacancies in the material to facilitate the combination with the implanted fluorine ions; S5, using a reactive ion etching (RIE) device to perform fluorine ion implantation, wherein the implantation region is the gate dielectric passivation layer at the gate etching location; S6. Remove the gate dielectric passivation layer in the source and drain electrode regions to expose the source and drain electrode metals, and deposit a gate electrode film by electron beam evaporation or magnetron sputtering.

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