A method for depositing a stress medium layer in a trench and a shallow trench isolation structure

Abstract

The present application discloses a method for depositing a stress medium layer in a trench and a shallow trench isolation structure. The method includes: a first deposition process, based on a set first deposition thickness, depositing a first dielectric layer in a first trench by using the HARP process; a first plasma process, based on a set first plasma process power and a first plasma process time, performing a first plasma process on the entire film layer of the first dielectric layer by using a plasma containing an inert gas, wherein the first deposition thickness does not exceed the treatment depth of the first plasma process; based on a set first number of cycles, repeatedly performing the first deposition process and the first plasma process for multiple cycles until the first trench is filled, so as to form a compressive stress medium layer in the first trench. Compared with the prior art, the unexpected technical effect of the present application is that a dielectric layer with different stresses, especially a compressive stress dielectric layer, can be selectively deposited in the trench as needed.

Description

Technical Field

[0001] This application generally relates to the technical field of shallow trench isolation structure fabrication. More specifically, this application relates to a method for depositing a stress medium layer in a trench and a shallow trench isolation structure. Background Art

[0002] When fabricating metal-oxide-semiconductor (MOS) devices, introducing stress engineering is an important technical means to improve device performance. Stress engineering can affect the mobility of carriers by introducing stress in specific regions of a transistor, thereby improving the electrical characteristics of the transistor. Specifically, tensile stress can be introduced in the NMOS region. In an NMOS transistor, electrons are the main carriers, and tensile stress can increase the mobility of electrons. Correspondingly, compressive stress can be introduced in the PMOS region. In a PMOS transistor, holes are the main carriers, and compressive stress can increase the mobility of holes.

[0003] In semiconductor integrated circuit manufacturing processes, shallow trench isolation (STI) structures are typically used to isolate individual active regions. Therefore, it is desirable to use trench structures to selectively introduce different stresses into different regions.

[0004] For structures with a technology node of sub-45 nm and a large device aspect ratio, a deposition method called HARP (High Aspect Ratio Process) is typically used for trench filling. However, the filling ability of the HARP process is limited, and voids are likely to form.

[0005] In view of this, there is an urgent need to provide a preparation scheme for depositing a stress medium layer in a trench, so as to selectively deposit a medium layer with different stresses, especially a compressive stress medium layer, in the trench as needed. In addition, it is also desirable to reduce the generation of voids during the deposition process. Summary of the Invention

[0006] To at least solve one or more of the above-mentioned technical problems, this application proposes a preparation scheme for depositing a stress medium layer in a trench and a corresponding shallow trench isolation structure in multiple aspects.

[0007] In a first aspect, the present application provides a method for depositing a stress medium layer in a trench, including: a first deposition process of depositing a first medium layer in a first trench by using a HARP process based on a set first deposition thickness; a first plasma process of performing a first plasma process on the entire film layer of the first medium layer by using a plasma containing an inert gas based on a set first plasma process power and a first plasma process time, wherein the first deposition thickness of the first medium layer does not exceed the process depth of the first plasma process at the first plasma process power and the first plasma process time; and based on a set first number of cycles, repeatedly performing the first deposition process and the first plasma process for multiple cycles until the first trench is filled to form a compressive stress medium layer in the first trench.

[0008] In some embodiments, the compressive stress of the compressive stress medium layer is -100 MPa to -50 MPa.

[0009] In some embodiments, the method satisfies at least one of the following conditions: the first deposition thickness is 50 Å to 100 Å; the first plasma process power is 300 W to 500 W; the first plasma process time is 10 s to 15 s; the inert gas is Ar or He; the first number of cycles is 25 to 35; the chamber pressure of the first deposition process is 500 torr to 600 torr; and the chamber pressure of the first plasma process is 20 torr to 50 torr.

[0010] In some embodiments, the first trench is disposed in a region of a semiconductor structure for forming a PMOS device.

[0011] In some embodiments, the method further includes: a second deposition process of depositing a second medium layer in a second trench by using a HARP process based on a set second deposition thickness; a second plasma process of performing a second plasma process on the film surface of the second medium layer by using a plasma containing an inert gas based on a set second plasma process power and a second plasma process time, wherein the second deposition thickness of the second medium layer exceeds the process depth of the second plasma process at the second plasma process power and the second plasma process time; and based on a set second number of cycles, repeatedly performing the second deposition process and the second plasma process for multiple cycles until the second trench is filled to form a tensile stress medium layer in the second trench.

[0012] In some embodiments, the tensile stress of the tensile stress medium layer is 100 MPa to 150 MPa.

[0013] In some embodiments, the method satisfies at least one of the following conditions: the second deposition thickness is 150 Å to 200 Å; the second plasma treatment power is 150 W to 250 W; the second plasma treatment time is 5 s to 10 s; the inert gas is Ar or He; the second number of cycles is 10 to 20; the chamber pressure for the second deposition process is 500 torr to 600 torr; and the chamber pressure for the second plasma treatment is 20 torr to 50 torr.

[0014] In some embodiments, the second trench is disposed in a region of the semiconductor structure for forming an NMOS device.

[0015] In a second aspect, the present application provides a method for depositing a stress medium layer in a trench, including: providing a semiconductor structure having a first region and a second region thereon, the first region being for forming a PMOS device, and at least one first trench being in the first region, the second region being for forming an NMOS device, and at least one second trench being in the second region; forming a compressive stress medium layer or a tensile stress medium layer at least in the first trench of the first region and the second trench of the second region; removing the compressive stress medium layer in the second region or removing the tensile stress medium layer in the first region; forming a tensile stress medium layer in the second trench of the second region or forming a compressive stress medium layer in the first trench of the first region; wherein: the compressive stress medium layer is formed according to the formation method of the compressive stress medium layer in the foregoing first aspect.

[0016] In some embodiments, it further includes forming the tensile stress medium layer according to the formation method of the tensile stress medium layer in the foregoing first aspect.

[0017] In a third aspect, the present application provides a shallow trench isolation structure, and the dielectric layer in the trench of the shallow trench isolation structure is prepared by the preparation method described in any embodiment of the first aspect or the preparation method described in any embodiment of the second aspect.

[0018] Compared with the prior art, the unexpected technical effect of the present application is that different stress dielectric layers, especially compressive stress dielectric layers, can be selectively deposited in the trench as needed.

[0019] In the embodiments of the present application, a plasma treatment process is introduced into HARP, and a dielectric layer is deposited in the trench in a deposition-surface treatment cycle deposition mode. During the deposition process, different stress-performance dielectric layers can be obtained by setting / regulating the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment in each cycle, thereby improving the device performance. In particular, when forming a compressive stress dielectric layer, by performing multiple cycles of deposition-surface treatment, and the thickness of the deposited film layer in each deposition does not exceed the treatment depth of the plasma treatment, the entire film layer of the formed dielectric layer can be treated each time, rather than being limited to the surface of the dielectric layer. Therefore, this cycle treatment mode can change the stress of the dielectric layer to obtain a compressive stress dielectric layer. In addition, since the trench filling after plasma surface treatment reduces the occurrence of overhangs, this improves the filling ability of HARP, ensures that there are no holes in the trench, guarantees the stability of the product, and improves the product yield. Further, in some embodiments, different stress dielectric layers can be selectively deposited in the trenches in different regions (NMOS / PMOS regions), and the deposition of different stress dielectric layers and the plasma surface treatment can both be completed in the same machine tool. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present application will become readily understood. In the drawings, several embodiments of the present application are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0021] Figure 1A An exemplary flowchart showing a method for depositing a stress dielectric layer in a trench according to some embodiments of the present application;

[0022] Figure 1B An exemplary schematic diagram showing obtaining different stress performances by deposition-surface treatment according to the present application;

[0023] Figure 2A A schematic cross-sectional structure diagram showing the formation of a trench in a semiconductor structure according to some embodiments of the present application;

[0024] Figure 2B A schematic cross-sectional structure diagram showing the deposition of a dielectric layer according to some embodiments of the present application;

[0025] Figure 2C A schematic cross-sectional structure diagram showing the plasma treatment of a dielectric layer according to some embodiments of the present application;

[0026] Figure 2D A schematic cross-sectional structure diagram showing the formation of a stress dielectric layer according to some embodiments of the present application;

[0027] Figure 2EShows a schematic cross-sectional structure of planarizing a stress medium layer in some embodiments of the present application;

[0028] Figure 3 Shows an exemplary flowchart of a method for depositing a stress medium layer in a trench in some other embodiments of the present application;

[0029] Figure 4A Shows a schematic cross-sectional structure of providing a semiconductor structure having a first region and a second region in some other embodiments of the present application;

[0030] Figure 4B Shows a schematic cross-sectional structure of forming a first stress medium layer in some other embodiments of the present application;

[0031] Figure 4C Shows a schematic cross-sectional structure of forming a photoresist above the first stress medium layer in some other embodiments of the present application;

[0032] Figure 4D Shows a schematic cross-sectional structure of dissolving the photoresist in the second region in some other embodiments of the present application;

[0033] Figure 4E Shows a schematic cross-sectional structure of removing the first stress medium layer in the second region and the remaining photoresist layer in some other embodiments of the present application;

[0034] Figure 4F Shows a schematic cross-sectional structure of forming a second stress medium layer in some other embodiments of the present application;

[0035] Figure 4G Shows a schematic cross-sectional structure of planarizing the first stress medium layer and the second stress medium layer in some other embodiments of the present application;

[0036] Figure 5 Shows a schematic diagram of the influence of plasma treatment power and number of cycles on the stress performance of the dielectric layer. Detailed Description of the Invention

[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0038] It should be understood that the terms "comprising" and "including" as used in the specification and claims of this application indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0039] It should also be understood that the terms used in the specification of this application are merely for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification and claims of this application, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" as used in the specification and claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0040] It should also be understood that, for ease of description, spatial relative terms such as "below", "beneath", "under", "above", "on", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. When an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0041] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] The embodiments of this application provide a preparation scheme for depositing a stress medium layer in a trench. By introducing a plasma treatment process in HARP, a dielectric layer is deposited in the trench in a deposition-surface treatment cycle deposition mode. During the deposition process, different stress performance dielectric layers can be obtained by adjusting the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment in each cycle, thereby improving the device performance.

[0043] Figure 1A An exemplary flowchart of method 100 for depositing a stress medium layer in a trench according to some embodiments of this application is shown.

[0044] As Figure 1AAs shown, in step S110, a dielectric layer is deposited in the trench using the HARP process based on the set deposition thickness. Next, in step S120, the aforementioned dielectric layer is processed using a plasma containing an inert gas based on the set plasma processing power and plasma processing time. Then, in step S130, based on the set number of cycles, the steps of depositing the dielectric layer and the plasma processing step are cycled multiple times until the aforementioned trench is filled, and a stress dielectric layer is formed in the aforementioned trench. The stress performance of the stress dielectric layer can be controlled by adjusting the deposition thickness, plasma processing power, plasma processing time, and number of cycles in a single cycle.

[0045] Figure 1B FIG. shows an exemplary schematic diagram of obtaining different stress performances through deposition - surface treatment in the present application.

[0046] As Figure 1B shown in S140, first, using the HARP process, an oxide dielectric layer 112, such as silicon oxide SiO 2 . is deposited on the substrate 111 (such as a silicon substrate) at a high temperature. Then, as shown in S150, the HARP oxide dielectric layer is processed using a plasma containing an inert gas such as Ar. As shown by the arrows, the aforementioned deposition - plasma processing process is cycled multiple times.

[0047] The HARP deposition oxide process itself is a pure thermal process. The HARP oxide itself contains more groups: -CH3, -OH, etc., and is relatively loose. When the thickness of the dielectric layer deposited in a single cycle is relatively thick, for example, exceeding the processing depth of the subsequent plasma processing, the plasma processing only affects the surface structure of the dielectric layer film, and the bottom layer of the film is still relatively loose. In this way, when the device comes out of the high - temperature environment, compared with the substrate, the HARP oxide will shrink more, thus showing tensile stress (as shown by 160 in the figure).

[0048] The inventors found that if the thickness of the dielectric layer deposited in a single cycle is very thin, for example, not exceeding the processing depth of the subsequent plasma processing, when the dielectric layer is subjected to high - power and long - time plasma processing, the entire film layer of the dielectric layer can be processed, that is, the entire film layer becomes dense, not limited to the surface of the film layer. By cyclically performing this deposition of a thin film layer, high - power, and long - time plasma processing, each time the groups in the oxide dielectric layer are removed, making the entire dielectric layer denser after multiple cycles. In this way, when the device returns from the high - temperature environment to room temperature again, the dielectric layer shrinks less compared with the substrate, that is, the coefficient of thermal expansion is smaller, thus showing compressive stress (as shown by 170 in the figure).

[0049] Based on the above principle, in the embodiments of the present application, a plasma treatment process is introduced into HARP to deposit the dielectric layer in the trench in a cyclic deposition mode of deposition - surface treatment. During the deposition process, different stress - performance dielectric layers can be obtained by adjusting the thickness of the deposited dielectric layer, the power of plasma treatment, and the time of plasma treatment in each cycle, so as to improve the device performance. Further, by performing cyclic deposition - surface treatment in multiple times, it is convenient to control the treatment depth layer by layer when forming a compressive - stress dielectric layer, so that the entire formed dielectric layer can be treated, rather than being limited to the surface of the dielectric layer. Therefore, this cyclic treatment mode can effectively change the stress of the dielectric layer.

[0050] In addition, since the plasma treatment will remove the groups in the oxide dielectric layer, making the dielectric layer denser, which is beneficial to reducing the pores in the dielectric layer.

[0051] Further, as HARP is a thermal reaction process of conformal growth, the valence - bond concentration on the substrate surface will affect its growth rate, and a lower deposition rate can obtain better filling ability. Therefore, in the deposition process of the next cycle, since the previous plasma treatment reduces the valence bonds on the surface of the oxide dielectric layer, this can reduce the deposition rate of HARP, thereby obtaining better filling performance.

[0052] It can be understood that since the plasma treatment is performed by spraying from top to bottom during the plasma treatment process, the treatment effect at the top of the trench is stronger, and more valence bonds on the surface of the top oxide are reduced, while the treatment effect at the bottom of the trench is weaker, and fewer valence bonds on the surface of the bottom oxide are reduced. Thus, in the deposition process of the next cycle, the deposition rate of HARP oxide at the top of the trench is more affected, and the deposition rate at the bottom of the trench is less affected. The deposition rate of HARP oxide at the top of the trench is less than that at the bottom of the trench. Therefore, the occurrence of hanging at the top of the trench can be reduced, which is also beneficial to reducing the pores in the deposited dielectric layer and improving the filling effect.

[0053] Further, based on the above principle, it can be seen that the deposition of dielectric layers with different stresses and the plasma surface treatment can both be completed in the same machine. This is beneficial to reducing the material transfer and machine replacement time, thereby significantly improving the production efficiency, and can reduce equipment investment and space occupation, thus reducing the production cost. In addition, continuously completing step S110, step S120, and step S130 in the same machine can better control the production process and reduce errors.

[0054] Based on Figure 1A the preparation process of the method for depositing a stress dielectric layer in a trench, the following will be combined with Figures 2A - 2EThe schematic diagram of the semiconductor cross-sectional structure shown details the exemplary process flow of the method for depositing a stress medium layer in a trench according to some embodiments of the present application.

[0055] Figure 2A The schematic cross-sectional structure diagram shows the formation of a trench in a semiconductor structure according to an embodiment of the present application.

[0056] As Figure 2A shown, a semiconductor structure 210 is provided, and a trench 220 is formed in the semiconductor structure 210.

[0057] In an embodiment of the present application, the semiconductor structure 210 may include a substrate 211, an oxide layer 212 and a nitride layer 213 stacked in sequence on the substrate 211, and the oxide layer 212 is located on the upper surface of the substrate 211. In other embodiments, the semiconductor structure 210 may also include only the substrate 211 and a nitride layer on the substrate, or include the substrate 211, multiple oxide layers and multiple nitride layers stacked in sequence on the substrate 211, and the embodiments of the present application do not limit this.

[0058] Specifically, the material of the substrate 211 is a material containing Si element, and specifically may be at least one of the following materials: Si, SiGe, SiC, SiGeC or other compound semiconductors containing Si element. The substrate 211 may be a semiconductor single-layer structure or a multi-layer structure composed of these materials. The substrate 211 may also be silicon on insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon-germanium-on-insulator stacked silicon (S-SiGeOI), germanium-silicon-on-insulator (SiGeOI), etc.

[0059] Specifically, the material that can be used for the nitride layer 213 is silicon nitride, and the material that can be used for the oxide layer 212 is silicon dioxide.

[0060] In an embodiment of the present application, the trench 220 extends from the surface of the nitride layer 213 away from the substrate 211 towards the substrate 211, penetrates through the nitride layer 213 and the oxide layer 212, and extends into the interior of the substrate 211.

[0061] Specifically, the trench 220 is mainly prepared by lithography technology and can be formed by various known processes, and the embodiments of the present application do not limit this aspect. For example, the preparation process of the trench 220 includes: coating a photoresist on the semiconductor structure 210, selectively exposing the photoresist through an exposure machine, developing to remove the exposed or unexposed part of the photoresist, etching or depositing to form a pattern in the exposed area, removing the remaining photoresist, and continuing to form the required groove through dry etching or wet etching.

[0062] Specifically, the trench 220 has sidewalls, a bottom, and an upward opening. The shape of the trench 220 can be various shapes such as rectangular, circular, cross-shaped, etc., and the number of trenches 220 can also be multiple.

[0063] Specifically, the trench 220 can be a trench in semiconductor chip manufacturing processes such as shallow trench isolation (STI), interlayer dielectric (ILD), etc. In the STI process, the trench is used to isolate different transistors to prevent current leakage and crosstalk, thereby improving the performance of the integrated circuit. In the ILD process, the trench is used to form a conductive path to connect circuit elements at different levels.

[0064] Figure 2B A schematic cross-sectional structure diagram of the deposited dielectric layer according to an embodiment of the present application is shown.

[0065] As Figure 2B shown, based on the set deposition thickness, a dielectric layer 230 is deposited in the trench 220 and on the upper surface of the semiconductor structure 210 using the HARP process. In some embodiments of the present application, during the deposition of the dielectric layer 230, the dielectric layer may also be deposited only in the trench 220 or on a part of the upper surface of the trench 220 and the semiconductor structure 210, but at least the deposited dielectric layer should cover the trench 220.

[0066] Specifically, the material used for the dielectric layer 230 can be any suitable dielectric material known in the art. For example, it can be silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), fluorosilicate glass, undoped silicate glass (USG), or tetraethyl orthosilicate, or a combination of one or more of them. The embodiments of the present application are not limited herein.

[0067] Specifically, in the HARP process, chemical vapor deposition is carried out through a thermal process, and the process temperature of the HARP process is generally 500°C to 600°C.

[0068] In the HARP process, the control of the deposition thickness can usually be achieved through the following several factors. The HARP process uses ozone (O 3)(and tetraethyl orthosilicate (TEOS)) to form an oxide film through a thermal chemical reaction. By precisely controlling the flow rates and ratios of these chemical raw materials, the thickness of the deposited film can be affected. The temperature during the deposition process has a significant impact on the reaction rate of the chemical reaction and the quality and purity of the thin film. A higher temperature can increase the reaction rate of the chemical reaction, thereby affecting the deposition rate and the thickness of the thin film. The pressure during the deposition process also affects the growth of the thin film. A lower pressure usually results in a slower deposition rate, but can improve the quality of the thin film in the vertical direction. The reaction time during the deposition process is a direct method for controlling the thickness of the thin film. By controlling the reaction time, the thickness of the deposited thin film can be precisely controlled. Therefore, by adjusting one or more of the above process parameters of HARP, the desired deposition thickness can be obtained.

[0069] Figure 2C The cross-sectional structural schematic diagram of the plasma treatment of the dielectric layer according to the embodiment of the present application is shown.

[0070] As Figure 2C shown, based on the set plasma treatment power and plasma treatment time, the foregoing dielectric layer 230 is treated with a plasma 240 containing an inert gas. Specifically, the foregoing inert gas is Ar or He.

[0071] Specifically, the foregoing dielectric layer 230 is treated with a plasma 240 containing Ar or He, which will remove the -CH 3 , -H, -OH and other equivalent bonds on the surface of the dielectric layer 230. During the process of removing the valence bonds on the surface of the dielectric layer 230, only the valence bonds on the surface of the dielectric layer 230 are blown away by the plasma 240, and a physical reaction occurs. Compared with removing the valence bonds by a chemical reaction, in the process of blowing away the valence bonds on the surface of the dielectric layer 230 in the embodiment of the present application, other properties of the dielectric layer 230 are not affected.

[0072] By adjusting the plasma treatment power and plasma treatment time, the treatment depth of the dielectric layer can be controlled, and the amount of valence bonds removed from the surface of the dielectric layer can be adjusted, so as to adjust the tightness of the dielectric layer and change the thermal expansion coefficient of the dielectric layer, in order to provide different stress performances. Figure 2D The cross-sectional structural schematic diagram of the formation of the stress dielectric layer according to the embodiment of the present application is shown.

[0073] As Figure 2D shown, based on the set number of cycles, the foregoing steps of depositing the dielectric layer and the plasma treatment step are cycled multiple times until the foregoing trench is filled, and a stress dielectric layer 250 is formed on the foregoing trench and the upper surface of the semiconductor structure 210.

[0074] Specifically, the stress performance of the stress medium layer 250 can be determined by the number of cycles, the thickness of the medium layer deposited each time during the cycle, the plasma treatment power during the cycle, and the plasma treatment time. The stress medium layer 250 can be a tensile stress medium layer or a compressive stress medium layer. When the stress medium layer 250 is a tensile stress medium layer, the foregoing trench 220 is disposed in the region of the semiconductor structure 210 for forming an NMOS device. When the stress medium layer 250 is a compressive stress medium layer, the foregoing trench 220 is disposed in the region of the semiconductor structure 210 for forming a PMOS device.

[0075] In some embodiments of the present application, during multiple cycles, the medium layer may also be deposited only in the trench 220 or on the trench 220 and a part of the upper surface of the semiconductor structure 210, but at least the deposited medium layer should cover the trench 220.

[0076] Specifically, during multiple cycles of the foregoing steps of depositing the medium layer and the plasma treatment step, by depositing the medium layer, the foregoing medium layer is treated with a plasma 240 containing Ar or He, and then the medium layer is deposited again. Since the medium layer is treated with a plasma containing Ar or He, this will take away the valence bonds on the surface of the medium layer, reducing the valence bonds on the surface of the medium layer at the top of the trench 220, thereby weakening the deposition rate when depositing the medium layer on the top of the trench again. However, the bottom of the trench 220 is less affected by the treatment effect, and the deposition rate is less affected. Therefore, the occurrence of hanging at the top of the trench 220 can be reduced, the premature sealing of the trench 220 can be avoided, and thus the holes formed during the deposition of the medium layer by the HARP process can be reduced.

[0077] Figure 2E Fig. shows a schematic cross-sectional structure diagram of the planarization treatment of the stress medium layer according to an embodiment of the present application.

[0078] As Figure 2E shown, the stress medium layer 250 in the foregoing trench and on the upper surface of the semiconductor structure 210 is planarized so that the upper surface of the remaining stress medium layer 250 is flush with the upper surface of the semiconductor structure 210.

[0079] Specifically, during the planarization process, a chemical mechanical polishing (CMP) process can be used.

[0080] The above describes the process flow of selectively depositing a medium layer with different stress performances in the trench.

[0081] In an embodiment of forming a compressive stress medium layer, when forming a compressive stress medium layer by using the method 100 of depositing a stress medium layer in a trench according to an embodiment of the present application, the trench is disposed in the region of the semiconductor structure for forming a PMOS device.

[0082] The method for forming a compressive stress dielectric layer includes: a first deposition process, depositing a first dielectric layer in a first trench by using a HARP process based on a set first deposition thickness; a first plasma process, performing a first plasma process on the entire film layer of the first dielectric layer by using a plasma containing an inert gas based on a set first plasma process power and a first plasma process time, wherein the first deposition thickness of the first dielectric layer does not exceed the processing depth of the first plasma process at the first plasma process power and the first plasma process time; and based on a set first number of cycles, repeatedly performing the first deposition process and the first plasma process for multiple cycles until the first trench is filled to form a compressive stress dielectric layer in the first trench.

[0083] Specifically, during the process of forming the compressive stress dielectric layer, a first dielectric layer with a first deposition thickness is deposited in the first trench by using a HARP process. Considering that the maximum processing depth of plasma processing under conditions such as high power and long time is about 100 Å, therefore, the above-mentioned first deposition thickness is set to not exceed 100 Å, preferably it can be set to 50 Å - 100 Å, and exemplarily it can be 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, etc. Of course, it can also be other values within the above range, which are not limited herein. In some embodiments, during the first deposition process, the pressure in the chamber can be set at 500 torr - 600 torr.

[0084] Next, the dielectric layer is treated with a plasma containing an inert gas, wherein the inert gas is Ar or He, and the first plasma treatment power is 300W~500W, and exemplarily can be 300W, 320W, 340W, 360W, 380W, 400W, 420W, 440W, 460W, 480W, 500W, etc., and of course it can also be other values ​​within the above range, which is not limited here; the first plasma treatment time is 10s~15s, and exemplarily can be 10s, 11s, 12s, 13s, 14s, 15s, etc., and of course it can also be other values ​​within the above range, which is not limited here; the chamber pressure of the first plasma treatment is 20 torr~50torr, and exemplarily can be 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 50 torr, etc., and of course it can also be other values ​​within the above range, which is not limited here. During the plasma treatment process, the lower the chamber pressure, the more stable the plasma and the more uniform the treatment effect. However, when the first deposition process and the first plasma process are performed in the same chamber, since the two processes are performed in a cycle, it is necessary to frequently switch back and forth between the pressures required for each process. This pressure switching will bring some negative effects. For example, the pressure switching may cause the deposits on the inner wall or components of the chamber to peel off, resulting in particle contamination; since the pressure switching is usually achieved by exhausting the gas, when the switching is achieved by exhausting the gas with a large flow rate in order to save time, the gas flow may blow the particles on the semiconductor device, causing contamination, etc. Therefore, in some embodiments of the present application, the chamber pressure of the plasma treatment can be increased to minimize the pressure difference between the deposition process and the plasma treatment process, thereby reducing the adverse effects of the pressure switching.

[0085] Then, the first deposition process and the first plasma process are cycled for 25 to 35 times, illustratively, 25, 26, 27, 28, 30, 31, 33, 35, etc., until the aforementioned groove is filled. A compressive stress dielectric layer with a compressive stress of -100 MPa to -50 MPa is formed in the aforementioned groove. It can be understood that the number of cycles may depend on the depth of the groove to be filled and the thickness of the dielectric layer obtained after a single cycle of treatment.

[0086] In an embodiment of forming a tensile stress dielectric layer, when the tensile stress dielectric layer is formed by using the method 100 of depositing a stress dielectric layer in a trench according to an embodiment of the present application, the trench is disposed in a region of the semiconductor structure for forming an NMOS device.

[0087] The method for forming a tensile stress dielectric layer includes: a second deposition process, depositing a second dielectric layer in a second trench by using a HARP process based on a set second deposition thickness; a second plasma process, performing a second plasma process on the film surface of the second dielectric layer by using a plasma containing an inert gas based on a set second plasma process power and a second plasma process time, wherein the second deposition thickness of the second dielectric layer exceeds the processing depth of the second plasma process under the second plasma process power and the second plasma process time; and based on a set second number of cycles, repeatedly performing the second deposition process and the second plasma process for multiple cycles until the second trench is filled to form a tensile stress dielectric layer in the second trench.

[0088] Specifically, during the process of forming the tensile stress dielectric layer, a second dielectric layer with a second deposition thickness is deposited in the second trench by using a HARP process. Considering that the maximum processing depth of plasma processing under conditions such as high power and long time is about 100 Å, therefore, the above-mentioned second deposition thickness is set to exceed 100 Å, preferably it can be set to 150 Å - 200 Å, and exemplarily it can be 150 Å, 160 Å, 170 Å, 180 Å, 190 Å, 200 Å, etc. Of course, it can also be other values within the above range, which are not limited herein. In some embodiments, during the second deposition process, the pressure in the chamber can be set to 500 torr - 600 torr.

[0089] Then, the dielectric layer is processed by using a plasma containing an inert gas, wherein the inert gas is Ar or He, the second plasma process power is 150 W - 250 W, and exemplarily it can be 150 W, 160 W, 170 W, 180 W, 190 W, 200 W, 210 W, 220 W, 230 W, 240 W, 250 W, etc. Of course, it can also be other values within the above range, which are not limited herein; the second plasma process time is 5 s - 10 s, and exemplarily it can be 5 s, 6 s, 7 s, 8 s, 9 s, 10 s, etc. Of course, it can also be other values within the above range, which are not limited herein; the chamber pressure of the second plasma process is 20 torr - 50 torr, and exemplarily it can be 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 50 torr, etc. Of course, it can also be other values within the above range, which are not limited herein. The reason for setting the chamber pressure is the same as above and will not be repeated here.

[0090] Then, the second deposition process and the second plasma treatment cycle are performed 10 to 20 times, which can be, for example, 10 times, 11 times, 12 times, 14 times, 15 times, 16 times, 18 times, 20 times, etc., until the aforementioned trench is filled. A tensile stress dielectric layer with a tensile stress of 100 MPa to 150 MPa is formed in the aforementioned trench. It can be understood that the above number of cycles can depend on the depth of the trench to be filled and the thickness of the dielectric layer obtained after a single cycle treatment.

[0091] In the above two embodiments, since chemical vapor deposition is carried out through a thermal process in the HARP process, the surface of the dielectric layer deposited by the HARP process has more -CH 3 , -H, -OH and other equivalent bonds, which are relatively loose. After depositing the dielectric layer by the HARP process, that is, after the dielectric layer comes out of the high-temperature environment, compared with the semiconductor structure containing Si elements, the dielectric layer will shrink more and exhibit tensile stress.

[0092] In the above embodiment of forming a tensile stress dielectric layer, the thickness of the dielectric layer deposited in a single cycle is relatively thick, for example, exceeding the treatment depth of the subsequent plasma treatment. The treatment time of the plasma treatment of this dielectric layer with a lower power and containing Ar or He is shorter. Therefore, the plasma treatment only affects the surface structure of the dielectric layer film, and the bottom layer of the film is still relatively loose. When the steps of depositing the dielectric layer and the plasma treatment step are performed through multiple cycles, a tensile stress dielectric layer can still be obtained. Compared with the embodiment of forming a compressive stress dielectric layer, since the dielectric layer obtained in a single cycle is thicker, the number of cycles required to fill the trench with the same depth is less. Moreover, by plasma-treating this dielectric layer, the holes formed during the deposition of the dielectric layer by the HARP process can be reduced, and a relatively dense tensile stress dielectric layer can be obtained.

[0093] In the above embodiment of forming a compressive stress dielectric layer, the thickness of the dielectric layer deposited in a single cycle is relatively thin, for example, not exceeding the treatment depth of the subsequent plasma treatment. The treatment time of the plasma treatment of this dielectric layer with a higher power and containing Ar or He is longer. Therefore, the plasma treatment can penetrate the entire film layer, making the entire film layer denser, not only limited to the surface of the film layer. When the steps of depositing the dielectric layer and the plasma treatment step are performed through multiple cycles, the obtained stress dielectric layer will shrink less compared with the semiconductor structure containing Si elements, so that a compressive stress dielectric layer can be obtained. Compared with the embodiment of forming a tensile stress dielectric layer, since the dielectric layer obtained in a single cycle is thinner, the number of cycles required to fill the trench with the same depth is more. Similarly, by plasma-treating this dielectric layer, the holes formed during the deposition of the dielectric layer by the HARP process can be reduced, and a relatively dense compressive stress dielectric layer can be obtained.

[0094] CMOS technology typically combines NMOS and PMOS transistors to achieve complementary functions. Therefore, the embodiments of this application also provide a method for simultaneously forming a stress medium layer in the NMOS region and the PMOS region to meet the stress requirements of different regions and improve the performance of NMOS and PMOS devices at the same time.

[0095] Figure 3 FIG. 4 shows an exemplary flowchart of a method 300 for depositing a stress medium layer in a trench according to other embodiments of this application.

[0096] As Figure 3 shown, in step S310, a semiconductor structure is provided, which has a first region and a second region. The aforementioned first region is used to form a PMOS device, and there is at least one first trench in the first region. The second region is used to form an NMOS device, and there is at least one second trench in the second region. Then, in step S320, a compressive stress medium layer or a tensile stress medium layer is formed at least in the first trench of the first region and the second trench of the second region. In step S330, the compressive stress medium layer in the aforementioned second region is removed, or the tensile stress medium layer in the first region is removed. Then, in step S340, a tensile stress medium layer is formed in the second trench of the aforementioned second region, or a compressive stress medium layer is formed in the first trench of the first region.

[0097] Specifically, the aforementioned steps S320 and S340 can be completed in the same machine tool, which can reduce the material transfer and machine replacement time, thus significantly improving the production efficiency. It can also reduce the equipment investment and space occupation, thereby reducing the production cost. In addition, completing steps S320 and S340 in the same machine tool can better control the production process and reduce errors.

[0098] Based Figure 3 on the preparation process of the method 300 for depositing a stress medium layer in a trench, the following combines Figures 4A - 4G with the schematic cross-sectional structure diagram of the semiconductor shown in FIG. 5 to detail the exemplary process flow of the method for depositing a stress medium layer in a trench according to some embodiments of this application. Note that only one implementation manner of the aforementioned method is described here, that is, the medium layer of the first trench is formed first, and then the medium layer of the second trench is formed. Those skilled in the art can similarly deduce the process flow implementation of the other implementation manner, which will not be elaborated here.

[0099] Figure 4A FIG. 5 shows a schematic cross-sectional structure diagram of a semiconductor structure provided with a first region and a second region according to an embodiment of this application.

[0100] As Figure 4AAs shown, a semiconductor structure 410 is provided, which has a first region 420 and a second region 430. The first region 420 has a first trench 440, and the second region 430 has a second trench 450. The first region is used to form PMOS devices, and the second region is used to form NMOS devices.

[0101] In an embodiment of the present application, the first region 420 may have one or more trenches, and the second region 430 may also have one or more trenches, but at least ensure that each of the first region 420 and the second region 430 has at least one trench.

[0102] In an embodiment of the present application, the semiconductor structure 410 may include a substrate 411, an oxide layer 412 and a nitride layer 413 stacked on the substrate 411 in sequence. The semiconductor structure 410 may have the same structure and materials as those of the aforementioned semiconductor structure 210, which will not be elaborated here.

[0103] In an embodiment of the present application, the first trench 440 and the second trench 450 extend from the surface of the nitride layer 413 away from the substrate 411 towards the substrate 411, penetrate through the nitride layer 413 and the oxide layer 412, and extend into the interior of the substrate 411. The process for forming the first trench 440 and the second trench 450 is the same as that of the trench 220, and the shapes of the first trench 440 and the second trench 450 may be the same as that of the trench 220, which will not be elaborated here.

[0104] Figure 4B The cross-sectional structure diagram of forming the first stress medium layer in an embodiment of the present application is shown.

[0105] As Figure 4B shown, a first stress medium layer 460 is formed in the first trench of the first region 420, on the upper surface of the first region 420, in the second trench of the second region 430, and on the upper surface of the second region 430. In some embodiments of the present application, the first stress medium layer may also be formed only in the first trench of the first region 420 and the second trench of the second region 430, or in the first trench of the first region 420, a part of the upper surface of the first region 420, the second trench of the second region 430, and a part of the upper surface of the second region 430, but at least ensure that the deposited first stress medium layer covers the first trench of the first region 420 and the second trench of the second region 430. In this embodiment, the first stress medium layer is a compressive stress medium layer.

[0106] Figure 4C The cross-sectional structure diagram of forming a photoresist above the first stress medium layer in an embodiment of the present application is shown.

[0107] As Figure 4CAs shown, a photoresist layer 470 is deposited above the first stress medium layer 460. Among them, the photoresist layer 470 can be a positive photoresist or a negative photoresist.

[0108] Figure 4D The cross-sectional structure diagram showing the dissolution of the photoresist layer in the second region according to the embodiment of the present application is shown.

[0109] As Figure 4D shown, when the photoresist layer 470 is a positive photoresist, the photoresist layer in the second region 430 is exposed. After the photoresist layer in the second region 430 is exposed to light, its characteristics change and it becomes easy to dissolve. Then, the photoresist layer 470 is developed, and the photoresist layer in the second region 430 is dissolved after development, leaving only the photoresist layer in the first region 420.

[0110] When the photoresist layer 470 is a negative photoresist, the photoresist layer in the first region 420 is exposed. After the photoresist layer in the first region 420 is exposed to light, its characteristics change and it becomes difficult to dissolve. Then, the photoresist layer 470 is developed, and the photoresist layer in the second region 430 is dissolved after development, leaving only the photoresist layer in the first region 420.

[0111] Through the exposure and development processes, the photoresist layer in the second region 430 is removed, exposing the surface of the first stress medium layer in the second region 430.

[0112] Figure 4E The cross-sectional structure diagram showing the removal of the first stress medium layer in the second region and the remaining photoresist layer according to the embodiment of the present application is shown.

[0113] As Figure 4E shown, using the photoresist layer in the first region, the first stress medium layer 460 in the second trench of the second region 430 is removed through an etching process. Then, the photoresist layer in the first region is removed.

[0114] Specifically, the aforementioned etching process can be a dry etching process, a wet etching process, or a combined dry and wet etching process. Among them, when using a dry etching process, the etching gas for dry etching can be a gas containing fluorine, chlorine, or bromine. When using a wet etching process, the wet etching can be a hydrofluoric acid solution. When using a combined dry and wet etching process, first, dry etching can be performed with a plasma of a gas containing fluorine, chlorine, or bromine, and then cleaning can be performed with a hydrofluoric acid solution, so as to completely remove the first stress medium layer 460 in the second trench of the second region 430.

[0115] Figure 4F The cross-sectional structure diagram showing the formation of the second stress medium layer according to the embodiment of the present application is shown.

[0116] As Figure 4FAs shown, a second stress medium layer 480 is formed on the upper surface of the first stress medium layer 460, in the second trench of the second region 430, and on the upper surface of the second region 430. In some embodiments of the present application, the second stress medium layer may also be formed only in the second trench of the second region 430, or the second stress medium layer may be formed on the upper surface of the first stress medium layer 460 and in the second trench of the second region 430, or the second stress medium layer may be formed on a part of the upper surface of the first stress medium layer 460 and in the second trench of the second region 430, or the second stress medium layer may be formed on a part of the upper surface of the first stress medium layer 460, in the second trench of the second region 430, and on a part of the upper surface of the second region 430, but at least the deposited second stress medium layer should cover the second trench of the second region 430. In this embodiment, the second stress medium layer is a tensile stress medium layer.

[0117] Figure 4G The cross-sectional structure diagram showing the planarization process of the first stress medium layer and the second stress medium layer in the embodiment of the present application is shown.

[0118] As Figure 4G shown, the first stress medium layer 460 and the second stress medium layer 480 are planarized so that the upper surfaces of the remaining first stress medium layer 460 and the second stress medium layer 480 are flush with the upper surface of the semiconductor structure 410.

[0119] Specifically, during the planarization process, a chemical mechanical polishing (CMP) process may be used.

[0120] In the above embodiments, by forming stress medium layers with different types of stress in the trenches of the first region 420 and the second region 430 respectively, when the first region 420 and the second region 430 are respectively used to form different MOS devices, a stress medium layer that helps improve the performance of the MOS device can be purposefully filled in the trenches, thereby improving the performance of the formed device.

[0121] Figure 5 The schematic diagram showing the influence of plasma treatment power and cycle times on the stress performance of the dielectric layer is shown. In this diagram, the final thicknesses of the dielectric layers obtained in various cases are the same, for example, all 1500 Å. As shown in the figure, the stress performances of the dielectric layers in four cases are shown, which are respectively:

[0122] Point A, the plasma treatment power is 150 W, the cycle is 15 times, and the stress of the dielectric layer is 137 MPa;

[0123] Point B, the plasma treatment power is 200 W, the cycle is 15 times, and the stress of the dielectric layer is 110 MPa;

[0124] At point C, the plasma treatment power is 300 W, the cycle is 30 times, and the stress of the dielectric layer is -48 MPa;

[0125] At point D, the plasma treatment power is 500 W, the cycle is 30 times, and the stress of the dielectric layer is -90 MPa.

[0126] It can be seen that since the thickness of the final dielectric layer is the same, the fewer the number of cycles, the greater the thickness of the film deposited in a single cycle. When the plasma treatment power is small, only the surface of the film is treated, and the dielectric layer is relatively loose. Therefore, when returning from a high-temperature environment to room temperature, the dielectric layer shrinks more compared to the substrate, showing tensile stress. On the contrary, when the thickness of the final dielectric layer is the same, the more the number of cycles, the smaller the thickness of the film deposited in a single cycle. When the plasma treatment power increases, more groups in the dielectric layer will be removed, and the entire film layer will be treated, making the dielectric layer denser and having a smaller coefficient of thermal expansion. Therefore, when returning from a high-temperature environment to room temperature, the dielectric layer shrinks less compared to the silicon-containing substrate, showing compressive stress.

[0127] Therefore, the embodiment of the present application can introduce a plasma treatment process in HARP to deposit the dielectric layer in the trench in the mode of deposition-surface treatment cycle deposition. During the deposition process, different stress performance dielectric layers can be obtained by adjusting the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment in each cycle, thereby improving the device performance.

[0128] In summary, compared with the prior art, the unexpected technical effect of the present application is that different stress dielectric layers can be selectively deposited in the trench as needed.

[0129] The embodiment of the present application controls the stress performance of the stress dielectric layer by setting or adjusting the number of cycles, the deposition thickness, the plasma treatment power, and the plasma treatment time, and can selectively deposit different stress dielectric layers in the trench as needed. Thus, a tensile stress dielectric layer is formed in the trench in the area for forming the NMOS device, and a compressive stress dielectric layer is formed in the trench in the area for forming the PMOS device, improving the mobility of the carriers in the corresponding area, thereby improving the performance of the corresponding device.

[0130] The embodiment of the present application also provides a shallow trench isolation structure. The dielectric layer in the trench of the shallow trench isolation structure can be prepared by the aforementioned method 100 for depositing a stress dielectric layer in the trench or the method 300 for depositing a stress dielectric layer in the trench. The specific structure of the shallow trench isolation structure can refer to the description of the process flow and the corresponding semiconductor cross-sectional structure in combination with the drawings above, which will not be repeated here.

[0131] Although several embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many changes, alterations, and alternative ways may occur to those skilled in the art without departing from the spirit and scope of the present application. It should be understood that various alternatives to the embodiments of the present application described herein may be employed in practicing the present application. The appended claims are intended to define the scope of the present application and thus cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for depositing a stressed dielectric layer in a trench, characterized in that: include: A first deposition process, based on a set first deposition thickness, depositing a first dielectric layer in the first trench by using a HARP process; A first plasma treatment, based on a set first plasma treatment power and a set first plasma treatment time, using a plasma containing an inert gas to perform a first plasma treatment on the entire film layer of the first dielectric layer, wherein the first deposition thickness of the first dielectric layer does not exceed a treatment depth of the first plasma treatment at the first plasma treatment power and the first plasma treatment time; Based on the set first cycle number, the first deposition process and the first plasma process are performed multiple times in a cycle until the first trench is filled to form a compressive stress dielectric layer in the first trench; the method satisfies the following conditions: The first deposition thickness is 50Å~100Å; The first plasma treatment power is 300W~500W; The first plasma treatment time is 10s to 15s; The inert gas is Ar or He; The first cycle number is 25 to 35 times; The chamber pressure of the first deposition process is 500 torr to 600 torr; and The chamber pressure of the first plasma treatment is 20 torr~50 torr.

2. The method according to claim 1, characterized in that The compressive stress of the compressive stress medium layer is -100MPa~-50MPa.

3. The method according to claim 1, characterized in that The first trench is disposed in a region of the semiconductor structure for forming a PMOS device.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: a second deposition process, depositing a second dielectric layer in the second trench by using a HARP process based on a set second deposition thickness; second plasma treatment, based on the set second plasma treatment power and second plasma treatment time, using plasma containing an inert gas to perform a second plasma treatment on the film surface of the second dielectric layer, wherein the second deposition thickness of the second dielectric layer exceeds the treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; Based on the set second cycle number, the second deposition process and the second plasma process are performed for multiple cycles until the second trench is filled to form a tensile stress dielectric layer in the second trench.

5. The method according to claim 4, characterized in that The tensile stress of the tensile stress medium layer is 100MPa-150MPa.

6. The method according to claim 4, characterized in that The method satisfies at least one of the following conditions: The second deposition thickness is 150Å~200Å; The second plasma treatment power is 150W~250W; The second plasma treatment time is 5s to 10s; The inert gas is Ar or He; The second cycle number is 10 to 20 times; The chamber pressure of the second deposition process is 500 torr to 600 torr; and The chamber pressure of the second plasma treatment is 20 torr~50 torr.

7. The method according to claim 4, characterized in that The second trench is disposed in a region of the semiconductor structure for forming an NMOS device.

8. A method for depositing a stressed dielectric layer in a trench, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure has a first region and a second region, wherein the first region is used to form a PMOS device and has at least one first trench, and the second region is used to form an NMOS device and has at least one second trench; forming a compressive stress dielectric layer or a tensile stress dielectric layer at least in the first trench of the first region and in the second trench of the second region; removing the compressive stress dielectric layer in the second region or removing the tensile stress dielectric layer in the first region; forming a tensile stress dielectric layer in the second trench of the second region or forming a compressive stress dielectric layer in the first trench of the first region; in: The compressive stress dielectric layer is formed according to the method according to any one of claims 1-2.

9. The method according to claim 8, characterized in that The tensile stress dielectric layer is formed according to the following method: A second deposition process is performed, based on the set second deposition thickness, by using a HARP process to deposit a second dielectric layer in the groove; A second plasma treatment, based on a set second plasma treatment power and a set second plasma treatment time, using a plasma containing an inert gas to perform a second plasma treatment on the film surface of the second dielectric layer, wherein the second deposition thickness of the second dielectric layer exceeds a treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; Based on the set second cycle number, the second deposition process and the second plasma process are performed for multiple cycles until the trench is filled to form a tensile stress dielectric layer in the trench.

10. A shallow trench isolation structure, characterized in that: The dielectric layer in the trench of the shallow trench isolation structure is prepared by the method according to any one of claims 1 to 9.

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