A back-contact battery with a front-facing inverted pyramid structure and a preparation method thereof

Abstract

The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery with a front-side inverted pyramid structure and a preparation method thereof, comprising the following steps: S1. Perform gettering treatment on a silicon wafer; then perform high-temperature diffusion; S2. Remove the phosphorus-rich silicon oxide layer on the back side of the silicon wafer, and then perform single-sided polishing on this surface; S3. Form a first semiconductor layer on the polished surface of the silicon wafer in S2; S4. Clean and remove the PSG layer naturally formed on the surface of the first semiconductor layer; S5. Deposit a mask layer on the back side; S6. Form second semiconductor opening regions distributed at intervals on the back side; S7. Perform polishing; S8. Remove the phosphorus-rich silicon oxide layer on the front side, and then perform texturing cleaning using a texturing solution comprising an alkali and a cyclodextrin-based texturing additive. The present invention can form different pyramid morphologies on the front and back sides, which is beneficial to effectively reducing the front-side reflectivity while ensuring good back-side passivation performance, thereby facilitating the improvement of the open-circuit voltage, short-circuit current, and battery efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery with a front-side inverted pyramid structure and a preparation method thereof. Background Art

[0002] A back-contact battery is a battery structure in which there is no metal grid line on the front side, and the PN junction region and the metal electrodes are both located on the back side of the battery. The purpose is to avoid the occlusion of incident light by the front electrode grid line in the traditional battery structure, so as to maximize the utilization of incident light and reduce optical losses. Therefore, how to reduce the reflectivity of the front side is the key to improving the battery efficiency of the back-contact battery.

[0003] At present, the front side of the back-contact battery has a regular pyramid morphology and a relatively high reflectivity. In theory, the inverted pyramid structure can achieve a lower reflectivity, but the inverted pyramid structure is usually formed by the MACE (metal-assisted chemical etching) method. During the subsequent cleaning process, metal ions cannot be completely removed, and thus are introduced into the silicon wafer body during the high-temperature coating process, forming recombination centers, which seriously reduces the open-circuit voltage and battery efficiency of the solar cell.

[0004] It should be noted that this part of the content of the present invention only provides the background technology related to the present invention, and does not necessarily constitute the prior art or the well-known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defect that the front-side reflectivity of the back-contact battery in the prior art is high, which affects the short-circuit current and battery efficiency of the battery, and to provide a back-contact battery with a front-side inverted pyramid structure and a preparation method thereof, which can form different pyramid morphologies on the front and back sides, is beneficial to effectively reducing the front-side reflectivity while ensuring good back-side passivation performance, and thus is beneficial to improving the open-circuit voltage, short-circuit current and battery efficiency.

[0006] To achieve the above purpose, in the first aspect, the present invention provides a preparation method of a back-contact battery with a front-side inverted pyramid structure, including the following steps:

[0007] S1. Perform gettering treatment on the silicon wafer. The process of the gettering treatment includes: depositing a phosphorus-rich silicon oxide layer with a thickness of 100-1000 Å on both surfaces of the silicon wafer, and the phosphorus doping concentration of the phosphorus-rich silicon oxide layer is 1e18 cm -3 -5e19 cm -3 ; then perform high-temperature diffusion, and the temperature of the high-temperature diffusion is 700-900 °C;

[0008] S2. Remove the phosphorus-rich silicon oxide layer on the back side of the silicon wafer, and then perform single-sided polishing on this surface;

[0009] S3. Form a first semiconductor layer on the polished surface of the silicon wafer in S2;

[0010] S4. Clean and remove the PSG layer naturally formed on the surface of the first semiconductor layer;

[0011] S5. Deposit a mask layer on the surface of the first semiconductor layer;

[0012] S6. Perform a first etching on the mask layer on the back surface of the silicon wafer in S5 to remove the mask layer and the corresponding part of the first semiconductor layer, forming spaced-apart second semiconductor opening regions;

[0013] S7. Polish to remove the damaged layer in the second semiconductor opening region on the back surface and the first semiconductor overplating layer on the front surface;

[0014] S8. Remove the phosphorus-rich silicon oxide layer on the front surface, and then perform texturing cleaning using a texturing solution including an alkali and a cyclodextrin-based texturing additive to form an inverted pyramid texture on the front surface, and at the same time form a regular pyramid texture in the second semiconductor opening region on the back surface, and remove at least part of the thickness of the mask layer;

[0015] S11. Form a second semiconductor layer on the back surface.

[0016] In some preferred embodiments of the present invention, the reflectivity of the inverted pyramid texture on the front surface is 7% - 8%, and the reflectivity of the regular pyramid texture on the back surface is 11% - 12%.

[0017] In some preferred embodiments of the present invention, in S8, the corresponding pyramid lateral dimension of the inverted pyramid texture on the front surface is 0.8 - 2 μm, the pyramid height is 0.5 - 0.8 μm, the corresponding pyramid lateral dimension of the regular pyramid texture on the back surface is 1 - 3 μm, and the pyramid height is 1.0 - 1.5 μm.

[0018] In some preferred embodiments of the present invention, in S8, the mass content of cyclodextrin in the cyclodextrin-based texturing additive is 0.0001 wt% - 0.1 wt%.

[0019] In some preferred embodiments of the present invention, the cyclodextrin-based texturing additive further includes: based on the total amount of the cyclodextrin-based texturing additive, 0.01 wt% - 0.5 wt% of sodium lignosulfonate, 0.1 wt% - 5 wt% of sodium alginate, and 0.05 wt% - 0.1 wt% of sodium benzoate.

[0020] In some preferred embodiments of the present invention, the texturing cleaning in S8 includes at least two steps: first, perform the first texturing using a first texturing solution including a first cyclodextrin-containing texturing additive, and then perform the second texturing using a second texturing solution including a second cyclodextrin-containing texturing additive. The mass content of cyclodextrin in the first cyclodextrin-containing texturing additive is 0.001 wt% - 0.1 wt%, and the mass content of cyclodextrin in the second cyclodextrin-containing texturing additive is 0.0001 wt% - 0.01 wt%.

[0021] In some preferred embodiments of the present invention, the alkali in the S8 texturing solution includes sodium hydroxide and / or potassium hydroxide. The mass content of the alkali in the texturing solution is 1 wt% - 2 wt%, and the mass content of the cyclodextrin-containing texturing additive is 0.5 wt% - 2 wt%.

[0022] In some preferred embodiments of the present invention, the conditions for the texturing cleaning in S8 include: the texturing temperature is 70°C - 85°C, and the texturing time is 8 - 15 min.

[0023] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the front side in S8 is removed by a chain machine, and the speed of the driving roller of the chain machine is controlled to be 1.2 - 3.0 m / min.

[0024] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the front side in S8 is removed using a solution containing hydrofluoric acid. The mass content of hydrofluoric acid in this solution is 5 wt% - 10 wt%.

[0025] In some preferred embodiments of the present invention, the deposition of the phosphorus-rich silicon oxide layer in S1 is carried out by a low-pressure diffusion method using POCl 3 as the phosphorus source. The conditions for the low-pressure diffusion include: the ambient pressure is 30 - 100 mba, and the diffusion time is 5 - 20 min.

[0026] In some preferred embodiments of the present invention, the time for the high-temperature diffusion in S1 is 90 - 120 min.

[0027] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the back side of the silicon wafer in S2 is removed by a chain machine, and the speed of the driving roller of the chain machine is controlled to be 1.2 - 3.0 m / min.

[0028] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the back side of the silicon wafer is removed using a solution containing hydrofluoric acid. The mass content of hydrofluoric acid in this solution is 5 wt% - 10 wt%.

[0029] In some preferred embodiments of the present invention, the single-sided polishing in S2 makes the single-sided etching depth of the silicon wafer 2 - 5 μm; and / or, the polishing in S7 makes the single-sided etching depth within 1 μm.

[0030] In some preferred embodiments of the present invention, in S2, single-sided polishing is carried out using a mixed polishing solution containing an alkali, a polishing additive, and water, where the alkali is potassium hydroxide and / or sodium hydroxide, the mass content of the alkali is 2 wt% - 5 wt%, and the mass content of the polishing additive is 0.5 wt% - 2 wt%; the conditions for single-sided polishing include: the reaction temperature is 60 - 75 °C, and the reaction time is 90 - 150 s.

[0031] In some preferred embodiments of the present invention, in S7, polishing is carried out using a mixed polishing solution containing an alkali, a polishing additive, and water, where the alkali is potassium hydroxide and / or sodium hydroxide, the mass content of the alkali is 1 wt% - 3 wt%, and the mass content of the polishing additive is 0.5 wt% - 2 wt%; the conditions for polishing include: the reaction temperature is 60 - 75 °C, and the reaction time is 30 - 180 s.

[0032] In some preferred embodiments of the present invention, the preparation method of the back-contact battery with a front-side inverted pyramid structure further includes:

[0033] S9. A passivation layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer obtained in S8; wherein, the passivation layer includes a second tunneling oxide layer and a second doped amorphous layer; the thickness of the second tunneling oxide layer is 0.5 - 1 nm, and the thickness of the second doped amorphous layer is 1 - 5 nm;

[0034] S10. Secondary cleaning is carried out to remove the anti-reflection layer overplating and passivation layer overplating on the back side.

[0035] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer.

[0036] In some preferred embodiments of the present invention, the preparation method of the back-contact battery with a front-side inverted pyramid structure further includes:

[0037] S12. A second etching opening is carried out on a part of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area;

[0038] S13. A conductive film layer is deposited on the back side obtained in S12;

[0039] S14. A third etching opening is carried out on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove;

[0040] S15. Metal electrodes are respectively formed on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located.

[0041] In a second aspect, the present invention provides a back-contact battery with a front-side inverted pyramid structure, which is obtained by the preparation method of the back-contact battery with a front-side inverted pyramid structure described in the first aspect.

[0042] Beneficial effects:

[0043] Through the above technical solutions of the present invention, especially S1-S2 and S7-S8, S1 can absorb metal impurities in the silicon wafer, improve the surface flatness of the back side, thereby improving the passivation performance of the first semiconductor layer, and cooperate with S2 to polish one side to remove the phosphorus-rich silicon oxide layer on the back side and retain the phosphorus-rich silicon oxide layer on the front side. The phosphorus-rich silicon oxide layer is used to protect the front-side damaged layer. In combination with the texturing and cleaning using alkali and a specific cyclodextrin-containing texturing additive in S8, no metal ions need to be introduced. The nucleating agent cyclodextrin adsorbs at the scribe line cuts of the damaged layer on the front side to form a mask, and gradually grows a quasi-inverted pyramid structure with the scribe line as the vertex, forming an inverted pyramid textured surface structure on the front side, enhancing the anti-reflection effect on the front side, and improving the open-circuit voltage and battery efficiency of the battery. At the same time, after the back side is polished in S7 and textured in S8, the cyclodextrin nucleating agent will not adsorb on the back side, forming a uniform regular pyramid textured surface structure, thus ensuring that the passivation performance of the back side is not affected. At the same time, different pyramid morphologies are formed on the front and back sides, which is beneficial to effectively reduce the front-side reflectivity while ensuring good passivation performance on the back side, thereby facilitating the improvement of the open-circuit voltage, short-circuit current, and battery efficiency.

[0044] In a preferred embodiment of the present invention, since the front side of the back-contact battery of the present invention has an inverted pyramid structure, compared with the regular pyramid structure on the front side of the existing back-contact battery, it is easier to form a passivation layer. Therefore, adopting a specific tunneling amorphous passivation layer structure on the front side is beneficial to ensure the passivation effect on the front side, while reducing the equipment cost of plate-type PECVD. The thicknesses of the second tunneling oxide layer and the second doped amorphous layer only need to be maintained at 50%-80% of the existing process to maintain the same passivation. And due to the thinning of the doped amorphous layer, the parasitic absorption of the film layer is reduced, which is more conducive to increasing the current, improving the short-circuit current and battery efficiency of the back-contact battery.

[0045] In the preferred embodiment of the present invention, S8 texturing and cleaning adopts two-step texturing, and the cyclodextrin content corresponding to the two-step texturing decreases within an appropriate range. After the two-step texturing, the reflectivity of the inverted pyramid on the front side is 7%-8%, and the anti-reflection effect is greatly enhanced, further improving the short-circuit current of the back contact battery. The reflectivity of the positive pyramid on the back side is 11%-12%, and the passivation performance of the second semiconductor layer is not affected, while meeting the requirements of the pyramid morphology on the front and back sides. In the first texturing, since the damaged layer on the front side of the silicon wafer is not removed, there are many dangling bonds at the damaged part of the diamond wire cutting (there are diamond wire marks when the silicon wafer is incoming, which is formed by the silicon rod being cut into silicon wafers by the diamond wire). In the first texturing process, the texturing additive adopts a high content of cyclodextrin, and a large amount of nucleating agent cyclodextrin is adsorbed at the line mark cutting to form a mask, and an inverted pyramid-like structure gradually grows along the line mark as the vertex. At the same time, the second semiconductor opening area on the back side is polished to remove the damaged layer (such as the laser damaged layer) caused by the etching opening, and there are no obvious defects on the surface. During texturing, the cyclodextrin nucleating agent will not be adsorbed on the back side, so a uniform positive pyramid morphology can be formed, which is beneficial to the deposition of the second semiconductor layer, thereby increasing the open circuit voltage of the battery; in conjunction with the second texturing, the concentration of the nucleating agent cyclodextrin contained therein is low. Under low concentration conditions, the nucleating agent will not be adsorbed on the cutting damage to form a mask layer, but can remove the cutting damage layer on the surface of the front inverted pyramid velvet. The texturing time is short and the temperature is low, so the etching amount is very small, which will not affect the pyramid morphology on the front and back sides, thereby being more conducive to ensuring the passivation level of the front film layer and improving battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 It is a schematic diagram of the structure of the front inverted pyramid of the back contact battery of the present invention.

[0048] Figure 2 It is a schematic structural diagram of the back contact battery of the present invention.

[0049] Figure 3 An electron microscope image of a front inverted pyramid structure in one embodiment;

[0050] Figure 4 This is an electron microscope image of a back positive pyramid structure in one embodiment.

[0051] Description of Reference Numerals

[0052] Silicon wafer 1, first tunneling oxide layer 2, first doped polysilicon layer 3, intrinsic amorphous silicon layer 4, second doped amorphous silicon 5, second tunneling oxide layer 6, second doped amorphous layer 7, anti-reflection layer 8, transparent conductive film layer 9, metal electrode 10; first semiconductor opening area W2, second semiconductor opening area W1, isolation trench W3. DETAILED DESCRIPTION

[0053] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0054] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0055] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0056] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0057] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0058] In the present invention, the reflectivity is obtained by ultraviolet spectrophotometer testing, and the size and height of the pyramid are measured by SEM images.

[0059] In a first aspect, the present invention provides a method for preparing a back contact battery having a front inverted pyramid structure, comprising the following steps:

[0060] S1. Perform gettering treatment on the silicon wafer. The process of gettering treatment includes: depositing a phosphorus-rich silicon oxide layer with a thickness of 100 - 1000 Å on both surfaces of the silicon wafer, and the phosphorus doping concentration of the phosphorus-rich silicon oxide layer is 1e18 cm -3 -5e19 cm -3 , preferably 1.5e18 cm -3 -5e19 cm -3 ; then perform high-temperature diffusion, and the temperature of high-temperature diffusion is 700 - 900 °C;

[0061] S2. Remove the phosphorus-rich silicon oxide layer on the back surface of the silicon wafer, and then perform single-sided polishing on this surface;

[0062] S3. Form a first semiconductor layer on the polished surface of the S2 silicon wafer;

[0063] S4. Clean and remove the PSG layer naturally formed on the surface of the first semiconductor layer;

[0064] S5. Deposit a mask layer on the surface of the first semiconductor layer;

[0065] S6. Perform a first etching on the mask layer on the back surface of the S5 silicon wafer to remove the mask layer and the corresponding part of the first semiconductor layer, and form second semiconductor opening areas distributed at intervals;

[0066] S7. Polish to remove the damaged layer in the second semiconductor opening area on the back surface and the first semiconductor overcoating layer on the front surface;

[0067] S8. Remove the phosphorus-rich silicon oxide layer on the front surface, and then perform texturing cleaning using a texturing solution including an alkali and a cyclodextrin-containing texturing additive to form an inverted pyramid texture on the front surface, and at the same time form a positive pyramid texture in the second semiconductor opening area on the back surface, and remove at least part of the thickness of the mask layer (preferably remove more than half of the thickness of the mask layer);

[0068] S11. Form a second semiconductor layer on the back surface.

[0069] The thickness of the phosphorus-rich silicon oxide layer is 100 - 1000 Å. Specifically, for example, it can be 100 Å, 200 Å, 300 Å, 400 Å, 500 Å, 600 Å, 700 Å, 800 Å, 900 Å, 1000 Å, etc. and the range between any two point values, and 200 - 1000 Å can be preferred.

[0070] In the present invention, in S2, the phosphorus-rich silicon oxide layer on the back surface is removed, and the phosphorus-rich silicon oxide layer on the front surface is retained to protect the front damaged layer through the phosphorus-rich silicon oxide layer. And through S7 polishing, first remove the front overcoating layer (polycrystalline), and then use hydrofluoric acid to remove the phosphorus-rich silicon oxide layer on the front surface in S8.

[0071] In some preferred embodiments of the present invention, the reflectivity of the front-side inverted pyramid suede is 7%-8%, and the reflectivity of the back-side regular pyramid suede is 11%-12%. The different pyramid suede structures on the front and back sides of the back-contact battery of the present invention cooperate with their respective appropriate reflectivities, which is conducive to effectively reducing the reflectivities of the front and back sides and thus enhancing the anti-reflection effect.

[0072] In some preferred embodiments of the present invention, in S8, the corresponding pyramid lateral dimension of the front-side inverted pyramid suede is 0.8-2 μm, and the pyramid height is 0.5-0.8 μm; the corresponding pyramid lateral dimension of the back-side regular pyramid suede is 1-3 μm, and the pyramid height is 1.0-1.5 μm. The different pyramid suede structures on the front and back sides of the back-contact battery of the present invention cooperate with their respective appropriate dimensions and heights, which is more conducive to the passivation of the front and back surface films.

[0073] In some preferred embodiments of the present invention, in S8, the mass content of cyclodextrin in the cyclodextrin-containing suede additive is 0.0001 wt%-0.1 wt%.

[0074] In some preferred embodiments of the present invention, the suede-making cleaning in S8 includes at least two steps: first, perform the first suede-making with a first suede-making solution including a first cyclodextrin-containing suede additive, and then perform the second suede-making with a second suede-making solution including a second cyclodextrin-containing suede additive. The mass content of cyclodextrin in the first cyclodextrin-containing suede additive is 0.001 wt%-0.1 wt%, and the mass content of cyclodextrin in the second cyclodextrin-containing suede additive is 0.0001 wt%-0.01 wt%. By performing two-step suede-making with the corresponding suede-making solutions with different cyclodextrin contents, the reflectivity of the front-side inverted pyramid is 7%-8%, and the anti-reflection effect is greatly enhanced, further improving the short-circuit current of the back-contact battery. The reflectivity of the back-side regular pyramid is 11%-12%, and the passivation performance of the second semiconductor layer is not affected, while meeting the requirements for the pyramid morphology of the front and back sides.

[0075] The contents of other solutes in the first cyclodextrin-containing suede additive and the second cyclodextrin-containing suede additive of the present invention are the same, and will not be elaborated here.

[0076] In some preferred embodiments of the present invention, the cyclodextrin-containing suede additive further includes: based on the total amount of the cyclodextrin-containing suede additive, 0.01 wt%-0.5 wt% of sodium lignosulfonate, 0.1 wt%-5 wt% of sodium alginate, and 0.05 wt%-0.1 wt% of sodium benzoate.

[0077] Using an appropriate amount of sodium lignosulfonate can form densely distributed nucleation points, and appropriate amounts of sodium alginate and sodium benzoate can control the reaction rate. In combination with cyclodextrin, it is more conducive to forming pyramid suede with uniform size.

[0078] In some preferred embodiments of the present invention, the alkali in the S8 texturing solution includes sodium hydroxide and / or potassium hydroxide, the mass content of the alkali in the texturing solution is 1 wt% - 2 wt%, and the mass content of the cyclodextrin-containing texturing additive is 0.5 wt% - 2 wt%. Here, the texturing solution can be, for example, the first texturing solution or the second texturing solution, and each independently selects within the above component and content ranges.

[0079] In some preferred embodiments of the present invention, the conditions for texturing and cleaning in S8 include: the texturing temperature is 70°C - 85°C, and the texturing time is 8 - 15 min.

[0080] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the front side in S8 is removed by a chain machine, and the speed of the driving roller of the chain machine is controlled to be 1.2 - 3.0 m / min.

[0081] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the front side in S8 is removed by a solution containing hydrofluoric acid, and the mass content of hydrofluoric acid in this solution is 5 wt% - 10 wt%.

[0082] The method for removing the mask layer in S8 of the present invention can be carried out with reference to the prior art as long as the mask layer can be removed. Exemplarily, the solution for removing the mask layer is a mixed solution containing hydrofluoric acid and water, the mass content of hydrofluoric acid is 5 wt% - 10 wt%, the treatment temperature is 20°C - 30°C, and the reaction time is 120 - 600 s.

[0083] In some preferred embodiments of the present invention, the deposition of the phosphorus-rich silicon oxide layer in S1 uses POCl 3 as a phosphorus source and is carried out by a low-pressure diffusion method. The conditions for low-pressure diffusion include: the ambient pressure is 30 - 100 mba, and the diffusion time is 5 - 20 min. The present invention uses an appropriate low-pressure diffusion deposition method to deposit the phosphorus-rich silicon oxide layer, which is beneficial to the uniform distribution of phosphorus in the silicon oxide layer.

[0084] In some preferred embodiments of the present invention, the time for high-temperature diffusion in S1 is 90 - 120 min, which is more conducive to enhancing the external gettering effect of phosphorus.

[0085] The silicon wafer of S1 in the present invention can be a raw wafer.

[0086] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the back side of the silicon wafer in S2 is removed by a chain machine, and the speed of the driving roller of the chain machine is controlled to be 1.2 - 3.0 m / min.

[0087] In some preferred embodiments of the present invention, the phosphorus-rich silicon oxide layer on the back side of the silicon wafer is removed by a solution containing hydrofluoric acid, and the mass content of hydrofluoric acid in this solution is 5 wt% - 10 wt%.

[0088] In some preferred embodiments of the present invention, single-sided polishing in S2 makes the single-sided etching depth of the silicon wafer 2-5 μm, preferably 2.5-5 μm, which is more conducive to improving the surface flatness of the back surface, thereby improving the passivation performance of the first semiconductor layer.

[0089] The first etching in S6 of the present invention can be, for example, laser etching, and the damaged layer corresponding to S7 is a laser damaged layer.

[0090] Preferably, the polishing in S7 makes the single-sided etching depth within 1 μm, preferably 0.6-1 μm, which can effectively remove the damaged layer and overplating under the condition of low etching amount, while preventing over-polishing from damaging the passivation film layer on the back surface.

[0091] In the present invention, the single-sided etching depth of the silicon wafer is obtained by calculation after weighing.

[0092] In some preferred embodiments of the present invention, the single-sided polishing in S2 uses a mixed polishing solution containing alkali, polishing additive and water, wherein the alkali is potassium hydroxide and / or sodium hydroxide, the mass content of the alkali is 2 wt%-5 wt%, and the mass content of the polishing additive is 0.5 wt%-2 wt%. The polishing additive is obtained by commercial purchase.

[0093] Preferably, the conditions for single-sided polishing in S2 include: the reaction temperature is 60-75 °C, and the reaction time is 90-150 s.

[0094] Preferably in the present invention, the solution used to clean and remove the PSG layer in S4 is a solution containing hydrofluoric acid, and the mass content of hydrofluoric acid in this solution is 1 wt%-5 wt%. Preferably, the conditions for cleaning and removing the PSG layer include: the reaction time is 1-3 min, and the reaction temperature is 20-30 °C.

[0095] In some preferred embodiments of the present invention, the polishing in S7 uses a mixed polishing solution containing alkali, polishing additive and water, wherein the alkali is potassium hydroxide and / or sodium hydroxide, the mass content of the alkali is 1 wt%-3 wt%, and the mass content of the polishing additive is 0.5 wt%-2 wt%. The polishing additive is obtained by commercial purchase.

[0096] Preferably, the conditions for polishing in S7 include: the reaction temperature is 60-75 °C, and the reaction time is 30-180 s.

[0097] The single-sided polishing in S2 and the polishing in S7 of the present invention can each independently use a tank cleaning machine.

[0098] In some preferred embodiments of the present invention, the method for preparing the back-contact battery with a front-side inverted pyramid structure further includes:

[0099] S9. A passivation layer and an anti-reflection layer are sequentially formed on the front surface of the silicon wafer obtained in S8;

[0100] S10, secondary cleaning to remove the anti-reflection layer and passivation layer on the back.

[0101] Preferably, the passivation layer includes a second tunneling oxide layer and a second doped amorphous layer. The front passivation layer adopts a tunneling amorphous structure, which is more conducive to taking into account the passivation of the front side and reducing the equipment cost of plate-type PECVD.

[0102] Further preferably, the thickness of the second tunneling oxide layer is 0.5-1 nm, and the thickness of the second doped amorphous layer is 1-5 nm. The thickness of the second tunneling oxide layer and the second doped amorphous layer only needs to be maintained at 50%-80% of the existing process to maintain the same passivation, and due to the thinning of the doped amorphous layer, the parasitic absorption of the film layer is reduced, which is more conducive to increasing the current, thereby improving the short-circuit current and battery efficiency of the back contact battery.

[0103] The second tunneling oxide layer, the second doped amorphous layer and the anti-reflection layer of the present invention can be independently prepared by, for example, a tubular PECVD method. The second doped amorphous layer is preferably N-type doped amorphous silicon.

[0104] The method of removing the anti-reflection layer and the passivation layer on the back side in S10 of the present invention can refer to the prior art respectively. Exemplarily, a chain cleaning machine is used to remove the anti-reflection layer, and the solution for removing the anti-reflection layer is an aqueous solution containing hydrofluoric acid, the mass content of hydrofluoric acid is 5wt%-10wt%, the reaction temperature is 20-35°C, and the speed of the chain cleaning machine transmission roller is 1.2-3.0m / min. A tank cleaning machine is used to remove the passivation layer, and the solution for removing the passivation layer is a low-concentration alkali solution, the alkali solution is an alkali solution with a mass content of 0.5wt%-2wt%, wherein the alkali can be potassium hydroxide and / or sodium hydroxide, the reaction temperature is 30-50°C, and the reaction time is 30-120s; after completely removing the back side coating, a standard RCA solution is used for cleaning to obtain a clean interface.

[0105] The type and thickness of the anti-reflection layer may refer to the corresponding range in the prior art. Exemplarily, the anti-reflection layer is silicon nitride, and the thickness of the silicon nitride is 70-120 nm.

[0106] The first semiconductor layer of the present invention includes a first passivation layer and a first doped silicon layer, and the second semiconductor layer includes a second passivation layer and a second doped silicon layer. The first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. The first doped silicon layer and the second doped silicon layer are each independently polycrystalline silicon, amorphous silicon or microcrystalline silicon. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer. One of the first doped polycrystalline silicon layer and the second doped silicon layer is N-type and the other is P-type.

[0107] In some preferred embodiments of the present invention, the first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer. The use of a combined passivation structure, in conjunction with the specific preparation method of the present invention, is more conducive to improving the short-circuit current and battery efficiency of the battery. The intrinsic silicon layer is preferably intrinsic amorphous silicon, and the second doped silicon layer is preferably doped amorphous silicon or doped microcrystalline silicon.

[0108] For the parameters such as the thickness of each film layer contained in the first semiconductor layer and the second semiconductor layer of the present invention, reference can be made to the prior art. Exemplarily, the thickness of the first tunneling oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 70-300 nm, and the effective doping concentration is greater than 5e18 cm -3 , the thickness of the intrinsic silicon layer is 5-15 nm, the thickness of the second doped silicon layer is 5-20 nm, and the effective doping concentration is 1e18 cm -3 -5e19 cm -3 .

[0109] In some preferred embodiments of the present invention, the preparation method of the back contact battery provided with the front-side inverted pyramid structure further includes:

[0110] S12. Perform a second etching opening on a part of the second semiconductor layer on the back surface of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area;

[0111] S13. Deposit a conductive film layer on the back surface obtained in S12;

[0112] S14. Perform a third etching opening on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form an isolation groove;

[0113] S15. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located, respectively.

[0114] In a second aspect, the present invention provides a back contact battery provided with a front-side inverted pyramid structure, which is obtained by the preparation method of the back contact battery provided with the front-side inverted pyramid structure described in the first aspect.

[0115] The embodiments of the present invention are described in detail below. They are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention.

[0116] Example 1

[0117] A back contact battery is obtained through the following steps:

[0118] S1. Perform gettering treatment on the original silicon wafer 1 (N-type monocrystalline silicon wafer);

[0119] Using POCl3 As the source wafer, a phosphorus-rich silicon oxide layer with a thickness of 300 Å and a phosphorus doping concentration of 1e19 cm is deposited on the surface of the N-type monocrystalline silicon wafer 1 by low-pressure diffusion method. -3 Through high-temperature diffusion treatment, phosphorus is diffused on the surface, so that the metal impurities in the wafer 1 are adsorbed on the surface of the wafer 1; the high-temperature diffusion process is heat treatment at 800 °C for 100 min; the conditions of low-pressure diffusion include: the ambient pressure is 50 mba, and the diffusion time is 10 min.

[0120] S2. Remove the phosphorus-rich silicon oxide layer on the back surface, and then perform single-sided polishing on this surface;

[0121] Use a chain machine to remove the phosphorus-rich silicon oxide layer on the back surface of the wafer 1 in S1. The solution used is a solution containing hydrofluoric acid. The mass content of hydrofluoric acid is 8 wt%, the reaction temperature is room temperature, and the speed of the driving roller of the chain machine is 2.0 m / min.

[0122] Use a tank cleaning machine to perform single-sided polishing on the wafer 1 in S2. The polishing solution used is a mixed solution of potassium hydroxide, polishing additive and water. Among them, the mass content of potassium hydroxide is 3 wt%, the mass content of the polishing additive is 0.5 wt%, the reaction temperature is 65 °C, the reaction time is 120 s, and the single-sided etching depth of the wafer 1 after polishing is 3 μm;

[0123] S3. Form a first semiconductor layer on the polished surface of the wafer 1 in S3. The first semiconductor layer includes a first tunneling oxide layer 2 (tunneling silicon oxide) and a first doped polysilicon layer 3 (N-type) formed in sequence on the back surface.

[0124] The thickness of the first tunneling oxide layer 2 is 1.5 nm, and the thickness of the first doped polysilicon layer 3 is 100 nm, and the effective doping concentration is 5e19 cm -3 .

[0125] S4. Clean and remove the PSG layer on the surface of the first semiconductor layer;

[0126] The solution for removing the PSG layer is a solution containing hydrofluoric acid. The mass content of hydrofluoric acid is 2 wt%, the reaction time is 2 min, and the reaction temperature is 25 °C.

[0127] S5. Deposit a mask layer on the first semiconductor layer;

[0128] S6. Perform first laser etching on the first semiconductor layer on the mask layer on the back surface of the wafer 1 in S4 to remove the mask layer and the corresponding part of the first semiconductor layer, and form second semiconductor opening regions W1 distributed at intervals;

[0129] S7. Polish to remove the laser damage layer on the back surface and the first semiconductor coating layer on the front surface;

[0130] A polishing method is used to remove the laser damage layer in the second semiconductor opening area W1 and the wrap-around coating layer on the front side of the first semiconductor. The polishing solution used is a mixed solution of sodium hydroxide, a polishing additive (commercial product), and water, where the mass content of sodium hydroxide is 2 wt%, the mass content of the polishing additive is 0.5 wt%, the reaction temperature is 65 °C, the reaction time is 120 s, and the single-sided etching depth of polishing is 0.8 μm.

[0131] S8. Remove the phosphorus-rich silicon oxide layer on the front side, and then perform texturing cleaning. At the same time, an inverted pyramid texture surface and a regular pyramid texture surface are respectively formed in the second semiconductor opening areas W1 on the front and back sides. The inverted pyramid texture surface is as Figure 1 shown, and all mask layers are removed;

[0132] A chain machine is used to remove the phosphorus-rich silicon oxide layer on the front side of the S8 silicon wafer 1. The solution used is a solution containing hydrofluoric acid, and the mass content of hydrofluoric acid is 6 wt%. The reaction temperature is at room temperature, and the speed of the driving roller of the chain machine is 2 m / min.

[0133] In the texturing cleaning, the texturing is carried out in two steps: first, the first texturing is carried out using a first texturing solution including a first cyclodextrin-containing texturing additive, and then the second texturing is carried out using a second texturing solution including a second cyclodextrin-containing texturing additive.

[0134] Among them, for the first texturing: a first texturing solution of potassium hydroxide, a first cyclodextrin-containing texturing additive, and water is used, where the mass content of potassium hydroxide is 1%, and the mass content of the first cyclodextrin-containing texturing additive is 0.5%; the texturing time is 10 min, and the texturing temperature is 75 °C. The first cyclodextrin-containing texturing additive contains the following components: 0.05 wt% of cyclodextrin, 0.1 wt% of sodium lignosulfonate, 0.5 wt% of sodium alginate, 0.08 wt% of sodium benzoate, and the balance is water.

[0135] For the second texturing: a second texturing solution of potassium hydroxide, a second cyclodextrin-containing texturing additive, and water is used, where the mass content of potassium hydroxide is 1 wt%, and the mass content of the texturing additive is 0.5 wt%; the texturing time is 4 min, and the texturing temperature is 70 °C. The components of the second cyclodextrin-containing texturing additive are basically the same as those of the first cyclodextrin-containing texturing additive, except that the concentration of the nucleating agent cyclodextrin contained is lower, specifically 0.001 wt% of cyclodextrin.

[0136] After two-step texturing, the reflectivity of the front-side inverted pyramid is 7.23%, and the reflectivity of the back-side regular pyramid is 11.05%. The lateral dimension of the pyramid on the front-side inverted pyramid texture surface is 0.8 - 1.0 μm, and the height of the pyramid is 0.5 - 0.8 μm. The lateral dimension of the pyramid on the back-side regular pyramid texture surface is 1 - 2 μm, and the height of the pyramid is 1.0 - 1.5 μm. The electron microscope images of the front-side inverted pyramid structure and the back-side regular pyramid structure are respectively as Figure 3 , Figure 4 shown.

[0137] The method for removing part of the mask layer is solution etching. The solution is a mixed solution of hydrofluoric acid and water. The concentration of hydrofluoric acid is 7wt%, the treatment temperature is 25°C, and the reaction time is 300 s.

[0138] S9. On the front side of the silicon wafer 1, a passivation layer and an antireflection layer 8 are sequentially formed by the tube PECVD method;

[0139] The passivation layer includes a second tunneling oxide layer 6 and an N-type second doped amorphous layer 7; the thickness of the second tunneling oxide layer 6 is 0.5 nm, and the thickness of the second doped amorphous layer 7 is 2 nm; the antireflection layer 8 is silicon nitride, and the thickness of the silicon nitride is 110 nm.

[0140] S10. Perform secondary cleaning to remove the antireflection layer and the passivation layer overcoating on the back side;

[0141] Use a chain cleaner to remove the antireflection layer overcoating. The solution for removing the antireflection layer overcoating is an aqueous solution containing hydrofluoric acid. The mass content of hydrofluoric acid is 6wt%, the reaction temperature is 25°C, and the speed of the drive roller of the chain cleaner is 2 m / min. Use a tank cleaner to remove the passivation layer overcoating. The solution for removing the passivation layer overcoating is a low-concentration alkali solution. The alkali solution is a KOH solution with a mass content of 1wt%. The reaction temperature is 40°C, and the reaction time is 80 s; after completely removing the overcoating on the back side, clean it with a standard RCA solution to obtain a clean interface.

[0142] S11. Form a second semiconductor layer on the back side. The second semiconductor layer includes an intrinsic amorphous silicon layer 4 and a second doped amorphous silicon layer 5 (P-type) sequentially formed on the back side;

[0143] The thickness of the intrinsic amorphous silicon layer 4 is 10 nm, the thickness of the second doped amorphous silicon layer 5 is 15 nm, and the effective doping concentration is 5e18 cm -3 .

[0144] S12. Perform a second etching on the polished area on the back side of the S6 silicon wafer to remove the second semiconductor layer and form a first semiconductor opening region W2;

[0145] S13. Form a transparent conductive film layer 9 on the entire back side of the S7 silicon wafer;

[0146] S14. Perform a third etching on the back transparent conductive film layer 9 of the S8 silicon wafer to form isolation grooves W3; after etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0147] S15. Form metal electrodes 10 on the outer surfaces of the regions corresponding to the first semiconductor opening region W2 and the second semiconductor opening region W1 on the back of the silicon wafer 1, as Figure 2 shown.

[0148] Example 2

[0149] Carry out according to the method of Example 1, the difference is that the mass content of cyclodextrin in the first cyclodextrin-containing texturing additive is adjusted to 0.01 wt%, the contents of other solutes remain unchanged, and the balance is water. The reflectivity of the front inverted pyramid textured surface obtained correspondingly is 7.52%, and the reflectivity of the back regular pyramid textured surface is 11.38%; the corresponding pyramid lateral dimension of the front inverted pyramid textured surface is 1.0 - 1.5 μm, the pyramid height is 0.5 - 0.8 μm, and the corresponding pyramid lateral dimension of the back regular pyramid textured surface is 1.5 - 2.5 μm, the pyramid height is 1.0 - 1.5 μm.

[0150] Example 3

[0151] Carry out according to the method of Example 1, the difference is that the mass content of cyclodextrin in the second cyclodextrin-containing texturing additive is adjusted to 0.0005 wt%, the contents of other solutes remain unchanged, and the balance is water. The reflectivity of the front inverted pyramid textured surface obtained correspondingly is 7.15%, and the reflectivity of the back regular pyramid textured surface is 11.28%.

[0152] Example 4

[0153] Carry out according to the method of Example 1, the difference is that the time of low-pressure diffusion in S1 is 5 min. The thickness of the phosphorus-rich silicon oxide layer obtained correspondingly is 100 Å, and the phosphorus doping concentration is 1.8e19 cm -3 .

[0154] Example 5

[0155] Carry out according to the method of Example 1, the difference is that the polishing in S2 is controlled so that the single-sided etching depth is 2 μm. The process to be adjusted to meet this condition is: the mass content of potassium hydroxide in the polishing solution is 2 wt%, and the reaction temperature is 60 °C.

[0156] Example 6

[0157] Carry out according to the method of Example 1, the difference is that the polishing in S7 is controlled so that the single-sided etching depth is 0.5 μm. The process to be adjusted to meet this condition is: the reaction time is 60 s.

[0158] Comparative Example 1

[0159] It was carried out according to the method of Example 1, except that in the conventional post-texturing method (i.e., a first semiconductor layer and a mask layer were first formed on the back surface of a double-sided polished silicon wafer, then a second semiconductor opening region was formed, and then texturing and cleaning were carried out. After that, a second semiconductor layer was deposited on the back surface, and a passivation layer and an antireflection layer were deposited on the front surface; then a first semiconductor opening region was formed), in the texturing and cleaning step, a conventional MACE (metal-assisted chemical etching) method was used to form an inverted pyramid texture on both the front and back surfaces. Specifically, a copper catalyst and an etching solution were used to form an inverted pyramid texture on both the front and back surfaces, and then the metal ions on the surface were removed by cleaning.

[0160] Comparative Example 2

[0161] It was carried out according to the method of Example 1, except that in S2, a trough cleaning machine was used to remove the phosphorus-rich silicon oxide layer on both sides. In the subsequent steps, the damage of the diamond wire marks on the front surface could not be retained, resulting in the front surface being polished, so the front surface texture was a regular pyramid texture.

[0162] Comparative Example 3

[0163] It was carried out according to the method of Example 1, except that in S8, the cyclodextrin-containing texturing additive was replaced with a conventional texturing additive: its composition was 0.05 wt% of ammonium salt of hydrolyzed polyacrylonitrile, 0.1 wt% of sodium dodecyl sulfate, 0.5 wt% of polyvinyl alcohol, 0.08 wt% of sodium benzoate, and the balance was water. The dosage of the texturing additive remained unchanged.

[0164] Comparative Example 4

[0165] It was carried out according to the method of Example 1, except that in S8, cyclodextrin was not added to the specific texturing additive.

[0166] Test Example

[0167] The back-contact batteries obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0168] Table 1

[0169]

[0170] From the above results, it can be seen that compared with the comparative examples, by adopting the embodiment scheme of the present invention, different pyramid morphologies on the front and back surfaces can be formed, which is beneficial to effectively reducing the front surface reflectivity while ensuring good back surface passivation performance, thereby being beneficial to improving the open-circuit voltage, short-circuit current, and battery efficiency.

[0171] Furthermore, according to Embodiment 1 and Embodiments 2-6, it can be seen that by adopting the preferred solution of the present invention, it is more conducive to improving the open-circuit voltage, short-circuit current and battery efficiency.

[0172] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A method for preparing a back contact battery with a front inverted pyramid structure, characterized in that: The steps include: S1. The silicon wafer is subjected to a gettering treatment. The gettering treatment process includes: depositing a phosphorus-rich silicon oxide layer with a thickness of 100-1000Å on both sides of the silicon wafer. The phosphorus doping concentration of the phosphorus-rich silicon oxide layer is 1e18cm -3 -5e19cm -3 ; Then high temperature diffusion is carried out, and the temperature of high temperature diffusion is 700-900℃; S2, removing the phosphorus-rich silicon oxide layer on the back of the silicon wafer, and then single-sided polishing the surface; S3, forming a first semiconductor layer on the polished surface of the silicon wafer S2; S4, cleaning and removing the PSG layer naturally formed on the surface of the first semiconductor layer; S5, depositing a mask layer on the surface of the first semiconductor layer; S6, performing a first etching on the mask layer on the back side of the S5 silicon wafer to remove the mask layer and a corresponding portion of the first semiconductor layer, thereby forming second semiconductor opening regions distributed at intervals; S7, polishing to remove the damaged layer in the second semiconductor opening area on the back side and the first semiconductor coating layer on the front side; S8, removing the phosphorus-rich silicon oxide layer on the front side, and then using a texturing liquid including alkali and a cyclodextrin-containing texturing additive to perform texturing cleaning, so as to form an inverted pyramid velvet surface on the front side, and at the same time form a positive pyramid velvet surface in the second semiconductor opening area on the back side, and remove more than half of the thickness of the mask layer; the reflectivity of the inverted pyramid velvet surface on the front side is 7%-8%, and the reflectivity of the positive pyramid velvet surface on the back side is 11%-12%; the cyclodextrin-containing texturing additive also includes: based on the total amount of the texturing additive, 0.01wt%-0.5wt% of sodium lignin sulfonate, 0.1wt%-5wt% of sodium alginate, and 0.05wt%-0.1wt% of sodium benzoate; S8: the texturing cleaning comprises at least two steps: firstly, a first texturing liquid comprising a first cyclodextrin-containing texturing additive is used for a first texturing, and then a second texturing liquid comprising a second cyclodextrin-containing texturing additive is used for a second texturing, wherein the mass content of cyclodextrin in the first cyclodextrin-containing texturing additive is 0.001wt%-0.1wt%, and the mass content of cyclodextrin in the second cyclodextrin-containing texturing additive is 0.0001wt%-0.01wt%; S11, forming a second semiconductor layer on the back side.

2. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: In S8, the corresponding pyramid lateral size of the inverted pyramid velvet surface on the front side is 0.8-2μm, and the pyramid height is 0.5-0.8μm, and the corresponding pyramid lateral size of the positive pyramid velvet surface on the back side is 1-3μm, and the pyramid height is 1.0-1.5μm.

3. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: The alkali in the S8 texturing solution includes sodium hydroxide and / or potassium hydroxide, the mass content of the alkali in the texturing solution is 1wt%-2wt%, and the mass content of the cyclodextrin texturing additive is 0.5wt%-2wt%.

4. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1 or 3, characterized in that: The conditions for the texturing and cleaning in S8 include: the texturing temperature is 70°C-85°C, and the texturing time is 8-15 minutes.

5. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: In S8, the phosphorus-rich silicon oxide layer on the front side is removed by a chain machine, and the speed of the transmission roller of the chain machine is controlled to be 1.2-3.0m / min.

6. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1 or 5, characterized in that: In S8, the phosphorus-rich silicon oxide layer on the front side is removed by using a solution containing hydrofluoric acid, wherein the mass content of the hydrofluoric acid in the solution is 5wt%-10wt%.

7. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: The deposition of the phosphorus-rich silicon oxide layer in S1 is carried out by low-pressure diffusion using POCl3 as the phosphorus source. The conditions of the low-pressure diffusion include: an ambient pressure of 30-100 mba and a diffusion time of 5-20 min. And / or, the time of high temperature diffusion in S1 is 90-120 minutes.

8. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: In S2, the phosphorus-rich silicon oxide layer on the back of the silicon wafer is removed by a chain machine, and the speed of the chain machine transmission roller is controlled to be 1.2-3.0m / min; and / or, The phosphorus-rich silicon oxide layer on the back of the silicon wafer is removed by using a solution containing hydrofluoric acid, wherein the mass content of hydrofluoric acid in the solution is 5wt%-10wt%.

9. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: The single-side polishing in S2 makes the single-side etching depth of the silicon wafer 2-5 μm; and / or the polishing in S7 makes the single-side etching depth within 1 μm.

10. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1 or 9, characterized in that: The single-side polishing in S2 uses a mixed polishing solution containing alkali, polishing additives and water, wherein the alkali is potassium hydroxide and / or sodium hydroxide, the mass content of the alkali is 2wt%-5wt%, and the mass content of the polishing additive is 0.5wt%-2wt%; the conditions for single-side polishing include: reaction temperature of 60-75°C, reaction time of 90-150s; and / or, The polishing in S7 uses a mixed polishing solution containing alkali, polishing additives and water, wherein the alkali is potassium hydroxide and / or sodium hydroxide, the mass content of the alkali is 1wt%-3wt%, and the mass content of the polishing additive is 0.5wt%-2wt%; the polishing conditions include: reaction temperature of 60-75°C, reaction time of 30-180s.

11. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: The method for preparing a back contact battery with a front inverted pyramid structure further comprises: S9, forming a passivation layer and an anti-reflection layer in sequence on the front side of the silicon wafer obtained in S8; wherein the passivation layer comprises a second tunneling oxide layer and a second doped amorphous layer; the thickness of the second tunneling oxide layer is 0.5-1 nm, and the thickness of the second doped amorphous layer is 1-5 nm; S10, secondary cleaning to remove the anti-reflection layer and passivation layer on the back.

12. The method for preparing a back contact battery with a front inverted pyramid structure according to claim 1, characterized in that: The first semiconductor layer includes a first tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer; and / or, The method for preparing a back contact battery with a front inverted pyramid structure further comprises: S12, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S13, depositing a conductive film layer on the back surface obtained in S12; S14, performing a third etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation groove; S15, forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

13. A back contact battery with a front inverted pyramid structure, characterized in that: The battery is prepared by the method for preparing a back-contact battery with a front inverted pyramid structure as described in any one of claims 1 to 12.

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