Display substrate and display device

Abstract

The display substrate comprises a substrate, a first shielding structure arranged on the substrate, a frame connecting structure, a plurality of pixel circuits, a plurality of data lines and a plurality of multiplexing circuits. The plurality of pixel circuits and the plurality of data lines are located in the display area, and the plurality of data lines are connected with the plurality of pixel circuits. The plurality of multiplexing circuits are located in the peripheral area and are connected with the plurality of data lines. The first shielding structure is located in the display area and located on the side, close to the substrate, of the pixel circuits. The orthographic projection of the first shielding structure on the substrate is at least partially overlapped with the orthographic projection of the plurality of pixel circuits on the substrate. The frame connecting structure is located in the peripheral area and integrated with the first shielding structure. The frame connecting structure comprises a first connecting structure located in the frame corner area, and the first connecting structure is located on the side, close to the display area, of the multiple multiplexing circuits in the frame corner area and extends in a step shape along the edge of the display area.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present application provide a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, including: a substrate, a first shielding structure arranged on the substrate, a frame connection structure, a plurality of pixel circuits, a plurality of data lines and a plurality of multiplexing circuits. The substrate includes a display area and a peripheral area located at least on one side of the display area. The peripheral area includes: at least one first peripheral area extending along a first direction, at least one second peripheral area extending along a second direction and at least one frame corner area. At least one frame corner area is connected between adjacent first peripheral areas and second peripheral areas. The first direction intersects with the second direction, for example, the first direction may be perpendicular to the second direction. A plurality of pixel circuits and a plurality of data lines are located in the display area, and the plurality of data lines extend along the second direction and are connected to the plurality of pixel circuits. A plurality of multiplexing circuits are located in the peripheral area and are connected to the plurality of data lines. The first shielding structure is located in the display area and is located on a side of the plurality of pixel circuits close to the substrate. The orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the plurality of pixel circuits on the substrate. The frame connection structure is located in the peripheral area and is an integral structure with the first shielding structure. The frame connection structure includes: a first connection structure located in the frame corner area, the first connection structure extends in a stepped manner along the edge of the display area, and the first connection structure is located on a side of multiple multiplexing circuits in the frame corner area close to the display area.

[0006] In some exemplary embodiments, the display substrate further includes: a plurality of first signal lines, a plurality of first transfer holes, and a plurality of transfer electrodes. The plurality of first signal lines are located in the display area, extend along the first direction, and are connected to the plurality of pixel circuits. The plurality of first transfer holes and the plurality of transfer electrodes are located in the peripheral area; the plurality of transfer electrodes are connected to the first ends of the plurality of first signal lines extending to the peripheral area through the plurality of first transfer holes. The orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the plurality of first transfer holes in the frame corner area on the substrate.

[0007] In some exemplary embodiments, the first connection structure includes: a plurality of first connection bars extending along the first direction, and a plurality of second connection bars extending along the second direction, wherein the plurality of first connection bars and the plurality of second connection bars are connected at intervals to form a step shape.

[0008] In some exemplary embodiments, the first connection structure is located on a side of the plurality of first transfer holes in the corner area of ​​the frame away from the display area.

[0009] In some exemplary embodiments, at least one of the plurality of first connecting bars is in the shape of a straight bar extending along the first direction, and at least one of the plurality of second connecting bars is in the shape of a straight bar extending along the second direction.

[0010] In some exemplary embodiments, the border connection structure also includes: a plurality of first auxiliary connecting strips located in the border corner area and extending along the first direction, and a plurality of second auxiliary connecting strips extending along the second direction, the plurality of first auxiliary connecting strips and the plurality of second auxiliary connecting strips are located on the first connection structure and a side of the plurality of first transfer holes in the border corner area close to the display area, the plurality of first auxiliary connecting strips, the plurality of second auxiliary connecting strips and the first connection structure are connected to form a plurality of first closed areas, and each first closed area surrounds at least one first transfer hole among the plurality of first transfer holes.

[0011] In some exemplary embodiments, the second connection strip of the first connection structure is located on a side of the plurality of first transfer holes in the frame corner area close to the display area. The first connection strip of the first connection structure includes a straight line segment and a folded line segment extending along the first direction, the folded line segment is located on a side of the plurality of first transfer holes close to the display area in the second direction, and the folded line segment is bent toward the display area.

[0012] In some exemplary embodiments, the display substrate further comprises: a plurality of data lead lines and a plurality of second transfer holes located in the peripheral area. The plurality of data lead lines are connected to the plurality of data lines through the plurality of second transfer holes; and the orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the plurality of second transfer holes in the frame corner area on the substrate.

[0013] In some exemplary embodiments, the first connection structure is located at a side of the plurality of first transfer holes and the plurality of second transfer holes in the corner area of ​​the frame close to the display area.

[0014] In some exemplary embodiments, the multiplexing circuit includes a plurality of multiplexing control transistors. The display substrate further includes: a second shielding structure located in the corner area of ​​the frame, the second shielding structure having an orthographic projection on the substrate covering an orthographic projection of an active layer of the plurality of multiplexing control transistors of the multiplexing circuit on the substrate, and the second shielding structure and the first connecting structure are an integrated structure.

[0015] In some exemplary embodiments, the border connection structure also includes: a second connection structure located in the corner area of ​​the border, the second connection structure extending in a stepped manner along the edge of the display area, and a plurality of multiplexing circuits located in the corner area of ​​the border are located on a side away from the first connection structure; the second connection structure and the second shielding structure are an integrated structure.

[0016] In some exemplary embodiments, the border connection structure also includes: a third connection structure located in the corner area of ​​the border and in a mesh shape, the third connection structure is located on the side of the multiple multiplexing circuits in the corner area of ​​the border away from the display area, and is an integrated structure with the second shielding structure.

[0017] In some exemplary embodiments, the border connection structure further includes: a third connection structure located in the border corner area and in a mesh shape, the third connection structure being located on a side of the multiple multiplexing circuits in the border corner area away from the display area and being an integral structure with the first connection structure.

[0018] In some exemplary embodiments, the third connecting structure includes: a plurality of third connecting bars extending along the first direction, a plurality of fourth connecting bars extending along the second direction, and a fifth connecting bar, the plurality of third connecting bars are connected to the plurality of fourth connecting bars, the fifth connecting bar is connected to ends of the plurality of third connecting bars away from the display area, and the fifth connecting bar is located on a side of the plurality of third connecting bars and the plurality of fourth connecting bars away from the display area.

[0019] In some exemplary embodiments, the fifth connecting strip is an arc segment extending along an edge of the display area.

[0020] In some exemplary embodiments, the peripheral area includes: two first peripheral areas, two second peripheral areas and four border corner areas, the two first peripheral areas include: a first border area and a second border area, the two second peripheral areas include: a third border area and a fourth border area, the four border corner areas include: a first border corner area, a second border corner area, a third border corner area and a fourth border corner area, the first border corner area is connected between the first border area and the third border area, the second border corner area is connected between the first border area and the fourth border area, the third border corner area is connected between the second border area and the third border area, and the fourth border corner area is connected between the second border area and the fourth border area. The plurality of multiplexing circuits are arranged in the first border area, the first border corner area and the second border corner area; the first connection structure is located in the first border corner area and the second border corner area.

[0021] On the other hand, this embodiment provides a display device, including the display substrate as mentioned above.

[0022] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0024] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0026] Figure 3 is a partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present disclosure;

[0027] Figure 4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0028] Figure 5 for Figure 1 A partial enlarged schematic diagram of the middle area S1;

[0029] Fig. 6A for Figure 5 Schematic diagram of the bottom blocking metal layer in ;

[0030] Figure 6B for Figure 5 Schematic diagram of the semiconductor layer in FIG.

[0031] Figure 6C for Figure 5 A schematic diagram of a display substrate after forming a first conductive layer;

[0032] Fig.6D for Figure 5 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0033] Fig. 6E for Figure 5 A schematic diagram of a via formed by the bottom shielding metal layer and the fourth insulating layer;

[0034] Fig. 6F for Figure 5 A schematic diagram of a display substrate after a third conductive layer is formed;

[0035] Figure 6G for Fig. 6F A schematic diagram of a third conductive layer in FIG.

[0036] Figure 6H for Figure 5 A schematic diagram of a fourth conductive layer in FIG.

[0037] Figure 7 for Figure 1 Another partial enlarged schematic diagram of the middle area S1;

[0038] Fig. 8A for Figure 7 Schematic diagram of the bottom blocking metal layer in ;

[0039] Figure 8B for Figure 7 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0040] Figure 8C for Figure 7 A schematic diagram of a via formed by a bottom shielding metal layer and a fourth insulating layer;

[0041] Fig.8D for Figure 7 A schematic diagram of a display substrate after a third conductive layer is formed;

[0042] Fig.9A for Figure 1 Another partial enlarged schematic diagram of the middle area S1;

[0043] Fig. 9B for Fig.9A Schematic diagram of the bottom blocking metal layer in ;

[0044] Fig. 9C for Fig.9A A schematic diagram of a via formed by a bottom shielding metal layer and a fourth insulating layer;

[0045] Fig.10 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0046] Fig.11A for Fig.10 A partial enlarged schematic diagram of the middle area S2;

[0047] Fig. 11B for Fig.11A Schematic diagram of the bottom blocking metal layer in ;

[0048] Fig. 11C for Fig.11A A schematic diagram of a via formed by a bottom shielding metal layer and a fourth insulating layer;

[0049] Fig. 12A for Fig.10 Another partial enlarged schematic diagram of the middle area S2;

[0050] Fig. 12B for Fig. 12A Schematic diagram of the bottom blocking metal layer in ;

[0051] Fig. 12C for Fig. 12A A schematic diagram of a via formed by a bottom shielding metal layer and a fourth insulating layer;

[0052] Fig.13 is another partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present disclosure;

[0053] Fig.14A for Figure 1 Another partial enlarged schematic diagram of the middle area S1;

[0054] Fig. 14B for Fig.14A A schematic diagram of a bottom shielding metal layer, a first semiconductor layer, a second conductive layer, a third conductive layer and a fifth conductive layer in FIG.

[0055] Fig. 14C for Fig.14A A schematic diagram of a plurality of vias formed by a bottom shielding metal layer and a fourth insulating layer;

[0056] Fig.14D for Fig.14A A schematic diagram of a display substrate after a third conductive layer is formed;

[0057] Fig.15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0059] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0060] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0061] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0062] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0063] In this specification, connection may include "electrical connection". "Electrical connection" includes the situation where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.

[0064] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0065] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged. In addition, the gate electrode may also be called a control electrode.

[0066] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0067] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0068] In the present disclosure, "about" and "substantially" mean that the limits are not strictly defined and the situation within the range of process and measurement errors is allowed. In the present disclosure, "same" may include the situation where the index values ​​differ by less than 10%.

[0069] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the present disclosure, "A extends along direction B" means "the main part of A extends along direction B".

[0070] The “A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, or the distance between the surfaces of A and B close to the substrate and the substrate is basically the same, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. “The orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A contains the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The “shape of A” mentioned in the present disclosure means the shape of the orthographic projection of A on the substrate.

[0071] In some implementations, by providing a bottom shielding metal (BSM) in the display area of ​​the display substrate, the afterimage can be improved. In order to maintain the voltage uniformity of the bottom shielding metal, a ring winding is usually provided in the peripheral area to connect the extended end of the bottom shielding metal in the display area. However, this method requires occupying more peripheral space, which is not conducive to narrow frame design. Moreover, in order to effectively prevent static electricity, the bottom shielding metal is usually connected to the first power supply signal VDD. The ring winding located in the peripheral area and transmitting the first power supply signal VDD is easy to overlap with other circuits (such as multiplexing circuits) or wiring (such as gate drive signal wiring) and cause poor display and other problems.

[0072] The present embodiment provides a display substrate, comprising: a substrate, a first shielding structure arranged on the substrate, a frame connection structure, a plurality of pixel circuits, a plurality of data lines and a plurality of multiplexing circuits. The substrate comprises a display area and a peripheral area located at least on one side of the display area. The peripheral area comprises: at least one first peripheral area extending along a first direction, at least one second peripheral area extending along a second direction and at least one frame corner area. The frame corner area is connected between adjacent first peripheral areas and second peripheral areas. The first direction intersects with the second direction, for example, the first direction may be perpendicular to the second direction. A plurality of pixel circuits and a plurality of data lines are located in the display area, and the plurality of data lines extend along the second direction and are connected to the plurality of pixel circuits. A plurality of multiplexing circuits are located in the peripheral area and are connected to the plurality of data lines. The first shielding structure is located in the display area and is located on one side of the plurality of pixel circuits close to the substrate. The orthographic projection of the first shielding structure on the substrate at least partially overlaps with the orthographic projection of the plurality of pixel circuits on the substrate. The frame connection structure is located in the peripheral area and is an integral structure with the first shielding structure. The frame connection structure includes: a first connection structure located in the frame corner area, the first connection structure extends in a stepped manner along the edge of the display area, and the first connection structure is located on a side of multiple multiplexing circuits in the frame corner area close to the display area.

[0073] This embodiment optimizes the design of the frame connection structure of the bottom shielding metal layer so that the first connection structure in the frame corner area extends in a stepped manner on the side of the multiplexing circuit close to the display area, which can effectively reduce the impact of the frame connection structure on the multiplexing circuit and is conducive to achieving a narrow frame design.

[0074] In some exemplary embodiments, the display substrate may further include: a plurality of first signal lines located in the display area, a plurality of first transfer holes located in the peripheral area, and a plurality of transfer electrodes. The plurality of first signal lines may extend in a first direction and be connected to a plurality of pixel circuits. The plurality of transfer electrodes may be connected to the first end portions of the plurality of first signal lines extending to the peripheral area through the plurality of first transfer holes. The orthographic projection of the first connection structure on the substrate may not overlap with the orthographic projection of the plurality of first transfer holes in the frame corner area on the substrate. In some examples, the first connection structure may be located on the side of the plurality of first transfer holes in the frame corner area away from the display area. In other examples, the first connection structure may include a plurality of first connection bars extending in the first direction and a plurality of second connection bars extending in the second direction, and the second connection bars of the first connection structure may be located on the side of the plurality of first transfer holes in the frame corner area close to the display area. This example reduces the risk of electrostatic discharge (ESD) and avoids defects by designing the first connection structure to avoid the first transfer hole.

[0075] In some exemplary embodiments, the display substrate may further include: a second shielding structure located in a corner region of the frame, wherein the orthographic projection of the second shielding structure on the substrate may cover the orthographic projection of the active layer of the multiplexing control transistors of the multiplexing circuit in the corner region of the frame on the substrate. The second shielding structure and the first connecting structure may be an integral structure. In this example, by providing the second shielding structure below the multiplexing circuit, the stability of the multiplexing control transistor of the multiplexing circuit may be increased.

[0076] The solution of this embodiment is described below by means of some examples.

[0077] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate of this embodiment may include: a display area AA and a frame area BB surrounding the periphery of the display area AA. The frame area BB may include: two first peripheral areas extending along the first direction X (for example, including the first frame area B1 and the second frame area B2), two second peripheral areas extending along the second direction Y (for example, including the third frame area B3 and the fourth frame area B4), and a plurality of frame corner areas connected between adjacent first peripheral areas and second peripheral areas (for example, including the first frame corner area C1, the second frame corner area C2, the third frame corner area C3 and the fourth frame corner area C4). For example, the first frame area B1 may be the lower frame area of ​​the display substrate, the second frame area B2 may be the upper frame area of ​​the display substrate, the third frame area B3 may be the left frame area of ​​the display substrate, and the fourth frame area B4 may be the right frame area of ​​the display substrate.

[0078] In some examples, the first frame corner area C1 is connected between the first frame area B1 and the third frame area B3, the second frame corner area C2 is connected between the first frame area B1 and the fourth frame area B4, the third frame corner area C3 is connected between the third frame area B3 and the second frame area B2, and the fourth frame corner area C4 is connected between the second frame area B2 and the fourth frame area B4. The first frame corner area C1, the second frame corner area C2, the third frame corner area C3, and the fourth frame corner area C4 may each correspond to the arc edge of the display area AA. The edges of the first frame corner area C1, the second frame corner area C2, the third frame corner area C3, and the fourth frame corner area C4 away from the display area AA may all be curved edges (e.g., arc edges). The first frame corner area C1 and the second frame corner area C2 may be referred to as lower corner areas, and the third frame corner area C3 and the fourth frame corner area C4 may be referred to as upper corner areas.

[0079] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit may be P-type transistors or may be N-type transistors. Using the same type of transistors in the pixel circuit may simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In other examples, the plurality of transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0080] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and a light-emitting functional layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0081] In some examples, a pixel unit of display area AA may include: three light-emitting elements, and the three light-emitting elements may include: a light-emitting element emitting a first color light (e.g., red light), a light-emitting element emitting a second color light (e.g., green light), and a light-emitting element emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In other examples, a pixel unit may include four light-emitting elements, and the four light-emitting elements may include a light-emitting element emitting red light, a light-emitting element emitting green light, a light-emitting element emitting blue light, and a light-emitting element emitting white light. For another example, a pixel unit may include four light-emitting elements, and the four light-emitting elements may include a light-emitting element emitting red light, a light-emitting element emitting blue light, and two light-emitting elements emitting green light.

[0082] In some examples, the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three light-emitting elements, the three light-emitting elements may be arranged in parallel horizontally, vertically, or in a triangle; when a pixel unit includes four light-emitting elements, the four light-emitting elements may be arranged in parallel horizontally, vertically, or in a square. However, this embodiment is not limited to this.

[0083] Figure 2 FIG. 1 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is described by taking a 7T1C structure as an example. Figure 2 As shown, the pixel circuit of this example includes seven transistors (i.e., the first transistor T1 to the seventh transistor T7) and a storage capacitor Cst. The first transistor T1 is also called the first reset transistor, the second transistor T2 is also called the compensation transistor, the third transistor T3 is also called the drive transistor, the fourth transistor T4 is also called the data write transistor, the fifth transistor T5 is also called the first light emission control transistor, the sixth transistor T6 is also called the second light emission control transistor, and the seventh transistor T7 is also called the second reset transistor. The light emitting element EL may include a first electrode, a second electrode, and a light emitting functional layer disposed between the first electrode and the second electrode. Among them, the first electrode of the light emitting element EL may be an anode, and the second electrode of the light emitting element EL may be a cathode.

[0084] In some examples, the seven transistors of the pixel circuit may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polycrystalline silicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0085] In some examples, such as Figure 2As shown, the pixel circuit can be connected to the scan line GL, the data line DL, the first power line PL1, the light emitting control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the first reset control line RST1 and the second reset control line RST2. The light emitting element EL can be connected to the pixel circuit and the second power line PL2. The first power line PL1 can be configured to provide a constant first power signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second power signal VSS, and the first power signal VDD is greater than the second power signal VSS. The scan line GL can be configured to provide a scan signal to the pixel circuit, the data line DL can be configured to provide a data signal to the pixel circuit, the light emitting control line EML can be configured to provide a light emitting control signal to the pixel circuit, the first reset control line RST1 can be configured to provide a first reset control signal to the pixel circuit, and the second reset control line RST2 can be configured to provide a second reset control signal to the pixel circuit. In some examples, the second reset control line RST2 electrically connected to the nth row of pixel circuits and the first reset control line RST1 electrically connected to the n+1th row of pixel circuits can be an integrated structure. In this way, the number of signal lines of the display substrate can be reduced, which is beneficial to realizing a narrow frame design of the display substrate. However, this embodiment is not limited to this.

[0086] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their sizes can be, for example, between the first power signal VDD and the second power signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be set to provide the first initial signal.

[0087] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the scan line GL, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The gate of the compensation transistor T2 is electrically connected to the scan line GL, the first electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3. The gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is electrically connected to the first power line PL1, and the second electrode of the first light emission control transistor T5 is electrically connected to the first electrode of the driving transistor T3. The gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second light emission control transistor T6 is electrically connected to the anode of the light emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3. The second reset transistor T7 is electrically connected to the anode of the light emitting element EL and is configured to reset the anode of the light emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the anode of the light emitting element EL. The first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second plate of the storage capacitor Cst is electrically connected to the first power line PL1.

[0088] In this example, the first node N1 can be a connection point between the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the compensation transistor T2, the second node N2 can be a connection point between the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 can be a connection point between the driving transistor T3, the compensation transistor T2 and the second light-emitting control transistor T6, and the fourth node N4 can be a connection point between the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0089] Figure 3 It is a partial cross-sectional schematic diagram of a display area of ​​at least one embodiment of the present disclosure. Figure 3 The structure of a sub-pixel in the display area is taken as an example for illustration. Figure 3 In the figure, a pixel circuit of each sub-pixel includes a first-type transistor 16 and a capacitor 17 as an example. The first-type transistor 16 may be a low-temperature polysilicon thin-film transistor. For example, the first-type transistor 16 may be Figure 2 The sixth transistor T6 or the seventh transistor T7 of the pixel circuit shown in FIG. Figure 2 The storage capacitor Cst of the pixel circuit shown.

[0090] In some examples, such as Figure 3 As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 100, and a circuit structure layer 120, a light emitting structure layer 130, and an encapsulation structure layer 140 sequentially arranged on the substrate 100. Among them, the circuit structure layer 120 of the display area may include: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 130 of the display area may include: a light emitting element of a plurality of sub-pixels. In other examples, a touch structure layer may be provided on the side of the encapsulation structure layer 140 away from the substrate 100 to integrate a touch function.

[0091] In some examples, the circuit structure layer 120 of the display substrate may include: a bottom shielding metal layer 200 disposed on the base 100, a first semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source-drain metal layer), and a fourth conductive layer (also referred to as a second source-drain metal layer). A first insulating layer (also called a buffer layer) 101 may be provided between the bottom blocking metal layer 200 and the first semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be provided between the first semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be provided between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be provided between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first flat layer) 106 may be provided between the third conductive layer and the fourth conductive layer, and the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 100; a seventh insulating layer (also called a second flat layer) 107 may be provided on the side of the fourth conductive layer away from the substrate 100. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105 may be inorganic insulating layers, and the sixth insulating layer 106 and the seventh insulating layer 107 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, the fifth insulating layer may be omitted between the third conductive layer and the fourth conductive layer, and only the sixth insulating layer may be provided between the third conductive layer and the fourth conductive layer.

[0092] In some examples, the substrate 100 may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked, and the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the water and oxygen resistance of the substrate.

[0093] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and has semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors. This embodiment is not limited to this.

[0094] In some examples, such as Figure 3 As shown, the first semiconductor layer of the display area may include: an active layer 160 of the first type transistor 16 of the pixel circuit. The active layer 160 of the first type transistor 16 may include: a first area 1601, a second area 1602, and a channel area 1600 located between the first area 1601 and the second area 1602. The first conductive layer may include: a first gate 163 of the first type transistor 16, and a first plate 171 of the capacitor 17. The orthographic projection of the first gate 163 of the first type transistor 16 on the substrate 100 may cover the orthographic projection of the channel area 1600 of the active layer 160 on the substrate 100. The second conductive layer may include: a second electrode 172 of the capacitor 17. The orthographic projections of the second electrode 172 and the first electrode 171 of the capacitor 17 on the substrate 100 may at least partially overlap, for example, the two may coincide.

[0095] In some examples, such as Figure 3 As shown, the third conductive layer of the display area may include: a first source 161 and a first drain 162 of the first type transistor 16. The first source 161 of the first type transistor 16 may be electrically connected to the first area 1601 of the active layer 160, and the first drain 162 may be electrically connected to the second area 1602 of the first active layer 160. The fourth conductive layer may include: an anode switching electrode 181. The anode switching electrode 181 may be electrically connected to the first drain 162 of the transistor 16 of the pixel circuit through a via hole opened in the fifth insulating layer 105 and the sixth insulating layer 106. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the anode switching electrode 181.

[0096] In some examples, such as Figure 3As shown, the light emitting structure layer 130 may include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 131, a light emitting functional layer 132 and a second electrode 133. The first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the seventh insulating layer 107, and electrically connected to the anode switching electrode 181 through a via hole provided in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 131. At least part of the light emitting functional layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the light emitting functional layer 132 and connected to the light emitting functional layer 132. The light emitting functional layer 132 may emit light of corresponding colors under the drive of the first electrode 131 and the second electrode 133.

[0097] In some examples, the light-emitting functional layer 132 of the light-emitting element may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0098] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the light-emitting functional layer can be formed by evaporation using a fine metal mask (FMM, FineMetal Mask) or an open mask (Open Mask), or by inkjet technology.

[0099] In some examples, such as Figure 3 As shown, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to flatten the surface of the display substrate, and it may relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and it may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0100] Figure 4 FIG. 4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 4 In the example, a multiplexing circuit using a 1:4 design is used as an example. Figure 4As shown, a multiplexing circuit MUX can be electrically connected to four multiplexing control lines (for example, including the first multiplexing control line ML1 to the fourth multiplexing control line ML4), a multiplexing data line SL, and multiple data lines (for example, including the first data line DL1 to the fourth data line DL4). The multiplexing circuit MUX can include four multiplexing control transistors (i.e., the first multiplexing control transistor M1 to the fourth multiplexing control transistor M4). The gates of the four multiplexing control transistors can be connected to different multiplexing control lines, i.e., the gate of the first multiplexing control transistor M1 is connected to the first multiplexing control line ML1, the gate of the second multiplexing control transistor M2 is connected to the second multiplexing control line ML2, the gate of the third multiplexing control transistor M3 is connected to the third multiplexing control line ML3, and the gate of the fourth multiplexing control transistor M4 is connected to the fourth multiplexing control line ML4.

[0101] In some examples, the first electrodes of the four multiplexing control transistors of a multiplexing circuit may all be connected to the same multiplexing data line SL. The second electrodes of the four multiplexing control transistors are respectively connected to different data lines of the display area. For example, the second electrode of the first multiplexing control transistor M1 is connected to the first data line DL1, the second electrode of the second multiplexing control transistor M2 is connected to the second data line DL2, the second electrode of the third multiplexing control transistor M3 is connected to the third data line DL3, and the second electrode of the fourth multiplexing control transistor M4 is connected to the fourth data line DL4. Each data line may be connected to at least one column of pixel circuits in the display area. A column of pixel circuits may include a plurality of pixel circuits arranged along the second direction. The four multiplexing control lines may control a plurality of multiplexing circuits MUX to provide data signals to the corresponding column pixel circuits of the display area.

[0102] In some examples, such as Figure 1 As shown, the bottom shielding metal layer may include: a first shielding structure located in the display area AA, and a frame connection structure 21 located in the peripheral area BB. The frame connection structure 21 may be connected to the portion of the first shielding structure extending to the peripheral area BB, thereby improving the static electricity problem existing in the first shielding structure. The frame connection structure 21 may include: a first connection structure 211 located in the first frame corner area C1 and the second frame corner area C2, a first frame trace 221 located in the first frame area B1, a second frame trace 222 located in the second frame area B2, a third frame trace 223 located in the third frame area B3, a fourth frame trace 224 located in the fourth frame area B4, a fifth frame trace 225 located in the third frame corner area C3, and a sixth frame trace 226 located in the fourth frame corner area C4.

[0103] In some examples, the first connection structure 211 located in the first frame corner area C1 can connect the first frame line 221 and the third frame line 223, and the first connection structure 211 located in the first frame corner area C2 can connect the first frame line 221 and the fourth frame line 224. The third frame line 223, the fifth frame line 225, the second frame line 222, the sixth frame line 226 and the fourth frame line 224 can be connected in sequence. The first frame line 221 and the second frame line 222 can be strips extending along the first direction X, and the third frame line 223 and the fourth frame line 224 can be strips extending along the second direction Y. The fifth frame line 225 and the sixth frame line 226 can be arc lines extending along the edge of the display area AA.

[0104] In some examples, the first connection structure 211 located in the first frame corner area C1 and the second frame corner area C2 can extend in a stepped manner along the edge of the display area AA. In this example, by using a stepped first connection structure 211 in the lower corner area, it is beneficial to compress the wiring space of the peripheral area BB, thereby facilitating the realization of a narrow frame design.

[0105] Figure 5 for Figure 1 A partial enlarged schematic diagram of the middle area S1. Figure 5 The circuit structure layer of area S1 is mainly illustrated. Fig. 6A for Figure 5 Schematic diagram of the bottom shielding metal layer in . In some examples, such as Figure 5 and Fig. 6AAs shown, the bottom shielding metal layer of the display substrate may include: a first shielding structure 31 located in the display area AA. The first shielding structure 31 may include: a plurality of first shielding blocks 310, a plurality of first extension strips 311 and a plurality of second extension strips 312. The plurality of first extension strips 311 may extend along the first direction X, and the plurality of second extension strips 312 may extend along the second direction Y. The first shielding blocks 310 adjacent to each other along the first direction X may be connected by the first extension strips 311, and the first shielding blocks 310 adjacent to each other along the second direction Y may be connected by the second extension strips 312. The first extension strip 311 may extend to connect with the third frame wiring 223 of the third frame area B3, or may extend to connect with the fourth frame wiring 224 of the fourth frame area B4, or may extend to connect with the fifth frame wiring 225 of the third frame corner area C3, or may extend to connect with the sixth frame wiring 226 of the fourth frame corner area C4. The second extension strip 312 may extend to connect with the first frame line 221 of the first frame area B1, or may extend to connect with the second frame line 222 of the second frame area B2, or may extend to connect with the first frame corner area C1 or the second frame corner area C2 and the first connection structure 211. The orthographic projection of a first blocking block 310 on the substrate may overlap with the orthographic projection of the active layer of at least one transistor of a pixel circuit on the substrate. For example, Figure 6C As shown, the orthographic projection of the first blocking block 310 on the substrate may cover the orthographic projection of the channel region of the active layer T30 of the third transistor T3 of the pixel circuit on the substrate.

[0106] In some examples, such as Fig. 6A As shown, the first connection structure 211 of the first frame corner area C1 may include: a plurality of first connection bars 2111 and a plurality of second connection bars 2112. The plurality of first connection bars 2111 may extend along the first direction X, and the plurality of second connection bars 2112 may extend along the second direction Y. The plurality of first connection bars 2111 and the plurality of second connection bars 2112 may be connected at intervals to form a step shape. A step formed by connecting a first connection bar 2111 and a second connection bar 2112 of the first connection structure 211 may be aligned with a row of pixel circuits of the display area AA.

[0107] In some examples, such as Fig. 6A As shown, the frame connection structure 21 may further include: a plurality of first auxiliary connection bars 231 and a plurality of second auxiliary connection bars 232 located in the first frame corner area C1. The plurality of first auxiliary connection bars 231 may extend along the first direction X, and the plurality of second auxiliary connection bars 232 may extend along the second direction Y. The plurality of first auxiliary connection bars 231 and the plurality of second auxiliary connection bars 232 may be located on one side of the first connection structure 211 close to the display area AA.

[0108] In some examples, such as Fig. 6A As shown, the first auxiliary connecting bar 231 may be located on a side of a first connecting bar 2111 close to the display area AA along the first direction X, and connected to the first connecting bar 2111. The second auxiliary connecting bar 232 may be located on a side of a second connecting bar 2112 close to the display area AA along the first direction X, one end of the second auxiliary connecting bar 232 may be connected to the first auxiliary connecting bar 231, and the other end may be connected to another first connecting bar 2111. One second connecting bar 2112, one first auxiliary connecting bar 231, one second auxiliary connecting bar 232 and one first connecting bar 2111 may be connected to form a first closed area K1, and the first closed area K1 may be substantially rectangular.

[0109] In some examples, such as Fig. 6A As shown, the line width L3 of the first auxiliary connecting bar 231 may be smaller than the line width L1 of the first connecting bar 2111, and the line width L4 of the second auxiliary connecting bar 232 may be smaller than the line width L2 of the second connecting bar 2112. The line width L3 of the first auxiliary connecting bar 231 and the line width L4 of the second auxiliary connecting bar 232 may be substantially the same; the line width L1 of the first connecting bar 2111 and the line width L2 of the second connecting bar 2112 may be substantially the same.

[0110] Figure 6B for Figure 5 Schematic diagram of the first semiconductor layer in FIG. Figure 6B As shown, the first semiconductor layer of the display substrate may include: an active layer of multiple transistors of a plurality of pixel circuits located in the display area AA (for example, including the active layer T10 of the first transistor T1 to the active layer T70 of the seventh transistor T7), and an active layer of multiple multiplexing control transistors of a plurality of multiplexing circuits located in the first border corner area C1 (for example, including the active layers M10a and M10b of the first multiplexing control transistor M1, the active layers M20a and M20b of the second multiplexing control transistor M2, the active layers M30a and M30b of the third multiplexing control transistor M3, and the active layers M40a and M40b of the fourth multiplexing control transistor M4).

[0111] In some examples, such as Figure 6BAs shown, the active layer T10 of the first transistor, the active layer T20 of the second transistor, the active layer T30 of the third transistor, the active layer T40 of the fourth transistor, the active layer T50 of the fifth transistor, the active layer T60 of the sixth transistor, and the active layer T70 of the seventh transistor of a single pixel circuit may be an integrated structure. The second area of ​​the active layer T10 of the first transistor is connected to the second area of ​​the active layer T20 of the second transistor, the first area of ​​the active layer T20 of the second transistor, the second area of ​​the active layer T30 of the third transistor, and the first area of ​​the active layer T60 of the sixth transistor are connected, the first area of ​​the active layer T30 of the third transistor, the second area of ​​the active layer T40 of the fourth transistor, and the second area of ​​the active layer T50 of the fifth transistor are connected, and the second area of ​​the active layer T60 of the sixth transistor is connected to the second area of ​​the active layer T70 of the seventh transistor. The first region of the active layer T10 of the first transistor, the first region of the active layer T70 of the seventh transistor, the first region of the active layer T50 of the fifth transistor, and the first region of the active layer T40 of the fourth transistor may be independently provided.

[0112] In some examples, such as Figure 6B As shown, the orthographic projections of the active layer T10 of the first transistor and the active layer T30 of the third transistor on the substrate may be approximately n-shaped, the orthographic projections of the active layer T20 of the second transistor and the active layer T60 of the sixth transistor on the substrate may be approximately L-shaped, and the orthographic projections of the active layer T40 of the fourth transistor, the active layer T50 of the fifth transistor, and the active layer T70 of the seventh transistor on the substrate may be approximately I-shaped. This embodiment is not limited to this.

[0113] In some examples, such as Figure 6B As shown, the active layer M10a of the first multiplexing control transistor and the active layer M20a of the second reset control transistor of a single multiplexing circuit can be an integrated structure, the active layer M10b of the first multiplexing control transistor and the active layer M20b of the second reset control transistor can be an integrated structure, the active layer M30a of the third multiplexing control transistor and the active layer M40a of the fourth reset control transistor can be an integrated structure, and the active layer M30b of the third multiplexing control transistor and the active layer M40b of the fourth reset control transistor can be an integrated structure. The integrated structure of the active layer M10a of the first multiplexing control transistor and the active layer M20a of the second reset control transistor, the integrated structure of the active layer M10b of the first multiplexing control transistor and the active layer M20b of the second reset control transistor, the integrated structure of the active layer M30a of the third multiplexing control transistor and the active layer M40a of the fourth reset control transistor, and the integrated structure of the active layer M30b of the third multiplexing control transistor and the active layer M40b of the fourth reset control transistor can be a rectangular projection on the substrate, and are arranged in two rows and two columns.

[0114] Figure 6C for Figure 5 Schematic diagram of a display substrate after forming a first conductive layer. In some examples, such as Figure 6C As shown, the first conductive layer of the display substrate may include: a plurality of gate signal lines located in the display area AA and extending along the first direction X (for example, including the first reset control line RST1(n), RST1(n+1), RST1(n+2), the scanning line GL(n), GL(n+1), the light emitting control line EML(n), EML(n+1)), the gates of a plurality of transistors of a plurality of pixel circuits (for example, including the first gate T21 of the second transistor T2) and the first electrode plate (for example, the first electrode plate Cst-1) of the storage capacitor; the gates of a plurality of multiplexing control transistors of a plurality of multiplexing circuits located in the first frame corner area C1 (for example, the gate M11 of the first multiplexing control transistor M1, the gate M21 of the second multiplexing control transistor M2, the gate M31 of the third multiplexing control transistor M3, the gate M41 of the fourth multiplexing control transistor M4), and the first power adapter line 511.

[0115] In some examples, such as Figure 6C As shown, the scan line GL(n) may be located between the first reset control line RST1(n) and the light emission control line EML(n) in the second direction Y. The overlapped portion of the scan line GL(n) and the active layer T20 of the second transistor of the pixel circuit of the same row may serve as the second gate of the second transistor T2. The scan line GL(n) and the first gate T21 of the second transistor T2 of the pixel circuit of the same row may be an integral structure. The overlapped portion of the scan line GL(n) and the active layer T40 of the fourth transistor T4 of the pixel circuit of the same row may serve as the gate of the fourth transistor T4.

[0116] In some examples, such as Figure 6C As shown, the orthographic projection of the first plate Cst-1 of the storage capacitor on the substrate can be roughly rectangular. The first plate Cst-1 of the storage capacitor can also serve as the gate of the third transistor T3. The orthographic projection of the first plate Cst-1 of the storage capacitor on the substrate can be located within the orthographic projection range of the first blocking block 310 of the first blocking structure 31 on the substrate.

[0117] In some examples, such as Figure 6C As shown, the overlapping portion of the light emitting control line EML (n) and the active layer of the fifth transistor of the pixel circuit of this row can be used as the gate of the fifth transistor T5, and the overlapping portion of the light emitting control line EML (n) and the active layer of the sixth transistor of the pixel circuit of this row can be used as the gate of the sixth transistor T6.

[0118] In some examples, such as Figure 6CAs shown, the first reset control line RST1(n) can also be used as the second reset control line connected to the pixel circuit of the previous row. The overlapping portion of the first reset control line RST1(n) with the active layer T10 of the first transistor of the pixel circuit of the current row can be used as the gate of the first transistor T1, and the overlapping portion of the first reset control line RST1(n) with the active layer T70 of the seventh transistor of the pixel circuit of the previous row can be used as the gate of the seventh transistor.

[0119] In some examples, such as Figure 6C As shown, the scan line GL(n) may have a first end 401 extending to the first frame corner area C1; the light emitting control line EML(n) may have a first end 402 extending to the first frame corner area C1, and the first reset control line RST1(n+1) may have a first end 403 extending to the first frame corner area C1. The orthographic projections of the plurality of first ends 401, 402, and 403 on the substrate may be located in a first closed area K1 formed by connecting the first connection structure 211, the first auxiliary connection bar 231, and the second auxiliary connection bar 232.

[0120] In some examples, such as Figure 6C As shown, the gate M11 of the first multiplexing control transistor M1, the gate M21 of the second multiplexing control transistor M2, the gate M31 of the third multiplexing control transistor M3, and the gate M41 of the fourth multiplexing control transistor M4 can be arranged in sequence along the first direction X, and all extend along the second direction Y. The first reset control transistor M1, the second multiplexing control transistor M2, the third multiplexing control transistor M3, and the fourth multiplexing control transistor M4 can be arranged in the first direction, and are located on the side of the first connection structure 211 away from the display area AA. The first connection bar 2111 of the first connection structure 211 can be adjacent to a multiplexing circuit in the second direction Y, and the second connection bar 2112 can be adjacent to the multiplexing circuit in the first direction X. The first reset control transistor M1, the second multiplexing control transistor M2, the third multiplexing control transistor M3, and the fourth multiplexing control transistor M4 can be arranged in sequence in the first direction X in a direction close to the second connection bar 2112.

[0121] In some examples, such as Figure 6C As shown, the first power adapter 511 may extend along the second direction Y and be located between two adjacent multiplexing circuits along the first direction X. One end of the first power adapter 511 may extend into the first closed area K1. The first power adapter 511 may be configured to transmit a first power signal.

[0122] Fig.6D for Figure 5 Schematic diagram of a display substrate after forming a second conductive layer. In some examples, such as Fig.6DAs shown, the second conductive layer of the display substrate may include: a plurality of initial signal lines located in the display area AA (for example, including the first initial signal lines INIT1(n), INIT1(n+1), the second initial signal lines INIT2(n-1), INIT2(n), INIT2(n+1)), the second plates Cst-2 of the storage capacitors of the plurality of pixel circuits, and a plurality of auxiliary shielding blocks 191; and a multiplexed data line SL located in the first border corner area C1.

[0123] In some examples, the orthographic projection of the auxiliary blocking block 191 on the substrate may partially overlap with the orthographic projection of the active layer T20 of the second transistor T2 of the pixel circuit on the substrate. For example, the active layer T20 of the second transistor T2 may include a first channel region, a second channel region, and a channel connection region connecting the first channel region and the second channel region, the first channel region overlaps with the first gate T21 of the second transistor T2, and the second channel region overlaps with the second gate of the second transistor T2. The orthographic projection of the auxiliary blocking block 191 on the substrate may at least partially overlap with the orthographic projection of the channel connection region of the active layer T20 of the second transistor T2 on the substrate. For example, the orthographic projection of the auxiliary blocking block 191 on the substrate may cover the orthographic projection of the channel connection region of the active layer T20 of the second transistor T2 on the substrate.

[0124] In some examples, the orthographic projection of the second plate Cst-2 of the storage capacitor on the substrate may overlap with the orthographic projection of the first plate Cst-1 on the substrate. The second plate Cst-2 may have a hollow portion, and the orthographic projection of the hollow portion on the substrate may be located within the orthographic projection range of the first plate Cst-1 on the substrate. The second plate Cst-2 of the storage capacitor of the same row of pixel circuits may be an integrated structure to realize the transmission of the first power supply signal along the first direction X.

[0125] In some examples, the first initial signal line INIT1(n) and the second initial signal line INIT2(n) may be substantially straight lines extending along the first direction X. An orthographic projection of the first initial signal line INIT1(n) on the substrate may be located on a side of an orthographic projection of the second initial signal line INIT2(n) on the substrate close to the third transistor T3.

[0126] In some examples, the first initial signal line INIT1(n) may have a first end 404 extending to the first frame corner area C1, and the second initial signal line INIT2(n) may have a first end 405 extending to the first frame corner area C1. The orthographic projections of the first ends 404 and 405 on the substrate may be located within a first closed area K1 formed by connecting the first connection structure 211, the first auxiliary connection bar 231, and the second auxiliary connection bar 232. The first ends 401, 402, 404, 405, and 403 may be arranged in sequence along the second direction Y.

[0127] In some examples, the multiplexing data line SL may be located on a side of the multiplexing circuit away from the display area AA along the second direction Y. The multiplexing data line SL may extend along the second direction Y, for example, to the first border area B1.

[0128] Fig. 6E for Figure 5 Schematic diagram of a via formed by the bottom shielding metal layer and the fourth insulating layer. In some examples, such as Fig. 6E As shown, the fourth insulating layer may be provided with a plurality of vias, for example, may include a plurality of vias located in the display area AA, and a plurality of vias located in the first frame corner area C1 (for example, including the first via V1 to the twenty-first via V21). The orthographic projection of the plurality of vias in the first frame corner area C1 on the substrate may not overlap with the orthographic projection of the first connection structure 211, the first auxiliary connection strip 231, and the second auxiliary connection strip 232 on the substrate. The first via V1 to the sixth via V6 may be located in the first closed area K1. In this example, the plurality of first signal lines may include a plurality of gate signal lines and a plurality of initial signal lines, and the plurality of first transfer holes may include the first via V1 to the sixth via V6.

[0129] Fig. 6F for Figure 5 Schematic diagram of a display substrate after a third conductive layer is formed. Figure 6G for Fig. 6F Schematic diagram of the third conductive layer in FIG. In some examples, such as Fig. 6F and Figure 6G As shown, the third conductive layer of the display substrate may include: a plurality of pixel connection electrodes located in the display area AA (for example, including the first pixel connection electrode 441 to the fourth pixel connection electrode 444), a plurality of first DC signal lines 451, and a plurality of first power lines PL1; a second power connection line 512 located in the first frame corner area C1, a plurality of switching electrodes (for example, the first switching electrode 411 to the fifth switching electrode 415), a plurality of reused connection electrodes (for example, including the first reused connection electrode 461 to the sixth reused connection electrode 466), and a frame DC transmission line 452.

[0130] In some examples, the first pixel connection electrode 441 may be connected to the first region of the active layer T10 of the first transistor T1 of the pixel circuit, and may also be connected to the first initial signal line (e.g., the first initial signal line INIT1(n-1)). The second pixel connection electrode 442 may be connected to the second region of the active layer T20 of the second transistor T2 of the pixel circuit and the gate of the third transistor T3. The third pixel connection electrode 443 may be connected to the second region of the active layer T60 of the sixth transistor T6. The fourth pixel connection electrode 444 may be connected to the first region of the active layer T70 of the seventh transistor T7 and the second initial signal line INIT2(n).

[0131] In some examples, the first power line PL1 may be in the shape of a straight line extending in the second direction Y. The first power line PL1 may be connected to the first region of the active layer T50 of the fifth transistor T5 of the pixel circuit, and may also be connected to the second electrode plate Cst-2 of the storage capacitor. The first power line PL1 may extend to the first frame corner area C1, and be connected to the second power connection line 512. The first power line PL1 and the connected second power connection line 512 may be an integral structure. The second power connection line 512 may be in the shape of a straight line extending in the first direction X. One end of the second power connection line 512 away from the display area AA may be connected to the first power connection line 511 through the sixth via V6. The first power connection line 511 may extend to the first frame area B1, and be connected to the frame power line in the first frame area B1, thereby realizing the transmission of the first power signal VDD.

[0132] In some examples, the first DC signal line 451 may be in the shape of a zigzag line extending along the second direction Y. A first DC signal line 451 may be provided between adjacent first power lines PL1. The frame DC transmission line 452 of the first frame corner area C1 may extend in a stepped manner along the edge of the display area AA. The orthographic projection of the frame DC transmission line 452 on the substrate may at least partially overlap with the orthographic projection of the first connection structure 211 on the substrate. For example, the orthographic projection of the frame DC transmission line 452 on the substrate may cover the orthographic projection of the first connection structure 211 on the substrate. The frame DC transmission line 452 and the first DC signal line 451 may be connected via a DC signal adapter line 453 located on the fourth conductive layer, thereby realizing the transmission of a DC signal (e.g., a first initial signal or a second initial signal) along the second direction Y in the display area AA.

[0133] In some examples, the first multiplexing connection electrode 461 may extend along the second direction Y. The first multiplexing connection electrode 461 may be connected to the second region of the active layer M10a of the first multiplexing control transistor M1 through a plurality of seventh vias V7 arranged along the second direction Y, and may also be connected to the second region of the active layer M10b of the first multiplexing control transistor M1 through a plurality of eighth vias V8 arranged along the second direction Y. The first multiplexing connection electrode 461 may serve as the second pole of the first multiplexing control transistor M1.

[0134] In some examples, the second multiplexing connection electrode 462 and the fifth multiplexing connection electrode 465 may be an integral structure. The second multiplexing connection electrode 462 may be connected to the first region of the active layer M10a of the first multiplexing control transistor M1 through a plurality of ninth vias V9 aligned along the second direction Y, and may also be connected to the first region of the active layer M10b of the first multiplexing control transistor M1 through a plurality of tenth vias V10 aligned along the second direction Y; the fifth multiplexing connection electrode 465 may be connected to the first region of the active layer M30a of the third multiplexing control transistor M3 through a plurality of fifteenth vias V15 aligned along the second direction Y, and may also be connected to the first region of the active layer M30b of the third multiplexing control transistor M3 through a plurality of sixteenth vias V16 aligned along the second direction Y; the integral structure of the second multiplexing connection electrode 462 and the fifth multiplexing connection electrode 465 may also be connected to the multiplexing data line SL through a nineteenth via V19. The second multiplexing connection electrode 462 can be used as the first electrode of the first multiplexing control transistor M1 and the first electrode of the second multiplexing control transistor M2, and the fifth multiplexing connection electrode 465 can be used as the first electrode of the third multiplexing control transistor M3 and the first electrode of the fourth multiplexing control transistor M4.

[0135] In some examples, the third multiplexing connection electrode 463 may extend along the second direction Y. The third multiplexing connection electrode 463 may be connected to the second region of the active layer M20a of the second multiplexing control transistor M2 through a plurality of eleventh vias V11 arranged along the second direction Y, and may also be connected to the second region of the active layer M20b of the second multiplexing control transistor M2 through a plurality of twelfth vias V12 arranged along the second direction Y. The third multiplexing connection electrode 463 may serve as the second pole of the second multiplexing control transistor M2.

[0136] In some examples, the fourth multiplexing connection electrode 464 may extend along the second direction Y. The fourth multiplexing connection electrode 464 may be connected to the second region of the active layer M30a of the third multiplexing control transistor M3 through a plurality of thirteenth via holes V13 arranged along the second direction Y, and may also be connected to the second region of the active layer M30b of the third multiplexing control transistor M3 through a plurality of fourteenth via holes V14 arranged along the second direction Y. The fourth multiplexing connection electrode 464 may serve as the second pole of the third multiplexing control transistor M3.

[0137] In some examples, the sixth multiplexing connection electrode 466 may extend along the second direction Y. The sixth multiplexing connection electrode 466 may be connected to the second region of the active layer M40a of the fourth multiplexing control transistor M4 through a plurality of seventeenth via holes V17 arranged along the second direction Y, and may also be connected to the second region of the active layer M40b of the fourth multiplexing control transistor M4 through a plurality of eighteenth via holes V18 arranged along the second direction Y. The sixth multiplexing connection electrode 466 may serve as the second pole of the fourth multiplexing control transistor.

[0138] In some examples, the first multiplexing control line ML1 may be connected to the gate M11 of the first multiplexing control transistor M1 through a twentieth via V20. The third multiplexing control line ML3 may be connected to the gate M31 of the third multiplexing control transistor M3 through a twenty-first via V21.

[0139] In some examples, the orthographic projections of the first to fifth transfer electrodes 411 to 415 on the substrate may be substantially strip-shaped extending along the first direction X. The orthographic projections of the first to fifth transfer electrodes 411 to 415 on the substrate may be located within a first closed area K1. The first transfer electrode 411 may be connected to the first end 401 of the scan line GL(n) through the first via hole V1. The second transfer electrode 412 may be connected to the first end 402 of the light emitting control line EML(n) through the second via hole V2. The third transfer electrode 413 may be connected to the first initial signal line INIT1(n) through the third via hole V3. The fourth connection electrode 414 may be connected to the second initial signal line INIT2(n) through the fourth via hole V4. The fifth connection electrode 415 may be connected to the first reset control line RST1(n+1) through the fifth via hole V5.

[0140] Figure 6H for Figure 5 Schematic diagram of the fourth conductive layer in FIG. In some examples, such as Figure 5 and Figure 6H As shown, the fourth conductive layer of the display substrate may include: multiple data lines (for example, data lines DL1, DL2, DL3 and DL4) and multiple first power auxiliary lines 513 located in the display area AA, and multiple anode connecting electrodes 181; multiple signal transfer lines (for example, the first signal transfer line 421 to the fifth signal transfer line 425) located in the first frame corner area C1, and a DC signal transfer line 453.

[0141] In some examples, one end of the DC signal adapter line 453 can be connected to the frame DC transmission line 452, and the other end can be connected to the first DC signal line 451 to achieve transmission of the DC signal (such as the first initial signal or the second initial signal line) along the second direction Y within the display area AA.

[0142] In some examples, the first power auxiliary line 513 can be connected to the first power line PL1, so that the first power signal VDD can be transmitted in the display area AA through a double-layer wiring, which is beneficial to reducing the transmission impedance.

[0143] In some examples, the data line DL1 can be connected to the second electrode of the first multiplexing control transistor M1. The data line DL2 can be connected to the second electrode of the second multiplexing control transistor M2. The data line DL3 can be connected to the second electrode of the third multiplexing control transistor M3, and the data line DL4 can be connected to the second electrode of the fourth multiplexing control transistor M4.

[0144] In some examples, the first signal transfer line 421 can be connected to the first transfer electrode 411, the second signal transfer line 422 can be connected to the second transfer electrode 412, the third signal transfer line 423 can be connected to the third transfer electrode 413, the fourth signal transfer line 424 can be connected to the fourth transfer electrode 414, and the fifth signal transfer line 425 can be connected to the fifth transfer electrode 415. The first signal transfer line 421, the second signal transfer line 422 and the fifth signal transfer line 425 can be connected to the corresponding gate drive circuit in the third frame area B3, so that the first signal transfer line 421 transmits the scan signal, the second signal transfer line 422 transmits the light-emitting control signal, and the fifth signal transfer line 425 transmits the first reset control signal; the third signal transfer line 423 and the fourth signal transfer line 424 can be connected to the initial frame line in the third frame area B3, so that the third signal transfer line 423 transmits the first initial signal, and the fourth signal transfer line 424 transmits the second initial signal.

[0145] In this example, in the first frame corner area C1 and the second frame corner area C2 of the display substrate, the first connection structure 211 can adopt a stepped design and be wired on the side of the multiplexing circuit MUX close to the display area AA, avoiding the multiple first transfer vias and the vias in the multiplexing circuit MUX located in the fourth insulating layer. In this way, the peripheral space can be compressed without compressing the device size, thereby achieving the purpose of a narrow frame. Moreover, by avoiding the vias opened in the fourth insulating layer, the risk of electrostatic discharge caused by the overlap of the bottom shielding metal layer and the vias opened in the fourth insulating layer can be reduced, and defects can be avoided.

[0146] Figure 7 for Figure 1 Another partial enlarged schematic diagram of the middle area S1. Fig. 8A for Figure 7 Schematic diagram of the bottom blocking metal layer in . Figure 8B for Figure 7 Schematic diagram of a display substrate after a second conductive layer is formed. Figure 8C for Figure 7Schematic diagram of vias formed by the bottom shielding metal layer and the fourth insulating layer. Fig.8D for Figure 7 Schematic diagram of a display substrate after a third conductive layer is formed.

[0147] In some examples, such as Figures 7 to 8D As shown, the frame connection structure 21 of the bottom shielding metal layer may include a first connection structure 211 located in the first frame corner area C1. The first connection structure 211 may include: a plurality of first connection bars 2111 extending along the first direction X, and a plurality of second connection bars 2112 extending along the second direction Y. The plurality of first connection bars 2111 and the plurality of second connection bars 2112 may be connected at intervals to form a step shape. The first connection bar 2111 may include: a straight line segment 2111-1 and a folded line segment 2111-2 extending along the first direction X. The folded line segment 2111-2 may be located on a side of the straight line segment 2111-1 close to the display area AA in the first direction X. The folded line segment 2111-2 may be located on a side of a plurality of first transfer vias (for example, including the first via V1 to the sixth via V6) close to the display area AA in the second direction Y. The folded line segment 2111-2 may be bent toward a side close to the display area AA in the second direction Y to avoid the plurality of first transfer vias.

[0148] In some examples, the second connection bar 2112 may be located on a side of the plurality of first transfer vias (eg, including the first to sixth vias V1 to V6 ) close to the display area AA. The second connection bar 2112 may be directly connected to the first extension section 311 of the first shielding structure 31 .

[0149] Compared to Figure 5 In the embodiment shown, the first connecting bar 2111 of the first connecting structure 211 is designed to be bent along the second direction Y, so that the first auxiliary connecting bar and the second auxiliary connecting bar can be omitted, thereby saving more frame space. The rest of the description of this embodiment can refer to the description of the aforementioned embodiment, so it is not repeated here.

[0150] Fig.9A for Figure 1 Another partial enlarged schematic diagram of the middle area S1. Fig.9A The bottom shielding metal layer, the first semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer are mainly illustrated. Fig. 9B for Fig.9A Schematic diagram of the bottom blocking metal layer in . Fig. 9C for Fig.9A Schematic diagram of vias formed by the bottom shielding metal layer and the fourth insulating layer.

[0151] In some examples, such as 9A to 9CAs shown, the bottom shielding metal layer of the display substrate may include: a first shielding structure 31 located in the display area AA, a second shielding structure 32 located in the first frame corner area C1, a first connection structure 211, a second connection structure 212, a plurality of first auxiliary connection bars 231, and a plurality of second auxiliary connection bars 232. The first connection structure 211 may include: a first connection bar 2111 extending along the first direction X and a second connection bar 2112 extending along the second direction Y. A step formed by connecting a first connection bar 2111 and a second connection bar 2112 may be aligned with three rows of pixel circuits. In other words, the length of the second connection bar 2112 along the second direction Y may be substantially the same as the length of the three rows of pixel circuits along the second direction Y.

[0152] In some examples, the first connection structure 211, the plurality of first auxiliary connection bars 231, and the second auxiliary connection bars 232 may be connected to form a plurality of first enclosed regions K1. Each first enclosed region K1 may correspond to a row of pixel circuits.

[0153] In some examples, the second shielding structure 32 may include a plurality of second shielding blocks 320. The orthographic projection of a single second shielding block 320 on the substrate may be a rectangle. The orthographic projection of a single second shielding block 320 on the substrate may cover the orthographic projection of the active layer of four multiplexing control transistors of a single multiplexing circuit MUX on the substrate. The second shielding block 320 may be located on a side of the second connecting bar 2112 of the first connecting structure 211 away from the display area AA. The second shielding block 320 may be directly connected to the second connecting bar 2112.

[0154] In some examples, the second connection structure 212 may extend in a stepped manner along the edge of the display area AA. The second connection structure 212 may include: a plurality of sixth connection bars 2121 extending along the first direction X and a plurality of seventh connection bars 2122 extending along the second direction Y. The sixth connection bar 2121 may be located on a side of the second blocking block 320 away from the display area AA in the second direction Y. The sixth connection bar 2121 may be aligned with a first auxiliary connection bar 231 along the first direction X. The seventh connection bar 2122 may be located on a side of the second blocking block 320 away from the display area AA in the first direction X. The seventh connection bar 2122, the second blocking block 320, and the second connection bar 2112 may be directly connected as an integral structure.

[0155] In some examples, the first connection structure 211 and the second connection structure 212 can be connected to form a plurality of second closed areas K2. A second blocking block 320 can be located in a second closed area K2 and directly connected to the second connection bar 2112 of the first connection structure 211 and the seventh connection bar 2122 of the second connection structure 212.

[0156] In some examples, such as Fig.9A As shown, the first frame corner area C1 may also be provided with a third power connection line 521 located in the first conductive layer and a fourth power connection line 522 located in the third conductive layer. The third power connection line 521 may be connected to the fourth power connection line 522. The third power connection line 521 and the fourth power connection line 522 may be located on the side of the multiplexing circuit MUX away from the display area AA. The third power connection line 521 and the fourth power connection line 522 may be configured to transmit a second power signal. The first multiplexing control line ML1, the second multiplexing control line ML2, the third multiplexing control line ML3 and the fourth multiplexing control line ML4 connected to the multiplexing circuit MUX may be located in the third conductive layer. The first multiplexing control line ML1, the third multiplexing control line ML3, the second multiplexing control line ML2 and the fourth multiplexing control line ML4 may be arranged in a direction away from the display area AA, and extend in a stepped manner on the side of the multiplexing circuit MUX away from the display area AA.

[0157] In this example, by providing a second shielding structure covering the active layer of the multiplexing control transistor of the multiplexing circuit MUX in the lower corner region (such as the first frame corner region C1), the stability of the multiplexing control transistor of the multiplexing circuit MUX can be increased. The remaining structure of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0158] Fig.10 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Fig.11A for Fig.10 A partial enlarged schematic diagram of the middle area S2. Fig. 11B for Fig.11A Schematic diagram of the bottom blocking metal layer in . Fig. 11C for Fig.11A Schematic diagram of vias formed by the bottom shielding metal layer and the fourth insulating layer.

[0159] In some examples, such as Figures 10 to 11C As shown, the bottom shielding metal layer of the display substrate may include: a first shielding structure 31 located in the display area AA, a second shielding structure 32 located in the first frame corner area C1, a first connection structure 211, a third connection structure 213, a plurality of first auxiliary connection bars 231, and a plurality of second auxiliary connection bars 232. The first connection structure 211 may include: a plurality of first connection bars 2111 extending along the first direction X and a plurality of second connection bars 2112 extending along the second direction Y. A step formed by connecting a first connection bar 2111 and a second connection bar 2112 may be aligned with three rows of pixel circuits. In other words, the length of the second connection bar 2112 along the second direction Y may be substantially the same as the length of the three rows of pixel circuits along the second direction Y.

[0160] In some examples, the second shielding structure 32 may include a plurality of third shielding blocks 321 and a plurality of shielding connection electrodes 322. The orthographic projection of a single third shielding block 321 on the substrate may be a rectangle. The orthographic projection of the third shielding block 321 on the substrate may cover the active layers of two multiplexing control transistors (e.g., the active layer M10a of the first multiplexing control transistor M1 and the active layer M20a of the second multiplexing control transistor M2) as an integrated structure. Each multiplexing circuit MUX may correspond to four third shielding blocks 321. The four third shielding blocks 321 may be arranged in an array of two rows and two columns, and adjacent third shielding blocks 321 may be connected by shielding connection electrodes 322. The four third shielding blocks 321 and the four shielding connection electrodes 322 corresponding to a single multiplexing circuit MUX may be an integrated structure.

[0161] In some examples, the third connection structure 213 may be mesh-shaped. The third connection structure 213 may be located on a side of the second shielding structure 32 away from the first connection structure 211. The third connection structure 213 may include: a plurality of third connection bars 2131 extending along the first direction X, a plurality of fourth connection bars 2132 extending along the second direction Y, and a fifth connection bar 2133. The fifth connection bar 2133 may be located on a side of the plurality of third connection bars 2131 and the plurality of fourth connection bars 2132 away from the display area AA. The fifth connection bar 2133 may be connected to the end of the plurality of third connection bars 2131 away from the display area AA as a whole. The third connection bar 2131 may be a straight bar extending along the first direction X, the fourth connection bar 2132 may be a straight bar extending along the second direction Y, and the fifth connection bar 2133 may be an arc or a broken line. For example, the line width of the fifth connection bar 2133 may be 10 micrometers (μm).

[0162] In some examples, the third blocking block 321 may be located between the second connecting bar 2112 of the first connecting structure 211 and the fourth connecting bar 2132 of the third connecting structure 213 in the first direction X. The third blocking block 321 may not be directly connected to the second connecting bar 2112 and the fourth connecting bar 2132, but may be connected to the second connecting bar 2112 through the first auxiliary connecting bar 231, and connected to the fourth connecting bar 2132 through the third connecting bar 2131.

[0163] This example can increase the stability of the multiplexing control transistor of the multiplexing circuit MUX by setting a second shielding structure 32 covering the active layer of the multiplexing control transistor of the multiplexing circuit MUX in the lower corner area (such as the first frame corner area C1 and the second frame corner area C2). Moreover, this example sets a mesh-shaped third connection structure 213 in the first frame corner area C1 and the second frame corner area C2, which can be beneficial to the voltage uniformity of the bottom shielding metal layer in the peripheral area and to avoid the vias opened in the fourth insulating layer. The remaining structure of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0164] Fig. 12A for Fig.10 Another partial enlarged schematic diagram of the middle area S2. Fig. 12B for Fig. 12A Schematic diagram of the bottom blocking metal layer in . Fig. 12C for Fig. 12A Schematic diagram of vias formed by the bottom shielding metal layer and the fourth insulating layer.

[0165] In some examples, such as FIG. 12A to FIG. 12C As shown, the bottom shielding metal layer of the display substrate may include: a first shielding structure 31 located in the display area AA, a first connection structure 211 located in the first frame corner area C1, a third connection structure 213, a plurality of first auxiliary connection bars 231, and a plurality of second auxiliary connection bars 232. The first connection structure 211 may include: a plurality of first connection bars 2111 extending along the first direction X and a plurality of second connection bars 2112 extending along the second direction Y. The third connection structure 213 may be mesh-shaped. The third connection structure 213 may be located on the side of the first connection structure 211 away from the display area AA. The third connection structure 213 may include: a plurality of third connection bars 2131 extending along the first direction X, a plurality of fourth connection bars 2132 extending along the second direction Y, and a fifth connection bar 2133. The first connection structure 211 and the third connection structure 213 may be connected to form a plurality of third closed areas K3. For example, the third closed area K3 may be formed by connecting the first connection bar 2111, the second connection bar 2112, the third connection bar 2131, and the fourth connection bar 2132. A multiplexing circuit MUX may be located in the third closed area K3. The orthographic projections of active layers of multiple multiplexing control transistors of the multiplexing circuit MUX on the substrate may be located within the orthographic projection range of the third closed area K3 on the substrate.

[0166] In this example, a mesh-shaped third connection structure 213 is provided in the lower corner region (such as the first frame corner region C1 and the second frame corner region C2), which can be beneficial to the voltage uniformity of the bottom shielding metal layer in the peripheral region and to avoid the vias opened in the fourth insulating layer. The remaining structure of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0167] Fig.13 FIG. 4 is another partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Fig.13 In the example, the structure of a sub-pixel in the display area is taken as an example for illustration. In this example, the pixel circuit includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor as an example for illustration. Fig.13 In the figure, each sub-pixel includes a first type transistor 16, a second type transistor 15 and a capacitor 17. The first type transistor 16 may be a low temperature polysilicon thin film transistor, and the second type transistor 15 may be an oxide thin film transistor.

[0168] In some examples, such as Fig.13 As shown, the circuit structure layer 120 may include: a bottom blocking metal layer 200 arranged on the substrate 100, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a fifth conductive layer (also referred to as a third gate metal layer), a third conductive layer and a fourth conductive layer. A first insulating layer (also referred to as a buffer layer) 101 may be provided between the bottom blocking metal layer 200 and the first semiconductor layer; a second insulating layer (also referred to as a first gate insulating layer) 102 may be provided between the first semiconductor layer and the first conductive layer; a third insulating layer (also referred to as a second gate insulating layer) 103 may be provided between the first conductive layer and the second conductive layer; an eighth insulating layer (also referred to as a third gate insulating layer) 108 may be provided between the second conductive layer and the second semiconductor layer; a ninth insulating layer (also referred to as a fourth gate insulating layer) 109 may be provided between the second semiconductor layer and the fifth conductive layer; a fourth insulating layer (also referred to as an interlayer insulating layer) 104 may be provided between the fifth conductive layer and the third conductive layer; a fifth insulating layer (also referred to as a passivation layer) 105 and a sixth insulating layer (also referred to as a first flat layer) 106 may be provided between the third conductive layer and the fourth conductive layer, and the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 100; a seventh insulating layer (also referred to as a second flat layer) 107 may be provided on the side of the fourth conductive layer away from the substrate 100. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, the eighth insulating layer 108 and the ninth insulating layer 109 can be inorganic insulating layers, and the sixth insulating layer 106 and the seventh insulating layer 107 can be organic insulating layers.

[0169] In some examples, such as Fig.13 As shown, the first semiconductor layer of the display area may include: an active layer 160 of the first type transistor 16. The first conductive layer may include: a first gate electrode 163 of the first type transistor 16, and a first plate 171 of the capacitor 17. The second conductive layer may include: a second plate 172 of the capacitor 17, and a bottom gate 154 of the second type transistor 15. The second semiconductor layer may include: an active layer 150 of the second type transistor 15. The fifth conductive layer may include: a top gate 153 of the second type transistor 15. The orthographic projection of the top gate 153 of the second type transistor 15 on the substrate 100 may partially overlap with the orthographic projection of the active layer 150 on the substrate 100. The orthographic projection of the bottom gate 154 of the second type transistor 15 on the substrate 100 may partially overlap with the orthographic projection of the active layer 150 on the substrate 100.

[0170] In some examples, such as Fig.13 As shown, the third conductive layer of the display area may include: a first source 161 and a first drain 162 of the first type transistor 16, a second source 151 and a second drain 152 of the second type transistor 15. The second source 151 of the second type transistor 15 may be electrically connected to one end of the active layer 150 of the second type transistor 15, and the second drain 152 of the second type transistor 15 may be electrically connected to the other end of the active layer 150. The fourth conductive layer may include: an anode transfer electrode 181. The rest of the description of the display substrate of this example may refer to Figure 3 The description of the embodiment shown is therefore not repeated here.

[0171] Fig.14A for Figure 1 Another partial enlarged schematic diagram of the middle area S1. Fig.14A The partial structure of the first frame corner area C1 is illustrated. Fig. 14B for Fig.14A A schematic diagram of a bottom shielding metal layer, a first semiconductor layer, a second conductive layer, a third conductive layer and a fifth conductive layer in FIG. Fig. 14C for Fig.14A A schematic diagram of a plurality of vias formed by a bottom shielding metal layer and a fourth insulating layer; Fig.14D for Fig.14A Schematic diagram of a display substrate after a third conductive layer is formed.

[0172] In some examples, such as FIG. 14A to FIG. 14DAs shown, the bottom shielding metal layer may include: a first shielding structure (for example, including a first extension bar 311 and a second extension bar 312) located in the display area AA, and a first connection structure 211 located in the first frame corner area C1. The first connection structure 211 may include: a plurality of first connection bars 2111 extending along the first direction X, and a plurality of second connection bars 2112 extending along the second direction Y. The first connection bar 2111 may be a straight bar extending along the first direction X, and the second connection bar 2112 may be a folded bar extending along the second direction Y.

[0173] In some examples, the first frame corner area C1 may not have a multiplexing circuit, and the multiplexing circuit may be set in the first frame area B1. By setting a plurality of data lead lines in the first frame corner area B1, the electrical connection between the data lines and the multiplexing circuit in the first frame area C1 is realized. Fig. 14B As shown, the plurality of data lead lines in the first frame corner area may be arranged at intervals in the first conductive layer and the second conductive layer. For example, the data lead line 55a may be located in the first conductive layer, and the data lead line 55b may be located in the second conductive layer. The first ends of the plurality of first signal lines may extend to the side of the second connecting bar 2112 away from the display area AA. For example, the first signal lines XL1 and XL2 may be located in the first conductive layer, the first signal lines XL3 and XL6 may be located in the second conductive layer, and the first signal lines XL4 and XL5 may be located in the fifth conductive layer.

[0174] In some examples, such as FIG. 14A to FIG. 14D As shown, the data line DL may be located in the fourth conductive layer. One data line DL may be connected to the data transfer electrode 56b located in the third conductive layer, and the data transfer electrode 56b may be connected to the data lead line 55b located in the second conductive layer through the thirty-first via hole V31 opened in the fourth insulating layer. Another data line DL may be connected to the data transfer electrode 56a located in the third conductive layer, and the data transfer electrode 56a may be connected to the data lead line 55a located in the first conductive layer through the thirty-second via hole V32 opened in the fourth insulating layer. The second transfer hole in this example may include the thirty-first via hole V31 and the thirty-second via hole V32. The first connecting bar 2111 may be located on the side of the second transfer hole close to the display area AA in the second direction Y.

[0175] In some examples, such as FIG. 14A to FIG. 14DAs shown, the second signal lines YL1 and YL2 may be located in the third conductive layer. The second signal line YL1 may extend to the display area AA. The second connecting bar 2112 may avoid the vias corresponding to the second signal lines YL1 and YL2. The seventh transfer electrode 417 and the eighth transfer electrode 418 may be located in the third conductive layer. The signal transfer lines ZL1, ZL2 and ZL3 may be located in the third conductive layer, and the signal transfer lines ZL4 and ZL5 may be located in the fourth conductive layer. The signal transfer line ZL1 may be connected to the first signal line XL1, the signal transfer line ZL4 may be connected to the first signal line XL2 through the seventh transfer electrode 417, the signal transfer line ZL2 may be connected to the first signal lines XL3 and XL4, the signal transfer line ZL5 may be connected to the first signal line XL5 through the eighth transfer electrode 418, and the signal transfer line ZL3 may be connected to the first signal line XL6. The first transfer hole of this example may include: a via hole connecting the signal transfer line ZL1 and the first signal line XL1, a via hole connecting the signal transfer line ZL4 and the seventh transfer electrode 417, a via hole connecting the signal transfer line ZL2 and the first signal line XL3, a via hole connecting the signal transfer line ZL2 and the first signal line XL4, a via hole connecting the signal transfer line ZL5 and the eighth connection electrode 418, and a via hole connecting the signal transfer line ZL3 and the first signal line XL6. The second connection bar 2112 may be located on a side of the first transfer hole close to the display area AA.

[0176] In this example, in the first frame corner area C1, the orthographic projection of the first connection structure 211 on the substrate does not overlap with the orthographic projection of the via hole opened in the fourth insulating layer on the substrate, avoiding the risk of electrostatic discharge. The first connection structure 211 can be located on the side of the first transfer via hole and the second transfer via hole close to the display area AA, which can be beneficial to the narrow frame design. The rest of the description of the display substrate of this example can refer to the description of the previous embodiment, so it will not be repeated here.

[0177] Fig.15 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.15As shown, the present embodiment provides a display device 91 which may include: a display substrate 910. The display substrate 910 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power and other departments), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0178] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0179] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a peripheral area located at least on one side of the display area, wherein the peripheral area comprises: at least one first peripheral area extending along a first direction, at least one second peripheral area extending along a second direction, and at least one frame corner area, wherein the at least one frame corner area is connected between adjacent first peripheral areas and second peripheral areas, and the first direction intersects with the second direction; A plurality of pixel circuits and a plurality of data lines are located in the display area, and the plurality of data lines extend along the second direction and are connected to the plurality of pixel circuits; a plurality of multiplexing circuits located in the peripheral area and connected to the plurality of data lines; A first shielding structure is located in the display area and on a side of the plurality of pixel circuits close to the substrate, wherein an orthographic projection of the first shielding structure on the substrate at least partially overlaps with an orthographic projection of the plurality of pixel circuits on the substrate; A frame connection structure, located in the peripheral area, the frame connection structure and the first shielding structure are an integrated structure; The frame connection structure includes: a first connection structure located in the frame corner area, the first connection structure extends in a stepped manner along the edge of the display area, and the first connection structure is located on a side of multiple multiplexing circuits in the frame corner area close to the display area.

2. The display substrate according to claim 1, characterized in that: The display substrate further comprises: a plurality of first signal lines, located in the display area, extending along the first direction and connected to the plurality of pixel circuits; A plurality of first transfer holes and a plurality of transfer electrodes are located in the peripheral area; the plurality of transfer electrodes are connected to the first ends of the plurality of first signal lines extending to the peripheral area through the plurality of first transfer holes; The orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the plurality of first transfer holes in the frame corner area on the substrate.

3. The display substrate according to claim 2, characterized in that: The first connection structure includes: a plurality of first connection bars extending along the first direction, and a plurality of second connection bars extending along the second direction, wherein the plurality of first connection bars and the plurality of second connection bars are connected at intervals to form a step shape.

4. The display substrate according to claim 3, characterized in that: The first connection structure is located on a side of the plurality of first transfer holes in the corner area of ​​the frame away from the display area.

5. The display substrate according to claim 4, characterized in that: At least one first connecting bar among the plurality of first connecting bars is in the shape of a straight bar extending along the first direction, and at least one second connecting bar among the plurality of second connecting bars is in the shape of a straight bar extending along the second direction.

6. The display substrate according to claim 4 or 5, characterized in that: The frame connection structure also includes: a plurality of first auxiliary connection strips located in the frame corner area and extending along the first direction, and a plurality of second auxiliary connection strips extending along the second direction, the plurality of first auxiliary connection strips and the plurality of second auxiliary connection strips are located on the first connection structure and a plurality of first transfer holes in the frame corner area on one side close to the display area, the plurality of first auxiliary connection strips, the plurality of second auxiliary connection strips and the first connection structure are connected to form a plurality of first closed areas, and each first closed area surrounds at least one first transfer hole among the plurality of first transfer holes.

7. The display substrate according to claim 3, characterized in that: The second connecting strip of the first connecting structure is located on a side of the plurality of first transfer holes in the corner area of ​​the frame close to the display area; The first connecting strip of the first connecting structure includes a straight line segment and a folded line segment extending along the first direction. The folded line segment is located on a side of the plurality of first transfer holes close to the display area in the second direction, and the folded line segment bends toward the display area.

8. The display substrate according to claim 2, characterized in that: The display substrate further comprises: A plurality of data lead-out lines and a plurality of second transfer holes are located in the peripheral area; the plurality of data lead-out lines are connected to the plurality of data lines through the plurality of second transfer holes; The orthographic projection of the first connection structure on the substrate does not overlap with the orthographic projection of the plurality of second transfer holes in the corner area of ​​the frame on the substrate.

9. The display substrate according to claim 8, characterized in that: The first connection structure is located at a side of the plurality of first transfer holes and the plurality of second transfer holes in the corner area of ​​the frame close to the display area.

10. The display substrate according to claim 1, characterized in that: The multiplexing circuit includes a plurality of multiplexing control transistors; The display substrate also includes: a second shielding structure located in the corner area of ​​the frame, the second shielding structure's orthographic projection on the substrate covers the orthographic projection of the active layer of multiple multiplexing control transistors of the multiplexing circuit on the substrate, and the second shielding structure is an integrated structure with the first connecting structure.

11. The display substrate according to claim 10, characterized in that: The frame connection structure also includes: a second connection structure located in the corner area of ​​the frame, the second connection structure extends in a stepped manner along the edge of the display area, and a plurality of multiplexing circuits located in the corner area of ​​the frame are located on a side away from the first connection structure; the second connection structure and the second shielding structure are an integrated structure.

12. The display substrate according to claim 10, characterized in that: The frame connection structure also includes: a third connection structure located in the frame corner area and in a mesh shape. The third connection structure is located on a side of the multiple multiplexing circuits in the frame corner area away from the display area and is an integrated structure with the second shielding structure.

13. The display substrate according to claim 1, characterized in that: The frame connection structure also includes: a third connection structure located in the frame corner area and in a mesh shape. The third connection structure is located on a side of the multiple multiplexing circuits in the frame corner area away from the display area and is an integrated structure with the first connection structure.

14. The display substrate according to claim 12 or 13, characterized in that: The third connecting structure includes: a plurality of third connecting bars extending along the first direction, a plurality of fourth connecting bars extending along the second direction, and a fifth connecting bar, the plurality of third connecting bars are connected to the plurality of fourth connecting bars, the fifth connecting bar is connected to ends of the plurality of third connecting bars away from the display area, and the fifth connecting bar is located on a side of the plurality of third connecting bars and the plurality of fourth connecting bars away from the display area.

15. The display substrate according to claim 14, characterized in that: The fifth connecting strip is an arc segment extending along the edge of the display area.

16. The display substrate according to claim 1, characterized in that: The peripheral area includes: two first peripheral areas, two second peripheral areas and four border corner areas, the two first peripheral areas include: a first border area and a second border area, the two second peripheral areas include: a third border area and a fourth border area, the four border corner areas include: a first border corner area, a second border corner area, a third border corner area and a fourth border corner area, the first border corner area is connected between the first border area and the third border area, the second border corner area is connected between the first border area and the fourth border area, the third border corner area is connected between the second border area and the third border area, and the fourth border corner area is connected between the second border area and the fourth border area; The multiplexing circuits are arranged in the first border area, the first border corner area and the second border corner area; The first connection structure is located in the first frame corner area and the second frame corner area.

17. A display device, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 16.

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