Providing adaptive cache bypass in processor-based device

Abstract

Providing adaptive cache bypass in a processor-based device is disclosed. In some aspects, a processor-based apparatus includes a processor that includes a cache. The processor is configured to calculate a cache result rate based on first one or more results of corresponding first one or more cache requests for a cache region of the cache during a sampling period. The processor is also configured to determine that the cache result rate fails to meet a cache result requirement. The processor is further configured to limit access to the cache region of the cache after the sampling period in response to determining that the cache result rate fails to meet the cache result requirement.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 929,525, filed on September 2, 2022, entitled “PROVIDING ADAPTIVE CACHE BYPASSIN PROCESSOR-BASED DEVICES,” which is incorporated herein by reference in its entirety. background I. Technical field

[0004] The technology of the present disclosure generally relates to using caches to reduce memory access latency in processor-based devices. II. Background Technology

[0005] Processor-based devices are subject to a phenomenon known as memory access latency, which is the time interval between the time a processor initiates a memory access request for data (i.e., by executing a memory load instruction) and the time the processor actually receives the requested data. In more extreme cases, the memory access latency for a memory access request may be large enough that the processor is forced to halt further execution of instructions while waiting for the memory access request to be completed. As a result, memory access latency is considered one of the factors that have the greatest impact on the performance of modern processor-based devices.

[0006] One way to minimize the effects of memory access latency is to use cache memory, also referred to simply as "cache". A cache is a memory device that has a smaller capacity than system memory, but can be accessed more quickly by the processor due to the type of memory used and / or the physical location of the cache relative to the processor. Thus, a cache can be used to store copies of data retrieved from frequently accessed memory locations in system memory (or from higher-level cache memory) to reduce memory access latency.

[0007] However, cache usage does not always result in an improvement in memory access latency. Caches generally provide the best performance when frequently accessed data exhibit temporal locality (i.e., a tendency to repeatedly access the same memory location during a given time period while a program is executing) and / or spatial locality (i.e., a tendency to access physically close memory locations during program execution). However, some applications may tend to require frequent memory accesses that exhibit both low temporal locality and low spatial locality. Such applications may suffer from low cache hit rates, which adversely affect overall system performance due to the number of memory access requests that result in both unsuccessful cache requests and subsequent requests to system memory. Specifically, some graphics workloads processed by a graphics processing unit (GPU) may result in a low cache hit rate to the GPU's read-only cluster cache (CCHE). Summary of the invention

[0008] Various aspects disclosed in the specific embodiments include providing adaptive cache bypass in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a processor-based device provides a processor including a cache and an adaptive bypass circuit. The adaptive bypass circuit tracks a cache result rate (e.g., a cache hit rate or a cache miss rate) and bypasses the cache for memory requests when the cache result rate fails to meet a cache result requirement (e.g., a cache hit threshold or a cache miss threshold). In exemplary operation, the processor (e.g., using the adaptive bypass circuit) calculates the cache result rate based on the first one or more results of the corresponding first one or more cache requests for a cache region of the cache during a sampling period (which may include, for example, a period in which a specified number T of cache requests are received). When the sampling period ends, the processor determines whether the cache result rate fails to meet the cache result requirement, and if so, the processor restricts access to the cache region of the cache after the sampling period.

[0009] Some aspects may provide that the cache region directed by the first one or more cache requests may include the entire cache. In such aspects, the processor is configured to restrict access to the cache region of the cache by disabling the cache (so that subsequent memory access requests are fulfilled directly from the next higher level cache, or if the next higher level cache is not provided, the subsequent memory access requests are fulfilled from the system memory without accessing the cache). According to some such aspects, the processor may then wait for a period of time (a "reset interval"), and then re-enable the cache and invalidate the contents of the cache. Then, if necessary, the operations for calculating the cache result rate and determining whether the cache result rate fails to meet the cache result requirement may be repeated. Some such aspects may provide that disabling the cache may include disabling the data memory of the cache while maintaining the operation of the tag memory of the cache. Disabling the data memory in this manner may result in power savings in addition to solving the memory latency problem. In such aspects, the processor may then continue to update the cache result rate based on the second one or more results of the corresponding second one or more cache requests to the cache, and may later determine that the cache result rate now meets the cache result requirement. In this case, the processor re-enables the cache and invalidates the contents of the cache.

[0010] In some aspects, a cache region may include a single cache line of a cache, or may include a subset of multiple cache lines that include a cache. According to such aspects, an adaptive bypass circuit of a processor maintains a tracking table that stores multiple entries that each correspond to a cache region (i.e., each entry corresponds to a single cache line or corresponds to a subset of a cache that includes multiple cache lines). The processor calculates a cache result rate by determining, for each cache request during a sampling period, whether an entry for the corresponding cache region exists in the tracking table, and adds such an entry if necessary. If the cache request results in a cache miss on the cache, the processor then updates the value of the cache miss rate indicator for the entry. If the cache miss rate indicator for the entry exceeds a cache miss threshold, the processor sets a bypass indicator for the entry. After the sampling period ends, when the processor receives a cache request for a cache region of the cache, the processor determines whether the bypass indicator for the entry corresponding to the cache region in the tracking table is set. If so, the processor bypasses the cache for the cache request. Some aspects may provide that the processor may then continue to update the value of the cache miss rate indicator for the entry based on the second one or more results of the corresponding second one or more cache requests to the cache, and may later determine that the cache miss rate for the entry now does not exceed the cache miss threshold. In this case, the processor clears the bypass indicator for the entry.

[0011] In another aspect, a processor-based device is provided. The processor-based device includes a processor, the processor including a cache. The processor is configured to calculate a cache result rate based on first one or more results of corresponding first one or more cache requests for a cache area of ​​the cache during a sampling period. The processor is further configured to determine that the cache result rate fails to meet a cache result requirement. The processor is further configured to, in response to determining that the cache result rate fails to meet the cache result requirement, restrict access to the cache area of ​​the cache after the sampling period.

[0012] In another aspect, a processor-based device is provided. The processor-based device includes components for calculating a cache result rate based on first one or more results of corresponding first one or more cache requests for a cache region of a cache during a sampling period. The processor-based device also includes components for determining that the cache result rate fails to meet a cache result requirement. The processor-based device also includes components for limiting access to a cache region of the cache after the sampling period in response to determining that the cache result rate fails to meet the cache result requirement.

[0013] In another aspect, a method for providing adaptive cache bypass is provided. The method includes calculating, using adaptive bypass circuitry of a processor-based device, a cache result rate based on first one or more results of corresponding first one or more cache requests to a cache region of a cache during a sampling period. The method also includes determining that the cache result rate fails to satisfy a cache result requirement. The method also includes limiting access to the cache region of the cache after the sampling period in response to determining that the cache result rate fails to satisfy the cache result requirement. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of an exemplary processor-based device including adaptive bypass circuitry for providing adaptive cache bypass;

[0015] Figure 2 According to some aspects, a method for providing adaptive cache bypass for an entire cache is provided. Figure 1 A block diagram of exemplary aspects of a processor-based device;

[0016] Figure 3 According to some aspects, a method for providing adaptive cache bypass on a cache region by cache region basis is provided. Figure 1 A block diagram of exemplary aspects of a processor-based device;

[0017] FIG. 4A to FIG. 4E is an example based on some aspects Figure 1 A flowchart of exemplary operation of an adaptive bypass circuit for providing adaptive cache bypass; and

[0018] Figure 5 Yes, it can include Figure 1 A block diagram of an exemplary processor-based device of a processor-based device. DETAILED DESCRIPTION

[0019] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0020] Various aspects disclosed in the specific embodiments include providing adaptive cache bypass in a processor-based device. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a processor-based device provides a processor including a cache and an adaptive bypass circuit. The adaptive bypass circuit tracks a cache result rate (e.g., a cache hit rate or a cache miss rate) and bypasses the cache for memory requests when the cache result rate fails to meet a cache result requirement (e.g., a cache hit threshold or a cache miss threshold). In exemplary operation, the processor (e.g., using the adaptive bypass circuit) calculates the cache result rate based on the first one or more results of the corresponding first one or more cache requests for a cache region of the cache during a sampling period (which may include, for example, a period in which a specified number T of cache requests are received). When the sampling period ends, the processor determines whether the cache result rate fails to meet the cache result requirement, and if so, the processor restricts access to the cache region of the cache after the sampling period.

[0021] Some aspects may provide that the cache region directed by the first one or more cache requests may include the entire cache. In such aspects, the processor is configured to restrict access to the cache region of the cache by disabling the cache so that subsequent memory access requests are fulfilled directly from the system memory or a higher level cache without accessing the cache. According to some such aspects, the processor may then wait for a period of time (a "reset interval"), and then re-enable the cache and invalidate the contents of the cache. Then, if necessary, the operations for calculating the cache result rate and determining whether the cache result rate fails to meet the cache result requirement may be repeated. Some such aspects may provide that disabling the cache may include disabling the data memory of the cache while maintaining operation of the tag memory of the cache. The processor may then continue to update the cache result rate based on the second one or more results of the corresponding second one or more cache requests to the cache, and may later determine that the cache result rate now meets the cache result requirement. In this case, the processor re-enables the cache and invalidates the contents of the cache.

[0022] In some aspects, a cache region may include a single cache line of a cache, or may include a subset of multiple cache lines that include a cache. According to such aspects, an adaptive bypass circuit of a processor maintains a tracking table that stores multiple entries that each correspond to a cache region (i.e., each entry corresponds to a single cache line or corresponds to a subset of a cache that includes multiple cache lines). The processor calculates a cache result rate by determining, for each cache request during a sampling period, whether an entry for the corresponding cache region exists in the tracking table, and adds such an entry if necessary. If the cache request results in a cache miss on the cache, the processor then updates the value of the cache miss rate indicator for the entry. If the cache miss rate indicator for the entry exceeds a cache miss threshold, the processor sets a bypass indicator for the entry. After the sampling period ends, when the processor receives a cache request for a cache region of the cache, the processor determines whether the bypass indicator for the entry corresponding to the cache region in the tracking table is set. If so, the processor bypasses the cache for the cache request. Some aspects may provide that the processor may then continue to update the value of the cache miss rate indicator for the entry based on the second one or more results of the corresponding second one or more cache requests to the cache, and may later determine that the cache miss rate for the entry now does not exceed the cache miss threshold. In this case, the processor clears the bypass indicator for the entry.

[0023] In this regard, Figure 1 An exemplary processor-based device 100 is illustrated that provides a processor 102 for providing adaptive cache bypass. In some aspects, the processor 102 may include a central processing unit (CPU) or a graphics processing unit (GPU) having one or more processor cores, and in some exemplary aspects, may be one of a plurality of similarly configured processors (not shown) of the processor-based device 100. The processor 102 is communicatively coupled to an interconnect bus 104, which in some embodiments may include interconnect bus 104 that is not shown for clarity. Figure 1 104 (e.g., bus controller circuitry and / or arbitration circuitry as non-limiting examples). Processor 102 is also communicatively coupled via interconnect bus 104 to memory controller 106, which controls access to and manages the flow of data to and from system memory 108. As a non-limiting example, system memory 108 provides addressable memory for data storage by processor-based device 100, and thus may include synchronous dynamic random access memory (SDRAM).

[0024] Figure 1The processor 102 also includes a cache 110 that can be used to cache local copies of frequently accessed data within the processor 102 for faster access (e.g., by memory access stages of an execution pipeline (not shown) of the processor 102). The cache 110 provides a plurality of cache lines 112(0)-112(L) for storing frequently accessed data retrieved from the system memory 108. The cache lines 112(0)-112(L) include corresponding tags 114(0)-114(L) (collectively referred to as tag memory 116), each of which stores information that enables the corresponding cache line 112(0)-112(L) to be mapped to a unique memory address. The cache lines 112(0)-112(L) also include data 118(0)-118(L) (collectively referred to as data memory 120), in which the actual data retrieved from the system memory 108 or from a higher level cache is stored. It will be appreciated that cache lines 112(0)-112(L) may include other data elements, such as validity indicators and / or dirty data indicators, which are not shown in the example for the sake of clarity. Figure 1 Shown in.

[0025] Figure 1 The processor 102 in the example of FIG. 1 is also communicatively coupled to a cache 122, which may include, for example, a level 2 (L2) cache, a level 3 (L3) cache, or a unified cache (UCHE) via the interconnect bus 104. The cache 110 and the cache 122 together constitute a hierarchical cache structure used by the processor-based device 100 to cache frequently accessed data for faster retrieval (compared to retrieving data from the system memory 108).

[0026] Figure 1 The processor-based device 100 may include any of known digital logic elements, semiconductor circuits, processing cores, and / or memory structures, as well as other elements or combinations thereof. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts on semiconductor sockets or packages. It will be understood that some embodiments of the processor-based device 100 may include more than Figure 1 For example, processor 102 may also include more or fewer memory devices, execution pipeline stages, controller circuits, buffers, and / or caches, which are not shown for clarity. Figure 1 Omit.

[0027] As discussed above, the use of a cache such as cache 110 may not always result in improvements in memory access latency, particularly in aspects where the processor 102 is a GPU and the cache 110 is a cluster cache (CCHE) for the GPU. A low cache hit rate can adversely affect overall performance due to the processing and memory access overhead incurred by executing both unsuccessful cache requests to cache 110 and subsequent requests to system memory 108 or cache 122. Therefore, in this regard, the processor 102 provides an adaptive bypass circuit 124. The adaptive bypass circuit 124 is configured to monitor cache requests to cache 110 and the results of such requests (i.e., successful cache accesses or "cache hits", in which the requested data is found in cache 110, or unsuccessful cache accesses or "cache misses", in which the requested data is not found and must be retrieved from system memory 108 or cache 122).

[0028] In exemplary operation, adaptive bypass circuit 124 calculates cache result rate 126 based on one or more results of corresponding one or more cache requests 128(0)-128(T) to a cache region of cache 110 during a sampling period. The sampling period may include a time interval during which a specified number T of cache requests are received. A cache region may include an entire cache or may include a single cache line or a cache line group, as described below with respect to Figure 2 and Figure 3 The cache result rate 126 may include a cache hit rate (i.e., the percentage or fraction of cache requests 128(0)-128(T) that result in a cache hit) or a cache miss rate (i.e., the percentage or fraction of cache requests 128(0)-128(T) that result in a cache miss).

[0029] Next, adaptive bypass circuit 124 determines whether cache result rate 126 fails to meet cache result requirement (at Figure 1126) may include a cache result requirement 130 and an operation for determining whether the cache result rate 126 fails to meet the cache result requirement 130. The cache result requirement 130 and the operation for determining whether the cache result rate 126 fails to meet the cache result requirement 130 will depend on the statistical value used as the cache result rate 126. For example, if the cache result rate 126 is a cache hit rate, the cache result requirement 130 may be a cache hit threshold, and determining whether the cache result rate 126 fails to meet the cache result requirement 130 may include determining that the cache hit rate is below the cache hit threshold. Similarly, if the cache result rate 126 is a cache miss rate, the cache result requirement 130 may be a cache miss threshold, and determining whether the cache result rate 126 fails to meet the cache result requirement 130 may include determining that the cache satisfy rate exceeds the cache miss threshold.

[0030] Upon determining that cache result rate 126 fails to satisfy cache result requirement 130, adaptive bypass circuitry 124 restricts access to a cache region (e.g., the entire cache, or a particular cache line or set of cache lines) of cache 110 after a sampling period. As used herein, "restricting access" and its derivatives refer to adaptive bypass circuitry 124 preventing cache requests from being made to cache 110 for memory requests to the cache region, and instead routing such memory requests directly to a higher level cache (such as cache 122), or to system memory 108 if such a cache is not available. This may require, as described below with respect to Figure 2 The cache 110 is completely disabled as discussed above, or as described below with respect to Figure 3 As discussed, limiting access to a single cache line or cache line group. In this way, cache 110 may be bypassed during time periods when cache result rate 126 indicates that use of cache 110 may not provide benefit or may even have a negative impact on system performance.

[0031] Figure 2 Illustrated Figure 1 In one exemplary aspect of a processor-based device 100, the adaptive bypass circuit 124 is configured to track a cache result rate 126 for the entire cache 110. In some aspects, the cache result rate 126 may include a cache hit rate 200, and the cache result requirement 130 may include a cache hit threshold (in Figure 2Such aspects may provide that the adaptive bypass circuit 124 determines that the cache result rate 200 fails to meet the cache result requirement 130 by determining that the cache hit rate 126 is below the cache hit threshold 202. Some aspects may provide that the cache result rate 126 may include a cache miss rate 204, and the cache result requirement 130 may include a cache miss threshold (at Figure 2 According to such aspects, the adaptive bypass circuit 124 can determine that the cache result rate 204 fails to meet the cache result requirement 130 by determining that the cache miss rate 126 exceeds the cache miss threshold 206.

[0032] It will be appreciated that thresholds such as cache hit threshold 202 and cache miss threshold 206 may be set to values ​​determined based on the needs of a particular implementation, and in some aspects may be configurable by a software process such as a driver. For example, if the average hit rate for cache 110 is determined to be 70%, a driver (not shown) may configure cache miss threshold 206 with a value of 30%, thereby causing cache 110 to be bypassed when cache miss rate 204 exceeds 30%. Properly configuring cache miss threshold 206 in this example may result in performance benefits as well as power savings. However, note that if cache miss threshold 206 is set to an inappropriate value (e.g., 20% in the example discussed herein), cache 110 may be unnecessarily bypassed for some memory access operations, which may actually result in greater power consumption due to more frequent accesses to the next higher level cache.

[0033] exist Figure 2In an example of , the adaptive bypass circuit 124 restricts access to a cache region (i.e., the entire cache 110) by disabling the cache 110. In aspects where the cache 110 is a read-write cache and thus may contain modified data or "dirty" data, the adaptive bypass circuit 124 may first perform a flush of dirty data stored in the cache 110 before disabling the cache 110. Some aspects may provide that the adaptive bypass circuit 124 is configured to subsequently re-enable the cache after a reset time interval has elapsed. The reset interval may be determined based on the needs of a particular implementation, and in some aspects may be configurable by a software process such as a driver. After re-enabling the cache at the expiration of the reset interval, the adaptive bypass circuit 124 invalidates the contents of the cache. In some aspects, the adaptive bypass circuit 124 may then repeat the operations for calculating the cache result rate 126, for example to determine whether an earlier condition that caused the unacceptable cache result rate 126 has been resolved, or whether it is appropriate to disable the cache 110 again.

[0034] In accordance with Figure 2 In some aspects of the present invention, adaptive bypass circuitry 124 may disable cache 110 by disabling data memory 120 of cache 110 but maintaining continued operation of tag memory 116 of cache 110. Adaptive bypass circuitry 124 may then continue to update cache result rate 126 based on a second one or more results of corresponding second one or more cache requests 208(0)-208(S) to cache 110. Adaptive bypass circuitry 124 may then determine whether cache result rate 126 now satisfies cache result requirement 130 and, if so, may re-enable cache 110 and invalidate the contents of cache 110.

[0035] Figure 3 Illustrated Figure 1 In another exemplary aspect of the processor-based device 100, the adaptive bypass circuit 124 is configured to track cache request results for each of a plurality of cache areas within the cache 110. In such aspects, the cache result requirement 130 includes a cache miss threshold (in Figure 3 Cache miss threshold 300 may be set to a value determined based on the needs of a particular implementation and, in some aspects, may be configurable by a software process such as a driver. Figure 3The adaptive bypass circuit 124 of the embodiment includes a tracking table 302, which includes a plurality of entries 304(0)-304(E), wherein each of the entries 304(0)-304(E) corresponds to a cache region of the cache 110. For example, in some aspects, each of the entries 304(0)-304(E) may correspond to a single one of the cache lines 112(0)-112(L), while some aspects may provide that each of the entries 304(0)-304(E) corresponds to a subset of the cache 110 including the plurality of cache lines 112(0)-112(L). For purposes of illustration, assume that in Figure 3 , each of entries 304(0)-304(E) corresponds to one of cache lines 112(0)-112(L), such that entry 304(0) corresponds to cache line 112(0), entry 304(1) (not shown) corresponds to cache line 112(1), and so on. In some aspects, tracking table 302 may include Figure 3 Additional information not shown in , such as least recently used (LRU) tracking information.

[0036] Entries 304(0)-304(E) each include a corresponding cache miss rate indicator (in Figure 3 MISS) 306(0)-306(E), and corresponding bypass indicators (in Figure 3 It will be appreciated that entries 304(0)-304(E) may store additional data, such as validity indicators, cache line addresses, etc., which are not shown for clarity, as non-limiting examples. Figure 3 middle.

[0037] In accordance with Figure 3In the example of , adaptive bypass circuit 124 is configured to determine, for each cache request of one or more cache requests 128(0)-128(T) that results in a cache miss during a sampling period, whether an entry corresponding to the cache region of the cache request exists in tracking table 302. Thus, for example, if cache request 128(0) is a miss and is directed to a cache region corresponding to cache line 112(0), adaptive bypass circuit 124 will determine whether an entry in entry 304(0) corresponds to cache line 112(0). If not, adaptive bypass circuit 124 adds an entry for cache line 112(0) (such as entry 304(0)) in entries 304(0)-304(E). Adaptive bypass circuit 124 then updates the value of the cache miss rate indicator (in this example, cache miss rate indicator 306(0) for entry 304(0)) for the entry corresponding to the cache region of cache 110. In some examples, if tracking table 302 is full when adaptive bypass circuit 124 attempts to add a new entry, adaptive bypass circuit 124 will apply a LRU replacement policy to select one of the existing entries 304 ( 0 )- 304 (E) for eviction.

[0038] When a cache miss rate indicator, such as cache miss rate indicator 306(0), is updated during a sampling period, adaptive bypass circuitry 124 determines whether the value of the cache miss rate indicator exceeds cache miss threshold 300. If so, adaptive bypass circuitry 124 sets the corresponding bypass indicator for the entry (e.g., bypass indicator 308(0) for entry 304(0) in the above example) to indicate that cache requests for the cache region corresponding to the entry should bypass cache 110. Thus, after the sampling period has elapsed, when a cache request for the cache region is received, adaptive bypass circuitry 124 may restrict access to the cache region corresponding to the entry (e.g., cache line 112(0) corresponding to entry 304(0)) by determining whether the bypass indicator for the entry (e.g., bypass indicator 308(0)) is set, and if so, bypass cache 110 for the cache request. In some aspects, after the sampling period, adaptive bypass circuitry 124 may continue to update cache miss rate indicators 306(0)-306(E) for subsequent cache requests 310(0)-310(S) that result in a cache miss. If adaptive bypass circuitry 124 subsequently determines that the updated value of the cache miss rate indicator for the entry does not exceed the cache miss threshold, adaptive bypass circuitry 124 clears the bypass indicator for the entry.

[0039] To further describe Figure 1 The processor-based device 100 is operable to provide adaptive cache bypass, FIG. 4A to FIG. 4E A flow chart illustrating an exemplary operation 400 is provided. For clarity, in describing FIG. 4A to FIG. 4E Time reference Figures 1 to 3 It will be appreciated that some aspects may provide that FIG. 4A to FIG. 4E Some of the operations shown may be performed in an order different from that illustrated herein and / or may be omitted. Figure 4A In the example, operation 400 begins at Figure 1 The processor 102 (eg, using Figure 1 The adaptive bypass circuit 124) during the sampling period is based on the cache (e.g., Figure 1 The cache area of ​​the cache 110) corresponds to the first one or more cache requests (e.g., Figure 1 The cache result rate (e.g., Figure 1 Cache result rate 126) (block 402). In some aspects, such as Figure 3 Those aspects illustrated (wherein the cache result rate 126 includes Figure 3 306(0)-306(E)), the operations of block 402 for calculating the cache result rate 126 may include performing a series of operations for each cache request of the first one or more cache requests 128(0)-128(T) that resulted in a cache miss during the sampling period (block 404). The adaptive bypass circuit 124 first determines the tracking table (e.g., Figure 3 Whether there is an entry for the cache area corresponding to the cache request in the tracking table 302 of Figure 3 406). If not, adaptive bypass circuitry 124 adds entry 304(0) corresponding to the cache region of cache 110 (block 408). Processing then resumes at block 410. If adaptive bypass circuitry 124 determines at decision block 406 that entry 304(0) corresponding to the cache region of cache request is present in the tracking table, adaptive bypass circuitry 124 updates the value of cache miss rate indicator 306(0) for entry 304(0) corresponding to the cache region of cache 110 (block 410). Operation 400 then resumes at block 410. Figure 4B Continue at block 412 of .

[0040] Reference now Figure 4B , operation 400 continues, where the adaptive bypass circuit 124 determines that the cache result rate 126 fails to meet the cache result requirement, such as Figure 1 130 (block 412). Some aspects may provide that the operation of block 412 for determining that cached result rate 126 fails to meet cached result requirement 130 includes determining cached result rate 126 (e.g., Figure 2 The cache hit rate of 200) is lower than the cache hit threshold (e.g., Figure 2 According to some aspects, the operation of block 412 for determining that the cache result rate 126 fails to satisfy the cache result requirement 130 may include determining the cache result rate 126 (e.g., Figure 2 The cache miss rate 204) exceeds the cache miss threshold (e.g., Figure 2 Cache miss threshold 206) (block 416). In some aspects (such as Figure 3 In some embodiments, the operations of block 412 for determining that the cache result rate 126 fails to satisfy the cache result requirement 130 may include determining that the value of the cache miss rate indicator 306(0) for the entry 304(0) exceeds the cache miss threshold 300 during the sampling period (block 418). In response to determining that the value of the cache miss rate indicator 306(0) for the entry 304(0) exceeds the cache miss threshold 300, the adaptive bypass circuit 124 sets the bypass indicator 308(0) for the entry 304(0) (block 420). Operation 400 is then performed at Figure 4C Continue at block 422 of .

[0041] Now go to Figure 4C , operation 400 continues with causing adaptive bypass circuit 124 to perform a series of operations in response to determining that cache result rate 126 fails to satisfy cache result requirement 130 (block 422). In aspects where cache 110 is a read-write cache, adaptive bypass circuit 124 performs a flush of dirty data stored in cache 110 (block 424). In all aspects, adaptive bypass circuit 124 restricts access to cache regions of cache 110 after the sampling period (block 426). In some aspects (such as Figure 2 In those aspects shown in FIG. 4 , the operations of block 426 for limiting access to cache regions of cache 110 may include deactivating cache 110 (block 428). Figure 2 Some aspects of the illustration may provide that the operations of block 426 for limiting access to cache regions of cache 110 include maintaining a tag memory (e.g., Figure 1 The tag memory 116) of the cache 110 is operated while disabling the data memory (e.g., Figure 1data storage device 120) (block 430). Figure 3 In the aspects shown, the operations of block 426 for limiting access to a cache region of cache 110 may include performing a series of operations (block 432) in response to a cache request for a cache region of cache 110. In such aspects, adaptive bypass circuitry 124 determines a bypass indicator (e.g., Figure 3 In response to determining that bypass indicator 308(0) is set, adaptive bypass circuit 124 bypasses cache 110 for the cache request (block 436). In some aspects, operation 400 is then performed at Figure 4D Continue at block 438 of .

[0042] refer to Figure 4D Operations 400 according to some aspects may include adaptive bypass circuit 124 re-enabling cache 110 after the reset interval (block 438). Adaptive bypass circuit 124 then invalidates the contents of cache 110 (block 440). Thus, a new sampling period may begin during which adaptive bypass circuit 124 may re-measure cache result rate 126.

[0043] Some aspects may provide that, when cache 110 is disabled, adaptive bypass circuit 124 may be configured to bypass cache 110 based on a corresponding second one or more cache requests (eg, Figure 2 The adaptive bypass circuit 124 may then determine that the cache result rate 126 satisfies the cache result requirement 130 (block 444). In response to determining that the cache result rate 126 satisfies the cache result requirement 130, the adaptive bypass circuit 124 may perform a series of operations (block 446). The adaptive bypass circuit 124 re-enables the cache 110 (block 448). The adaptive bypass circuit 124 then invalidates the contents of the cache 110 (block 450). In some aspects, the operations 400 of some aspects are then performed at Figure 4E Continue at box 452.

[0044] Now turn to Figure 4E , Figure 3Operations 400 in the illustrated aspects may continue with adaptive bypass circuitry 124 updating cache miss rate indicator 306(0) of entry 304(0) corresponding to a cache region of cache 110 (block 452). Adaptive bypass circuitry 124 then determines that cache miss rate indicator 306(0) of entry 304(0) corresponding to a cache region of cache 110 does not exceed cache miss threshold 300 (block 454). In response to determining that cache miss rate indicator 306(0) of entry 304(0) corresponding to a cache region of cache 110 does not exceed cache miss threshold 300, adaptive bypass circuitry 124 clears bypass indicator 308(0) of entry 304(0) (block 456).

[0045] Providing adaptive cache bypass in a processor-based device as disclosed in the various aspects described herein may be provided in or integrated into any processor-based device. Non-limiting examples include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, a motor vehicle, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0046] In this regard, Figure 5 An example of a processor-based device 500 is illustrated, which may include Figure 1 The processor-based device 100 shown in FIG. 5 includes a processor 502 in this example, which includes one or more central processing units (CPUs) in FIG. Figure 5504, which may also be referred to as a CPU core or processor core. The processor 502 may have a cache memory 506 coupled to the processor 502 for quick access to temporarily stored data. The processor 502 is coupled to a system bus 508 and may couple master devices and slave devices included in the processor-based device 500 to each other. As is well known, the processor 502 communicates with these other devices by exchanging address, control, and data information on the system bus 508. For example, the processor 502 may communicate a bus transaction request to a memory controller 510, which is an example of a slave device. Although in Figure 5 Although not illustrated in the figure, multiple system buses 508 may be provided, each of which constitutes a different structure.

[0047] Other master devices and slave devices may be connected to the system bus 508. Figure 5 As shown, as examples, these devices may include a memory system 512 (which includes a memory controller 510 and a memory array 514), one or more input devices 516, one or more output devices 518, one or more network interface devices 520, and one or more display controllers 522. Input device 516 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output device 518 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 520 may be any device configured to allow data exchange to and from network 524. Network 524 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth TM Networks and the Internet. Network interface device 520 may be configured to support any type of communication protocol desired.

[0048] The processor 502 may also be configured to access the display controller 522 via the system bus 508 to control information transmitted to one or more displays 526. The display controller 522 transmits information to be displayed to the display 526 via one or more video processors 528, which process the information to be displayed into a format suitable for the display 526. The display controller 522 and / or the video processor 528 may include a GPU or be integrated into a GPU. The display 526 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0049] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various exemplary components, blocks, modules, circuits and steps has been generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing departure from the scope of the present disclosure.

[0050] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0051] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0052] It is also noted that the operation steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operation can be performed in many different orders except for the illustrated order. In addition, the operation described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operation steps illustrated in the flow chart. Those skilled in the art will also understand that any of a variety of different technologies and processes can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles or any combination thereof.

[0053] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0054] Specific implementation examples are described in the following numbered clauses:

[0055] 1. A processor-based device, the processor-based device comprising:

[0056] a processor, the processor comprising a cache;

[0057] The processor is configured to:

[0058] calculating a cache result rate based on first one or more results of corresponding first one or more cache requests to a cache region of the cache during a sampling period;

[0059] determining that the cached result rate fails to meet a cached result requirement; and

[0060] In response to determining that the cache result rate fails to meet the cache result requirement, access to the cache region of the cache is restricted after the sampling period.

[0061] 2. A processor-based device according to clause 1, wherein:

[0062] The cache region of the cache includes the entire cache; and

[0063] The processor is configured to restrict access to the cache region of the cache by being configured to disable the cache.

[0064] 3. A processor-based device according to clause 2, wherein:

[0065] The cache result rate includes a cache hit rate;

[0066] The cache result requirement includes a cache hit threshold; and

[0067] The processor is configured to determine that the cache result rate fails to satisfy the cache result requirement by being configured to determine that the cache result rate is below the cache hit threshold.

[0068] 4. A processor-based device according to any of clauses 2 to 3, wherein:

[0069] The cache result rate includes a cache miss rate;

[0070] The cache result requirement includes a cache miss threshold; and

[0071] The processor is configured to determine that the cache result rate fails to satisfy the cache result requirement by being configured to determine that the cache result rate exceeds the cache miss threshold.

[0072] 5. A processor-based device according to any of clauses 2 to 4, wherein:

[0073] The cache is a read / write cache; and

[0074] The processor is further configured to perform a flush of dirty data stored in the cache before deactivating the cache.

[0075] 6. A processor-based device according to any of clauses 2 to 5, wherein the processor device is further configured to:

[0076] After a reset interval, re-enabling the cache; and

[0077] Invalidate the contents of the cache.

[0078] 7. A processor-based device according to any of clauses 2 to 6, wherein:

[0079] The processor is configured to disable the cache by being configured to disable a data memory of the cache while maintaining operation of a tag memory of the cache; and

[0080] The processor is further configured to:

[0081] updating the cache result rate based on second one or more results of corresponding second one or more cache requests to the cache;

[0082] determining that the cache result rate satisfies the cache result requirement; and

[0083] In response to determining that the cached result rate satisfies the cached result requirement:

[0084] re-enabling the cache; and

[0085] The contents of the cache are invalidated.

[0086] 8. A processor-based device according to any one of clauses 1 to 7, wherein:

[0087] The cache result rate includes a cache miss rate;

[0088] The processor is configured to calculate the cache result rate by being configured to, for each cache request of the first one or more cache requests for which the result was a cache miss during the sampling period, perform the following operations:

[0089] determining whether an entry for the cache region corresponding to the cache request exists in a tracking table;

[0090] In response to determining that the entry exists, updating a value of a cache miss rate indicator of the entry corresponding to the cache region of the cache; and

[0091] In response to determining that the entry does not exist, adding an entry corresponding to the cache region of the cache;

[0092] The processor is configured to determine that the cache result rate fails to meet a cache result requirement by being configured to:

[0093] during the sampling period, determining whether a value of the cache miss rate indicator of the entry exceeds a cache miss threshold; and

[0094] responsive to determining that the value of the cache miss rate indicator of the entry exceeds the cache miss threshold, setting a bypass indicator for the entry; and

[0095] The processor is configured to restrict access to the cache region of the cache by being configured to, in response to a cache request for the cache region of the cache:

[0096] determining whether a bypass indicator for the entry is set; and

[0097] In response to determining that the bypass indicator is set, the cache is bypassed for the cache request.

[0098] 9. The processor-based device of clause 8, wherein the cache region corresponds to a cache line of the cache.

[0099] 10. A processor-based apparatus as recited in any of clauses 8 to 9, wherein the cache region corresponds to a subset of a plurality of cache lines comprising the cache.

[0100] 11. A processor-based apparatus according to any of clauses 8 to 10, wherein the processor is further configured to, for each cache request of the second one or more cache requests to the cache region of the cache for which the result is a cache miss, perform the following operations:

[0101] updating the value of the cache miss rate indicator corresponding to the entry of the cache region of the cache;

[0102] determining whether the value of the cache miss rate indicator for the entry of the cache region of the cache does not exceed the cache miss threshold; and

[0103] In response to determining that the value of the cache miss rate indicator of the entry corresponding to the cache region of the cache does not exceed the cache miss threshold, the bypass indicator of the entry is cleared.

[0104] 12. A processor-based device according to any of clauses 1 to 11, wherein the capacitor is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor aircraft.

[0105] 13. A processor-based device, the processor-based device comprising:

[0106] means for calculating a cache result rate based on first one or more results of corresponding first one or more cache requests to a cache region of the cache during a sampling period;

[0107] means for determining that the cached result rate fails to meet a cached result requirement; and

[0108] Means for limiting access to the cache region of the cache after the sampling period in response to determining that the cache result rate fails to satisfy the cache result requirement.

[0109] 14. A method for providing adaptive cache bypass, the method comprising:

[0110] calculating, using adaptive bypass circuitry of the processor-based device, a cache result rate based on first one or more results of corresponding first one or more cache requests to a cache region of the cache during a sampling period;

[0111] determining that the cached result rate fails to meet a cached result requirement; and

[0112] In response to determining that the cache result rate fails to meet the cache result requirement, access to the cache region of the cache is restricted after the sampling period.

[0113] 15. A method according to clause 14, wherein:

[0114] The cache region of the cache includes the entire cache; and

[0115] Restricting access to the cache region of the cache includes disabling the cache.

[0116] 16. A method according to clause 15, wherein:

[0117] The cache result rate includes a cache hit rate;

[0118] The cache result requirement includes a cache hit threshold; and

[0119] Determining that the cache result rate fails to satisfy the cache result requirement includes determining that the cache result rate is below the cache hit threshold.

[0120] 17. A method according to any one of clauses 15 to 16, wherein:

[0121] The cache result rate includes a cache miss rate;

[0122] The cache result requirement includes a cache miss threshold; and

[0123] Determining that the cache result rate fails to satisfy the cache result requirement includes determining that the cache result rate exceeds the cache miss threshold.

[0124] 18. A method according to any one of clauses 15 to 17, wherein:

[0125] The cache is a read / write cache; and

[0126] The method also includes performing a flush of dirty data stored in the cache before deactivating the cache.

[0127] 19. A method according to any of clauses 15 to 18, wherein the processor-based device is further configured to:

[0128] After a reset interval, re-enabling the cache; and

[0129] Invalidate the contents of the cache.

[0130] 20. A method according to any one of clauses 15 to 19, wherein:

[0131] Disabling the cache includes disabling a data memory of the cache while maintaining operation of a tag memory of the cache; and

[0132] The method further comprises:

[0133] updating the cache result rate based on second one or more results of corresponding second one or more cache requests to the cache;

[0134] determining that the cache result rate satisfies the cache result requirement; and

[0135] In response to determining that the cached result rate satisfies the cached result requirement:

[0136] re-enabling the cache; and

[0137] Invalidate the contents of the cache.

[0138] 21. A method according to any one of clauses 14 to 20, wherein:

[0139] The cache result rate includes a cache miss rate;

[0140] The cache result rate is calculated by being configured to, for each cache request of the first one or more cache requests for which the result is a cache miss during the sampling period, perform the following operations:

[0141] determining that an entry for the cache region corresponding to the cache request exists in a tracking table; and

[0142] In response to determining that the entry exists, updating a value of a cache miss rate indicator of the entry corresponding to the cache region of the cache;

[0143] Determining that the cache result rate fails to meet the cache result requirement includes:

[0144] during the sampling period, determining that the value of the cache miss rate indicator for the entry exceeds a cache miss threshold; and

[0145] responsive to determining that the value of the cache miss rate indicator for the entry exceeds the cache miss threshold, setting a bypass indicator for the entry; and

[0146] In response to a cache request for the cache region of the cache, limiting access to the cache region of the cache comprises:

[0147] determining that a bypass indicator for the entry is set; and

[0148] In response to determining that the bypass indicator is set, the cache is bypassed for the cache request.

[0149] 22. The method of clause 21, wherein the cache region corresponds to a cache line of the cache.

[0150] 23. A method according to any of clauses 21 to 22, wherein the cache region corresponds to a subset of a plurality of cache lines comprising the cache.

[0151] 24. A method according to any of clauses 21 to 23, wherein the method further comprises, for each cache request of the second one or more cache requests to the cache region of the cache for which the result is a cache miss, performing the following operations:

[0152] updating the value of the cache miss rate indicator corresponding to the entry of the cache region of the cache;

[0153] determining that the value of the cache miss rate indicator for the entry of the cache region of the cache does not exceed the cache miss threshold; and

[0154] In response to determining that the value of the cache miss rate indicator of the entry corresponding to the cache region of the cache does not exceed the cache miss threshold, the bypass indicator of the entry is cleared.

Claims

1. A processor-based device, the processor-based device comprising: a processor, the processor comprising a cache; The processor is configured to: calculating a cache result rate based on first one or more results of corresponding first one or more cache requests to a cache region of the cache during a sampling period; determining that the cache result rate fails to meet a cache result requirement; as well as In response to determining that the cache result rate fails to meet the cache result requirement, access to the cache region of the cache is restricted after the sampling period.

2. The processor-based device of claim 1 , wherein: The cache region of the cache includes the entire cache; and The processor is configured to restrict access to the cache region of the cache by being configured to disable the cache.

3. The processor-based device of claim 2, wherein: The cache result rate includes a cache hit rate; The cache result requirement includes a cache hit threshold; and The processor is configured to determine that the cache result rate fails to satisfy the cache result requirement by being configured to determine that the cache result rate is below the cache hit threshold.

4. The processor-based device of claim 2, wherein: The cache result rate includes a cache miss rate; The cache result requirement includes a cache miss threshold; and The processor is configured to determine that the cache result rate fails to satisfy the cache result requirement by being configured to determine that the cache result rate exceeds the cache miss threshold.

5. The processor-based device of claim 2, wherein: The cache is a read / write cache; and The processor is further configured to perform a flush of dirty data stored in the cache before deactivating the cache.

6. The processor-based device of claim 2, wherein the processor device is further configured to: After a reset interval, re-enabling the cache; and Invalidate the contents of the cache.

7. The processor-based device of claim 2, wherein: The processor is configured to disable the cache by being configured to disable a data memory of the cache while maintaining operation of a tag memory of the cache; and The processor is further configured to: updating the cache result rate based on second one or more results of corresponding second one or more cache requests to the cache; Determining that the cache result rate meets the cache result requirement; as well as In response to determining that the cached result rate satisfies the cached result requirement: re-enabling said cache; as well as The contents of the cache are invalidated.

8. The processor-based device of claim 1 , wherein: The cache result rate includes a cache miss rate; The processor is configured to calculate the cache result rate by being configured to, for each cache request of the first one or more cache requests for which the result was a cache miss during the sampling period, perform the following operations: determining whether an entry for the cache region corresponding to the cache request exists in a tracking table; In response to determining that the entry exists, updating a value of a cache miss rate indicator of the entry corresponding to the cache region of the cache; as well as In response to determining that the entry does not exist, adding an entry corresponding to the cache region of the cache; The processor is configured to determine that the cache result rate fails to meet a cache result requirement by being configured to: during the sampling period, determining whether a value of the cache miss rate indicator of the entry exceeds a cache miss threshold; as well as responsive to determining that the value of the cache miss rate indicator of the entry exceeds the cache miss threshold, setting a bypass indicator for the entry; and The processor is configured to restrict access to the cache region of the cache by being configured to, in response to a cache request for the cache region of the cache: determining whether a bypass indicator for the entry is set; and In response to determining that the bypass indicator is set, the cache is bypassed for the cache request.

9. The processor-based device of claim 8, wherein the cache region corresponds to a cache line of the cache.

10. The processor-based device of claim 8, wherein the cache region corresponds to a subset of a plurality of cache lines comprising the cache.

11. The processor-based device of claim 8, wherein the processor is further configured to, for each cache request of the second one or more cache requests to the cache region of the cache for which the result is a cache miss, perform the following operations: updating the value of the cache miss rate indicator corresponding to the entry of the cache region of the cache; determining whether the value of the cache miss rate indicator for the entry of the cache region of the cache does not exceed the cache miss threshold; and In response to determining that the value of the cache miss rate indicator of the entry corresponding to the cache region of the cache does not exceed the cache miss threshold, the bypass indicator of the entry is cleared.

12. The processor-based device of claim 1, wherein the processor-based device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; Satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multirotors.

13. A processor-based device, the processor-based device comprising: means for calculating a cache result rate based on first one or more results of corresponding first one or more cache requests to a cache region of the cache during a sampling period; means for determining that the cached result rate fails to meet the cached result requirement; as well as Means for limiting access to the cache region of the cache after the sampling period in response to determining that the cache result rate fails to satisfy the cache result requirement.

14. A method for providing adaptive cache bypass, the method comprising: calculating, using adaptive bypass circuitry of the processor-based device, a cache result rate based on first one or more results of corresponding first one or more cache requests to a cache region of the cache during a sampling period; determining that the cache result rate fails to meet a cache result requirement; as well as In response to determining that the cache result rate fails to meet the cache result requirement, access to the cache region of the cache is restricted after the sampling period.

15. The method according to claim 14, wherein: The cache region of the cache includes the entire cache; and Restricting access to the cache region of the cache includes disabling the cache.

16. The method of claim 15, wherein: The cache result rate includes a cache hit rate; The cache result requirement includes a cache hit threshold; and Determining that the cache result rate fails to satisfy the cache result requirement includes determining that the cache result rate is below the cache hit threshold.

17. The method of claim 15, wherein: The cache result rate includes a cache miss rate; The cache result requirement includes a cache miss threshold; and Determining that the cache result rate fails to satisfy the cache result requirement includes determining that the cache result rate exceeds the cache miss threshold.

18. The method of claim 15, wherein: The cache is a read / write cache; and The method also includes performing a flush of dirty data stored in the cache before deactivating the cache.

19. The method of claim 15, wherein the processor-based device is further configured to: After a reset interval, re-enabling the cache; and Invalidate the contents of the cache.

20. The method of claim 15, wherein: Deactivating the cache includes deactivating a data memory of the cache while maintaining operation of a tag memory of the cache; and The method further comprises: updating the cache result rate based on second one or more results of corresponding second one or more cache requests to the cache; determining that the cache result rate satisfies the cache result requirement; and In response to determining that the cached result rate satisfies the cached result requirement: re-enabling the cache; and Invalidate the contents of the cache.

21. The method of claim 14, wherein: The cache result rate includes a cache miss rate; The cache result rate is calculated by being configured to, for each cache request of the first one or more cache requests for which the result is a cache miss during the sampling period, perform the following operations: determining that an entry for the cache region corresponding to the cache request exists in a tracking table; as well as In response to determining that the entry exists, updating a value of a cache miss rate indicator of the entry corresponding to the cache region of the cache; Determining that the cache result rate fails to meet the cache result requirement includes: during the sampling period, determining that the value of the cache miss rate indicator for the entry exceeds a cache miss threshold; and responsive to determining that the value of the cache miss rate indicator for the entry exceeds the cache miss threshold, setting a bypass indicator for the entry; and In response to a cache request for the cache region of the cache, limiting access to the cache region of the cache comprises: determining that a bypass indicator for the entry is set; and In response to determining that the bypass indicator is set, the cache is bypassed for the cache request.

22. The method of claim 21, wherein the cache region corresponds to a cache line of the cache.

23. The method of claim 21, wherein the cache region corresponds to a subset of a plurality of cache lines comprising the cache.

24. The method of claim 21, wherein the method further comprises, for each cache request of the second one or more cache requests to the cache region of the cache for which the result is a cache miss, performing the following operations: updating the value of the cache miss rate indicator corresponding to the entry of the cache region of the cache; determining that the value of the cache miss rate indicator for the entry of the cache region of the cache does not exceed the cache miss threshold; and In response to determining that the value of the cache miss rate indicator of the entry corresponding to the cache region of the cache does not exceed the cache miss threshold, the bypass indicator of the entry is cleared.

Images