Visual quality optimization for GPU synthesis

Abstract

Aspects presented herein relate to methods and apparatus for display processing, including devices, such as a CPU. The apparatus may obtain an indication of at least one frame comprising a plurality of layers, wherein the at least one frame is associated with a display process. The apparatus may map each of the plurality of layers for processing at the DPU or GPU. Further, the apparatus may detect whether each of the plurality of layers is a rotating animation layer or a non-rotating animation layer based on the mapping. The apparatus may also divide the frame buffer into a set of ROIs for each non-rotating animation layer. The apparatus may also assign a first per-tier processor at the DPU to each rotating animation tier, or at least one second per-tier processor at the DPU to each ROI of the set of ROIs in the frame buffer for each non-rotating animation tier.

Description

Technical Field

[0001] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display processing. Background Art

[0002] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may require the use of a GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values, and may issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0003] The GPU of a device may be configured to perform processes in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, the need for improved graphics or display processing continues to increase. Summary of the invention

[0004] The following presents the summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify the key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0005] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device may be a central processing unit (CPU), a display processing unit (DPU), a graphics processing unit (GPU), or any device that can perform display processing. The device may obtain an indication of at least one frame including a plurality of layers, wherein the at least one frame is associated with display processing. The device may also map each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU). In addition, based on mapping each of the plurality of layers for processing at a DPU or a GPU, the device may mark each of the plurality of layers mapped for processing at the DPU. The device may also detect whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the plurality of layers. In addition, the device may divide a frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers. The device may also assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or assign at least one second per-layer processor at the DPU to each ROI in a set of ROIs in a frame buffer for each non-rotational animation layer in the plurality of layers. The device may also send a second indication of allocating a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocating at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers. In addition, the device may process each non-rotational animation layer in the plurality of layers based on a second compositing stage for each ROI in the set of ROIs in the frame buffer.

[0006] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example content generation system.

[0008] Figure 2 An example graphics processing unit (GPU) is illustrated.

[0009] Figure 3 An example display framework including a display processor and a display is illustrated.

[0010] Figure 4 is a diagram illustrating an example mask layer for display processing.

[0011] Figure 5 is a diagram illustrating an example layer composition scheme for display processing.

[0012] Figure 6 is a diagram illustrating an example of layer processing for DPU synthesis and GPU synthesis.

[0013] Figure 7 is a diagram illustrating an example of a composition scheme for display processing.

[0014] Figure 8 is a diagram illustrating an example of a composition scheme for display processing.

[0015] Fig. 9 is a diagram illustrating an example of a flowchart for display layer processing associated with DPU composition and GPU composition.

[0016] Fig.10 is a communication flow diagram illustrating example communications between a DPU, a GPU, and a display.

[0017] Fig.11 is a flow chart showing an example method of processing.

[0018] Fig.12 is a flow chart showing an example method of processing. DETAILED DESCRIPTION

[0019] Some types of display processing devices can utilize complex multiple content layouts in a single display processing layer or multiple display processing layers. That is, for the graphics or display stack in the operating system of the device, there may be a single display processing layer (i.e., a display layer or layer associated with display processing) or multiple display processing layers. For example, there may be at least one display layer that can be associated with the screen or frame of the display processing device, so that the display panel at the device can be divided between display layers. In addition, for content or end users, there may be multiple content entities in the display processing layer. This may be due to operating system limitations and / or application rendering / resource management limitations. Further, some types of applications may choose to use a single display processing layer for rendering. Color processing capabilities based on each region (i.e., for each region of interest (ROI) in the layer) can be utilized with certain types of display processing unit (DPU) architectures. Current mobile consumer electronic devices utilize different types of DPU image processing (e.g., DPU flexible image processing per layer). Based on the content of different layers, providing accurate per-layer image processing may be important for the perception of end users. There may be multiple different types of per-layer image processing, such as video high dynamic range (HDR) layer tone mapping and processing and / or video standard dynamic range (SDR) layer visual contrast enhancement. The type of per-layer image processing may also include appropriate tone mapping for photo image layers, game layer color processing and flexible visual control options provided to end users, flexible visual control options for video layers provided to end users, and flexible visual control options for text / user interface (UI) layers provided to end users. In some aspects of display processing, there may be visual differences between DPU synthesis and GPU synthesis. For example, the visual difference may cause display screen flickering or refresh problems, such as stuttering (e.g., caused by the display application being unable to keep up with the refresh rate of the display). In addition, the visual difference between DPU synthesis and GPU synthesis may cause visual artifacts in different types of scenes. In some cases, DPU per-layer image processing may make this problem more serious. For example, after the display layer is switched or restored to GPU synthesis, the visual effects of DPU per-layer image processing may be reduced or eliminated. With the emergence of flexible DPU per-layer image processing in different scenes, the problem of reducing or eliminating the visual effects associated with GPU synthesis may become an important issue. For both DPU synthesis and GPU synthesis, there may be many problems with each layer of image processing. This may pose a challenge to the technical bottlenecks and engineering efforts of display devices. One of the reasons for these problems is that the DPU processing pipeline per layer may be complex and flexible. Compared to the DPU pipeline, it may be difficult to implement the same processing technology in the GPU pipeline. In order to keep the GPU path processing consistent with the DPU path processing for each layer of image processing, more engineering efforts may be required. In addition, GPU processing may generate more power consumption and may cause potential problems of performance degradation.Optimizing the power and / or performance of the GPU in different scenarios may be a challenge. For example, high-definition video tone mapping and processing in the GPU may require more engineering efforts because there are many limitations in power, performance and / or visual quality. Various aspects of the present disclosure can keep GPU per-layer processing consistent with DPU per-layer processing. That is, the various aspects presented herein can provide visual effects or image enhancements similar to per-layer processing for DPU synthesis for each layer of processing for GPU synthesis. For example, various aspects of the present disclosure can implement the same processing technology as the DPU pipeline in the GPU pipeline. In addition, various aspects of the present disclosure can keep GPU path processing consistent with DPU path processing for each layer of image processing. In addition, various aspects of the present disclosure can optimize the power and / or performance of each layer of image processing at the GPU compared to each layer of image processing at the DPU. For example, various aspects presented herein can provide high-definition or HDR video tone mapping and processing for both the GPU and the DPU.

[0020] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods implemented using other structures, functions, or structures and functions other than or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein can be embodied by one or more elements of the claims.

[0021] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure rather than limit it, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0022] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0023] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as a processing unit). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in a processing system may execute software. Software may be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" may refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including a code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0024] Therefore, in one or more examples described herein, the described functions can be implemented in hardware, software, or any combination thereof. If implemented with software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available media that can be accessed by a computer. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage device, magnetic disk storage device, other magnetic storage devices, a combination of computer-readable media of the above type, or any other medium that can be used to store instructions or data structure forms that can be accessed by a computer.

[0025] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphics content and / or reduce load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0026] As used herein, instances of the term "content" may refer to "graphic content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0027] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. As another example, the display processing unit may be configured to synthesize, blend or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently blended.

[0028] Figure 1 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to another device. In some aspects, this situation is referred to as split rendering.

[0029] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (such as display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head mounted display, or any other type of display device.

[0030] Memory external to the processing unit 120 and the content encoder / decoder 122, such as the system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0031] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0032] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0033] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagation signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0034] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0035] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0036] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0037] Reference again Figure 1In some aspects, the display processor 127 may include a synthesis component 198 configured to obtain an indication of at least one frame including a plurality of layers, wherein the at least one frame is associated with display processing. The synthesis component 198 may also be configured to map each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU). The synthesis component 198 may also be configured to mark each of the plurality of layers mapped for processing at the DPU based on mapping each of the plurality of layers for processing at the DPU or at the GPU. The synthesis component 198 may also be configured to detect whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the plurality of layers. The synthesis component 198 may also be configured to divide the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer of the plurality of layers. The synthesis component 198 may also be configured to assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or to assign at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers. The synthesis component 198 may also be configured to send a second indication of assigning the first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or to assign at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers. The synthesis component 198 may also be configured to process each non-rotational animation layer in the plurality of layers based on a second synthesis stage for each ROI in the set of ROIs in the frame buffer. Although the following description may focus on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0038] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, a vehicle-mounted computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0039] The GPU may process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU may process two types of data or data packets, such as context register packets and draw call data. The context register packet may be a collection of global state information, such as information about global registers, shaders, or constant data, which may adjust how the graphics context is to be processed. For example, the context register packet may include information about the color format. In some aspects of the context register packet, there may be a bit indicating which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, the context register may define multiple states of the GPU.

[0040] The context state can be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To this end, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in a pipeline based on the context register definition of the mode or state. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state may follow the changed mode or state.

[0041] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, a second level (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220 to 238, but GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and any combination or order of processing units may be used with a GPU according to the present disclosure. GPU 200 also includes command buffer 250, context register group 260, and context state 261.

[0042] like Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. In addition, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0043] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or drawing calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs may allow both tile rendering and direct rendering.

[0044] Figure 3is a block diagram 300 illustrating an example display framework including a processing unit 120 , a system memory 124 , a display processor 127 , and a display 131 , as may be identified in connection with device 104 .

[0045] The GPU may be included in a device that provides content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which may be a computer workstation, a mobile phone, a smart phone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. The operation of the GPU 310 may be controlled based on one or more graphics processing commands provided by the CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the multiple applications executed concurrently may utilize the GPU 310 at the same time. The processing technology may be performed by outputting frames via the processing unit 120 over a physical or wireless communication channel.

[0046] System memory 124, which may be executed by processing unit 120, may include user space 320 and kernel space 325. User space 320 (sometimes referred to as "application space") may include software applications and / or application frameworks. For example, software applications may include operating systems, media applications, graphics applications, workspace applications, etc. The application framework may include a framework used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application program interfaces (APIs), etc. Kernel space 325 may further include a display driver 330. Display driver 330 may be configured to control display processor 127. For example, display driver 330 may cause display processor 127 to synthesize a frame and send data of the frame to a display.

[0047] Display processor 127 includes display control block 335 and display interface 340. Display processor 127 may be configured to manipulate functions of display 131 (e.g., based on input received from display driver 330). Display control block 335 may be further configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of processing unit 120 on system memory 124.

[0048] The display interface 340 may be configured to cause the display 131 to display an image frame. The display interface 340 may output image data to the display 131 according to an interface protocol such as, for example, MIPIDSI (Mobile Industry Processor Interface, Display Serial Interface). That is, the display 131 may be configured according to the MIPIDSI standard. The MIPIDSI standard supports a video mode and a command mode. In an example where the display 131 operates in the video mode, the display processor 127 may continuously refresh the graphics content of the display 131. For example, the entire graphics content may be refreshed at each refresh cycle (e.g., line by line). In an example where the display 131 operates in the command mode, the display processor 127 may write the graphics content of the frame to the buffer 350.

[0049] In some such examples, display processor 127 may not continuously refresh the graphics content of display 131. Instead, display processor 127 may use vertical synchronization (Vsync) pulses to coordinate the rendering and consumption of graphics content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 may output new graphics content to buffer 350. Thus, the generation of a Vsync pulse may indicate that current graphics content has been rendered at buffer 350.

[0050] Based on the display controller 345, the display client 355, and the buffer 350, the frame is displayed at the display 131. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.

[0051] The display client 355 may be associated with a touch panel that senses interactions between a user and the display 131. When a user interacts with the display 131, one or more sensors in the touch panel may output a signal to the display controller 345 indicating which of the one or more sensors has sensor activity, the duration of the sensor activity, the pressure applied to the one or more sensors, etc. The display controller 345 may use the sensor output to determine the manner in which the user is interacting with the display 131. The display 131 may further be associated with / include other devices that operate in conjunction with the display client 355, such as a camera, a microphone, and / or a speaker.

[0052] Some processing techniques of device 104 may be performed through three stages (e.g., stage 1: rendering stage; stage 2: composition stage; and stage 3: display / delivery stage). However, other processing techniques may combine the composition stage and the display / delivery stage into a single stage, such that the processing technique may be performed based on a total of two stages (e.g., stage 1: rendering stage; and stage 2: composition / display / delivery stage). During the rendering stage, GPU 310 may process a content buffer based on the execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stages, pixel elements may be assembled to form a frame that is delivered to a physical display panel / subsystem (e.g., display 131) that displays the frame.

[0053] Instructions (e.g., software instructions) executed by a CPU or instructions executed by a display processor may cause the CPU or display processor to search and / or generate a synthesis strategy for synthesizing a frame based on dynamic priorities and runtime statistics associated with one or more synthesis strategy groups. A frame to be displayed by a physical display device (such as a display panel) may include multiple layers. In addition, the synthesis of a frame may be based on combining multiple layers into a frame (e.g., based on a frame buffer). After combining multiple layers into a frame, the frame may be provided to a display panel for display on the display panel. The process of combining each layer in a plurality of layers into a frame may be referred to as synthesis, frame synthesis, synthesis procedure, synthesis process, etc.

[0054] The frame synthesis procedure or synthesis strategy may correspond to a technique for synthesizing different layers in a plurality of layers into a single frame. The plurality of layers may be stored in a double data rate (DDR) memory. Each layer in the plurality of layers may further correspond to a separate buffer. A synthesizer or hardware synthesizer (HWC) associated with a block or function may determine the input of each layer / buffer and execute the frame synthesis procedure to generate an output indicating a synthesized frame. That is, the input may be a layer, and the output may be a frame synthesis procedure for synthesizing a frame to be displayed on a display panel.

[0055] Some aspects of display processing may utilize different types of mask layers, such as shape mask layers. A mask layer is a layer that can represent a portion of a display or display panel. For example, an area of ​​a mask layer may correspond to an area of ​​a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of the display area. In addition, for certain portions of the display area, the content of different mask layers may overlap with each other. Thus, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.

[0056] Figure 44 is a diagram illustrating an example mask layer for display processing. More specifically, diagram 400 depicts one type of mask layer that can represent portions of a display panel. Figure 4 As shown, diagram 400 includes a mask layer 402, which includes a top region 410 and a bottom region 420. The top region 410 includes regions 411, 412, 413, and 414, and the bottom region 420 includes regions 421, 422, 423, and 424. Figure 4 As depicted, mask layer 402 may represent different areas displayed on the display panel.

[0057] Some types of displays may use a certain type of mask layer (e.g., a shape mask layer) to reshape the display frame. For example, the mask layer may reshape the display frame to provide a more optimized visual shape at the display panel (e.g., improved rounded corners, improved circular shape, improved rectangular shape, etc.). These types of mask layers (e.g., shape mask layers) may be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software), or by hardware (e.g., display processing unit (DPU) hardware). In addition, these mask layers may be processed by other specific types of hardware logic modules (e.g., modules in display driver integrated circuits (DDICs) or bridge chips). In some aspects, these types of mask layers (e.g., shape mask layers) may be based on a certain unit, such as a pixel. That is, the shape generation base unit of the shape mask layer may be a single pixel.

[0058] Some aspects of display processing can utilize frame buffers to cache or store the composite output of the GPU. For example, after synthesis at the GPU, the display layer can be cached or stored in a frame buffer. In some aspects, the synthesis hardware (HW) or software (SW) stack can use a frame buffer target to cache the synthesis output (e.g., GPU synthesis output or CPU synthesis output). The cached synthesis output can then be transmitted to another processor (e.g., DPU) as an input layer. The frame buffer can have multiple different color formats, such as red (R) green (G) blue (B) α (A) (RGBA) format (e.g., RGBA8888 format). Moreover, the frame buffer can have a specific size (e.g., 32-bit triple buffer). For example, at the beginning of the display / graphics subsystem design, the frame buffer can be created as RGBA8888 format and 32-bit triple buffer. In some cases, if the frame layer does not use a specific synthesis (e.g., GPU or client synthesis), the frame buffer can be ignored. Moreover, the layer (e.g., a frame layer or display layer associated with the display process) can be directly extracted and synthesized. For example, a DPU or hardware synthesizer may extract the layers directly and then synthesize the layers.

[0059] Figure 5 5 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 500 depicts layer composition of display layers, where some layers (e.g., layers of a particular composition) are cached in a frame buffer and some layers are fetched and composed directly by the DPU. Figure 5 As shown, diagram 500 includes layer 510 , layer 511 , layer 512 , layer 513 , a frame buffer 530 (eg, an RGBA8888 format frame buffer), a DPU 540 , and a display 550 . Figure 5 It is depicted that layers synthesized at the GPU (i.e., layers associated with GPU synthesis) can be cached or stored in a frame buffer. For example, layer 510, layer 511, and layer 512 can be synthesized at the GPU and then cached / stored at frame buffer 530. Alternatively, layers that are not synthesized at the GPU (i.e., layers associated with non-GPU synthesis) can be directly extracted and synthesized at the DPU. For example, layer 513 can be directly extracted and synthesized at DPU 540. That is, layer 510, layer 511, and layer 512 can be a particular type of synthesis (e.g., GPU synthesis), while layer 513 can be another type of synthesis (non-GPU synthesis). After being cached / stored in frame buffer 530, layer 510, layer 511, and layer 512 can be transmitted to DPU 540. Further, after processing at DPU 540, layers 510 to 513 can be transmitted to display 550.

[0060] Some types of display processing devices (e.g., mobile devices, computers, TVs, or other consumer devices) can utilize complex multiple content layouts in a single display processing layer or multiple display processing layers. That is, for the graphics or display stack in the device's operating system, there can be a single display processing layer (i.e., a display layer or layers associated with display processing) or multiple display processing layers. For example, there can be at least one display layer that can be associated with a screen or frame of a display processing device, so that the display panel at the device can be divided between display layers. In addition, for content or end users, there can be multiple content entities in the display processing layer. This may be due to operating system limitations and / or application rendering / resource management limitations. Further, some types of applications may choose to use a single display processing layer for rendering. Color processing capabilities on a per-region basis (i.e., for each region of interest (ROI) in the layer) can be utilized with certain types of display processing unit (DPU) architectures.

[0061] Current mobile consumer electronic devices utilize different types of DPU image processing (e.g., DPU flexible image processing per layer). Based on the content of different layers, providing accurate per-layer image processing may be important for the perception of the end user. There may be multiple different types of per-layer image processing, such as video high dynamic range (HDR) layer tone mapping and processing and / or video standard dynamic range (SDR) layer visual contrast enhancement. The type of per-layer image processing may also include appropriate tone mapping for a photo image layer, game layer color processing and flexible visual control options provided to the end user, flexible visual control options for a video layer provided to the end user, and flexible visual control options for a text / user interface (UI) layer provided to the end user.

[0062] In some aspects of display processing, there may be visual differences between DPU synthesis and GPU synthesis. For example, this visual difference can cause display screen flickering or refresh problems, such as stuttering (for example, caused by the display application being unable to keep up with the refresh rate of the display). In addition, the visual difference between DPU synthesis and GPU synthesis can cause visual artifacts in different types of scenes. In some cases, DPU per-layer image processing can make this problem more serious. For example, after the display layer switches or reverts to GPU synthesis, the visual effects of DPU per-layer image processing may be reduced or eliminated. With the emergence of flexible DPU per-layer image processing in different scenes, the problem of reduced or eliminated visual effects associated with GPU synthesis may become an important issue.

[0063] Figure 6 6 is a diagram 600 illustrating an example of layer processing for DPU composition and GPU composition. For example, diagram 600 depicts per-layer processing of DPU composition 602 for display layer 610 (e.g., a layer of a composition) in a frame, where the layer includes different regions or regions of interest (ROIs). Figure 6 As shown, display layer 610 includes region 620, region 621, and region 622. Each of region 620, region 621, or region 622 may be associated with a region of interest (ROI) or an ROI for color processing. In addition, diagram 600 depicts a per-layer process of GPU composition 652 for display layer 660 (e.g., a layer of a composition) in a frame, where the layer includes different regions or ROIs. Figure 6As shown, display layer 660 includes region 670, region 671, and region 672. Each of region 670, region 671, or region 672 may be associated with an ROI or an ROI for color processing. More specifically, diagram 600 shows that each layer of processing may be performed for DPU synthesis (e.g., DPU synthesis 602) and / or GPU synthesis (e.g., GPU synthesis 652). Each layer of processing for DPU synthesis 602 may be associated with image enhancement (i.e., improving the quality or pixel count of the image) or an increased number of visual effects. However, each layer of processing for GPU synthesis 652 may not be associated with image enhancement or a reduced number of visual effects. Therefore, compared with each layer of processing for GPU synthesis 652, each layer of processing for DPU synthesis 602 may have more visual effects.

[0064] like Figure 6 As shown, for both DPU synthesis and GPU synthesis, there may be many problems in each layer of image processing. This may pose a challenge to the technical bottlenecks and engineering efforts of display devices. One of the reasons for these problems is that the DPU processing pipeline may be complex and flexible. Compared with the DPU pipeline, it may be difficult to implement the same processing technology in the GPU pipeline (for example, this may require more engineering efforts to GPU software, software application program interface (API), GPU driver and / or GPU hardware). In order to keep the GPU path processing consistent with the DPU path processing for each layer of image processing, more engineering efforts may be required. In addition, GPU processing may generate more power consumption and may cause potential problems of performance degradation. It may be a challenge to optimize the power and / or performance of the GPU in different scenarios. For example, high-definition (for example, HDR10) video tone mapping and processing in the GPU may require more engineering efforts because there are many limitations in power, performance and / or visual quality. Therefore, it may be beneficial to keep the GPU processing consistent with the DPU processing. For example, it may be beneficial to make the processing of each layer for GPU synthesis have visual effects or image enhancements similar to the processing of each layer for DPU synthesis.

[0065] Aspects of the present disclosure can keep GPU per-layer processing consistent with DPU per-layer processing. That is, the aspects presented herein can provide visual effects or image enhancements similar to per-layer processing for DPU synthesis for each layer of processing for GPU synthesis. For example, aspects of the present disclosure can implement the same processing technology as the DPU pipeline in the GPU pipeline. In addition, aspects of the present disclosure can keep GPU path processing consistent with DPU path processing for each layer of image processing. In addition, aspects of the present disclosure can optimize the power and / or performance of each layer of image processing at the GPU compared to each layer of image processing at the DPU. For example, the aspects presented herein can provide high-definition or HDR video tone mapping and processing for both the GPU and the DPU.

[0066] In some cases, various aspects of the present disclosure may analyze the layer stack of the current frame or screen at the display device (e.g., the stack of display layers). In addition, in some cases, various aspects of the present disclosure may be associated with a CPU, a DPU driver, a DPU, or a GPU. Moreover, the various aspects presented herein may identify display layers that may require DPU-specific processing and / or may be synthesized by a GPU (e.g., an operating system (OS) framework). After doing so, the various aspects presented herein may mark these layers as DPU-related layers (i.e., layers to be processed at the DPU). The various aspects presented herein may also determine whether each layer in the display layer is a rotational animation layer or a non-rotational animation layer. "Rotational animation layer" or "rotational animation layer" may refer to a layer that rotates during an animation (e.g., an animation at a DPU or GPU) or a layer associated with an animation frame. "Non-rotational animation layer" or "non-rotational animation layer" may refer to a layer that does not rotate during an animation (e.g., an animation at a DPU or GPU) or a layer associated with a non-animation frame. In addition, the various aspects presented herein may identify a non-rotational animation layer by determining whether the coordinates / shape of the relevant layer have any changes. If the associated layer corresponds to a change in coordinates / shape, the layer may be a rotational animation layer or may be associated with an animation frame.

[0067] In some aspects, for non-rotational animation layers, the various aspects presented herein may divide a frame buffer (e.g., a GPU synthesis output frame buffer) into different regions of interest (ROIs). A frame buffer may also be referred to as a "frame buffer" or any other appropriate term. For example, for non-rotational animation layers, the various aspects presented herein (e.g., a CPU or DPU driver) may divide a frame buffer (e.g., a GPU output) into multiple synthesis stages and then apply regional processing. As described herein, a related layer may be included in a region (i.e., ROI) of a DPU-related layer. A DPU-related layer may refer to a layer to be processed at a DPU. For each separate DPU-related layer, the various aspects presented herein may allocate an ROI. If some ROIs overlap, the various aspects presented herein will allocate ROIs according to the layer's hierarchy or display hierarchy (i.e., Z order or Z order). The various aspects presented herein may also allocate regions of DPU-unrelated layers (i.e., layers that may not be processed at a DPU).

[0068] In addition, for each ROI in the frame buffer, the ROI can be assigned to a separate synthesis stage and assigned to a DPU per-layer processor or component in the DPU pipeline (e.g., a processing pipeline or source surface processor pipeline (SSPP)). The ROI can be assigned to a synthesis stage or DPU per-layer processor for specifying color / image post-processing, three-dimensional (3D) lookup tables (LUTs), or other detail enhancement. The ROI for the DPU-related layer can be assigned to a higher layer level or display level (i.e., Z order or Z order). In a subsequent synthesis stage, the entire frame buffer (e.g., the frame buffer excluding the previous ROI area) can be acquired and synthesized at a lower layer level or display level (e.g., a level for the background). In addition, the frame buffer can be divided into multiple ROIs, and / or additional synthesis stages can be added for sub-frame buffer areas (e.g., logically newly added sub-frame buffer areas). In some aspects, ROI-specified area processing can be determined by the DPU-related layer level (e.g., Z order), blending mode, and / or the original processing configuration of the layer. For example, if the DPU-related layer is at the top of the regional layer stack and / or a layer has a constant blending value (i.e., a blending alpha value), then ROI-specified regional processing for the layer may be determined. In addition, if the DPU-related layer is not at the top of the regional layer stack and a layer is covered by one or more transparent layers, then ROI-specified regional processing for the layer may also be determined. In some cases, the DPU-related layer original processing configuration may correspond to the ROI-specified regional processing. In other cases, the various aspects presented herein may discard the original processing configuration of the layer. For example, a first layer may be associated with a first color temperature adjustment configuration, which may be applied to a frame buffer ROI by a DPU per-layer processor (e.g., a processing pipeline or SSPP).

[0069] Figure 7 700 is a diagram illustrating an example of a composition scheme for display processing. More specifically, diagram 700 depicts a composition scheme for a frame buffer 702 (e.g., a GPU composition output frame buffer), where diagram 700 includes a display layer 704 with a ROI, different composition stages, and corresponding components in DPU hardware 725. Figure 7 As shown, diagram 700 includes a display layer 704 having regions (e.g., region 710), and multiple compositing stages (e.g., compositing stage 720 and compositing stage 721). Region 710 may be a ROI or a DPU-related ROI (i.e., corresponding to a ROI processed at a DPU). Figure 7 As illustrated in FIG. 1 , the DPU hardware 725 includes a bus interface 726, a color converter 728, a plurality of latency buffer components (e.g., latency buffer component 730, latency buffer component 731, latency buffer component 732, and latency buffer component 733), and a plurality of image processing components (e.g., image processing component 740, image processing component 741, image processing component 742, and image processing component 743). The DPU hardware 725 also includes a crossbar switch 750, a multi-layer mixer (e.g., layer mixer 760, layer mixer 761, layer mixer 762, and layer mixer 763), a plurality of frame processing components (e.g., frame processing component 770 and frame processing component 771), and a plurality of physical display processing components (e.g., physical display processing component 780, physical display processing component 781, physical display processing component 782, and physical display processing component 783). In some aspects, the latency buffer component or the image processing component may correspond to a processing pipeline or a source surface processor pipeline (SSPP) in the DPU.

[0070] like Figure 7As depicted, the display layer 704 may be included in a plurality of layers obtained from a GPU, an application, or a game. For example, the CPU may obtain an indication of a plurality of layers (including the display layer 704) associated with at least one frame, wherein each of the plurality of layers includes a set of layer regions or ROIs (e.g., one or more layer regions or ROIs); and wherein each layer region or ROI in the set of layer regions or ROIs includes a plurality of pixels. Each layer region (e.g., region 710) in the layer regions in the display layer 704 may correspond to a specific component (e.g., one of the latency buffer components 730-733 or the image processing components 740-743) and / or a specific synthesis stage (e.g., one of the synthesis stages 720-721) in the DPU hardware 725. For example, each layer region in the set of layer regions may be assigned to a corresponding component in a set of components in the DPU pipeline. For example, region 710 may be assigned or assigned to the latency buffer component 730 or the image processing component 740. Furthermore, the frame buffer 702 (except for the region 710 ) may be allocated or assigned to the delay buffer component 731 or the image processing component 741 .

[0071] like Figure 7 As shown, regions or ROIs may also be associated with specific synthesis stages. For example, region 710 may be associated with synthesis stage 720, and frame buffer 702 (excluding region 710) may be associated with synthesis stage 721. Synthesis stages may also be associated with corresponding components in the DPU hardware 725. For example, the corresponding component may be associated with a synthesis stage (e.g., synthesis stages 720-721) for a specific color processing region (e.g., region 710). For example, a delay buffer component 730 or an image processing component 740 may be associated with synthesis stage 720 for region 710 (e.g., a color processing region), and a delay buffer component 731 or an image processing component 741 may be associated with synthesis stage 721 for frame buffer 702 (excluding region 710). Color processing regions may be associated with processing pipelines or source surface processor pipelines (SSPP) in the DPU, and correspond to adjusted color temperatures. As shown Figure 7 As shown, the entire frame buffer 702 except for the region or ROI (e.g., region 710) can be associated with a corresponding component (e.g., delay buffer component 731 or image processing component 741) and a synthesis stage (e.g., synthesis stage 721). The synthesis stage (synthesis stages 720-721) can include a blending stage, so that synthesizing a set of layer regions or ROIs can include blending at least some of the layer regions or ROIs in the set of layer regions or ROIs. In addition, as Figure 7 As depicted, frame buffer 702 may correspond to composite output at the GPU.

[0072] In addition, the various aspects presented herein may analyze the layer stack of the current frame and identify layers (OS frames) that may require DPU-specific processing and / or are planned to be synthesized by the GPU. After doing so, the various aspects presented herein may mark those layers as DPU-related layers. The various aspects presented herein may also identify non-animation layers (or layers associated with non-animation frames) by determining whether the coordinates / shape of the relevant layer have any changes. If the relevant layer corresponds to a change or adjustment of the coordinates / shape, the layer may be a rotational animation layer or may be associated with an animation frame. For animation layers or layers associated with animation frames, the various aspects presented herein may apply layer raw processing to the entire frame buffer. For example, if the size of the DPU-related layer is greater than a threshold (e.g., greater than the size ratio of the entire frame), then the various aspects presented herein may apply layer raw processing to the entire frame buffer. If the layer size ratio of the entire frame is greater than a threshold (e.g., the layer size ratio is 0.75), then the various aspects presented herein may apply raw processing to the entire frame buffer.

[0073] Figure 8 8 is a diagram illustrating an example of a composition scheme for display processing. More specifically, diagram 800 depicts a composition scheme for a frame buffer 802 (e.g., a GPU composition output frame buffer), where diagram 800 includes a display layer 804, a composition stage, and corresponding components in DPU hardware 825. Figure 8 As shown, diagram 800 includes display layer 804, and a synthesis stage (e.g., synthesis stage 820). Figure 8 As illustrated in FIG. 8 , the DPU hardware 825 includes a bus interface 826, a color converter 828, a plurality of latency buffer components (e.g., latency buffer component 830, latency buffer component 831, latency buffer component 832, and latency buffer component 833), and a plurality of image processing components (e.g., image processing component 840, image processing component 841, image processing component 842, and image processing component 843). The DPU hardware 825 also includes a crossbar switch 850, a multi-layer mixer (e.g., layer mixer 860, layer mixer 861, layer mixer 862, and layer mixer 863), a plurality of frame processing components (e.g., frame processing component 870 and frame processing component 871), and a plurality of physical display processing components (e.g., physical display processing component 880, physical display processing component 881, physical display processing component 882, and physical display processing component 883). In some aspects, the latency buffer component or the image processing component may correspond to a processing pipeline or a source surface processor pipeline (SSPP) in the DPU.

[0074] like Figure 8As depicted, the display layer 804 may be included in a plurality of layers obtained from a GPU, an application, or a game. For example, the CPU may obtain an indication of a plurality of layers (including the display layer 804) associated with at least one frame, wherein each of the plurality of layers includes a plurality of pixels. The display layer 804 or the frame buffer 802 may correspond to a specific component (e.g., one of the latency buffer components 830-833 or the image processing components 840-843) and / or a specific synthesis stage (e.g., the synthesis stage 820) in the DPU hardware 825. For example, the display layer 804 or the frame buffer 802 may be assigned to a corresponding component in a set of components in the DPU pipeline. For example, the display layer 804 may be assigned or assigned to the latency buffer component 830 or the image processing component 840. In addition, the entire frame buffer 802 may be assigned or assigned to the latency buffer component 830 or the image processing component 840.

[0075] like Figure 8 As shown, a display layer or frame buffer may be associated with a particular composition stage. For example, display layer 804 or frame buffer 802 may be associated with composition stage 820. Composition stages may also be associated with corresponding components in DPU hardware 825. For example, the corresponding component may be associated with a composition stage (e.g., composition stage 820) for a particular color processing area (e.g., area 810) for the entire frame buffer. For example, a delay buffer component 830 or an image processing component 840 may be associated with a composition stage 820 for area 810 (e.g., a color processing area) for frame buffer 802. A color processing area may be associated with a processing pipeline or SSPP in the DPU, and correspond to an adjusted color temperature for the entire frame. As shown in FIG. Figure 8 As shown, the entire frame buffer 802 can be associated with a corresponding component (e.g., a delay buffer component 830 or an image processing component 840) and a compositing stage (e.g., a compositing stage 820). The compositing stage (compositing stage 820) can include a blending stage, so that compositing associated with the layer or frame buffer can include blending the layer or frame buffer. Figure 8 As depicted, frame buffer 802 may correspond to composite output at the GPU.

[0076] Fig. 9 FIG. 9 is a diagram illustrating an example of a flow diagram for display layer processing associated with DPU composition and GPU composition. Fig. 9As shown, at 910, the various aspects presented herein (e.g., a CPU or a DPU driver) may obtain an indication of a frame including multiple layers. At 920, the various aspects presented herein may determine whether the current layer is a rotational animation layer. If it is determined at 920 that the layer is not a rotational animation layer, then at 930, the various aspects presented herein may divide the frame buffer into different regions or ROIs. After dividing the frame buffer into different ROIs, at 932, if certain conditions are met, the various aspects presented herein may process the DPU-related regions or ROIs. Moreover, at 934, the various aspects presented herein may avoid processing non-related ROIs. At 936, the various aspects presented herein may synthesize the ROI in the DPU processing stage. At 938, the synthesized ROI may correspond to the frame buffer output from the DPU mixer. If it is determined at 920 that the layer is a rotational animation layer, then at 940, the various aspects presented herein may determine whether the DPU-related layer size is greater than a threshold. If so, then at 942, aspects presented herein may apply layer processing to the entire frame buffer.

[0077] Aspects of the present disclosure may include multiple benefits or advantages. For example, the various aspects presented herein may divide the GPU synthesis output frame buffer, and resynthesize the divided segments of the GPU synthesis output frame buffer. The various aspects presented herein may also conditionally apply DPU processing to the frame buffer area. In addition, in some cases, the various aspects of the present disclosure may keep the GPU per-layer processing consistent with the DPU per-layer processing. That is, the various aspects presented herein may provide visual effects or image enhancements similar to the per-layer processing for DPU synthesis for each layer of processing for GPU synthesis. For example, the various aspects of the present disclosure may implement the same processing technology as the DPU pipeline in the GPU pipeline. In addition, the various aspects of the present disclosure may keep the GPU path processing consistent with the DPU path processing for each layer of image processing. In addition, the various aspects of the present disclosure may optimize the power and / or performance of each layer of image processing at the GPU compared to the per-layer image processing at the DPU. For example, the various aspects presented herein may provide high-definition or HDR video tone mapping and processing for both the GPU and the DPU. In addition, the various aspects presented herein may cover GPU synthesis scenarios associated with DPU per-layer processing. For example, the various aspects presented herein may be applicable to certain types of GPU compositing (e.g., floating windows, floating buttons, animations, etc.). The various aspects presented herein may result in optimizing the visual quality of the display layer. In addition, the various aspects presented herein may provide fallback optimization for DPU per-layer processing and GPU per-layer processing.

[0078] Fig.10 FIG. 1 is a communication flow diagram 1000 showing a process according to one or more techniques of the present disclosure. Fig.10As shown, diagram 1000 includes example communications between a CPU 1002 (DPU driver, other central processing unit, or display processor), a GPU 1004, and a DPU 1006, according to one or more techniques of this disclosure.

[0079] At 1010, CPU 1002 may obtain an indication of at least one frame including a plurality of layers (e.g., CPU 1002 may obtain indication 1012 from GPU 1004), wherein the at least one frame is associated with display processing. In some cases, the plurality of layers may be associated with a layer stack or a region layer stack.

[0080] At 1020, CPU 1002 may map each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU).

[0081] At 1030 , based on mapping each of the plurality of layers for processing at the DPU or the GPU, the CPU 1002 may mark each of the plurality of layers mapped for processing at the DPU.

[0082] At 1040, the CPU 1002 may detect whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the plurality of layers. In some aspects, detecting whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer may include identifying whether a coordinate and shape set for each of the plurality of layers includes an adjustment. For example, the CPU may identify whether a coordinate and shape set for each of the plurality of layers includes an adjustment. In addition, each rotational animation layer in the plurality of layers may include a coordinate and shape set with an adjustment, and each non-rotational animation layer in the plurality of layers may include a coordinate and shape set without an adjustment. The rotational animation layer may be a layer at the DPU or GPU that rotates during animation, and the non-rotational animation layer may be a layer at the DPU or GPU that does not rotate during animation.

[0083] At 1050, the CPU 1002 may partition the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers. The frame buffer may correspond to a composite output at the GPU.

[0084] At 1060, the CPU 1002 may assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or assign at least one second per-layer processor at the DPU to each ROI in a set of ROIs in a frame buffer for each non-rotational animation layer in the plurality of layers. The first per-layer processor may correspond to a first compositing stage for each rotational animation layer in the plurality of layers, and the at least one second per-layer processor may correspond to a second compositing stage for each ROI in the set of ROIs in the frame buffer. In addition, each ROI in the set of ROIs may be assigned a higher compositing priority than other ROIs in the set of ROIs for each non-rotational animation layer in the plurality of layers. In some aspects, if the available layer size at the DPU is greater than a layer size threshold, the first per-layer processor at the DPU may be assigned to each rotational animation layer in the plurality of layers. The layer size threshold may be configured or adjusted by a central processing unit (CPU).

[0085] At 1070, CPU 1002 may send a second indication to assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or to assign at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers (e.g., CPU 1002 may send indication 1072 to DPU 1006).

[0086] At 1080, the CPU 1002 may process each non-rotational animation layer in the plurality of layers based on a second compositing stage for each ROI in the set of ROIs in the frame buffer. In some aspects, processing each non-rotational animation layer in the plurality of layers based on the second compositing stage may include blending each non-rotational animation layer in the plurality of layers based on the second compositing stage. For example, the CPU may blend each non-rotational animation layer in the plurality of layers based on the second compositing stage. Each non-rotational animation layer in the plurality of layers may be processed if at least one of the following is true: (i) the non-rotational animation layer is at the top of the region layer stack and the non-rotational animation layer has a constant blending alpha value, or (ii) the non-rotational animation layer is not at the top of the region layer stack and the non-rotational animation layer is covered by one or more transparent layers. In addition, each non-rotational animation layer in the plurality of layers may be associated with a color profile adjustment or a color-related adjustment.

[0087] Fig.11 1100 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a CPU (or other central processing unit), a DPU driver, a DPU (or other display processor), a GPU (or other graphics processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 10The examples are performed using any device that displays the process.

[0088] At 1102, the CPU may obtain an indication of at least one frame including a plurality of layers, wherein the at least one frame is associated with a display process, such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1010, CPU 1002 may obtain an indication of at least one frame including a plurality of layers, wherein the at least one frame is associated with a display process. In addition, step 1102 may be performed by Figure 1 In some cases, the plurality of layers may be associated with a layer stack or a regional layer stack.

[0089] At 1104, the CPU may map each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU), such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1020, CPU 1002 may map each of the multiple layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU). In addition, step 1104 may be performed by Figure 1 The display processor 127 in is executed.

[0090] At 1108, the CPU may detect whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the plurality of layers, such as in combination with Figures 1 to 10 For example, Fig.10 As described in step 1040, the CPU 1002 may detect whether each of the multiple layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the multiple layers. In addition, step 1108 may be performed by Figure 1 , executed by the display processor 127 in . In some aspects, detecting whether each of the multiple layers is a rotational animation layer or a non-rotational animation layer may include: identifying whether the coordinate and shape set of each of the multiple layers includes adjustment. For example, the CPU may identify whether the coordinate and shape set of each of the multiple layers includes adjustment. In addition, each rotational animation layer in the multiple layers may include a coordinate and shape set with adjustment, and each non-rotational animation layer in the multiple layers may include a coordinate and shape set without adjustment. The rotational animation layer may be a layer at the DPU or GPU that rotates during animation, and the non-rotational animation layer may be a layer at the DPU or GPU that does not rotate during animation.

[0091] At 1110, the CPU may divide the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers, such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1050, CPU 1002 may divide the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers. In addition, step 1110 may be performed by Figure 1 The display processor 127 in the processor is executed. The frame buffer may correspond to the composite output at the GPU.

[0092] At 1112, the CPU may assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or assign at least one second per-layer processor at the DPU to each ROI in a set of ROIs of a frame buffer for each non-rotational animation layer in the plurality of layers, as in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1060, the CPU 1002 may allocate a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocate at least one second per-layer processor at the DPU to each ROI in the ROI set in the frame buffer for each non-rotational animation layer in the plurality of layers. In addition, step 1112 may be performed by Figure 1 The display processor 127 in the DPU may be executed. The first per-layer processor may correspond to a first compositing stage for each rotational animation layer in the plurality of layers, and the at least one second per-layer processor may correspond to a second compositing stage for each ROI in the set of ROIs in the frame buffer. In addition, each ROI in the set of ROIs may be assigned a higher compositing priority than other ROIs in the set of ROIs for each non-rotational animation layer in the plurality of layers. In some aspects, if the available layer size at the DPU is greater than a layer size threshold, the first per-layer processor at the DPU may be assigned to each rotational animation layer in the plurality of layers. The layer size threshold may be configured or adjusted by a central processing unit (CPU).

[0093] Fig.12 1200 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a CPU (or other central processing unit), a DPU driver, a DPU (or other display processor), a GPU (or other graphics processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 10 The examples are performed using any device that displays the process.

[0094] At 1202, the CPU may obtain an indication of at least one frame including a plurality of layers, wherein the at least one frame is associated with a display process, such as in conjunction with Figures 1 to 10 For example, Fig.10As described in step 1010, CPU 1002 may obtain an indication of at least one frame including a plurality of layers, wherein the at least one frame is associated with a display process. In addition, step 1202 may be performed by Figure 1 In some cases, the plurality of layers may be associated with a layer stack or a regional layer stack.

[0095] At 1204, the CPU may map each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU), such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1020, CPU 1002 may map each of the multiple layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU). In addition, step 1204 may be performed by Figure 1 The display processor 127 in is executed.

[0096] At 1206, based on mapping each of the plurality of layers for processing at the DPU or GPU, the CPU may mark each of the plurality of layers mapped for processing at the DPU, such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in 1030 of , based on mapping each of the multiple layers to be processed at the DPU or GPU, the CPU 1002 can mark each of the multiple layers that are mapped to be processed at the DPU. In addition, step 1206 can be performed by Figure 1 The display processor 127 in is executed.

[0097] At 1208, the CPU may detect whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the plurality of layers, such as in combination with Figures 1 to 10 For example, Fig.10 As described in step 1040, the CPU 1002 may detect whether each of the multiple layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the multiple layers. In addition, step 1208 may be performed by Figure 1, executed by the display processor 127 in . In some aspects, detecting whether each of the multiple layers is a rotational animation layer or a non-rotational animation layer may include: identifying whether the coordinate and shape set of each of the multiple layers includes adjustment. For example, the CPU may identify whether the coordinate and shape set of each of the multiple layers includes adjustment. In addition, each rotational animation layer in the multiple layers may include a coordinate and shape set with adjustment, and each non-rotational animation layer in the multiple layers may include a coordinate and shape set without adjustment. The rotational animation layer may be a layer at the DPU or GPU that rotates during animation, and the non-rotational animation layer may be a layer at the DPU or GPU that does not rotate during animation.

[0098] At 1210, the CPU may divide the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers, such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1050, CPU 1002 may divide the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers. In addition, step 1210 may be performed by Figure 1 The display processor 127 in the processor is executed. The frame buffer may correspond to the composite output at the GPU.

[0099] At 1212, the CPU may assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or assign at least one second per-layer processor at the DPU to each ROI in a set of ROIs of a frame buffer for each non-rotational animation layer in the plurality of layers, as in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1060, the CPU 1002 may allocate a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocate at least one second per-layer processor at the DPU to each ROI in the ROI set in the frame buffer for each non-rotational animation layer in the plurality of layers. In addition, step 1212 may be performed by Figure 1 The display processor 127 in the DPU may be executed. The first per-layer processor may correspond to a first compositing stage for each rotational animation layer in the plurality of layers, and the at least one second per-layer processor may correspond to a second compositing stage for each ROI in the set of ROIs in the frame buffer. In addition, each ROI in the set of ROIs may be assigned a higher compositing priority than other ROIs in the set of ROIs for each non-rotational animation layer in the plurality of layers. In some aspects, if the available layer size at the DPU is greater than a layer size threshold, the first per-layer processor at the DPU may be assigned to each rotational animation layer in the plurality of layers. The layer size threshold may be configured or adjusted by a central processing unit (CPU).

[0100] At 1214, the CPU may send a second indication to assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or to assign at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers, as described in conjunction with Figures 1 to 10 For example, Fig.10 As described in step 1070, the CPU 1002 may send a second instruction about allocating a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocating at least one second per-layer processor at the DPU to each ROI in the ROI set in the frame buffer for each non-rotational animation layer in the plurality of layers. In addition, step 1214 may be performed by Figure 1 The display processor 127 in is executed.

[0101] At 1216, the CPU may process each non-rotational animation layer in the plurality of layers based on a second compositing stage for each ROI in the set of ROIs in the frame buffer, such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in 1080, CPU 1002 may process each non-rotation animation layer in the plurality of layers based on a second synthesis stage for each ROI in the ROI set in the frame buffer. In addition, step 1216 may be performed by Figure 1 , executed by the display processor 127 in . In some aspects, processing each non-rotational animation layer in the multiple layers based on the second compositing stage may include: blending each non-rotational animation layer in the multiple layers based on the second compositing stage. For example, the CPU may blend each non-rotational animation layer in the multiple layers based on the second compositing stage. Each non-rotational animation layer in the multiple layers may be processed if at least one of the following conditions is true: (i) the non-rotational animation layer is at the top of the region layer stack and the non-rotational animation layer has a constant blending alpha value, or (ii) the non-rotational animation layer is not at the top of the region layer stack and the non-rotational animation layer is covered by one or more transparent layers. In addition, each non-rotational animation layer in the multiple layers may be associated with a color configuration adjustment or a color-related adjustment.

[0102] In various configurations, a method or apparatus for display processing is provided. The apparatus may be a CPU (or other central processing unit), a DPU (or other display processor), a GPU (or other graphics processor), a DPU driver, a DDIC, an apparatus for display processing, and / or some other processor that can perform display processing. In various aspects, the apparatus may be a display processor 127 within a device 104, or may be some other hardware within a device 104 or another device. The apparatus (e.g., a display processor 127) may include a component for obtaining an indication of at least one frame including a plurality of layers, wherein the at least one frame is associated with display processing. The apparatus (e.g., a display processor 127) may also include a component for mapping each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU). The apparatus (e.g., a display processor 127) may also include a component for detecting whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the plurality of layers. The apparatus (e.g., a display processor 127) may also include a component for dividing a frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer of the plurality of layers. The device (e.g., display processor 127) may also include a component for assigning a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or assigning at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers. The device (e.g., display processor 127) may also include a component for processing each non-rotational animation layer in the plurality of layers based on a second synthesis stage for each ROI in the set of ROIs in the frame buffer. The device (e.g., display processor 127) may also include a component for marking each of the plurality of layers mapped for processing at the DPU based on mapping each of the plurality of layers for processing at the DPU or at the GPU. The device (e.g., display processor 127) may also include a component for sending a second indication of assigning a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or assigning at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers.

[0103] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the display processing techniques described can be used by a CPU, a central processing unit, a DPU driver, a DPU, a display processor, a GPU, or some other processor that can perform display processing to implement the synthesis techniques described herein. Compared with other display processing techniques, this can also be implemented at a low cost. In addition, the display processing techniques of this article can improve or accelerate data processing or execution. In addition, the display processing techniques of this article can improve resource or data utilization and / or resource efficiency. Additionally, various aspects of the present disclosure can utilize synthesis techniques to improve memory bandwidth efficiency and / or increase processing speed at the CPU, DPU or GPU.

[0104] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is merely an illustration of the exemplary method. It should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged based on design preferences. In addition, some blocks can be combined or omitted. The attached method claims provide the elements of each block in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0105] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0106] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, which may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of various aspects described throughout this disclosure that are known or will later be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Words such as "module," "mechanism," "element," "device," etc. cannot replace the word "component." Therefore, no claim element will be understood as a part plus function unless the element is explicitly stated using the phrase "component for..."

[0107] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent as one or more instructions or codes on a computer-readable medium.

[0108] According to the present disclosure, the term "or" may be understood as "and / or" in the absence of context dictating otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used for some features disclosed herein but not for other features, features not using such language may be understood to have such implicit meanings in the absence of context dictating otherwise.

[0109] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. In this way, computer-readable media may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices. As used herein, disk and disc include: compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0110] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0111] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuits or logic elements.

[0112] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0113] Aspect 1 is a device for display processing, the device comprising a memory and at least one processor, the at least one processor being coupled to the memory and, based at least in part on information stored in the memory, the at least one processor being configured to: obtain an indication of at least one frame comprising a plurality of layers, wherein the at least one frame is associated with display processing; map each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU); detect whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer based on the mapping of each of the plurality of layers; divide a frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers; and assign a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or assign at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers.

[0114] Aspect 2 is an apparatus according to Aspect 1, wherein the first per-layer processor corresponds to a first compositing stage for each rotation animation layer in the plurality of layers, and wherein the at least one second per-layer processor corresponds to a second compositing stage for each ROI in the set of ROIs in the frame buffer.

[0115] Aspect 3 is an apparatus according to aspect 2, wherein the at least one processor is further configured to: process each non-rotational animation layer of the plurality of layers based on the second compositing stage for each ROI in the set of ROIs in the frame buffer.

[0116] Aspect 4 is a device according to Aspect 3, wherein in order to process each non-rotational animation layer in the multiple layers based on the second synthesis stage, the at least one processor is configured to: blend each non-rotational animation layer in the multiple layers based on the second synthesis stage.

[0117] Aspect 5 is an apparatus according to Aspect 3, wherein each non-rotational animation layer in the multiple layers is processed if at least one of the following conditions is true: (i) the non-rotational animation layer is at the top of the regional layer stack and the non-rotational animation layer has a constant blending alpha value, or (ii) the non-rotational animation layer is not at the top of the regional layer stack and the non-rotational animation layer is covered by one or more transparent layers.

[0118] Aspect 6 is the apparatus of aspect 3, wherein each non-rotational animation layer of the plurality of layers is associated with a color profile adjustment or a color-related adjustment.

[0119] Aspect 7 is the apparatus according to aspect 2, wherein each ROI in the set of ROIs is assigned a higher composition priority than other ROIs in the set of ROIs for each non-rotational animation layer in the plurality of layers.

[0120] Aspect 8 is a device according to any one of Aspects 1 to 7, wherein in order to detect whether each of the multiple layers is a rotational animation layer or a non-rotational animation layer, the at least one processor is configured to: identify whether the coordinate and shape set of each of the multiple layers includes adjustment.

[0121] Aspect 9 is an apparatus according to aspect 8, wherein each rotational animation layer in the plurality of layers comprises the set of coordinates and shapes with the adjustment, and wherein each non-rotational animation layer in the plurality of layers comprises the set of coordinates and shapes without the adjustment.

[0122] Aspect 10 is an apparatus according to any one of aspects 1 to 9, wherein the rotational animation layer is a layer at the DPU or the GPU that rotates during animation, and wherein the non-rotational animation layer is a layer at the DPU or the GPU that does not rotate during the animation.

[0123] Aspect 11 is an apparatus according to any one of Aspects 1 to 10, wherein the at least one processor is further configured to: based on mapping each of the multiple layers for processing at the DPU or the GPU, mark each of the multiple layers mapped for processing at the DPU.

[0124] Aspect 12 is an apparatus according to any one of Aspects 1 to 11, wherein if the available layer size at the DPU is greater than a layer size threshold, the first per-layer processor at the DPU is allocated to each rotational animation layer in the multiple layers.

[0125] Aspect 13 is the apparatus according to aspect 12, wherein the layer size threshold is configurable or adjustable by a central processing unit (CPU).

[0126] Aspect 14 is an apparatus according to any one of aspects 1 to 13, wherein the plurality of layers are associated with a layer stack or a regional layer stack.

[0127] Clause 15 is an apparatus according to any one of clauses 1 to 14, wherein the frame buffer corresponds to a composition output at the GPU.

[0128] Aspect 16 is an apparatus according to any one of Aspects 1 to 15, wherein the at least one processor is further configured to: send a second indication of allocating the first per-layer processor at the DPU to each rotational animation layer in the multiple layers, or allocating the at least one second per-layer processor at the DPU to each ROI in the ROI set in the frame buffer for each non-rotational animation layer in the multiple layers.

[0129] Aspect 17 is an apparatus according to any one of Aspects 1 to 16, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor, and wherein the at least one processor is configured to obtain the indication of the at least one frame via at least one of the antenna or the transceiver.

[0130] Aspect 18 is a method for implementing the display processing of any one of aspects 1 to 17.

[0131] Aspect 19 is an apparatus for display processing, the apparatus comprising means for implementing any one of aspects 1 to 17.

[0132] Aspect 20 is a computer-readable medium (eg, non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 17.

Claims

1. A device for display processing, the device comprising: Memory; and at least one processor coupled to the memory and based at least in part on the information stored in the memory, the at least one processor configured to: obtaining an indication of at least one frame comprising a plurality of layers, wherein the at least one frame is associated with the display process; mapping each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU); detecting, based on the mapping of each of the plurality of layers, whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer; partitioning the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers; as well as Allocate a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocate at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers.

2. The apparatus of claim 1 , wherein the first per-layer processor corresponds to a first compositing stage for each rotation animation layer in the plurality of layers, and wherein the at least one second per-layer processor corresponds to a second compositing stage for each ROI in the set of ROIs in the frame buffer.

3. The apparatus of claim 2, wherein the at least one processor is further configured to: Each non-rotational animation layer in the plurality of layers is processed based on the second compositing stage for each ROI in the set of ROIs in the frame buffer.

4. The apparatus of claim 3, wherein in order to process each non-rotational animation layer in the plurality of layers based on the second compositing stage, the at least one processor is configured to: blend each non-rotational animation layer in the plurality of layers based on the second compositing stage.

5. The apparatus of claim 3 , wherein each non-rotational animation layer in the plurality of layers is processed when at least one of the following conditions is true: (i) the non-rotational animation layer is at the top of a region layer stack and the non-rotational animation layer has a constant blending alpha value, or (ii) the non-rotational animation layer is not at the top of the region layer stack and the non-rotational animation layer is covered by one or more transparent layers. 6 . The apparatus of claim 3 , wherein each non-rotational animation layer of the plurality of layers is associated with a color profile adjustment or a color-related adjustment. 7 . The apparatus of claim 2 , wherein each ROI in the set of ROIs is assigned a higher compositing priority than other ROIs in the set of ROIs for each non-rotational animation layer in the plurality of layers.

8. The apparatus of claim 1, wherein in order to detect whether each of the plurality of layers is the rotational animation layer or the non-rotational animation layer, the at least one processor is configured to: identify whether a coordinate and shape set of each of the plurality of layers includes an adjustment.

9. The apparatus of claim 8, wherein each rotational animation layer of the plurality of layers comprises the set of coordinates and shapes with the adjustment, and wherein each non-rotational animation layer of the plurality of layers comprises the set of coordinates and shapes without the adjustment.

10. The apparatus of claim 1, wherein the rotational animation layer is a layer at the DPU or the GPU that rotates during animation, and wherein the non-rotational animation layer is a layer at the DPU or the GPU that does not rotate during the animation.

11. The apparatus of claim 1 , wherein the at least one processor is further configured to: Based on mapping each of the plurality of layers for the processing at the DPU or the GPU, marking each of the plurality of layers that are mapped for the processing at the DPU.

12. The apparatus of claim 1, wherein the first per-layer processor at the DPU is allocated to each rotation animation layer in the plurality of layers if the available layer size at the DPU is greater than a layer size threshold.

13. The apparatus of claim 12, wherein the layer size threshold is configurable or adjustable by a central processing unit (CPU). The apparatus of claim 1 , wherein the plurality of layers are associated with a layer stack or a regional layer stack.

15. The apparatus of claim 1 , further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one processor is configured to obtain the indication of the at least one frame via at least one of the antenna or the transceiver; and wherein the frame buffer corresponds to a synthesized output at the GPU.

16. The apparatus of claim 1, wherein the at least one processor is further configured to: Sending a second indication to assign the first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or to assign the at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers.

17. A method of display processing, the method comprising: obtaining an indication of at least one frame comprising a plurality of layers, wherein the at least one frame is associated with the display process; mapping each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU); detecting, based on the mapping of each of the plurality of layers, whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer; partitioning the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers; as well as Allocate a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocate at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers.

18. The method of claim 17, wherein the first per-layer processor corresponds to a first compositing stage for each rotation animation layer in the plurality of layers, and wherein the at least one second per-layer processor corresponds to a second compositing stage for each ROI in the set of ROIs in the frame buffer.

19. The method according to claim 18, further comprising: Each non-rotational animation layer in the plurality of layers is processed based on the second compositing stage for each ROI in the set of ROIs in the frame buffer.

20. The method of claim 19, wherein processing each non-rotational animation layer in the plurality of layers based on the second compositing stage comprises: Each non-rotational animation layer in the plurality of layers is blended based on the second compositing stage.

21. The method of claim 19, wherein each non-rotational animation layer in the plurality of layers is processed if at least one of the following conditions is true: (i) the non-rotational animation layer is at the top of a region layer stack and the non-rotational animation layer has a constant blending alpha value, or (ii) the non-rotational animation layer is not at the top of the region layer stack and the non-rotational animation layer is covered by one or more transparent layers.

22. The method of claim 19, wherein each non-rotational animation layer of the plurality of layers is associated with a color profile adjustment or a color-related adjustment.

23. The method of claim 18, wherein each ROI in the set of ROIs is assigned a higher compositing priority than other ROIs in the set of ROIs for each non-rotational animation layer in the plurality of layers.

24. The method of claim 17, wherein detecting whether each layer of the plurality of layers is the rotational animation layer or the non-rotational animation layer comprises: Identifying whether the coordinate and shape set of each layer in the plurality of layers includes an adjustment, wherein each rotational animation layer in the plurality of layers includes the coordinate and shape set with the adjustment; and wherein each non-rotational animation layer in the plurality of layers includes the coordinate and shape set without the adjustment.

25. The method of claim 17, wherein the rotational animation layer is a layer at the DPU or the GPU that rotates during an animation, and wherein the non-rotational animation layer is a layer at the DPU or the GPU that does not rotate during the animation.

26. The method of claim 17, further comprising: Based on mapping each of the plurality of layers for the processing at the DPU or the GPU, marking each of the plurality of layers that are mapped for the processing at the DPU.

27. A method according to claim 17, wherein the first per-layer processor at the DPU is allocated to each rotational animation layer in the multiple layers when the available layer size at the DPU is greater than a layer size threshold, wherein the layer size threshold can be configured or adjusted by a central processing unit (CPU).

28. The method of claim 17, further comprising: Sending a second indication to assign the first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or to assign the at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers, wherein the plurality of layers are associated with a layer stack or a region layer stack; and wherein the frame buffer corresponds to a composite output at the GPU.

29. An apparatus for display processing, the apparatus comprising: means for obtaining an indication of at least one frame comprising a plurality of layers, wherein the at least one frame is associated with the display process; means for mapping each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU); means for detecting, based on the mapping of each of the plurality of layers, whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer; means for partitioning a frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer of the plurality of layers; and Component for allocating a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocating at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers.

30. A computer readable medium storing computer executable code for display processing, the code when executed by a processor causing the processor to: obtaining an indication of at least one frame comprising a plurality of layers, wherein the at least one frame is associated with the display process; mapping each of the plurality of layers for processing at a display processing unit (DPU) or a graphics processing unit (GPU); detecting, based on the mapping of each of the plurality of layers, whether each of the plurality of layers is a rotational animation layer or a non-rotational animation layer; partitioning the frame buffer into a set of regions of interest (ROIs) for each non-rotational animation layer in the plurality of layers; as well as Allocate a first per-layer processor at the DPU to each rotational animation layer in the plurality of layers, or allocate at least one second per-layer processor at the DPU to each ROI in the set of ROIs in the frame buffer for each non-rotational animation layer in the plurality of layers.

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