Low voltage signal path in radio frequency signal generator

Abstract

An apparatus includes a voltage mode filter circuit, a current mode output circuit, and a regulation circuit. The voltage mode filter circuit is configured to generate a voltage signal on an output terminal thereof. The current mode output circuit includes an input transistor including a gate terminal coupled to the output terminal of the voltage mode filter circuit and a source terminal coupled to the regulated node. The regulation circuit is configured to regulate a voltage level on the node to maintain a constant gate-source bias voltage for the input transistor to generate a current for biasing the current mode output circuit.

Description

Background Art

[0001] The present disclosure relates generally to radio frequency (RF) signal generators, and more particularly to techniques for reducing the power supply voltage level and power consumption of RF signal generators such as arbitrary waveform generator (AWG) systems. The RF signal generator may be implemented with an orthogonal architecture, in which a baseband signal is up-converted to an RF signal using a single sideband (SSB) modulation system that modulates a quadrature local oscillator (LO) signal using a quadrature baseband signal. Such RF signal generators are used in applications such as wireless transmitters, and for generating control pulses for quantum bits (qubits) in quantum computing systems, among others. In particular, in quantum computing applications, it is desirable to have an AWG system that can generate RF control pulses with variable amplitude and low distortion for controlling the qubits of a quantum processor. Furthermore, it is critical to minimize the power consumption of the AWG system, especially in the environment of cryogenic RF signal generation for qubit control.

[0002] An RF signal generator may have various signal processing stages implemented using current mode circuits, which provide a favorable tradeoff between power and performance. For example, current mode circuits allow current reuse, where the current of one stage is shared with another stage to improve power efficiency. On the other hand, current mode circuits sometimes include stacked transistor architectures, which may require relatively high supply voltages (and therefore higher power) to provide the necessary headroom to operate the transistors in saturation mode. Summary of the invention

[0003] Exemplary embodiments of the present disclosure include techniques for reducing power supply voltage levels and power consumption of RF signal generator systems (e.g., arbitrary waveform generator systems). In addition, exemplary embodiments of the present disclosure include techniques for interfacing voltage mode circuits with current mode circuits in RF generator systems.

[0004] In an exemplary embodiment, a device includes a voltage mode filter circuit, a current mode output circuit, and a regulating circuit. The voltage mode filter circuit is configured to generate a voltage signal at its output terminal. The current mode output circuit includes an input transistor, the input transistor including a gate terminal coupled to the output terminal of the voltage mode filter circuit and a source terminal coupled to a regulated node. The regulating circuit is configured to regulate the voltage level on the node to maintain a constant gate-source bias voltage for the input transistor, thereby generating a current for biasing the current mode output circuit.

[0005] Advantageously, the regulation circuit provides a mechanism for interfacing a voltage mode filter circuit with a current mode output circuit while ensuring that the bias voltage (e.g., gate-source voltage) of an input transistor of the current mode circuit is maintained at a constant bias voltage by adjusting the voltage level on the regulation node as needed so that the input transistor generates a stable quiescent current at a desired level for biasing the current mode output circuit. Without the regulation circuit, the bias voltage of the input transistor may vary due to variations in the supply voltage, which would result in variations in the quiescent current of the input transistor and, therefore, an unstable bias point of the current mode output circuit.

[0006] In an exemplary embodiment, as can be combined with the preceding paragraphs, the voltage mode filter circuit includes an analog quartic low pass filter circuit implementing a unity gain source follower circuit. Advantageously, the voltage mode filter circuit includes a filter architecture with fewer stacked transistors compared to the current mode filter circuit, which allows a relatively low supply voltage (e.g., 500mV–700-05700mV) to be used for the voltage mode baseband filter circuit, and thus achieves lower power consumption and improved power efficiency.

[0007] Another exemplary embodiment includes a system including a radio frequency signal generator configured to convert a baseband signal into a radio frequency signal. The radio frequency signal generator includes a baseband filter stage, an output stage, and a regulation circuit. The baseband filter stage includes a voltage mode filter circuit configured to filter the baseband signal and generate a voltage signal at an output terminal of the voltage mode filter circuit. The output stage is configured to generate and output the radio frequency signal. The output stage includes a plurality of current mode stages including a baseband input stage. The baseband input stage includes an input transistor including a gate terminal coupled to the output terminal of the voltage mode filter circuit and a source terminal coupled to a regulation node. The regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage of the input transistor, thereby generating a current for biasing the current mode stage of the output stage.

[0008] In an exemplary embodiment, as may be combined with the preceding paragraphs, the current mode stage of the output stage includes a mixer stage and an attenuation stage. The mixer stage and the attenuation stage have a commonly connected input node connected to the output node of the baseband input stage. The output node of the attenuation stage is coupled to a negative power supply node. Advantageously, in this configuration, the mixer stage and the attenuation stage are effectively placed at the same level of the stack structure of the output stage (e.g., reducing the height of the transistor stack structure), which provides additional headroom that allows the output stage to operate at a reduced power supply voltage.

[0009] Another exemplary embodiment includes a system including a quantum processor and an arbitrary waveform generator. The quantum processor includes at least one superconducting qubit. The arbitrary waveform generator includes at least one arbitrary waveform generator channel configured to convert a baseband signal into a radio frequency control pulse that controls at least one superconducting qubit. At least one arbitrary waveform generator channel includes a baseband filter stage, an output stage, and a conditioning circuit. The baseband filter stage includes a voltage mode filter circuit configured to filter the baseband signal and generate a voltage signal at an output terminal of the voltage mode filter circuit. The output stage is configured to generate and output the radio frequency control pulse. The output stage includes a plurality of current mode stages, which include a baseband input stage. The baseband input stage includes an input transistor including a gate terminal coupled to the output terminal of the voltage mode filter circuit and a source terminal coupled to a conditioning node. The conditioning circuit is configured to adjust the voltage level on the regulated node to maintain a constant gate-source bias voltage of the input transistor, thereby generating a current for biasing the current mode stage of the output stage.

[0010] Another exemplary embodiment includes a system including a radio frequency signal generator configured to convert a baseband signal into a radio frequency signal. The radio frequency signal generator includes a baseband filter stage, a mixer stage, an output stage, and a regulation circuit. The baseband filter stage includes a voltage mode filter circuit configured to filter the baseband signal and generate a voltage signal at an output terminal of the voltage mode filter circuit. The mixer stage includes a voltage mode mixer circuit configured to convert the filtered baseband signal into a radio frequency signal. The output stage includes a plurality of current mode stages including a radio frequency signal input stage. The radio frequency signal input stage includes an input transistor, the input transistor including a gate terminal coupled to an output terminal of the voltage mode mixer circuit and a source terminal coupled to a regulated node. The regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage of the input transistor, thereby generating a current for biasing a current mode stage of the output stage.

[0011] Advantageously, in this configuration, the voltage-mode mixer is placed between the voltage-mode filter and the current-mode output stage, which eliminates one stage of the transistor stack in the current-mode output stage (which would otherwise be present if the current-mode output stage included a current-mode mixer stage). This configuration provides additional headroom to operate the current-mode output stage at a reduced supply voltage.

[0012] Another exemplary embodiment includes a method comprising: generating a voltage signal at an output terminal of a voltage mode filter circuit; applying the voltage signal to a gate terminal of an input transistor of a current mode output circuit, wherein the input transistor includes a source terminal coupled to a supply voltage node; and adjusting a voltage level on the supply voltage node to maintain a constant gate-source bias voltage of the input transistor, thereby generating a current for biasing the current mode output circuit.

[0013] Further embodiments will be described in the following detailed description of exemplary embodiments, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A radio frequency signal generator system according to an exemplary embodiment of the present disclosure is schematically illustrated.

[0015] Figure 2A and 2B A radio frequency signal generator system according to another exemplary embodiment of the present disclosure is schematically shown.

[0016] Figure 3A A voltage mode baseband filter circuit according to an exemplary embodiment of the present invention is schematically illustrated.

[0017] Figure 3B A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated.

[0018] Figure 3C A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated.

[0019] Figure 3D A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated.

[0020] Figure 3E A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated.

[0021] Figure 3F A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated.

[0022] Figure 4 A radio frequency signal generator system according to another exemplary embodiment of the present disclosure is schematically shown.

[0023] Figure 5A Schematically shows another exemplary embodiment of the present disclosure. Figure 4 A voltage mode baseband filter circuit implemented in an RF signal generator system.

[0024] Figure 5B Schematically shows another exemplary embodiment of the present disclosure. Figure 4 A replica bias circuit implemented in an RF signal generator system.

[0025] Figure 6 A radio frequency signal generator system according to another exemplary embodiment of the present disclosure is schematically shown.

[0026] Fig. 7A and 7B A radio frequency signal generator system according to another exemplary embodiment of the present disclosure is schematically shown.

[0027] Figure 8 A radio frequency signal generator system according to another exemplary embodiment of the present disclosure is schematically shown.

[0028] Fig. 9 A radio frequency signal generator system according to another exemplary embodiment of the present disclosure is schematically shown.

[0029] Fig.10 A quantum computing system according to an exemplary embodiment of the present disclosure is schematically shown, which implements an arbitrary waveform generator system and a calibration circuit.

[0030] Fig.11 A quantum computing system according to another exemplary embodiment of the present disclosure is schematically illustrated.

[0031] Fig.12 An exemplary computing environment configured to execute program instructions for controlling a calibration process of a calibration system according to an exemplary embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present disclosure will now be described in more detail with respect to systems and methods for reducing the power supply voltage level and power consumption of RF signal generator systems such as arbitrary waveform generator systems, and techniques for interfacing voltage-mode circuits with current-mode circuits in RF generator systems. It should be understood that the various features shown in the accompanying drawings are schematic diagrams that are not drawn to scale. In addition, the same or similar reference numerals are used in all drawings to represent the same or similar features, elements, or structures, and therefore, a detailed explanation of the same or similar features, elements, or structures will not be repeated for each drawing. In addition, the term "exemplary" as used herein means "used as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" should not be construed as being more preferred or advantageous than other embodiments or designs.

[0033] In addition, it should be understood that the phrase "configured to" used in conjunction with circuits, structures, elements, components, etc. that perform one or more functions or otherwise provide some functions is intended to cover embodiments in which the circuits, structures, elements, components, etc. are implemented in hardware, software, and / or a combination thereof, and in implementations that include hardware, where the hardware may include discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application specific integrated circuit (ASIC) chips, field programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.), one or more integrated circuits, and / or a combination thereof. Thus, by way of example only, when a circuit, structure, element, component, etc. is defined as being configured to provide a particular functionality, it is intended to cover, but not be limited to, embodiments in which the circuit, structure, element, component, etc. is comprised of elements, processing devices, and / or integrated circuits that enable it to perform the particular functionality when in an operational state (e.g., connected or otherwise deployed in a system, powered on, receiving input, and / or generating output), as well as embodiments in which the circuit, structure, element, component, etc. is in a non-operational state (e.g., not connected or otherwise deployed in a system, not powered on, not receiving input, and / or not generating output) or in a partially operational state.

[0034] Figure 1 Schematically illustrates a radio frequency signal generator system according to an exemplary embodiment of the present disclosure. In particular, Figure 1 Schematically illustrated is an RF signal generator system 100 that includes a baseband I / Q signal generator 110, a digital-to-analog converter stage 120 (or DAC stage 120), a baseband filter stage 130, a mixer stage 140, an amplifier stage 150, an impedance matching network 160, a local oscillator (LO) signal generator circuit 170, and an LO signal output driver circuit 180, the functions of which will be explained in further detail below. A calibration control system 190 is configured to calibrate the various stages of the RF signal generator system 100 using digital control signals. As described herein, the calibration control system 190 is implemented using a combination of software (e.g., program execution) and hardware (e.g., control logic and circuitry) to implement various control functions.

[0035] like Figure 1, the DAC stage 120 includes an input coupled to the output of the baseband signal generator 110. The baseband filter stage 130 includes an input coupled to the output of the DAC stage 120. The mixer stage 140 includes an input coupled to the output of the baseband filter stage 130. The amplifier stage 150 includes an input coupled to the output of the mixer stage 140, and an output coupled to the input of the impedance matching network 160, and the output of the impedance matching network 160 is coupled to the output node (RF_OUT) of the RF signal generator system 100. The LO signal generator circuit 170 is configured to generate an LO signal (e.g., a quadrature LO signal) used by the mixer stage 140 to perform up-conversion of the baseband signal. The LO signal output driver circuit 180 is configured to control the input of the LO signal to the mixer stage 140 for different operating modes (e.g., real-time operating mode and calibration mode) of the RF signal generator system 100, as will be discussed in more detail below.

[0036] It should be understood that the RF signal generator system 100 can be implemented for various applications. For example, in some embodiments, the RF signal generator system 100 includes an RF transmitter for wireless applications, wherein the output of the RF signal generator system 100 is coupled to an antenna system, which is configured to transmit the RF output signal generated by the RF signal generator system 100. In other embodiments, the RF signal generator system 100 includes a waveform generator (e.g., an AWG or a function generator), wherein the output of the RF signal generator system 100 is coupled to the input of a sensor device, wherein the RF output signal generated by the RF signal generator system 100 is configured to excite the sensor device. In other embodiments, for quantum computing applications, the RF signal generator system 100 includes an AWG system, which is configured to generate RF control pulses to control the operation of, for example, a superconducting qubit, an active superconducting coupler circuit that couples two superconducting qubits, or other superconducting quantum devices, etc.

[0037] In the context of the exemplary embodiments discussed herein, RF signals include signals having frequencies ranging from, for example, about 20 kHz to about 300 GHz. In some embodiments, the RF signal generator system 100 includes an analog quadrature system configured to generate quadrature (I / Q) signals (e.g., baseband I / Q signals and LO I / Q signals) and perform quadrature modulation (or I / Q signal modulation) to generate RF signals for a given application. As is known in the art, a quadrature signal includes an in-phase (I) signal component and a quadrature phase (Q) signal component. A pair of orthogonal signals have the same frequency but differ in phase by 90 degrees. For example, by convention, the I signal is a cosine waveform and the Q signal is a sine waveform. For purposes of illustration, exemplary embodiments of the present disclosure will be described in the context of an orthogonal RF signal generator system, although other types of RF signal generator systems and modulation techniques may be utilized to implement exemplary signal processing circuits and methods as discussed herein.

[0038] exist Figure 1 In an exemplary embodiment of the present invention, the baseband signal generator 110 is configured to generate digital quadrature signals I and Q, which represent input baseband data for a given application. For example, for quantum computing applications, the baseband signal generator 110 is configured to implement pulse shaping techniques to generate RF control pulses with desired envelope shapes (e.g., Gaussian pulses, cosine pulses (e.g., the sum of half cosines), hyperbolic secant pulses, etc.), which are applied to superconducting qubits or active qubit coupler circuits to perform single qubit gate operations, entangled gate operations, etc.

[0039] The DAC stage 120 is configured to convert the digital quadrature signals I and Q into analog baseband signals I'(t) and Q'(t) with a target baseband frequency. More specifically, the DAC stage 120 includes a multi-bit DAC circuit, which includes a first DAC circuit 121 and a second DAC circuit 122. The first DAC circuit 121 is configured to convert the digital baseband component I into an analog baseband component with a baseband frequency, and the second DAC circuit 122 is configured to convert the digital baseband component Q into an analog baseband component with the same baseband frequency but with a 90 degree phase shift relative to the baseband frequency. The DAC stage 120 generates and outputs an analog baseband signal, and performs at a given sampling rate (fS) or sampling frequency (e.g., a baseband frequency in the range of about 100kHz to about 1GHz, depending on a given application). In some embodiments, the first DAC circuit 121 and the second DAC circuit 122 implement a configurable hardware architecture, in which various operating parameters of the DAC stage 120 can be adjusted by a digital control signal input to the DAC stage 120. For example, in some embodiments, digital control may be used to adjust DAC operating parameters including, but not limited to, sampling ratio, analog output gain, etc.

[0040] Based on the Nyquist Sampling Theorem, the maximum fundamental output frequency f that a DAC with a sampling frequency fs can generate is O The signal is equal to half the sampling rate or f s / 2 (called the first Nyquist zone). In the frequency domain, when the generated frequency f O When the sine waveform is O will be expressed as f O spectral components at , and there will be additional higher frequency components generated at the output of the DAC stage 120, which are called “images” and are f S and f O For example, the higher frequency component is determined as |(n×f S )±f O |, where n=1, 2, 3, ... The image has the same information content as the basic spectral components, but at higher frequencies and smaller amplitudes. Unwanted imagery is suppressed / rejected using, for example, a baseband filter stage 130.

[0041] The baseband filter stage 130 is configured to filter the analog baseband signals output from the DAC stage 120, thereby generating filtered analog baseband signals I(t) and Q(t). The baseband filter stage 130 includes a first filter circuit 131 and a second filter circuit 132. The first filter circuit 131 is configured to filter the in-phase analog signal I′(t) output from the first DAC circuit 121, and the second filter circuit 132 is configured to filter the quadrature-phase analog signal Q′(t) output from the second DAC circuit 122. In some embodiments, the first and second filter circuits 131 and 132 include low-pass filters configured to pass fundamental spectral components of the corresponding analog signals I′(t) and Q′(t) while suppressing image components of the corresponding analog signals I′(t) and Q′(t). In other embodiments, the first and second filter circuits 131 and 132 can be configured as bandpass filters to pass a desired frequency band of high-frequency image components of the corresponding analog signals I'(t) and Q'(t) while suppressing the fundamental frequency spectral components and other image components of the corresponding analog signals I'(t) and Q'(t). In other embodiments, the first and second filter circuits 131 and 132 can be configured as high-pass filters, as may be desired for a given application.

[0042] In some embodiments, the baseband filter stage 130 includes a configurable filter circuit, wherein, for example, the cutoff frequencies of the first and second filter circuits 131 and 132 can be adjusted, or wherein the first and second filter circuits 131 and 132 can be configured to have different filter types (e.g., low pass, band pass, etc.) required for a given application. For example, in some embodiments, the band pass filter can be configured using two low pass filters that use known signal filtering techniques and architectures. In some embodiments, the filter configuration is digitally controlled by a digital control signal input to the baseband filter stage 130.

[0043] For example, a higher DAC sampling frequency may be utilized as needed to transmit baseband data and / or relax the filter response of the downstream filter of the baseband filter stage 130. In fact, an increase in the DAC sampling frequency results in the possibility of accommodating a higher baseband transmission frequency (i.e., the analog signals I′(t) and Q′(t) have a higher baseband frequency). In addition, an increase in the DAC sampling frequency results in an increase in the center frequency f of the baseband component. O and the center frequency of the higher frequency image n×f S ±f O The increase in the spacing between the two relaxes the required sharpness of the filter cutoff at the corner frequency of the filter. However, a higher DAC sampling rate leads to increased power consumption. Therefore, the tradeoff between power consumption and DAC sampling frequency and the sharpness of the filter cutoff at the corner frequency of the filter is a factor that should be considered.

[0044] In some embodiments, the mixer stage 140 is configured to perform analog I / Q signal modulation, e.g., single sideband (SSB) modulation, by mixing the filtered analog signals I(t) and Q(t) output from the baseband filter stage 130 with quadrature LO signals (e.g., in-phase LO signal (LO_I) and quadrature phase LO signal (LO_Q)) to generate and output an analog RF signal (e.g., a single sideband modulated RF output signal). The local oscillator signals LO_I and LO_Q each have the same LO frequency, but the LO_Q signal is phase shifted by 90 degrees relative to the LO_I signal. For amplitude modulation, the filtered analog signals I(t) and Q(t) amplitude modulate the LO_I and LO_Q signals.

[0045] More specifically, the mixer stage 140 includes a first mixer circuit 141 (e.g., an I mixer circuit), a second mixer circuit 142 (e.g., a Q mixer circuit), and a signal combiner circuit 143. The first mixer circuit 141 is configured to mix the filtered analog signal I(t) with the LO_I signal and generate a first RF signal output. The second mixer circuit 142 is configured to mix the filtered analog signal Q(t) with the LO_Q signal and generate a second RF signal output. The first and second RF signals output from the first and second mixer circuits 141 and 142 are input to the signal combiner circuit 143 and combined (e.g., added) to generate a single-sideband RF signal output.

[0046] In some embodiments, the quadrature phase shifter circuit is implemented to generate quadrature LO signals LO_I and LO_Q signals. For example, the quadrature phase shifter circuit is configured to receive the LO signal as an input and output quadrature LO signals LO_I and LO_Q based on the LO input signal. In this configuration, the LO_I signal includes the same frequency and phase as the input LO signal, and the LO_Q signal includes the same frequency as the input LO signal, but with a 90 degree phase shift. The quadrature phase shifter circuit can be implemented using one of a variety of quadrature phase shifting techniques known to those of ordinary skill in the art.

[0047] The mixer stage 140 performs an up-conversion mixing process configured to generate an RF analog signal having a center frequency greater than the baseband frequency of the baseband signal output from the DAC stage 120. In some embodiments, the LO frequency of the mixer stage 140 is in the range of 100 MHz to about 10 GHz, depending on the application. More specifically, as understood by those of ordinary skill in the art, as a result of the mixing operation of the first and second mixer circuits 141 and 142, the first and second RF signals output from the corresponding first and second mixer circuits 141 and 142 each include a double-sideband RF signal. The double-sideband signal includes an upper sideband (USB) and a lower sideband (LSB), which are arranged above and below the LO frequency at equal distances. The upper sideband includes a spectrum band higher than the LO frequency, and the lower sideband includes a spectrum band lower than the LO frequency. Each of the upper sideband and the lower sideband carries the same information content of the I / Q signal. For example, assume that the filtered analog signals I(t) and Q(t) (ie, the modulating signals) have a center frequency f M (IF), and assuming the LO signal has a frequency f LO The first and second RF signals output from the first and second mixer circuits 141 and 142 will each have (i) an upper sideband of a spectral component centered at (f LO +f M ) frequency band, and (ii) the lower sideband of the spectral components, which is centered at (fLO +f M ) frequency band.

[0048] In some embodiments, the signal combiner circuit 143 is configured to add the first RF signal and the second RF signal output from the first mixer circuit 141 and the second mixer circuit 142, in which case the signal combiner circuit 143 will output a "real" lower sideband signal as a single sideband modulated RF signal (with a suppressed carrier frequency) having a center frequency that is derived from the frequencies f of the modulating signals I(t) and Q(t). M Up-convert to the center frequency of the lower sideband (f LO –f M ). In other embodiments, the signal combiner circuit 143 is configured to subtract the first RF signal and the second RF signal output from the first mixer circuit 141 and the second mixer circuit 142, in which case the signal combiner circuit 143 will output a "real" upper sideband signal as a single sideband modulated RF signal (with suppressed carrier) having a frequency f from the modulated signals I(t) and Q(t). M Up-converted to the center frequency of the upper sideband (f LO +f M ). In other embodiments, the mixer stage 140 is configured as a double-sideband modulator (with a suppressed carrier frequency). More specifically, the mixer stage 140 can be configured to provide double-sideband modulation by maintaining the LO_Q input of the second mixer 142 at a constant zero voltage level (i.e., LO_Q=0). In this case, the second mixer circuit 142 will have a zero output (i.e., no RF signal is output from the second mixer circuit 142), and the output of the signal combiner circuit 143 will be the double-sideband RF signal output from the first mixer circuit 141.

[0049] The amplifier stage 150 is configured to receive the modulated RF signal output from the mixer stage 140, and amplify or attenuate the modulated RF signal to a desired power level, and drive the output of the RF signal generator system 100 (e.g., drive an antenna, sensor device, qubit, etc. coupled to the output of the RF signal generator system 100). In some embodiments, the amplifier stage 150 includes a programmable gain, where the gain can be expressed as the difference between the input power level (at the input of the amplifier stage 150) and the output power level (at the output of the amplifier stage 150), or more specifically, as a ratio of output to input power. In some embodiments, the amplifier stage 150 is used to increase the power level of the RF output signal to a level sufficient to transmit the modulated RF signal at a given power level and over a desired transmission distance (wirelessly or wired). In other embodiments, the amplifier stage 150 includes a programmable gain attenuation stage. The programmable gain attenuation stage includes a programmable amplifier configured to amplify the modulated RF signal with a gain factor of 1 or less, in such a way that the programmable gain attenuation stage can attenuate the power level of the modulated RF signal output from the mixer stage 140 as needed for a given application.

[0050] The impedance matching network 160 is configured to match the source impedance or load impedance of the output of the amplifier stage 150 to the characteristic impedance of the output load (e.g., antenna input, duplexer, etc.) of the RF signal generator system 100. In some embodiments, the impedance matching network 160 includes a balanced-unbalanced transformer to convert the differential / balanced output of the amplifier stage 150 to a single-ended / unbalanced output. In some embodiments, the resonant parameters (e.g., impedance and bandwidth) of the impedance matching network 160 remain substantially unchanged, wherein the impedance matching network 160 is designed to have a center frequency corresponding to the desired operating frequency of the load. In other embodiments, the impedance matching network 160 is configured with multiple injection points to provide different impedance matching and filtering characteristics. Different injection points can be selected by a digital control signal applied to the impedance matching network 160. The impedance matching network 160 can have high-pass and low-pass characteristics, wherein different injection points can be selected to provide different impedance matching and response characteristics. In some embodiments, the impedance matching network 160 is designed to have a high Q factor, wherein the center frequency of the impedance matching network 160 can be adjusted to provide adequate impedance matching for different transmission frequencies, which are generated by, for example, changing the sampling frequency of the DAC stage 120 and / or changing the LO frequency of the mixer stage 140 according to a given application.

[0051] In some embodiments, the LO signal generator circuit 170 is configured to generate quadrature LO signals LO_I and LO_Q having target center frequencies, which are used by the mixer stage 140 to perform I / Q modulation and up-conversion. In some embodiments, for a differential signal framework, the LO signal generator circuit 170 is configured to generate complementary quadrature LO signals including complementary in-phase LO signals LO_I and LO_Q. and the complementary quadrature phase LO signal LO_Q and Ideally, the complementary quadrature LO signals LO_I, LO_Q, and They have the same amplitude and center frequency, but different phases 0°, 90°, 180° and 270° respectively.

[0052] The LO signal generator circuit 170 can be implemented using known circuit architectures and LO signal generation techniques. For example, in some embodiments, the LO signal generator circuit 170 includes a phase-locked loop (PLL) system configured to generate an LO signal having a target center frequency, and a phase shifter circuit that converts the LO signal generated by the PLL system into quadrature LO signals LO_I and LO_Q. For differential quadrature LO signals, in some embodiments, the LO signal generator circuit 170 can implement a quadrature phase shifter circuit that is configured to receive a complementary pair of LO signals LO and as input and generates complementary quadrature LO signals LO_I, LO_Q, and In some embodiments, the quadrature phase shifter circuit may be implemented using a quadrature polyphase phase shifter circuit having a single polyphase filter stage or multiple polyphase filter stages, as known to those of ordinary skill in the art.

[0053] The LO signal output driver circuit 180 includes an LO signal driver stage configured to drive the LO inputs of the first mixer circuit 141 and the second mixer circuit 142 in the mixer stage 140 using the orthogonal LO signal generated and output from the LO signal generator circuit 170. In some embodiments, the LO signal output driver circuit 180 is configured to selectively activate and deactivate the segments of the switching transistors of the first mixer circuit 141 and the second mixer circuit 142 to adjust the gain / attenuation of the RF output signal. Exemplary embodiments of the LO signal output driver circuit 180 will be discussed in further detail below in conjunction with FIG. 7.

[0054] like Figure 1As shown, each signal processing stage 110, 120, 130, 140, 150, 160, 170, and 180 of the RF signal generator system 100 includes a control signal input port that receives a digital control signal from a calibration system 190 or some processor or microcontroller configured to control the operation of the RF signal generator system 100. The calibration system 190 can generate digital control signals to configure the RF signal generator system 100 or its signal processing stages to operate in different modes. In addition, in some embodiments, some or all of the stages 110, 120, 130, 140, 150, 160, 170, and 180 have a configurable hardware framework, wherein various operating parameters of the stages can be adjusted by digital control signals for different operating modes of the RF signal generator system 100.

[0055] Figure 2A and 2B Schematically shows a radio frequency signal generator system according to another exemplary embodiment of the present disclosure. More specifically, Figure 2A and 2B The RF signal generator system 200 is schematically shown, wherein Figure 2A The voltage mode baseband filter stage 210 of the RF frequency signal generator system 200 is schematically shown. Figure 2B The current mode RF output stage 215 of the RF signal generator system 200 is schematically shown, wherein the current mode RF output stage 215 includes a baseband signal input stage 220, a current commutated mixer stage 230, a signal attenuation stage 240, an output transformer stage 250, a first DC offset compensation DAC 260, and a second DC offset compensation DAC 262. The RF signal generator system 200 also includes a regulation system 270, which includes a voltage regulator circuit 272 and a replica bias circuit 274, the functions of which will be explained in more detail below. In some embodiments, the RF signal generator system 200 includes a complementary quadrature architecture, which is configured to utilize complementary in-phase baseband signals I(t) and The complementary quadrature phase baseband signal Q(t) and and a complementary quadrature LO signal, and the complementary quadrature LO signal includes a complementary in-phase LO signal LO_I and and the complementary quadrature phase LO signal LO_Q and

[0056] In some embodiments, Figure 2A The voltage mode baseband filter stage 210 is schematically shown Figure 1 In addition, in some embodiments, the baseband signal input stage 220 and the current commutated mixer stage 230 are schematically shown. Figure 1In some embodiments, the signal attenuation stage 240 is schematically shown. Figure 1 An exemplary embodiment of the amplifier stage 150, furthermore, in some embodiments, the output transformer stage 250 represents Figure 1 1 , wherein the output transformer stage 250 includes circuitry for transforming the differential output signal into a single-ended output signal. The output transformer stage 250 may be implemented using a variety of techniques and circuit configurations to transform the differential output signal into a single-ended output signal, which techniques and circuit configurations are suitable for a given application and are known to those of ordinary skill in the art.

[0057] refer to Figure 2A The voltage-mode baseband filter stage 210 includes a first baseband filter 212 and a second baseband filter 214. The first baseband filter 212 includes a first voltage-mode baseband filter circuit 212-1 and a second voltage-mode baseband filter circuit 212-2, which are configured to receive and filter respective complementary in-phase baseband signals I ′(t) and And output the filtered complementary in-phase baseband signal I(t) and The second baseband filter 214 includes a first voltage-mode baseband filter circuit 214-1 and a second voltage-mode baseband filter circuit 214-2, which are configured to receive and filter the corresponding complementary quadrature-phase baseband signals Q'(t) and Q'(t), and output the filtered complementary quadrature-phase baseband signals Q(t) and Q(t). In some embodiments, each of the voltage-mode baseband filter circuits 212-1, 212-2, 214-1 and 214-2 includes a single-ended voltage-mode filter circuit, which is configured to receive and filter the corresponding unfiltered baseband signal I ′(t) , Q ′(t) and Convert it into a voltage signal, and filter the voltage signal into filtered baseband voltage signals I(t), Q(t) and and output, a single-ended voltage mode filter circuit includes a current mode baseband DAC stage (e.g., Figure 1 The current mode baseband signal generated by the DAC stage 120 is shown in the figure below. Figures 3A-3F An exemplary baseband filter circuit architecture is shown, and exemplary embodiments of a voltage-mode baseband filter circuit are discussed in further detail.

[0058] refer to Figure 2B, the current mode RF output stage 215 includes a current mode structure, in which signal processing is performed using current signals flowing in the I / Q signal paths of the baseband signal input stage 220, the current commutated mixer stage 230, and the signal attenuation stage 240. The baseband signal input stage 220 includes a plurality of baseband input transistors 221, 222, 223, and 224. In some embodiments, the baseband input transistors 221, 222, 223, and 224 are p-type metal oxide semiconductor (PMOS) transistors. Transistors 221 and 222 include a first differential transistor pair 220-1, in which transistors 221 and 222 have source terminals commonly connected to the output terminal of the voltage regulator circuit 272, and receive complementary baseband voltage signals I(t) and and the corresponding gate terminals of the baseband filter stage 210 ( Figure 2A ) of the respective first and second voltage mode baseband filter circuits 212-1 and 212-2. Transistors 223 and 224 comprise a second differential transistor pair 220-2, wherein transistors 223 and 224 have source terminals commonly connected to the output terminal of the voltage regulator circuit 272, and receive complementary baseband voltage signals Q(t) and The complementary baseband voltage signals are respectively received from the voltage mode baseband filter stage 210 ( Figure 2A ) of the respective first and second voltage mode baseband filter circuits 214-1 and 214-2 outputs. Transistors 221, 222, 223 and 224 each include a drain terminal connected to a respective one of the plurality of differential transistor pairs in the current commutated mixer stage 230.

[0059] In some embodiments, transistors 221, 222, 223, and 224 of baseband signal input stage 220 include variable gain elements (as schematically shown by the tilted arrows on the transistors) that are configurable to adjust the baseband signal gain in the I / Q signal path. For example, in some embodiments, each baseband input transistor 221, 222, 223, and 224 includes a variable width transistor that is structurally configured and controlled using known techniques to change the effective gate width of the transistor structure and thereby adjust the DC drain current I flowing through the corresponding transistor 221, 222, 223, and 224 when operating in saturation mode. D_1 ,I D_2 ,I D_3 and I D_4 The maximum amount of current (e.g., quiescent current).

[0060] For example, in some embodiments, each baseband input transistor 221, 222, 223, and 224 can be structurally configured to include multiple transistor segments coupled in parallel, wherein the number of segments that are active / inactive at a given time (via a digital switch control system) can be adjusted to change the effective gate width of a given baseband input transistor. In this regard, the effective width of the transistors 221, 222, 223, and 224 in the baseband signal input stage 220 can be configured to adjust the baseband signal gain in the I / Q signal path over a target gain range (e.g., a 20 dB gain range), wherein there are multiple gain step settings within the gain range. For example, in some embodiments, the DC baseband current can be adjusted to one of various target current levels within a given range, wherein the highest baseband current level is approximately 10 times greater than the lowest baseband current level (e.g., a range from about 35uA to about 350uA).

[0061] The current commutated mixer stage 230 includes a differential I mixer 230-1 and a differential Q mixer 230-2. The differential I mixer 230-1 includes a plurality of mixing transistors 231, 232, 233, and 234 (or, I mixer switch transistors 231, 232, 233, and 234). The differential Q mixer 230-2 includes mixing transistors 235, 236, 237, and 238 (alternatively, Q mixer switch transistors 235, 236, 237, and 238). In some embodiments, as shown in FIG. 2, the mixing transistors 231, 232, 233, 234, 235, 236, 237, and 238 are PMOS transistors. In some embodiments, the mixing transistors 231, 232, 233, 234, 235, 236, 237, and 238 are biased to operate in triode mode.

[0062] In the differential I mixer 230-1, the mixing transistors 231 and 232 comprise a first differential mixer transistor pair having source terminals commonly connected to the drain terminal of the transistor 221 in the baseband signal input stage 220, and respective gate terminals receiving complementary in-phase LO signals as inputs, respectively. The mixing transistors 233 and 234 comprise a second differential mixer transistor pair having source terminals commonly connected to the drain terminal of the transistor 222 in the baseband signal input stage 220, and respective gate terminals receiving complementary in-phase LO signals, respectively. and LO_I as the corresponding gate terminals of the inputs.

[0063] In the differential Q mixer 230-2, the mixing transistors 235 and 236 comprise a first differential mixer transistor pair having source terminals commonly connected to the drain terminal of the transistor 223 in the baseband signal input stage 220 and receiving the complementary quadrature phase LO signals LO_Q and LO_Q, respectively. Mixing transistors 237 and 238 comprise a second differential mixer transistor pair having source terminals commonly connected to the drain terminal of transistor 224 in baseband signal input stage 220 and receiving complementary quadrature phase LO signals, respectively. and LO_Q as the corresponding gate terminals of the inputs.

[0064] The current-commutated mixer stage 230 includes two output nodes, denoted as N OUT1 and N OUT2 .like Figure 2B As schematically shown in FIG. 1 , mixer transistors 231 , 233 , 235 and 237 have a common coupling to an output node N of the current commutated mixer stage 230 . OUT1 The drain terminals of the mixer transistors 232, 234, 236 and 238 have output nodes N coupled to the current commutated mixer stage 230. OUT2 The differential I mixer 230-1 and the differential Q mixer 230-2 are configured to provide analog I / Q modulation and up-conversion, wherein the connection of the mixing transistors of the differential I and Q mixers 230-1 and 230-2 (operating in triode mode) allows summing / subtraction of the output currents of the mixing transistors 231, 232, 233, 234, 235, 236, 237, and 238 to achieve SSBI / Q modulation, as understood by those of ordinary skill in the art.

[0065] The signal attenuation stage 240 is configured to adjust the signal strength of the RF output signal. Figure 2B In an exemplary embodiment of the present invention, the signal attenuation stage 240 is configured to adjust the amount of differential current flowing from the output nodes NOUT1 and NOUT2 to the output transformer stage 250. In this regard, the signal attenuation stage 240 is used to adjust the signal level output from the current-commutated mixer stage 230. The signal attenuation stage 240 includes a plurality of attenuation sections 240-1, ..., 240-s, which are controlled by corresponding differential control signals. Digital control. Figure 2B As shown, the first attenuation section 240-1 includes a first differential pair of transistors 241 and 242, and a second differential pair of transistors 243 and 244. In addition, the attenuation section 240-s includes a first differential pair of transistors 245 and 246, and a second differential pair of transistors 247 and 248. In some embodiments, the transistors 241, 242, 243, 244, 245, 246, 247, and 248 of the signal attenuation stage 240 are PMOS transistors. The number of attenuation sections 240-1, ..., 240-s implemented will depend on the desired resolution of the gain adjustment.

[0066] In the first attenuation section 240-1, the first differential pair transistors 241 and 242 have a common connection to the mixer output node N OUT1 The source terminals of the ATTN_1 and The transistor 241 has a drain terminal coupled to the output transformer stage 250, and the transistor 242 has a drain terminal coupled to the negative power supply node VSS (e.g., 0V ground voltage). In addition, the second differential pair transistors 243 and 244 have a common connection to the mixer output node N OUT2 The source terminals of the and V ATTN_1 Transistor 243 has a drain terminal coupled to the negative power supply node VSS, and transistor 244 has a drain terminal coupled to the output transformer stage 250 .

[0067] Similarly, in the attenuation section 240-s, the first differential transistor pair 245 and 246 have a common connection to the mixer output node N OUT1 The source terminals of the ATTN_s and The transistor 245 has a drain terminal coupled to the output transformer stage 250, and the transistor 246 has a drain terminal coupled to the negative power supply node VSS. In addition, the second differential transistor pair 247 and 248 have source terminals commonly connected to the mixer output node NOUT2, and receive differential control signals respectively. and V ATTN_s Transistor 247 has a drain terminal coupled to the negative power supply node VSS, and transistor 248 has a drain terminal coupled to the output transformer stage 250 .

[0068] In operation, the power from the output node N can be adjusted based on the number of activated attenuation segments 240-1, ..., 240-s. OUT1 and N OUT2 The amount of differential current flowing to the output transformer stage 250. When the corresponding differential control signal V ATTN and A given attenuation segment is “activated” when V ATTN _1 is logic "0" and When the first attenuation stage 240-1 is logic "1", the first attenuation stage 240-1 will be activated, so that the transistors 241 and 244 will be in the "on" state and allow some current to flow from the output node N OUT1 and N OUT2flows to the output transformer stage 250, and transistors 242 and 243 will be in the cut-off "off" state. On the other hand, when V ATTN _1 is logic "1" and When the voltage is logic "0", the first attenuation stage 240-1 will be "deactivated", so that transistors 241 and 244 will be in the "off" state, and transistors 242 and 243 will be in the "on" state, allowing some current to flow from the output node N OUT1 and N OUT2 Flows to the negative power supply node VSS (eg, ground). OUT1 and N OUT2 The current flowing to the negative power supply node VSS (eg, ground) does not contribute to the current flowing through the output transformer stage 250, so the RF output signal level is reduced.

[0069] In this configuration, the output node N OUT1 and N OUT2 The amount of differential current flowing to the output transformer stage 250 can be increased by increasing the number of activated attenuation segments, or decreased by decreasing the number of deactivated attenuation segments. The number of attenuation segments 240-1, ..., 240-s implemented will depend on the desired resolution of the gain adjustment. Note that when activated, the transistors of the signal attenuation stage 240 are configured to operate in a saturation mode.

[0070] In some embodiments, the first DC offset compensation DAC 260 and the second DC offset compensation DAC 262 are used in a Figure 1 The calibration control system 190 corrects the DC baseband current I under the control of the calibration system + ,I - , Q + and Q - The imbalance between Figure 2B As shown, the first DC offset compensation digital-to-analog converter 260 includes a first output terminal coupled to the drain terminal of the baseband input transistor 221, and a second output terminal coupled to the drain terminal of the baseband input transistor 222. The second DC offset compensation digital-to-analog converter 262 includes a first output terminal coupled to the drain terminal of the baseband input transistor 223, and a second output terminal coupled to the drain terminal of the baseband input transistor 224.

[0071] In this exemplary configuration, in response to a control signal received from the calibration control system, the first DC offset compensation DAC 260 is configured to apply the additional current I C_1 and I C_2 Injected into the I+ and I- baseband signal paths. The additional current I C_1 and I C_2The corresponding drain current I is added to the corresponding baseband input transistors 221 and 222. D_1 and I D_2 , thus balancing I + and I - baseband current, and thus significantly reduces or eliminates the I applied to the input of I-mixer 230-1. + and I - The DC offset between the baseband currents. The additional current I C_3 and I C_4 The corresponding drain currents I D_3 and I D_4 , thus balancing Q + and Q - baseband current, and thus significantly reduces or eliminates the Q applied to the input of Q mixer 230-2. + and Q - DC offset between baseband currents.

[0072] It is worth noting that the imbalance between the baseband currents can be compensated via the first and second DC offset DACs 260 and 262, and / or Figure 1 The first and second DAC circuits 121 and 122 in the embodiment are adjusted, for example, using the first and second DC offset compensation DACs 260 and 262 to ensure that the phase corresponding to a given phase, for example {I + and I -}, and {Q + and Q -}, any imbalance (offset) between the two baseband currents is minimized. On the other hand, the first and second DAC circuits 121 and 122 ( Figure 1 ) is preferably used to correct the baseband current I + and Q + Therefore, the use of the first and second DC offset compensation DACs 260 and 262, together with the first and second DAC circuits 121 and 122, provides the ability to correct the imbalance and ensure that all baseband currents I + ,I - , Q + and Q - are basically equal in size.

[0073] exist Figure 2BIn the exemplary I / Q modulation structure of the RF signal generator system 200 shown, it is desirable to eliminate or otherwise substantially minimize the imbalance between the baseband I and Q signals for the purpose of image rejection. In practice, I / Q imbalance may result in an unwanted spectrum at the image frequency. As described above, the SSB mixer is configured to up-convert the intermediate frequency (IF) of the baseband signal to only one of the sideband signal center frequencies of LO+IF or LO–IF without generating an image of the other sideband signal, which is particularly useful when using low IF frequencies, where frequency selective filtering is difficult. For example, if one wants to up-convert the baseband signal to only one of the sideband signal center frequencies of LO+IF or LO–IF, the image of the other sideband signal may be generated. RF =f LO -f IF The desired RF signal is generated on f, then the sideband signal (image signal) is IF +f LO The image frequencies will be suppressed by the sideband suppression provided by the SSB mixer. However, the imbalance in the amplitude of the baseband I and Q signals may result in relatively high spectral power being present at the image frequencies for the unwanted spectrum.

[0074] In addition, for analog I signals using differential and differential analog Q signal The differential I / Q scheme of the differential analog I signal I(t) and The unbalanced and / or differential analog Q signal Q(t) between An imbalance between the differential analog baseband signal I(t) and and / or the differential analog baseband signal Q(t) and The imbalance between the two may be a DC offset of the baseband analog signal generated by the DAC stage 120. The DC offset between the differential baseband signals means that the signals are not completely complementary due to the presence of the DC term. In the current-commutated mixer stage 230, the DC offset of the complementary baseband signal pair generates a DC term that is multiplied by the LO frequency, causing the output of the mixer stage 230 to include an undesired LO frequency component (LO leakage) that should otherwise be suppressed by means of I / Q modulation.

[0075] As described above, in the baseband signal input stage 220, the first differential transistor pair 220-1 is configured to receive the complementary in-phase baseband signals I(t) and (filtered baseband voltage signal), and the second differential transistor pair 220-2 is configured to receive the complementary quadrature-phase baseband signal Q(t) and (filtered baseband voltage signal), and in response, the first and second differential transistor pairs 220-1 and 220-2 generate current mode signals that are applied to the current commutated mixer stage 230. In this regard, in the baseband signal input stage 220, matching is critical between the first differential pair transistors 221 and 222 and between the second differential pair transistors 223 and 224. In addition, the matching between the first differential transistor pair 220-1 and the second differential transistor pair 220-2 is critical, and mismatching between transistors in the baseband signal input stage 220 may result in an imbalance of the I / Q baseband current signal, which may result in LO leakage and insufficient image suppression.

[0076] In some embodiments, Figure 1 The calibration control system 190 implements a control circuit and calibration method for configuring the RF signal generator system 200 to operate in a calibration mode, wherein the calibration control system can measure / estimate the DC baseband current I + ,I - , Q + and Q - , and determine the same relative {I + ,I -} and {Q + ,Q -}, which provides an indication of the DC offset causing LO leakage and determines the measured I + and Q + The difference (imbalance) between the baseband currents, where I + and Q + The imbalance between the baseband currents can degrade the image rejection, which results in the presence of unwanted sideband glitches.

[0077] By allowing a lower supply voltage (eg, 500 mV-700 mV) for the voltage-mode baseband filter stage 210, Figure 2A Utilization of the voltage-mode baseband filter stage 210 in the RF signal generator system 200 may provide improved power efficiency for the analog signal path in the RF signal generator system 200, in contrast to utilizing a current-mode baseband filter circuit including a stacked transistor architecture that may require a higher supply voltage (e.g., 900 mV or greater). However, the voltage-mode baseband filter stage 210 ( Figure 2A ) and the current mode RF output stage 215 ( Figure 2B) interface is not trivial because directly connecting the voltage-mode outputs of the baseband filter transistors to the transistors in the current-mode baseband input stage 220 does not generally provide suitable biasing of the transistors in the current-mode RF output stage 215 (unlike the current-mode connection provided between the current-mode baseband filter and the current-mode output stage based on a current mirror). In fact, in the case where the output common mode of the filter circuit of the voltage-mode baseband filter stage 210 is ground referenced and the bias of the current-mode RF output stage 215 is referenced to the positive supply, the biasing of the baseband filter transistors in the current-mode baseband input stage 220 is not generally provided by the current-mode RF output stage 215. Figure 2B The quiescent current (eg, I D1 ,I D2 ,I D3 and I D4 ) are particularly sensitive to power supply voltage changes.

[0078] In this regard, exemplary embodiments of the present disclosure provide a method for interfacing voltage mode baseband filter circuitry to a Figure 2B The current mode RF output stage 215 is configured to ensure that the quiescent current (e.g., I D1 ,I D2 ,I D3 and I D4 ) at a target current level. Generally, such techniques provide a mechanism for adjusting the voltage of the source node of the first differential transistor pair 220-1 and the source node of the second differential transistor pair 220-2 so that the baseband input transistors 221, 222, 223, and 224 operate in saturation mode with an appropriate gate-to-source voltage (V GS ) to achieve a desired quiescent current level (e.g., I D1 ,I D2 ,I D3 and I D4 ).

[0079] Figure 2B An exemplary embodiment is shown in which the regulation system 270 is configured to generate a regulated positive supply voltage, denoted as VDD_RF_Reg, which is applied to the N Reg The regulated voltage node (alternatively, the regulated node N Reg ), the source nodes of the input transistors 221, 222, 223 and 224 are commonly connected to this node. More specifically, Figure 2BIn an exemplary embodiment, voltage regulator circuit 272 and replica bias circuit 274 are configured to operate in cooperation to generate a voltage applied to regulated node N Reg In some embodiments, the voltage regulator circuit 272 includes a low dropout (LDO) voltage regulator circuit that is configured to receive as input (i) an unregulated positive supply voltage VDD_RF_Unreg and (ii) a reference voltage VDD_Replica output from the replica bias circuit 274, and generate a regulated supply voltage VDD_RF_Reg corresponding to VDD_Replica. The LDO voltage regulator circuit is a DC linear voltage regulator that is configured to regulate the LDO output voltage (VDD_RF_Reg) even when the unregulated positive supply voltage VDD_RF_Unreg is close to the LDO output voltage. In some embodiments, VDD_RF_Unreg is a supply voltage of approximately 900 mV or less that is applied from the positive supply node. The voltage regulator circuit 272 monitors the regulated node N Reg The regulation system 270 is configured to actively regulate the voltage on the regulated node N and actively regulate the power supply voltage VDD_RF_Reg to ensure that VDD_RF_Reg corresponds to VDD_Replica. In this regard, the regulation system 270 is configured to actively regulate the regulated node N Reg The voltage on 274 corresponds to VDD_Replica, which is set by the replica bias circuit 274.

[0080] In some embodiments, the replica bias circuit 274 includes a replica of the circuit components of the voltage-mode baseband filter and the RF output stack. In this regard, the replica bias circuit 274 will vary depending on the circuit architecture of the voltage-mode baseband filter and the RF output stack. Figures 3A-3F Exemplary embodiments of voltage mode baseband filters are discussed in further detail. Figure 4 , 5B 7A discuss an exemplary embodiment of the replica bias circuit 274.

[0081] Figure 3A A voltage mode baseband filter circuit according to an exemplary embodiment of the present invention is schematically illustrated. In particular, Figure 3A The voltage mode baseband filter circuit 300-1 is schematically shown, which is used to implement Figure 2A Each of the voltage mode baseband filter circuits 212-1, 212-2, 214-1 and 214-2 in FIG. Figure 3A As shown, the voltage mode baseband filter circuit 300-1 includes an input stage 302 and a filter circuit 310. The input stage 302 includes a constant current source 305 and a pull-down resistor R T, which are connected in series between a positive power supply node (VDD_DAC) and a negative power supply node (VSS). The input stage 302 is configured to generate a voltage (V IN In some embodiments, the constant current source 305 includes a current steering DAC that generates a DC current IFS (where IFS represents a full-scale DAC current level). FS Flowing through the pull-down resistor R T , to generate a common-mode DC voltage at the input node N1 of the filter circuit 310. In an exemplary non-limiting embodiment, the resistor RT has a relatively low resistance value (e.g., about 300 ohms), and the DC current IFS is configured to establish a common-mode input voltage of about 60 millivolts (mV), wherein the baseband voltage signal applied to the input node N1 has a peak-to-peak voltage (VPP) of about 120 mV.

[0082] The filter circuit 310 includes an analog biquadratic low-pass filter framework, which includes a first transistor 312 (e.g., a PMOS transistor), a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. The filter circuit 310 also includes a second transistor 314 used as a bias transistor. The first resistor R1 is coupled to the input node N1 and the second node N2 (or, the feedback node N2). The second resistor R2 is coupled to the second node N2 and the third node N3. The first capacitor C1 is coupled to the second node N2 and the fourth node N4, which provides a feedback path (from the node N4 to the node N2) of the filter circuit 310. The second capacitor C2 is coupled to the third node N3 and the negative power supply voltage node VSS. The first transistor 312 includes a gate terminal coupled to the third node N3, a source terminal coupled to the fourth node N4 (i.e., coupled to the feedback path of the filter circuit 310), and a drain terminal coupled to the negative power supply voltage node VSS.

[0083] As described above, the second transistor 314 includes a bias element configured to generate a bias current IBIAS for operating the filter circuit 310 at a given operating point. The second transistor 314 is a PMOS transistor that includes a gate terminal receiving a bias voltage VBP, a source terminal coupled to the positive power supply node VDD_BBF, and a drain terminal coupled to the fourth node N4. In some embodiments, the bias voltage VBP includes a DC control voltage that is generated and applied to the gate terminal of the second transistor 314. In some embodiments, the second transistor 314 is a mirror transistor in a current mirror circuit that generates a bias current IBIAS that is proportional to the reference current IREF (e.g., a ratio of 1:1, or greater), as understood by those skilled in the art.

[0084] Filter circuit 310 comprises an analog biquad low pass filter framework, which is a variation of a low pass 2nd order (2 complex poles) Sallen-Key filter (or positive feedback filter). Figure 3A The Sallen-Key filter configuration in is implemented using a single transistor 312 in a source follower configuration (providing unity gain) rather than an operational amplifier as is typically implemented in conventional Sallen-Key filter and biquadratic low-pass filter designs. In the filter circuit 310, the filter feedback loop is implemented by coupling the source terminal of the transistor 312 to the feedback node N2 via a first capacitor C1. Compared to conventional biquadratic low-pass filter circuits, the source follower-based implementation of the Sallen-Key filter circuit 310 provides lower power consumption, low distortion, and a smaller footprint (less footprint). In addition, by using the voltage-mode baseband filter circuit 300-1, an analog signal path can be implemented in an RF signal generator system, where at least the baseband filter stage operates with a relatively low supply voltage (e.g., 500mV to approximately 800mV) to achieve low power consumption.

[0085] exist Figure 3A In an exemplary embodiment of the present invention, the voltage output (VOUT) of the filter circuit 310 is taken at the fourth node N4, which is the source terminal of the first transistor 312. In other embodiments, the voltage output of the filter circuit 310 is taken from the node N3, which is the gate terminal of the first transistor 312. In the absence of a next stage load, the frequency response H(s) of the filter circuit 310 is almost the same at the gate and source terminals (nodes N3 and N4), where the frequency response is expressed as: where ω o Represents the center frequency, which is expressed as in and wherein the filter circuit 310 has a quality factor

[0086] Next, Figure 3B A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated. In particular, Figure 3B The voltage mode baseband filter circuit 300-2 is schematically shown, which is used to implement Figure 2A Each of the voltage mode baseband filter circuits 212-1, 212-2, 214-1 and 214-2. Figure 3B As shown, the voltage mode baseband filter circuit 300-2 is similar to Figure 3AThe voltage-mode baseband filter circuit 300-1 is a circuit that is similar to the voltage-mode baseband filter circuit 300-1, except that the voltage-mode baseband filter circuit 300-2 includes a buffer circuit 320. The buffer circuit 320 includes an input terminal and an output terminal, wherein the input terminal is coupled to the gate terminal (node ​​N3) of the first transistor 312, and the output terminal provides a voltage output (V OUT ), in some embodiments, the buffer circuit 320 includes a PMOS source follower buffer.

[0087] Figure 3B An exemplary embodiment is shown in which the output of the filter circuit 310 is taken at the gate terminal of the first transistor 312, while Figure 3A , the output of the filter circuit 310 is taken at the source terminal of the first transistor 312. As described above, the frequency response of the filter circuit 310 at the gate terminal and the source terminal of the first transistor 312 is similar, except that the frequency response at the gate terminal of the first transistor 312 is sharper (e.g., sharper cutoff) than the frequency response at the source terminal of the first transistor 312. However, the output impedance of the filter circuit 310 varies with frequency, which may result in a degraded filter response. The buffer circuit 320 is used to buffer the output of the filter circuit 310 and provide low output impedance over a wide frequency range and unity gain.

[0088] Next, Figure 3C A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated. In particular, Figure 3C The voltage mode baseband filter circuit 300-3 is schematically shown, which is used to implement Figure 2A Each of the voltage mode baseband filter circuits 212-1, 212-2, 214-1 and 214-2. Figure 3C As shown, the voltage mode baseband filter circuit 300-3 is similar to Figure 3A The voltage mode baseband filter circuit 300-1 is a voltage mode baseband filter circuit 300-3, except that the voltage mode baseband filter circuit 300-3 includes a cascaded multi-stage filter circuit 310. In particular, the voltage mode baseband filter circuit 300-3 includes a first filter stage 310-1 and a second filter stage 310-2, wherein each filter stage 310-1 and 310-2 includes Figure 3A The filter circuit 310 is a Sallen-Key filter circuit configuration.

[0089] More specifically, the first filter stage 310-1 is a Sallen-Key filter circuit that includes a first transistor 312-1, first and second resistors R1 and R2, and first and second capacitors C1 and C2 that have Figure 3AThe second filter stage 310-2 is a Sallen-Key filter circuit, which includes a first transistor 312-2, a first resistor R 12 and the second resistor R 22 , and a first capacitor C 12 and the second capacitor C 22 , they have Figure 3A The filter circuit 310 has the same connection topology. In addition, the first and second filter stages 310-1 and 310-2 include respective bias transistors 314-1 and 314-2 having a commonly connected gate terminal to receive a bias voltage VBP. Figure 3C In an exemplary embodiment of the present invention, the output node N3 of the first filter stage 310-1 (i.e., the gate terminal of the first transistor 312-1) is directly coupled to the input of the second filter stage 310-2, and the voltage output (V OUT ) is obtained at the fourth node N4 which is the source terminal of the first transistor 312-2. In other embodiments, the voltage output (V OUT ) can be obtained at the third node N3 which is the gate terminal of the first transistor 312-2.

[0090] Due to the filter structure, direct coupling of the first and second filter stages 310-1 and 310-2 is sufficient to implement a higher order filter without the need to implement a level shifter or complementary filter stage because the common mode output at the node N3 of the first filter stage 310-1 is substantially the same as the common mode input at the node N1 of the first filter stage 310-1. Figure 3C Only two filter stages 310-1 and 310-2 are shown, but it will be appreciated that a voltage-type baseband filter circuit can be implemented by directly DC-coupling three or more Sallen-Key filter stages in cascade because the common-mode voltage at each gate terminal (node ​​N3) of each Sallen-Key filter transistor (e.g., 312-1, 312-2, ... etc.) of each filter stage will have substantially the same common-mode voltage input at node N1 of the first filter stage (e.g., filter stage 310-1).

[0091] Next, Figure 3D A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated. In particular, Figure 3D The voltage mode baseband filter circuit 300-4 is schematically shown, which is used to implement Figure 2A Each of the voltage mode baseband filter circuits 212-1, 212-2, 214-1 and 214-2. Figure 3D As shown, the voltage mode baseband filter circuit 300-4 is similar to Figure 3C 3, except that the voltage-mode baseband filter circuit 300-4 includes a buffer circuit 330, wherein the buffer circuit 330 couples the output of the first filter stage 310-1 to the input of the second filter stage 310-2.

[0092] In some embodiments, the buffer circuit 330 is configured to shift the common mode voltage to a target level and provide a low output impedance over a wide frequency range and unity gain, thereby maintaining a high order cascade filter frequency response. In addition, in some embodiments, the buffer circuit 330 is configured to provide an additional pole that increases the order of the voltage mode baseband filter circuit 300-4, thereby providing a sharper filter response. In some embodiments, the buffer circuit 330 includes a PMOS source follower buffer, while in other embodiments, the buffer circuit 330 includes an NMOS source follower buffer.

[0093] Next, Figure 3E A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated. In particular, Figure 3E The voltage mode baseband filter circuit 300-5 is schematically shown, which is used to implement Figure 2A Each of the voltage mode baseband filter circuits 212-1, 212-2, 214-1 and 214-2. Figure 3E As shown, the voltage mode baseband filter circuit 300-5 is similar to Figure 3D The voltage-mode baseband filter circuit 300-4 includes, in addition to the voltage-mode baseband filter circuit 300-5, a third filter stage 310-3 and a second buffer circuit 340 coupling the output of the second filter stage 310-2 to the input of the third filter stage 310-3.

[0094] The third filter stage 310-3 is a Sallen-Key filter circuit, which includes the same filter architecture as the first and second filter stages 310-1 and 310-2. Specifically, the third filter stage 310-3 includes a first transistor 312-3, a first resistor R 13 and R 23 , and first and second capacitors C 13 and C 23 In addition, the third filter stage 310-3 includes a bias transistor 314-3 having a gate terminal commonly connected to the bias transistors 314-1 and 314-2 in the first filter stage 310-1 and the second filter stage 310-2 to receive a bias voltage V BP of the gate terminal.

[0095] In some embodiments, the first buffer circuit 330 and the second buffer circuit 340 are configured to provide a low output impedance (of the filter stage) over a wide frequency range and unity gain, thereby maintaining a high-order cascade filter frequency response. Additionally, in some embodiments, the first buffer circuit 330 and / or the second buffer circuit 340 may be configured to provide an additional pole that increases the order of the voltage-mode baseband filter circuit 300-5, thereby providing a sharper filter response. In some embodiments, in order to maintain a constant common-mode voltage across the filter stages 310-1, 310-2, and 310-3, the first buffer circuit 330 includes a PMOS source follower buffer and the second buffer circuit 340 includes an NMOS source follower buffer. In this regard, while the first buffer circuit 330 increases the common-mode output voltage of the first filter stage 310-1 by the VGS amount of the PMOS source follower transistor of the first buffer circuit 330, the second buffer circuit 340 reduces the common-mode output voltage of the second filter stage 310-2 by the VGS amount of the NMOS source follower transistor of the second buffer circuit 340. Assume that the V GS Close in magnitude to the V of an NMOS source follower GS , then the common-mode input voltage at the input of the third filter stage 310 - 3 will be approximately equal to the common-mode input voltage at the input node N1 of the first filter stage 310 - 1 .

[0096] Next, Figure 3F A voltage mode baseband filter circuit according to another exemplary embodiment of the present invention is schematically illustrated. In particular, Figure 3F The voltage mode baseband filter circuit 300-6 is schematically shown, which is used to implement Figure 2A Each of the voltage mode baseband filter circuits 212-1, 212-2, 214-1 and 214-2. Figure 3F As shown, the voltage mode baseband filter circuit 300-6 is similar to Figure 3E The voltage-mode baseband filter circuit 300-5 includes, in addition to the voltage-mode baseband filter circuit 300-6, a third buffer circuit 350 having an input terminal coupled to the output node N3 of the third filter stage 310-3 (i.e., the gate terminal of the first transistor 312-3), and an output terminal of the third buffer circuit 350 generating an output voltage V of the voltage-mode baseband filter circuit 300-6. OUT In some embodiments, the third buffer circuit 350 includes a PMOS source follower that increases the common-mode output voltage of the third filter stage 310 - 3 by the V of the PMOS source follower transistor of the third buffer circuit 350 . GS The amount.

[0097] It should be noted that Figures 3A to 3F The exemplary voltage-mode baseband filter circuit shown in provides various advantages. For example, the exemplary voltage-mode baseband filter circuit provides a circuit architecture that can utilize a relatively low positive supply voltage (e.g., 500 mV to 850 mV). In addition, the Sallen-Key filter architecture enables direct DC coupling (e.g., Figure 3C ) effectively cascades multiple filter stages to achieve higher order filters without the need to implement additional circuitry to match the common-mode input and output voltages. For example, in Figure 3C In an exemplary embodiment of the present invention, multiple Sallen-Key filter stages can be cascaded by directly coupling the gate terminals of the first transistors (e.g., transistors 312-1 and 312-2) of the filter stages so that the common-mode input voltage will match the common-mode output voltage of all filter stages at the gate node of the first transistor (because the gate terminal of the first transistor draws substantially no current). In addition, utilizing a buffer circuit to couple the input and output of the cascaded filter stages provides a lower power element that provides an additional pole to enhance the overall frequency response of the voltage-mode baseband filter circuit while providing the necessary DC voltage offset along the cascaded filter stages as needed to match the common-mode voltage.

[0098] Figure 4 Schematically illustrates a radio frequency signal generator system according to another exemplary embodiment of the present disclosure. More specifically, Figure 4 The RF signal generator system 400 according to an exemplary embodiment of the present disclosure is schematically shown, which includes a voltage-mode baseband filter stage 410, a current-mode RF output stage 415, a replica bias circuit 420, and a voltage regulator circuit 440. The voltage-mode baseband filter stage 410 includes a plurality of single-ended voltage-mode baseband filter circuits 411, 412, 413, and 414. In some embodiments, for example Figure 4 As shown in FIG. 1 , each of the single-ended voltage mode baseband filter circuits 411, 412, 413, and 414 implements Figure 3A An example of a voltage-mode baseband filter circuit 300-1 of FIG. 300-1, as discussed above, includes a Sallen-Key filter 310 using a single transistor 312 in a source follower configuration (with unity gain), wherein the filter output is taken from the source node (e.g., node N4) of transistor 312. In addition, Figure 4 In an exemplary embodiment, the current mode RF output stage 415 implements Figure 2B The current mode RF output stage 215 is as described above.

[0099] The single-ended voltage-type baseband filter circuit 411 receives the unfiltered baseband voltage signal I′(t) and outputs the filtered baseband voltage signal I(t) at the output node of the baseband filter circuit 411. The single-ended voltage-type baseband filter circuit 412 receives the unfiltered baseband voltage signal The filtered baseband voltage signal is outputted at the output node of the baseband filter circuit 412. The single-ended voltage-type baseband filter circuit 413 receives the unfiltered baseband voltage signal Q′(t) and outputs a filtered baseband voltage signal Q(t). The single-ended voltage-type baseband filter circuit 414 receives the unfiltered baseband voltage signal And output the filtered baseband voltage signal

[0100] The output nodes of the single-ended voltage type baseband filter circuits 411, 412, 413 and 414 are directly connected (DC coupled) to the gate terminals of the respective baseband input transistors 221, 222, 223 and 224 of the baseband signal input stage 220. For ease of explanation, Figure 4 Depicting a direct connection from the output node N4 of the single-ended voltage-type baseband filter circuit 411 to the gate terminal of the baseband input transistor 221. As described above, interfacing the voltage-type baseband filter stage 410 with the current-type RF output stage 415 is a challenge through direct connections (DC coupling) from the output nodes of the single-ended voltage-type baseband filter circuits 411, 412, 413, and 414 to the gate terminals of the corresponding baseband input transistors 221, 222, 223, and 224 of the baseband signal input stage 220.

[0101] In particular, the DC bias of the baseband input transistors 221, 222, 223, and 224 of the baseband signal input stage 220 is based on the VGS bias voltage of the baseband input transistors 221, 222, 223, and 224, wherein the VGS bias is referenced to the positive power supply VDD. On the other hand, the output common mode voltage of the single-ended voltage-type baseband filter circuits 411, 412, 413, and 414 is substantially ground-referenced (referenced to VSS) and therefore does not rely on the positive power supply. In this regard, since the output common mode voltage of the single-ended voltage-type baseband filter circuits 411, 412, 413, and 414 is directly applied to the gate terminals of the corresponding baseband input transistors 221, 222, 223, and 224, changes in the positive power supply voltage VDD will result in changes in the VGS voltage of the baseband input transistors 221, 222, 223, and 224, which in turn results in changes in the quiescent current (or bias current) flowing in the analog I / Q signal path of the current mode RF output stage 415. In fact, since the VGS bias of the baseband input transistors 221, 222, 223 and 224 is based on the difference between the output common-mode voltage of the single-ended voltage-type baseband filter circuits 411, 412, 413 and 414 and the power supply voltage VDD, the DC bias current generated by the baseband input transistors 221, 222, 223 and 224 is highly sensitive to changes in the power supply voltage VDD, which can lead to an unstable bias point of the current mode RF output stage 415.

[0102] exist Figure 4 In an exemplary embodiment of the present invention, the replica bias circuit 420 and the voltage regulator circuit 440 provide a system to interface the voltage mode baseband filter stage 410 with the current mode RF output stage 415 while providing a well-controlled bias point for the current mode RF output stage 415. Specifically, as described above, the voltage regulator circuit 440 and the replica bias circuit 420 are configured to regulate the voltage applied to the regulated node N Reg The source nodes of the input transistors 221, 222, 223 and 224 are commonly connected to the regulated node N Reg The replica bias circuit 420 is configured to generate a reference voltage VDD_Replica, which is input to the voltage regulator circuit 440 and used to generate a regulated voltage VDD_RF_Reg on the regulated node NReg relative to the output common mode voltage level on the output nodes of the single-ended voltage-type baseband filter circuits 411, 412, 413 and 414, so as to maintain a constant VDD of the input transistors 221, 222, 223 and 224. GS , and thus maintain a well-controlled quiescent current in the signal path of the current mode RF output stage 415 to achieve a stable bias point of the current mode RF output stage 415.

[0103] The replica bias circuit 420 includes replica elements of the baseband filter circuit 410 and the current mode RF output stage 415. For example, in Figure 4 In an exemplary embodiment of the present invention, the replica bias circuit 420 includes a first replica current source 425 (e.g., current mirror 425), a replica resistor RS, replica transistors 422, 424, 432, 434, and 436, and a second replica current source 430 (e.g., current mirror 430). The first replica current source 425 and the replica resistor RS correspond to the current source 305 and the resistor RT of one instance of the input stage 302 of the baseband filter circuit 410, respectively. The replica transistors 422 and 424 correspond to the transistors 312 and 314 of one instance of the filter circuit 310 of the baseband filter circuit 410, respectively. The replica transistor 432 corresponds to the baseband input transistor of the baseband input stage 220. The replica transistor 434 corresponds to the LO switch transistor in the current commutated mixer stage 230. The replica transistor 436 corresponds to the transistor in the attenuation stage 240. It should be noted that because the DC voltage drop across the output transformer stage 250 is negligible, the wiring resistance of the output transformer stage 250 does not need to be included in the replica bias circuit 420 .

[0104] The first replica current source 425 is configured to generate a current having a magnitude The bias current, I FS represents the full-scale DAC current, and K represents the scalar multiplier, where K>>1, and the replica resistor R S With resistance value K*R T In this regard, the first replica current source 425 and the replica resistor R S The replica bias circuit 420 is configured to generate an input common mode voltage on node N5 that matches the input common mode voltage generated by the input stage 302 and applied to the filter circuit 310. The input common mode voltage on node N5 biases the gate terminal of the replica transistor 422. The replica bias circuit 420 is configured to generate a bias current of magnitude β*I1 flowing in a current path through the replica transistors 424 and 422 (which operate in saturation mode), where I1 represents the bias current of the filter circuit 310 flowing through the transistors 314 and 312 operating in saturation mode, and β represents a scalar multiplier, where β<<1.

[0105] The second replica current source 430 is configured to generate a bias current having a certain amplitude flowing in a current path through the replica transistors 432, 434 and 436, where represents the desired bias current of the current mode RF output stage 415, and α represents a scalar multiplier, where α<<1. In the replica bias circuit 420, the replica transistors 432 and 436 are configured to operate in a saturation mode (similar to the transistors in the baseband signal input stage 220 and the attenuation stage 240), while the replica transistor 434 is configured to operate in a triode mode (similar to the mixing transistor in the current commutated mixer stage 230). In some embodiments, the second replica current source 430 is a variable current source that allows the amplitude α*I2 of the bias current to be adjusted in response to an adjustment of the desired bias current of the current mode RF output stage 415, such as when scaling (increasing or decreasing) the gain of the baseband input stage 220 to change the output amplitude of the RF output signal.

[0106] The replica transistors 422, 424, 432, 434 and 436 have a W / L size ratio designed based on the width / length (W / L) size ratio of the corresponding transistors in the current mode stage. For example, the W / L size ratio of the replica transistors is designed accordingly based on the following: in represents the size ratio of the circuit transistors, and represents the scaling factor. Specifically, the replica transistors 432, 434, and 436 in the replica bias circuit 420 are scaled versions of the corresponding transistors in the baseband input stage 220, the current commutated mixer stage 230, and the attenuation stage 240. The replica transistors are scaled by the same scaling factor to ensure that the current density remains the same between the current mode RF output stage 415 and the replica bias circuit 420.

[0107] The dimensions of the replica transistors 422 and 424 are configured so that the replica bias circuit 420 generates a voltage at a node N6, which corresponds to the output common-mode voltage generated at the node N4 of the single-ended voltage-type baseband filter circuits 411, 412, 413, and 414, and the voltage is applied to the gate terminals of the corresponding baseband input transistors 221, 222, 223, and 224. In addition, the dimensions of the replica transistors 432, 434, and 436 are configured so that the replica bias circuit 420 generates a reference voltage VDD_Replica at a node N7, which corresponds to the output common-mode voltage VDD_Replica required to be applied to the regulated node N7 relative to the output common-mode voltage of the single-ended voltage-type baseband filter circuits 411, 412, 413, and 414. Reg voltage to establish the appropriate V for baseband input transistors 221, 222, 223, and 224 GS The bias voltage is set so as to obtain a constant and stable bias current I2 generated by the baseband signal input stage 220 to properly bias the current mode RF output stage 415.

[0108] In other embodiments, Figure 4 The single-ended voltage mode baseband filter circuits 411, 412, 413 and 414 in the embodiment can be used Figure 3B , 3C , 3D, 3E or 3F, etc. to implement the example of the voltage mode baseband filter circuit. In addition, Figure 4 The replica bias circuit 420 in will be modified to provide a replica component corresponding to the filter circuit. For example, Figure 5A and 5B Schematically illustrates an exemplary voltage mode baseband filter circuit 500 and a replica bias circuit 520 according to another exemplary embodiment of the present disclosure, which can be implemented in the RF signal generator system 400. In particular, Figure 5A The voltage mode baseband filter circuit 500 schematically shows Figure 3B 5. The voltage-mode baseband filter circuit 500 is similar to the voltage-mode baseband filter circuit 300-2 and shows details of an exemplary configuration of the buffer circuit 320.

[0109] More specifically, the voltage-mode baseband filter circuit 500 includes a buffer circuit 510 including PMOS transistors 512 and 514, and a capacitor C3. The buffer circuit 510 includes a PMOS source follower buffer circuit, wherein the gate terminal of the PMOS transistor 512 is coupled to the output node N3 of the filter circuit 310. The PMOS transistor 514 operates as a current source to generate a bias current I1 that matches the bias current I1 generated by the PMOS transistor 314 of the filter circuit 310. The PMOS transistor 512 includes a source terminal coupled to an output node NOUT of the buffer circuit 510, which serves as an output node of the voltage-mode baseband filter circuit 500. The capacitor C3 is coupled to the output node N OUT and negative power supply node VSS. As described above, the addition of source follower buffer circuit 510 provides an additional filter pole to increase the order of the baseband filter and allows the filter output to have a sharper frequency response while providing a low output impedance to drive the next stage.

[0110] Figure 5B The replica bias circuit 520 is similar to Figure 4 The replica bias circuit 420 includes a replica bias circuit 520 corresponding to Figure 5AIn addition to the additional replica components of the source follower buffer circuit 510 of the source follower buffer circuit 510. More specifically, the replica bias circuit 520 includes replica transistors 522 and 524, which correspond to the PMOS transistors 512 and 514 of the source follower buffer circuit 510, respectively. The replica bias circuit 520 is configured to generate a bias current of amplitude β*I1 flowing in a current path through the replica transistors 524 and 522 (which operate in saturation mode). The replica bias circuit 520 is configured to generate a voltage on a node N8 (which corresponds to the output node N8 of the buffer circuit 510). OUT ), where the voltage generated at the node N8 corresponds to the output common mode voltage applied to the gate terminals of the baseband input transistors 221, 222, 223 and 224 of the baseband signal input stage 220.

[0111] As mentioned above, Figures 3A-3F The exemplary voltage-mode baseband filter circuit shown in provides a low voltage filter topology that can improve the power efficiency of the analog signal path of the RF signal generator system by allowing the use of a lower supply voltage (e.g., 500mV-700mV). In other embodiments, different topologies and signal processing techniques are used to modify the analog signal path of the RF signal generator system. Figure 2B The exemplary current-mode RF output stage 215 architecture is shown to effectively reduce the height of the current-mode transistor stack, thereby allowing the RF output stage to use a lower supply voltage (eg, less than 900 mV).

[0112] For example, Figure 6 Schematically illustrated is an RF signal generator system 600 according to another exemplary embodiment of the present invention, which includes an RF output stack configured to operate at a reduced power supply voltage. More specifically, the RF signal generator system 600 includes a voltage mode baseband filter stage 610 and a current mode RF output stage 615, which includes a baseband signal input stage 620, a current commutated mixer stage 630, an attenuation stage 640, and an output transformer stage 650. The RF signal generator system 600 also includes a regulation system 670 and an LO signal output driver circuit 680. The regulation system 670 includes a voltage regulator circuit 672 and a replica bias circuit 674.

[0113] The exemplary current mode RF output stage 615 is configured to operate at a lower VDD_RF supply voltage by placing the current commutated mixer stage 630 and the attenuation stage 640 at the same level in the stacked structure of the current mode RF output stage 615. In this exemplary configuration, the LO switch transistor of the current commutated mixer stage 630 and the attenuation transistor of the attenuation stage 640 are connected to the output of the baseband signal input stage 620 and operate at the same level as the current mode RF output stage 615. In addition, the output nodes NOUT1 and NOUT2 of the current commutated mixer stage 630 are directly coupled to the output transformer stage 650. Figure 6 In the exemplary stacked configuration shown, the LO switch transistor of the current commutated mixer stage 630 is biased in saturation mode.

[0114] The exemplary stack structure of the RF output stage effectively reduces the "height" of the stack structure (eg, reduces the number of transistors in the analog signal path from the baseband input stage 620 to the output transformer stage 650). Figure 2B 2 is in contrast to the exemplary stacked structure of the current-mode RF output stage 215, in which the current-commutated mixer stage 230 is stacked on the attenuation stage 240, in which the output nodes NOUT1 and NOUT2 of the current-commutated mixer stage 230 are directly coupled to the input of the attenuation stage 240, and in which the LO switching transistor of the current-commutated mixer stage 230 is biased in triode mode.

[0115] For complementary orthogonal architectures, similar to e.g. Figure 2A and 4 In the exemplary embodiment shown in , the voltage-mode baseband filter stage includes four single-ended voltage-mode baseband filter circuits configured to output filtered baseband voltage signals I(t), Q(t) and and applies it to the gate terminals of transistors in the baseband signal input stage 620. The regulation system 670 performs the same or similar functions as described above, except that the replica bias circuit 674 includes a replica device and topology configured to generate a reference voltage VDD_Replica based on the replica device and topology of the voltage mode baseband filter circuit, the current commutated mixer stage 630, and the attenuation stage 640. Fig. 7A An exemplary embodiment of the replica bias circuit 674 is discussed.

[0116] In some embodiments, mixing and attenuation functions are implemented at the same level in the stacked structure of the current-mode RF output stage 615, wherein the current-commutated mixer stage 630 is configured to up-convert the quadrature baseband signal to the RF signal, and wherein the current-commutated mixer stage 630 and the attenuation stage 640 operate in conjunction to attenuate the RF signal using a current-shunt attenuation scheme. For example, in some embodiments, the current-commutated mixer stage 630 includes a four-segment array of mixers (e.g., m segments for a differential I mixer and m segments for a differential Q mixer), and the attenuation stage 640 includes a parallel array of attenuator segments (e.g., n segments for I and Q signal paths), wherein the four-segment array of mixers and the attenuator segment array are connected to each current signal output node (e.g., I + ,I - , Q + , Q - ). When a given attenuator section is activated, the given attenuator section shunts a portion of the I / Q current signal to ground. To obtain a target attenuation factor, a target number of mixer sections in the current commutated mixer stage 630 are disabled and a target number of shunt attenuator sections in the attenuation stage 640 are enabled, where the attenuation factor is determined as a ratio of the number of active mixer sections to the number of active shunt attenuator sections.

[0117] The LO signal output driver circuit 680 is configured to apply a voltage signal to the gate terminal of the LO switch transistor of the mixer stage 4 so as to selectively activate and deactivate the mixer stage 4 as needed to achieve a target attenuation factor. Figure 6 Schematically shown, the LO signal output driver circuit 680 receives the control signal EN[1:m] and the complementary orthogonal LO signals LO_I, LO_Q, and And, it is from, for example, the LO signal generator circuit 170 ( Figure 1 ) is generated and output. In some embodiments, the LO signal output driver circuit 680 includes (i) a first set of m buffers that drive m versions of the LO signal (e.g., LO_I[1:m]), (ii) a first set of m buffers that drive m versions of the LO signal LO_I (e.g., [1:m]), (iii) a third set of m buffers driving m versions of the LO signal LO_Q (e.g., LO_Q[1:m]), and (ii) driving the LO signal m versions of (for example, [1:m]) of the fourth set of m buffers.

[0118] As explained in further detail below, the LO signal generated by the LO signal output driver circuit 680 may include an LO switch signal applied to the gate terminals of the mixer quad segments to enable (activate) the mixer quad segments for the mixing function and a DC voltage signal (e.g., a logic "1" voltage level) applied to the gate terminals of the mixer quad segments to select the mixer quad segments to be disabled (deactivated) to achieve the target attenuation factor. The control signal EN[1:m] specifies which mixer quad segments of the differential I and Q mixers are driven with the LO switch signal to perform the I / Q mixer function and which mixer quad segments of the I and Q mixers are driven with a static logic "1" voltage to disable such mixer quad segments to achieve the target attenuation factor.

[0119] like Figure 6 As further shown, attenuation stage 640 is controlled by complementary control signals ATTN[1:n] and The attenuation stage 640 includes n attenuation segments for the I signal path and n attenuation segments for the Q signal path. The control signals EN[1:m], ATTN[1:n] and By, for example, calibration control system 190 ( Figure 1 ) are generated in a coordinated manner to achieve a target attenuation factor. For example, the I and Q mixers can be disabled by driving all LO inputs to the mixer sections at a logic “1” level, and all parallel attenuation sections can be enabled to convert the baseband current signal (I + ,I - ,Q + ,Q - ) to ground (VSS) to implement the blanking function. The exemplary current steering method for implementing the blanking function is superior to conventional systems that implement voltage-gated blanking functions, which introduce signal loss and loading of the main signal.

[0120] On the other hand, in order to achieve the target attenuation factor, a certain number of mixer quad sections are configured so that a portion of the I / Q baseband signal current is up-converted by driving the input of such mixer quad section with an LO switch signal while driving the input of the remaining mixer quad section with a static voltage of a logic "1" level and activating a certain number of attenuation sections so as to shunt the rest of the I / Q baseband signal current to ground.

[0121] Fig. 7A and 7B Schematically illustrates an RF signal generator system according to another exemplary embodiment of the present invention, which includes a current mode RF output stack configured to operate at a reduced supply voltage. In particular, Fig. 7A and 7BSchematically shows the Figure 6 The architecture of the RF signal generator system 600 is the RF signal generator system 700, but wherein Fig. 7A and 7B Details of an exemplary circuit implementation of the current commutated mixer stage 730, the attenuation stage 740, and the replica bias circuit 774 are shown. Figure 6 In an exemplary embodiment, the RF signal generator system 700 includes an RF output stage architecture in which a current commutated mixer stage 730 and an attenuation stage 740 are placed at the same level of the output stack to eliminate one stack level in the RF output stage, thereby improving headroom and allowing the use of a lower supply voltage VDD.

[0122] The current commutated mixer stage 730 includes a differential I mixer 730-1 and a differential Q mixer 730-2, wherein the differential I mixer 730-1 includes a plurality of mixer quad sections 730-1[1:m] (e.g., m mixer quad segments), wherein the m mixer quad segments 730-1[1:m] include corresponding instances of a first transistor 731[1:m], a second transistor 732[1:m], a third transistor 733[1:m], and a fourth transistor 734[1:m]. The differential Q mixer 730-2 includes a similar array of mixer quad sections. For example, Figure 7B An exemplary layout of a differential I mixer 730 - 1 and a differential Q mixer 730 - 2 is schematically shown, each mixer having an array of mixer quadrants, according to an exemplary embodiment of the present disclosure.

[0123] like Figure 7B As shown, the differential I mixer 730-1 includes m mixer quadruple sections 730[1], 730[2], ..., 730[m]. The first quadruple mixer section 730[1] includes four mixer transistors 731-1, 732-1, 733-1, and 734-1, the second quadruple mixer section 730[2] includes four mixer transistors 731-2, 732-2, 733-2, and 734-2, and the mth quadruple mixer section 730[m] includes four mixer transistors 731-m, 732-m, 733-m, and 734-m. As shown, each mixer quad section 730[1], 730[2], ..., 730[m] is coupled to the baseband current signal output nodes I+ and I- of the baseband signal input stage 620 and to the output node N of the current commutated mixer stage 730. OUT1 and N OUT2 .

[0124] Similarly, the differential Q mixer 730-2 includes m mixer quadruplet sections 735[1], 735[2], ..., 735[m]. The first mixer quadruplet section 735[1] includes four mixer transistors 736-1, 737-1, 738-1, and 739-1, the second mixer quadruplet section 735[2] includes four mixer transistors 736-2, 737-2, 738-2, and 739-2, and the mth mixer quadruplet section 735[m] includes four mixer transistors 736-m, 737-m, 738-m, and 739-m. As shown, each mixer quadruplet section 735[1], 735[2], ..., 735[m] is coupled to the baseband current signal output node Q of the baseband signal input stage 620. + and Q - , and coupled to the output node N of the current-commutated mixer stage 730 OUT1 and N OUT2 .

[0125] like Figure 7B As further shown, in the differential I mixer 730-1, the mixer quad section 730[1] includes a received LO signal LO_I[1] and The mixer quad section 730[2] includes a receiving LO signal LO_I[2] and The mixer quad section 730[m] includes a receiving LO signal LO_I[m] and Similarly, in differential Q mixer 730-2, mixer quad section 735[1] includes receiving LO signal LO_Q[1] and The mixer quad section 735[2] includes a receiving LO signal LO_Q[2] and The mixer quad section 735[m] includes a receiving LO signal LO_Q[m] and The input terminal.

[0126] As described above, the LO signal output driver circuit 680 ( Figure 6 ) is configured to generate an LO switch signal and / or a DC LO voltage that drives the complementary inputs of the corresponding mixer quad sections 730[1], 730[2], ..., 730[m] of the differential I mixer 730-1. and drives the complementary inputs of the corresponding mixer quad sections 735[1], 735[2], ..., 735[m] of the differential Q mixer 730-2 As described above, to implement the attenuation function, one or more of the mixer quads in the differential I mixer 730-1 and the differential Q mixer 730-2 may be disabled by applying a DC LO voltage of a logic "1" level (logic high) to the input of a given mixer quad. For example, to disable the first mixer quads 730[1] and 735[1] in the differential I and Q mixers 730-1 and 730-2, the LO signal output driver circuit 680 ( Figure 6 ) drives the complementary input of the first mixer quad segment 730 [1] with a DC logic high / high to turn off the four mixer transistors 731-1, 732-1, 733-1 and 734-1, and (ii) drive the complementary input of the first mixer quad segment 735[1] with a DC logic high / high To turn off the four mixer transistors 736-1, 737-1, 738-1 and 739-1.

[0127] Refer to Fig. 7A , the attenuation stage 740 includes a first array of attenuation segments 740-1 and a second array of attenuation segments 740-2, the first array of attenuation segments 740-1 includes a plurality of attenuation segments 740[1], ..., 740[n], wherein each attenuation segment includes a pair of shunt transistors. Specifically, the first attenuation segment 740[1] includes first and second shunt transistors 741-1 and 742-1, and the nth attenuation segment 740[n] includes first and second shunt transistors 741-n and 742-n, the first shunt transistors 741-1, ..., 741-n (collectively referred to as first shunt transistors 741) having a baseband current signal output node I coupled to the baseband signal input stage 620. + The first shunt transistors 741 and the second shunt transistors 742 in the attenuation sections 740[1], ..., 740[n] have a gate terminal that is selectively coupled to the positive power supply node through a corresponding switch S1 and selectively coupled to the negative power supply node through a corresponding switch S2.

[0128] Attenuation stage 740 is controlled by complementary control signals ATTN[1:n] and The complementary control signal is applied to the attenuation section 740-1 of the first array and the attenuation section 740-2 of the second array. Fig. 7A As schematically shown in FIG. 1 , the first set of switches S1 of the attenuation sections 740[1], ..., 740[n] are controlled by the corresponding control signals and the second set of switches S2 of the attenuation segments 740[1], ..., 740[n] are controlled by corresponding control signals ATTN[1] ..., ATTN[n]. In the exemplary configuration, by selectively activating all switches S1 (via control signals ) to connect the gate terminals of the first shunt transistor 741 and the second shunt transistor 742 in all attenuation sections 740[1], ..., 740[n] to the positive power supply node, thereby turning off the first shunt transistor 741 and the second shunt transistor 742, thereby disabling all attenuation sections 740[1], ..., 740[n].

[0129] On the other hand, to implement the attenuation function, a given attenuation segment may be selectively enabled by deactivating switch S1 and activating switch S2 coupled to the gate terminals of the first and second shunt transistors 741 and 742 of the given attenuation segment. For example, to enable the first attenuation segment 740[1], the control signal ATTN[1] may be set to “close” switch S2 coupled to the gate terminals of the first and second shunt transistors 741-1 and 742-1, and the complementary signal The first attenuation segment 740[1] is de-asserted to “turn on” the switch S1 coupled to the gate terminals of the first and second shunt transistors 741-1 and 742-1. In this configuration, the gate terminals of the first and second shunt transistors 741-1 and 742-1 are coupled to ground (VSS), which turns on the first and second shunt transistors 741-1 and 742-1. When enabled, the first attenuation segment 740[1] converts the baseband signal current I + and I - A portion of the current is shunted to ground.

[0130] Although Fig. 7A The attenuation segment 740-2 of the second array is not specifically shown, but it should be noted that the attenuation segment 740-2 of the second array has the same configuration as the attenuation segment 740-1 of the first array, except that the first and second shunt transistors in the attenuation segment 740-2 of the second array will have a first transistor coupled to the corresponding baseband current signal output node Q + and Q - The first and second arrays of attenuation segments 740-1 and 740-2 have the same number n of attenuation segments, and in operation, the first and second arrays of attenuation segments 740-1 and 740-2 will have the same number of attenuation segments enabled and disabled at a given time to ensure that the same amount of attenuation is applied equally to the I and Q phases (thereby preventing imbalance of the I and Q signals).

[0131] Fig. 7AThe replica bias circuit 774 shown in FIG. 7 is similar to the replica bias circuit discussed above in that the replica bias circuit 774 includes (i) a circuit configured to generate a bias current having an amplitude α*I2 (where I2 represents Fig. 7A The invention also provides for the present invention to provide a plurality of baseband filter circuits, namely, (i) a replica current source 780 (e.g., a current mirror) corresponding to the desired bias current of the current-mode RF output stage of the present invention, (ii) a replica transistor 782 corresponding to the input transistor of the baseband signal input stage 620, and (iii) a baseband filter replica circuit 784 which includes replica devices and replica topologies corresponding to devices and types of single-ended voltage-mode baseband filter circuits utilized in the voltage-mode baseband filter stage 610.

[0132] The replica bias circuit 774 further includes replica transistors 786[1:m] corresponding to the mixer transistors in the array of the mixer quadrants of the differential I and Q mixers 730-1 and 730-2, and further, the replica bias circuit 774 includes an array of replica transistors 788[1:n] corresponding to the shunt transistors in the attenuation sections of the first and second arrays of attenuation sections 740-1 and 740-2, the array of replica transistors 786[1:m] being used for the respective voltages V1[1:m] of the mixer transistors. The array of replica transistors 788[1:n] being provided by the respective voltages V2[1:n]. In the replica bias circuit, control voltages V1[1:m] and V2[1:n] are coordinated with control signals that activate / deactivate the mixer quad and attenuation sections so that the total number of on (enabled) transistors in the array of replica transistors 786[1:m] and the corresponding number of on (enabled) mixer quad and attenuation sections in the array of replica transistors 788[1:n] match those in the primary functional circuit. In addition, as with the other replica bias circuits discussed above, the output amplitude can be varied by coarse control of the segmented driver stages and / or using fine control of the current entering the replica circuit.

[0133] Next, Figure 8 Schematically illustrates an RF signal generator system 800 according to another exemplary embodiment of the present invention, which includes an RF output stack configured to operate at a reduced supply voltage. More specifically, the RF signal generator system 800 includes a voltage mode baseband filter stage 810 and an RF output stage 815, the latter including an RF signal input stage 820, a voltage mode mixer stage 830, an attenuation stage 840, an output transformer stage 850, a first DC offset compensation DAC 860 and a second DC offset compensation DAC 862. The RF signal generator system 800 further includes a regulation system 870, which includes a voltage regulator circuit 872 and a replica bias circuit 874.

[0134] The RF signal generator system 800 is similar to the above-described exemplary embodiments, except that a voltage-mode mixer stage 830 is disposed between a voltage-mode baseband filter stage 810 and an RF signal input stage 820. The voltage-mode baseband filter stage 810 includes a plurality of single-ended voltage-mode baseband filter circuits 810-1, 810-2, 810-3, and 810-4 that output corresponding filtered baseband voltage signals I(t), Q(t) and The voltage-mode mixer stage 830 is configured to receive the filtered baseband voltage signal I(t), Q(t) and and complementary quadrature LO signal LO_I, LO_Q and The mixing operation is performed using voltage-mode differential I and Q mixers to generate and output complementary in-phase RF signals RF_I and and complementary quadrature phase RF signals RF_Q and

[0135] The RF signal input stage 820 includes a first differential transistor pair 820-1, which includes transistors for receiving the in-phase RF signals RF_I and The RF signal input stage 820 includes a second differential transistor pair 820-2, which includes transistors 821 and 822 having gate terminals for receiving quadrature phase RF signals RF_Q and RF_Q_Q, respectively. The gate terminals of the input transistors 823 and 824 are connected to the RF signal input stage 820. The RF signal input stage 820 generates an RF current signal applied to the attenuation stage 840. The attenuation stage 840 and the output transformer stage 850 perform the same as above. Figure 2B The attenuation stage 240 and the output transformer stage 250 discussed above function similarly. The exemplary RF output stage 815 is configured to operate at a lower VDD_RF supply voltage by placing the voltage mode mixer stage 830 and the RF signal input stage 820 at the same level in the stacked structure of the RF output stage 815, which effectively eliminates one level of transistors in the stack of the RF output stage 815 to provide additional headroom for utilizing the lower VDD supply voltage.

[0136] The voltage-mode baseband filter stage 810 includes a plurality of single-ended voltage-mode baseband filter circuits 810-1, 810-2, 810-3, and 810-4, which may be used, for example, Figures 3A-3F , or any of the exemplary baseband filter circuits shown in FIG. Figure 8 As shown, the voltage mode baseband filter circuit 810-1 includes an input stage 812 and a voltage mode baseband filter circuit 814, which are connected to the input stage 812 and the voltage mode baseband filter circuit 814. Figures 3A-3F Like elements shown operate in the same or similar manner.

[0137] In addition, the voltage-mode baseband filter circuit 810-1 includes a DC offset compensation DAC 816, which is configured to inject a DC compensation current into the input node N1 in conjunction with the DC offset compensation DACs 860 and 862 to correct the DC offset. As described above, the DC offset is determined by the differential current signal I + and I - The differential current signal Q + and Q - A static asymmetry occurs between Figure 8 In an exemplary embodiment of the present invention, DC offset cancellation is performed at different points (e.g., two different points) in the circuit architecture, which helps to cancel the range and resolution of the offset voltage. The DC offset compensation is configured to minimize the offset between the I+ and I- channels and minimize the Q + and Q - The channels are offset from each other such that spectral leakage at the LO frequency (eg, output signal at the LO frequency) is minimized.

[0138] Adjusting system 870 to match, for example, Figure 4 , 6 7A. For example, in some embodiments, the replica bias circuit 874 may use, for example, Figure 4 or Figure 5B , but without the replica mixer transistor 434.

[0139] Next, Fig. 9 Schematically shows an RF signal generator system 900 according to another exemplary embodiment of the present invention. The RF signal generator system 900 includes Figure 2A and 2B , except that the RF signal generator system 900 includes a regulation system 910 based on current regulation rather than voltage regulation. Specifically, the regulation system 910 includes a current source 912 (e.g., a current mirror 912) coupled between a positive power supply node VDD and a regulated node N Reg and is configured to adjust the regulated node N to which the source nodes of the baseband input transistors 221, 222, 223 and 224 are commonly connected. Reg In this regard, as opposed to utilizing an LDO voltage regulator and a replica bias circuit as in the exemplary embodiment discussed above, a current source 912 is used to generate a voltage level injected into the regulated node N Reg The fixed current I2 in is used to bias the current mode RF output stage 215.

[0140] In some embodiments, the RF signal generator system 900 includes a voltage mode baseband filter stage (eg, Figure 2A ), which can be used, for example Figures 3A-3F The single-ended voltage-mode baseband filter circuits shown in FIG. 1 are implemented by any of the single-ended voltage-mode baseband filter circuits shown in FIG. 1 , wherein the voltage-mode baseband filter circuit has an output terminal coupled to the respective gate terminals of the input transistors 221, 222, 223, and 224 of the baseband input stage 220. In operation, the current source 912 generates a fixed quiescent current that forces the DC V of the baseband input transistors 221, 222, 223, and 224 to remain constant despite variations in the VDD supply voltage. GS The bias voltage is at an appropriate level so that each of the individual baseband input transistors 221, 222, 223, and 224 conducts a current corresponding to its share of the fixed quiescent current I2. Reg If the voltage on the baseband input transistors 221, 222, 223 and 224 is too low, the total current flowing through the baseband input transistors 221, 222, 223 and 224 will be less than I2, which will naturally lead to the regulated node N Reg The voltage on the baseband input transistors 221, 222, 223 and 224 increases until the total current flowing through the baseband input transistors 221, 222, 223 and 224 matches the fixed quiescent current I2 generated by the current source 912. As a result, the DC V of each baseband input transistor 221, 222, 223 and 224 GS The bias voltage will stabilize to the appropriate V GS values ​​to produce a total appropriate quiescent current to match the fixed quiescent current I2.

[0141] It should be appreciated that the exemplary RF signal generation system as described herein is configured to operate at relatively low supply voltages and low power consumption (e.g., in the milliwatt range), which allows the RF signal generation system to be implemented using cryogenic electronics for quantum computing applications and other applications or systems that operate at cryogenic temperatures. For example, in the context of a quantum computing system implementing superconducting qubits and other components, the exemplary RF signal generation system as discussed herein can be implemented as an AWG system configured to generate RF control pulses to control superconducting qubits to perform high-fidelity qubit gate operations (e.g., single-qubit gate operations, entangled gate operations, etc.).

[0142] For example, Fig.10A quantum computing system 1000 is schematically shown that implements an arbitrary waveform generator system and calibration circuit according to an exemplary embodiment of the present disclosure. The quantum computing system 1000 includes an arbitrary waveform generator system 1002 (or AWG system 1002) and a quantum processor 1004. The quantum processor 1004 includes a plurality (N) of superconducting qubits 1006-1, ..., 1006-N. These superconducting qubits 1006-1, ..., 1006-N may include superconducting transmon qubits, superconducting fluxonium qubits, superconducting multimode qubits, and other types of superconducting qubits, or a combination of different types of superconducting qubits, which are suitable for a given application. Furthermore, in some embodiments, quantum processor 1004 includes a coupler circuit (e.g., a passive coupler circuit and / or an active coupler circuit), wherein a given coupler circuit is configured to couple a pair of superconducting qubits to implement an entangled gate operation (e.g., a two-qubit gate operation).

[0143] Quantum processor 1004 also includes a plurality of control lines (e.g., transmission line resonators), including but not limited to qubit drive lines, flux bias lines, state readout lines, and active coupler drive lines. In some embodiments, the qubit drive lines are coupled (e.g., capacitively coupled) to corresponding superconducting qubits in superconducting qubits 1006-1, ..., 1006-n, and the qubit drive lines are configured to apply control pulses (generated by AWG system 1002) to the corresponding superconducting qubits 1006-1, ..., 1006-n to independently change the state of the corresponding superconducting qubits (e.g., single-qubit gate operations), for example, to change the state of a given superconducting qubit to be in, for example, a ground state |0>, an excited state |1>, or a superposition state. As is known in the art, the state of a superconducting qubit can be changed by applying a microwave control pulse having a transition frequency (denoted as f) equal to that of the qubit. 01 ), wherein the transition frequency f01 corresponds to an energy difference between the ground state |0> and the excited state |1> of the qubit. In some embodiments, superconducting qubits 1006-1, ..., 1006-n are configured to have different operating frequencies (transition frequencies) such that the transition frequencies of adjacent qubits are detuned.

[0144] The state readout lines are coupled to respective ones of the superconducting qubits 1006-1, ..., 1006-n to read the state of the superconducting qubits using known techniques (e.g., dispersion readout). In embodiments where the superconducting qubits include frequency tunable qubits (e.g., flux tunable transport qubits or flux qubits, etc.), the flux bias control lines will be coupled (e.g., inductively coupled) to the corresponding superconducting qubits to apply flux bias control signals to the tuning structure of the superconducting qubits to tune the operating frequency of the tunable qubits as required for a given application. Additionally, for active coupler circuits, the coupler drive lines will be coupled (e.g., capacitively coupled) to respective coupler circuits, each of which will have an operating frequency or transition frequency. A given coupler circuit will be driven by a control pulse generated by the AWG system 1002 or some other pulse signal generator to achieve exchange coupling between superconducting qubits coupled through the given coupler circuit and achieve a two-qubit gate operation.

[0145] like Fig.10 As shown in FIG. 1 , an AWG system 1002 includes a multi-channel AWG framework including a plurality of AWG channels 1002-1, ..., 1002-c. AWG channels 1002-1, ..., 1002-c are configured to generate control pulses applied to qubit drive lines to control corresponding superconducting qubits in superconducting qubits 1006-1, ..., 1006-n.

[0146] AWG channels 1002-1, ..., 1002-c each include a respective control pulse envelope generator 1010, a DAC stage 1020, a filter stage 1030, an I / Q mixer stage 1040, an amplifier / attenuator stage 1050, a matching network 1060, an LO signal generator circuit 1070, and an LO signal output driver circuit 1080. The control pulse envelope generator 1010 is configured to implement a pulse shaping technique to generate RF control pulses having a desired control pulse envelope shape (e.g., Gaussian pulses, cosine pulses (e.g., sum of half cosines), hyperbolic secant pulses, etc.) that are applied to superconducting qubits or active qubit coupler circuits to perform single qubit gate operations, entangled gate operations, etc. In essence, this pulse shaping technique suppresses / reduces transients associated with turning on and off control pulses. In addition, pulse shaping techniques include DRAG (derivative removal of adiabatic heat) correction pulses, which can be used in conjunction with shaped pulses (such as Gaussian pulses, cosine pulses, or hyperbolic secant pulses) to further suppress unwanted state transitions while maintaining the same pulse envelope area (or integral of the pulse envelope).

[0147] In each AWG channel of AWG system 1002, the digital control pulse envelope signal (digital I and Q components) is converted to an analog control pulse envelope signal (analog baseband I / Q signal), and an I / Q mixer stage 1040 modulates the quadrature LO signal using the baseband I / Q signal by performing, for example, SSB modulation as described above, to generate a modulated signal in the form of an RF control pulse, which is applied, for example, to a qubit driver line to control a given qubit. The functions of the various stages 1020, 1030, 1050, 1060, 1070, and 1080 are similar to Figure 1 , and the corresponding stages in FIG2 , etc., and their details will not be repeated.

[0148] like Fig.10 As further shown in FIG. 1 , in some embodiments, each AWG channel 1002-1, ..., 1002-c of the AWG system 1002 includes a dedicated calibration circuit 1090-1, ..., 1090-c implemented on a chip with the AWG system 1002. As described above, the calibration circuits 1090-1, ..., 1090-c are configured to calibrate the corresponding AWG channels 1002-1, ..., 1002-c of the AWG system 1002 for different operating modes. The calibration circuits 1090-1, ..., 1090-c include hardware control and logic circuits (e.g., DC offset compensation DACs, control logic circuits for generating control signals, etc.) as described above. In some embodiments, the calibration circuits 1090-1, ..., 1090-c are controlled by software running on a computing platform that controls the quantum computing system 1000.

[0149] For example, Fig.11 A quantum computing system according to another exemplary embodiment of the present disclosure is schematically shown. In particular, Fig.11 Schematically illustrated is a quantum computing system 1100 that includes a quantum computing platform 1110, a control system 1120, and a quantum processor 1130. In some embodiments, the quantum computing platform 1110 implements a software control program, such as a calibration control process 1112, which performs functions such as configuring the AWG system, controlling execution of high-level functions of the calibration process, and the like.

[0150] In addition, the quantum computing platform 1110 performs calibration procedures that are periodically performed on a quantum system such as a quantum processor to calibrate various quantum elements such as a readout resonator, a data qubit, and a coupler circuit to achieve high-fidelity gate operations (e.g., single-qubit gate operations and entangled gate operations). For example, various types of in-situ calibration procedures are periodically performed to, for example, determine the resonant frequency of the readout resonator, determine the transition frequency of the qubit, determine the coherence time (T1) of the qubit (where the coherence time T1 of a given qubit represents the time it takes for the qubit state to decay from an excited state to a ground state), determine the transverse relaxation time (T2) (or dephasing time) of the qubit, calibrate the control pulses applied to the qubit to perform single-qubit gate operations, calibrate the control pulses applied to the active coupler circuit to perform entangled gate operations, and so on.

[0151] In some embodiments, the control system 1120 includes a multi-channel arbitrary waveform generator 1122 and a qubit readout control system 1124 (wherein, Fig.10 An exemplary AWG system 1002 that may be embedded in a control system 1120 is schematically shown.) The quantum processor 1130 includes a solid-state semiconductor chip having a superconducting qubit array 1132 and a network 1134 of qubit drive lines, coupler drive lines, and qubit state readout lines, as well as other circuit QED components that may be required for a given application or quantum system configuration.

[0152] In some embodiments, the control system 1120 and the quantum processor 1130 are arranged in a dilution refrigeration system 1140, which can generate cryogenic temperatures sufficient to operate multiple components of the control system 1120 for quantum computing applications. For example, the quantum processor 1130 may need to be cooled to near absolute zero, such as 10-15 millikelvin (mK), to allow superconducting qubits to exhibit quantum behavior. In some embodiments, the dilution refrigeration system 1140 includes a multi-stage dilution refrigerator, in which components of the control system 1120 can be maintained at different cryogenic temperatures as needed. For example, while the quantum processor 1130 may need to be cooled to, for example, 10-15 mK, the circuit components of the control system 1120 may operate at low temperatures above 10-15 mK (e.g., low temperatures in the range of 3K-4K), depending on the configuration of the quantum computing system.

[0153] In some embodiments, superconducting qubit array 1132 includes a plurality of superconducting transmission qubits and superconducting tunable coupling qubits, wherein each pair of superconducting qubits is connected by a corresponding superconducting qubit coupler using techniques as discussed herein. A network 1134 of qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, etc., is configured to apply microwave control signals to superconducting qubits and coupler circuits in superconducting qubit array 1132 to perform various types of gate operations, such as single gate operations, entangled gate operations, etc., and to read the quantum state of the superconducting qubits. The network 1134 of qubit drive lines, flux bias lines, coupler drive lines, and qubit state readout lines, etc., is connected to control system 1120 via an appropriate hardware input / output (I / O) interface, which connects I / O signals between control system 1120 and quantum processor 1130. For example, a hardware I / O interface may include various types of hardware and components, such as RF cables, wiring, RF elements, optical fibers, heat exchangers, filters, amplifiers, isolators, and the like.

[0154] The quantum computing platform 1110 includes a software and hardware platform, which includes various software layers configured to perform various functions, including but not limited to, generating and implementing various quantum applications using a suitable quantum programming language, configuring and implementing various quantum gate operations, compiling quantum programs into quantum assembly languages, implementing and utilizing a suitable quantum instruction set architecture (ISA), performing calibration operations to calibrate quantum circuit elements and gate operations, etc. In addition, the quantum computing platform 1110 includes a hardware architecture of processors, memories, etc., which is configured to control the execution of quantum applications and interface with the control system 1120 to (i) generate digital control signals that are converted by the control system 1120 into analog microwave control signals to control the operation of the quantum processor 1130 when executing a given quantum application, and (ii) obtain and process digital signals received from the control system 1120, which digital signals represent processing results generated by the quantum processor 1130 when performing different gate operations for a given quantum application. In some exemplary embodiments, any suitable computing system architecture (e.g., such as Fig.12 The invention relates to a quantum computing platform 1110 of a quantum computing system 1100 implemented by a computer system architecture configured to implement a method of supporting quantum computing operations by executing computer-readable program instructions, which are contained on a computer program product, and which includes a computer-readable storage medium (or medium) having such computer-readable program instructions thereon, for causing a processor to execute a control method as discussed herein.

[0155] Various aspects of the present disclosure are described by narrative text, flow charts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flow chart, depending on the technology involved, the operations may be performed in an order different from the order shown in a given flow chart. For example, again depending on the technology involved, two operations shown in consecutive flow chart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0156] Computer program product embodiments ("CPP embodiments" or "CPP") are terms used in this disclosure to describe any collection of one or more storage media (also referred to as "media") collectively included in a collection of one or more storage devices that collectively include machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. Without limitation, a computer-readable storage medium may be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), static random access memories (SRAM), compact disk read-only memories (CD-ROMs), digital versatile disks (DVDs), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or pits / land formed in a major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, should not be construed as storing in the form of transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, light pulses through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As will be appreciated by those skilled in the art, data is typically moved at certain occasional points in time during normal operation of the storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device transitory because the data is not transitory while it is stored.

[0157] The computing environment 1200 includes an example of an environment for executing at least some of the computer code involved in performing the methods of the present invention, such as computer code for controlling, for example, Figure 119 and the calibration process control code 1226 of the calibration control system 190 and the calibration circuit 1090-1, ..., 1090-c, etc. of FIG. 19. In addition to the block 1226, the computing environment 1200 includes, for example, a computer 1201, a wide area network (WAN) 1202, an end user device (EUD) 1203, a remote server 1204, a public cloud 1205, and a private cloud 1206. In this embodiment, the computer 1201 includes a processor set 1210 (including a processing circuit 1220 and a cache 1221), a communication architecture 1211, a volatile memory 1212, a permanent storage device 1213 (including an operating system 1222 and a block 1226, as described above), a peripheral device set 1214 (including a user interface (UI), a device set 1223, a storage device 1224, and an Internet of Things (IoT) sensor set 1225) and a network module 1215. The remote server 1204 includes a remote database 1230. The public cloud 1205 includes a gateway 1240 , a cloud coordination module 1241 , a host physical machine set 1242 , a virtual machine set 1243 , and a container set 1244 .

[0158] Computer 1201 may take the form of a desktop computer, laptop computer, tablet computer, smart phone, smart watch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or developed in the future that is capable of running programs, accessing a network, or querying a database such as remote database 1230. As is well known in the art of computer technology, and depending on the technology, the performance of computer-implemented methods may be distributed among multiple computers and / or among multiple locations. On the other hand, in this presentation of computing environment 1200, the detailed discussion focuses on a single computer, particularly computer 1201, to keep the presentation as simple as possible. Computer 1201 may be located in the cloud, even though it is not necessarily located in the cloud. Fig.12 12 is not shown in the cloud, on the other hand, computer 1201 need not be in the cloud unless it can be indicated with certainty to any extent.

[0159] Processor set 1210 includes one or more computer processors of any type known now or to be developed in the future. Processing circuit 1220 may be distributed over multiple packages, such as multiple coordinated integrated circuit chips. Processing circuit 1220 may implement multiple processor threads and / or multiple processor cores. Cache 1221 is a memory located in the processor chip package and is typically used for data or code that should be quickly accessed by threads or cores running on processor set 1210. Cache memory is typically organized into multiple levels based on relative proximity to the processing circuit. Alternatively, some or all of the caches of the processor set may be located "off chip". In some computing environments, processor set 1210 may be designed to work with qubits and perform quantum computing.

[0160] Computer readable program instructions are typically loaded onto the computer 1201 to cause the processor set 1210 of the computer 1201 to perform a series of operating steps to implement a computer-implemented method, so that the instructions so executed will instantiate the method specified in the flow chart and / or the narrative description of the computer-implemented method included in this document (collectively referred to as the "method of the present invention"). These computer readable program instructions are stored in various types of computer readable storage media, such as cache 1221 and other storage media discussed below. The program instructions and related data are accessed by the processor set 1210 to control and direct the execution of the method of the present invention. In the computing environment 1200, in box 1226, at least some of the instructions for performing the method of the present invention may be stored in a permanent storage device 1213.

[0161] The communications fabric 1211 is the signaling pathways that allow the various components of the computer 1201 to communicate with each other. Typically, the structure is made up of switches and conductive pathways, such as those that make up a bus, a bridge, physical input / output ports, etc. Other types of signal communication pathways may be used, such as fiber optic communication pathways and / or wireless communication pathways.

[0162] The volatile memory 1212 is any type of volatile memory now known or developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory is characterized by random access, but this is not required unless expressly stated. In the computer 1201, the volatile memory 1212 is located in a single package and is internal to the computer 1201, but alternatively or additionally, the volatile memory can be distributed over multiple packages and / or located external to the computer 1201.

[0163] Permanent memory 1213 is any form of non-volatile memory for computers known now or developed in the future. The non-volatility of the memory means that the stored data is maintained regardless of whether the computer 1201 and / or the permanent memory 1213 are powered directly. Permanent memory 1213 can be a read-only memory (ROM), but usually at least a portion of permanent memory allows the writing of data, the deletion of data, and the rewriting of data. Some common forms of persistent storage include disks and solid-state storage devices. Operating system 1222 can take several forms, such as various known proprietary operating systems using kernels or operating systems of open source portable operating system interface types. The code included in box 1226 generally includes at least some of the computer codes involved in the execution of the method of the present invention.

[0164] The peripheral device set 1214 includes a peripheral device set of the computer 1201. The data communication connection between the peripheral device and other components of the computer 1201 can be implemented in various ways, such as a Bluetooth connection, a near field communication (NFC) connection, a connection made by a cable (such as a universal serial bus (USB) type cable), a plug-in type connection (e.g., a secure digital (SD) card), a connection made through a local area communication network, and even a connection made through a wide area network such as the Internet. In various embodiments, the UI device set 1223 may include components such as display screens, speakers, microphones, wearable devices (such as goggles and smart watches), keyboards, mice, printers, touchpads, game controllers, and tactile devices. The memory 1224 is an external memory, such as an external hard drive, or a pluggable memory, such as an SD card. The storage 1224 can be persistent and / or volatile. In some embodiments, the storage 1224 can take the form of a quantum computing storage device for storing data in the form of quantum bits. In embodiments where the computer 1201 needs to have a large amount of storage (e.g., where the computer 1201 locally stores and manages a large database), the storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 1225 consists of sensors that can be used in IoT applications. For example, one sensor may be a thermometer, while another sensor may be a motion detector.

[0165] The network module 1215 is a collection of computer software, hardware, and firmware that allows the computer 1201 to communicate with other computers via the WAN 1202. The network module 1215 may include hardware, such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data transmitted over a communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control function and the network forwarding function of the network module 1215 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software defined networks (SDN)), the control function and forwarding function of the network module 1215 are executed on physically separated devices, so that the control function manages several different network hardware devices. Computer-readable program instructions for executing the method of the present invention can be downloaded to the computer 1201 from an external computer or an external storage device typically via a network adapter card or a network interface included in the network module 1215.

[0166] WAN 1202 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances by any technology now known or developed in the future for transmitting computer data. In some embodiments, a WAN may be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area, such as a Wi-Fi network. A WAN and / or LAN typically includes computer hardware, such as copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers.

[0167] End-user device (EUD) 1203 is any computer system used and controlled by an end-user (e.g., a customer of an enterprise operating computer 1201), and may take any form discussed above in conjunction with computer 1201. EUD 1203 typically receives useful and useful data from the operation of computer 1201. For example, in the hypothetical case where computer 1201 is designed to provide recommendations to an end-user, the recommendations would typically be transmitted from network module 1215 of computer 1201 to EUD 1203 via WAN 1202. In this manner, EUD 1203 may display or otherwise present the recommendations to the end-user. In some embodiments, EUD 1203 may be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0168] Remote server 1204 is any computer system that provides at least some data and / or functionality to computer 1201. Remote server 1204 may be controlled and used by the same entity that operates computer 1201. Remote server 1204 represents a machine that collects and stores useful and useful data for use by other computers such as computer 1201. For example, in the hypothetical case where computer 1201 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 1201 from remote database 1230 of remote server 1204.

[0169] The public cloud 1205 is any computer system that can be used by multiple entities, which provides on-demand availability of computer system resources and / or other computer capabilities, especially data storage (cloud storage) and computing capabilities, without the need for direct active management by users. Cloud computing generally uses the sharing of resources to achieve consistency and economy of scale. The direct and active management of the computing resources of the public cloud 1205 is performed by the computer hardware and / or software of the cloud coordination module 1241. The computing resources provided by the public cloud 1205 are generally implemented by virtual computing environments running on various computers that constitute the computers of the host physical machine set 1242, which is the entire domain of physical computers in the public cloud 1205 and / or available for the public cloud. Virtual computing environments (VCEs) generally take the form of virtual machines from the virtual machine set 1243 and / or containers from the container set 1244. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after instantiation of the VCEs. The cloud orchestration module 1241 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages active instantiations of VCE deployments. The gateway 1240 is a collection of computer software, hardware, and firmware that allows the public cloud 1205 to communicate over the WAN 1202 .

[0170] Some further explanation of a virtualized computing environment (VCE) will now be provided. A VCE can be stored as an "image". A new active instance of the VCE can be instantiated from the image. Two common types of VCEs are virtual machines and containers. Containers are VCEs that use operating system-level virtualization. This refers to an operating system feature in which the kernel allows the existence of multiple isolated user space instances, called containers. From the perspective of the programs running in them, these isolated user space instances typically behave like actual computers. Computer programs running on a normal operating system can utilize all of the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices assigned to the container, a feature known as containerization.

[0171] Private cloud 1206 is similar to public cloud 1205, except that the computing resources are only available to a single enterprise. Although private cloud 1206 is depicted as communicating with WAN 1202, in other embodiments, the private cloud can be completely disconnected from the Internet and can only be accessed through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is tied together by standardized or proprietary technologies that enable coordination, management, and / or data / application portability between the multiple constituent clouds. In this embodiment, public cloud 1205 and private cloud 1206 are both part of a larger hybrid cloud.

[0172] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: a voltage mode filter circuit configured to generate a voltage signal at an output terminal thereof; a current mode output circuit comprising an input transistor including a gate terminal coupled to the output terminal of the voltage mode filter circuit and a source terminal coupled to a regulated node; as well as A regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage of the input transistor to generate a current for biasing the current mode output circuit.

2. The apparatus of claim 1, wherein the voltage mode filter circuit and the current mode output circuit comprise an analog signal processing path of a radio frequency signal generator.

3. The apparatus of any preceding claim, wherein the voltage mode filter circuit comprises an analog Sallen-Key filter circuit based on a unity gain source follower.

4. The apparatus according to any one of the preceding claims, wherein the regulating circuit comprises: a low dropout voltage regulator circuit configured to receive as inputs an unregulated supply voltage and a reference voltage and to generate a regulated supply voltage corresponding to the reference voltage at the regulated node; as well as A replica bias circuit is configured to generate the reference voltage based on replica devices and topology of the voltage mode filter circuit and the current mode output circuit.

5. The apparatus of any of the preceding claims, wherein the regulation circuit comprises a current source coupled to the regulated node and configured to generate a current that fixes an amount of current flowing through the input transistor to bias the current mode output circuit.

6. A system comprising: A radio frequency signal generator, wherein the radio frequency signal generator is configured to convert a baseband signal into a radio frequency signal, and the radio frequency signal generator comprises: a baseband filter stage comprising a voltage mode filter circuit configured to filter the baseband signal and generate a voltage signal at an output terminal of the voltage mode filter circuit; an output stage configured to generate and output the RF signal, the output stage comprising a plurality of current mode stages including a baseband input stage, wherein the baseband input stage comprises an input transistor including a gate terminal coupled to the output terminal of the voltage mode filter circuit and a source terminal coupled to a regulated node; and A regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage of the input transistor to generate a current for biasing the current mode stage of the output stage.

7. The system of claim 6, wherein the voltage mode filter circuit comprises an analog Sallen-Key filter circuit based on a unity gain source follower.

8. The system according to any one of claims 6 to 7, wherein the regulating circuit comprises: a low dropout voltage regulator circuit configured to receive as inputs an unregulated supply voltage and a reference voltage and to generate a regulated supply voltage corresponding to the reference voltage at the regulated node; as well as A replica bias circuit is configured to generate the reference voltage based on replica devices and topology of the baseband filter stage and the output stage.

9. The system of any one of claims 6 to 8, wherein the regulation circuit comprises a current source coupled to the regulated node and configured to generate a current that fixes an amount of current flowing through the input transistor to bias the current mode stage of the output stage.

10. The system of any one of claims 6 to 9, wherein the current mode stage of the output stage comprises a mixer stage having an input node coupled to an output node of the baseband input stage and an attenuation stage having an input node coupled to the output node of the mixer stage.

11. The system of any one of claims 6 to 10, wherein the current mode stage of the output stage comprises a mixer stage and an attenuation stage, wherein the mixer stage and the attenuation stage have a commonly connected input node connected to the output node of the baseband input stage, and wherein the output node of the attenuation stage is coupled to a negative supply node.

12. The system of claim 11, wherein: The mixer stage comprises a plurality of mixer sections; The attenuation stage includes a plurality of attenuation segments; selectively enabling or disabling, by a control system, the mixer sections and the attenuation sections to obtain a target attenuation factor based on a ratio of the number of enabled mixer sections to the number of enabled attenuation sections; as well as Each enabled attenuation segment is configured to shunt a portion of a baseband current signal output from the baseband input stage to the negative supply node.

13. A system comprising: a quantum processor comprising at least one superconducting qubit; An arbitrary waveform generator, the arbitrary waveform generator comprising at least one arbitrary waveform generator channel, the arbitrary waveform generator channel configured to convert a baseband signal into a radio frequency control pulse for controlling the at least one superconducting qubit, wherein the at least one arbitrary waveform generator channel comprises: a baseband filter stage comprising a voltage mode filter circuit configured to filter the baseband signal and generate a voltage signal at an output terminal of the voltage mode filter circuit; an output stage configured to generate and output the RF control pulses, the output stage comprising a plurality of current mode stages including a baseband input stage, wherein the baseband input stage comprises an input transistor including a gate terminal coupled to the output terminal of the voltage mode filter circuit and a source terminal coupled to a regulated node; and A regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage of the input transistor to generate a current for biasing the current mode stage of the output stage.

14. The system of claim 13, wherein the voltage mode filter circuit comprises a unity gain source follower based analog Sallen-Key filter circuit.

15. The system according to any one of claims 13 to 14, wherein the regulating circuit comprises: a low dropout voltage regulator circuit configured to receive as inputs an unregulated supply voltage and a reference voltage and to generate a regulated supply voltage corresponding to the reference voltage at the regulated node; as well as A replica bias circuit is configured to generate the reference voltage based on replica devices and topology of the baseband filter stage and the output stage.

16. The system of any one of claims 13 to 15, wherein the regulation circuit comprises a current source coupled to the regulated node and configured to generate a current that fixes an amount of current flowing through the input transistor to bias the current mode stage of the output stage.

17. The system of any one of claims 13 to 16, wherein the current mode stage of the output stage comprises a mixer stage having an input node coupled to an output node of the baseband input stage and an attenuation stage having an input node coupled to the output node of the mixer stage.

18. The system of any one of claims 13 to 17, wherein the current mode stage of the output stage comprises a mixer stage and an attenuation stage, wherein the mixer stage and the attenuation stage have a commonly connected input node connected to the output node of the baseband input stage, and wherein the output node of the attenuation stage is coupled to a negative supply node.

19. The system of claim 18, wherein: The mixer stage comprises a plurality of mixer sections; The attenuation stage includes a plurality of attenuation segments; selectively enabling or disabling, by a control system, the mixer sections and the attenuation sections to obtain a target attenuation factor based on a ratio of the number of enabled mixer sections to the number of enabled attenuation sections; as well as Each enabled attenuation segment is configured to shunt a portion of a baseband current signal output from the baseband input stage to the negative supply node.

20. A system comprising: A radio frequency signal generator, wherein the radio frequency signal generator is configured to convert a baseband signal into a radio frequency signal, and the radio frequency signal generator comprises: a baseband filter stage comprising a voltage mode filter circuit configured to filter the baseband signal and generate a voltage signal at an output terminal of the voltage mode filter circuit; a mixer stage, the mixer stage comprising a voltage-mode mixer circuit configured to convert the filtered baseband signal to the radio frequency signal; an output stage comprising a plurality of current mode stages including a radio frequency signal input stage, wherein the radio frequency signal input stage comprises an input transistor including a gate terminal coupled to the output terminal of the voltage mode mixer circuit and a source terminal coupled to a regulated node; and A regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage of the input transistor to generate a current for biasing the current mode stage of the output stage.

21. The system of claim 20, wherein the voltage mode filter circuit comprises a unity gain source follower based analog Sallen-Key filter circuit.

22. The system of any one of claims 20 to 21, wherein the regulating circuit comprises: a low dropout voltage regulator circuit configured to receive as inputs an unregulated supply voltage and a reference voltage and to generate a regulated supply voltage corresponding to the reference voltage at the regulated node; as well as A replica bias circuit is configured to generate the reference voltage based on replica devices and topology of the baseband filter stage and the output stage.

23. The system of any one of claims 20 to 22, wherein the regulation circuit comprises a current source coupled to the regulated node and configured to generate a current that fixes an amount of current flowing through the input transistor to bias the current mode stage of the output stage.

24. A method comprising: generating a voltage signal at an output terminal of a voltage mode filter circuit; applying the voltage signal to a gate terminal of an input transistor of a current mode output circuit, wherein the input transistor includes a source terminal coupled to a regulated node; as well as The voltage level on the regulated node is adjusted to maintain a constant gate-source bias voltage of the input transistor, thereby generating a current for biasing the current mode output circuit.

25. The method of claim 24, wherein adjusting the voltage level on the regulated node comprises one of: generating, by a low dropout voltage regulator circuit, a regulated supply voltage at the regulated node, the regulated supply voltage corresponding to a reference voltage generated by a replica bias circuit based on replica devices and topology of the baseband filter stage and the output stage; and A current is generated by a current source and applied to the regulated node to fix an amount of current flowing through the input transistor to bias the current mode output circuit.

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