Semiconductor device and preparation method thereof, memory and memory system

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a memory and a storage system, at least one crack surface guide structure extending along a second direction is arranged in a first cutting channel block, adjacent to a first device block in a first direction, of the semiconductor device, and the second direction intersects with the first direction. And the split surface guide structure comprises a first part and a second part which extend along the second direction, and the second part has higher split surface passing ability than the first part, so that when the chip is invisibly cut, the chip can be split according to the preset direction and the preset part.

Description

Semiconductor device and manufacturing method thereof, memory and storage system Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same, as well as a memory and a storage system. Background Art

[0002] A wafer undergoes three transformations before becoming a true semiconductor chip: first, the block-shaped ingot is cut into wafers; second, transistors are formed on the front of the wafer through a previous process; and finally, packaging, or cutting, is performed to transform the wafer into a complete semiconductor chip. The packaging process is a post-process, in which the wafer is cut into several hexahedral individual chips. This process of obtaining independent chips is called "singulating," while the process of sawing the wafer into independent rectangular blocks is called "die sawing." Recently, with the increasing integration of semiconductors, wafer thickness has become increasingly thinner, which has also brought considerable difficulty to the "singling" process.

[0003] The packaging process of 3D NAND chips is particularly challenging. As the number of storage array layers within 3D NAND chips increases exponentially, the problem of unnecessary cracks in the chips and resulting damage is becoming increasingly serious.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, as well as a memory and a storage system, which can solve the technical problem in the prior art that chips cannot be cracked in a specified direction during invisible cutting.

[0006] In one aspect, an embodiment of the present application provides a semiconductor device, comprising:

[0007] A first semiconductor structure, comprising a first device block and a first scribe line block adjacent to the first device block in a first direction;

[0008] The first cutting street block includes at least one crack surface guiding structure extending along a second direction, the second direction intersecting the first direction, and the crack surface guiding structure includes a first portion and a second portion extending along the second direction, and the second portion is more crack surface-passable than the first portion.

[0009] In some embodiments, the second portion comprises an air gap.

[0010] In some embodiments, the first portion includes two ends in the second direction, and the first portion includes a first curved surface bordering the second portion, and the first curved surface is concave toward the first portion relative to the two ends in the first direction.

[0011] In some embodiments, the first portion includes two end portions in the second direction, and the second portion includes a gap between the first portion and a virtual cross-section formed by the two end portions of the first portion.

[0012] In some embodiments, the first portion comprises a first material, and the first material comprises one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

[0013] In some embodiments, the first portion includes a first material, the second portion includes a second material, and the Young's modulus of the second material is smaller than the Young's modulus of the first material.

[0014] In some embodiments, the first material or the second material includes one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

[0015] In some embodiments, the first device block includes a first gate line isolation structure, the crack surface guide structure includes a second gate line isolation structure, the second gate line isolation structure includes the first portion and the second portion, and the width of the second gate line isolation structure in a cross section in the first direction is greater than the width of the first gate line isolation structure in the cross section.

[0016] In some embodiments, the first cutting road block includes a plurality of stacked structures formed by alternately stacking gate layers and interlayer insulating layers in the second direction, and a channel structure or a virtual channel structure located in the stacked structure and spaced apart from the second gate line isolation structure.

[0017] In some embodiments, the first cutting street block includes a plurality of the channel structures or virtual channel structures and a plurality of the second gate line isolation structures, and the plurality of channel structures or virtual channel structures are alternately spaced with the plurality of second gate line isolation structures in the first direction.

[0018] In some embodiments, the first cutting street block includes a first X cutting street block adjacent to the device block in the first direction, and a first Y cutting street block adjacent to the device block in a third direction, wherein the third direction intersects with the first direction; the crack surface guide structure includes a first X crack surface guide structure located on the first X cutting street block, and a first Y crack surface guide structure located on the first Y cutting street block.

[0019] In some embodiments, the split surface guiding structure includes a first end in the second direction and a retracted portion away from the first end, and a transverse cross-sectional area of ​​the split surface guiding structure in the first direction gradually expands from the retracted portion toward the first end.

[0020] In some embodiments, the semiconductor device further includes a second semiconductor structure, the second semiconductor structure includes a second device block and a second cutting street block, and the first device block and the second device block are stacked and bonded together in the second direction.

[0021] In some embodiments, the second scribe line block includes a silicon substrate.

[0022] In some embodiments, the crack surface guide structure includes a first end in the second direction and a retracted portion away from the end, and the lateral cross-sectional area of ​​the crack surface guide structure in the first direction gradually expands from the retracted portion toward the first end, and the first end is closer to the second cutting path block of the second semiconductor device relative to the retracted portion.

[0023] In some embodiments, the first cutting street block has a first thickness, the first device block has a second thickness, the second thickness is greater than the first thickness, and the back end surface of the first cutting street block facing away from the second cutting street block is concave relative to the end surface of the first device block on the same side as the back end surface.

[0024] On the other hand, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0025] Providing a first semiconductor structure, the first semiconductor structure comprising a first device block and a first scribe line block adjacent to the first device block in a first direction;

[0026] At least one crack surface guiding structure extending along the second direction is formed in the first cutting street structure. The second direction intersects the first direction, and the crack surface guiding structure includes a first portion and a second portion extending along the second direction. The second portion has a stronger crack surface passability than the first portion.

[0027] In some embodiments, the step of forming the crack guiding structure includes forming the first portion and forming the second portion within the first portion, wherein the second portion includes an air gap.

[0028] In some embodiments, the step of forming the crack guiding structure includes forming the first portion with a first material, and the first material includes one of polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

[0029] In some embodiments, the step of forming the crack guiding structure includes first forming the first portion with a first material, and then forming the second portion with a second material inside the first portion, wherein the Young's modulus of the second material is smaller than that of the first material.

[0030] In some embodiments, the step of forming the first portion with a first material includes forming the first portion with one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide, and the step of forming the second portion with a second material includes forming the second portion with one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

[0031] In some embodiments, the step of forming a crack surface guide structure includes forming a first gate line isolation structure in the first device block, and forming a second gate line isolation structure in the first cutting road block as the crack surface guide structure and including the first portion and the second portion, and the width of the second gate line isolation structure in a cross section in the first direction is set to be greater than the width of the first gate line isolation structure in the cross section.

[0032] In some embodiments, the step of forming the first cutting road block includes forming a plurality of stacked layers formed by alternating stacking of sacrificial dielectric layers and interlayer insulating layers in the second direction, and a channel structure or a virtual channel structure located in the stacked layer and spaced apart from a preset position of the second gate line isolation structure.

[0033] In some embodiments, the step of forming the crack surface guiding structure includes forming a plurality of second gate line isolation structures, and arranging the plurality of second gate line isolation structures spaced apart from the channel structure or the dummy channel structure in the first direction.

[0034] In some embodiments, the method further includes providing a second semiconductor structure, wherein the second semiconductor structure includes a second device block and a second scribe line block; and stacking and bonding the first device block and the second device block together in the second direction.

[0035] In some embodiments, the step of providing the second semiconductor structure includes providing a silicon substrate, and the second scribe line area includes the silicon substrate.

[0036] In some embodiments, the method also includes removing the end of the first cutting road block on the side facing away from the second cutting road block to form a first cutting road block with a thinned end face, and the thickness of the first cutting road block with a thinned end face in the second direction is less than the thickness of the first device block in the second direction.

[0037] On the other hand, an embodiment of the present application provides a memory, comprising:

[0038] A memory array, wherein the memory array includes the first semiconductor structure or the second semiconductor structure in the aforementioned semiconductor device,

[0039] A peripheral circuit includes the first semiconductor structure or the second semiconductor structure in the aforementioned semiconductor device.

[0040] In another aspect, an embodiment of the present application provides a storage system, comprising:

[0041] the aforementioned memory; and

[0042] A control device controls the operation of the memory.

[0043] The semiconductor device and its preparation method, as well as the memory and storage system disclosed in the embodiments of the present application are designed with a crack surface guiding structure on the cutting path, and two first and second parts with different cracking easiness are set in the crack surface guiding structure, and the second part has a stronger crack surface passability than the first part. Through such a configuration, during the stealth dicing before grinding (SDBG) process, the cracks in the cutting path block will preferentially pass through the weaker second part, avoiding the situation in the traditional solution where a large amount of metal located in the cutting path block cannot be disconnected, thereby improving the product cutting yield without increasing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of some embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] 1a and 1b are schematic cross-sectional views of a semiconductor device according to some embodiments of the present application;

[0046] 2a to 2c are schematic cross-sectional views of another semiconductor device according to some embodiments of the present application;

[0047] 3a and 3b are schematic diagrams showing the distribution of crack surface guiding structures in semiconductor devices according to some embodiments of the present application;

[0048] 4a and 4b are schematic cross-sectional views of another semiconductor device provided in some embodiments of the present application;

[0049] 5a and 5b are schematic flow charts of methods for manufacturing semiconductor devices according to some embodiments of the present application.

[0050] 6a to 6d are schematic structural diagrams corresponding to the processes shown in FIG. 5b in the method for preparing a semiconductor device provided in some embodiments of the present application.

[0051] FIG7 is a schematic block diagram of a memory provided in some embodiments of the present application.

[0052] FIG8 is a schematic block diagram of a storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0053] The specific structural and functional details disclosed herein are merely representative and are for the purpose of describing exemplary embodiments of the present application. However, the present application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0054] In the description of the present application, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variations thereof are intended to cover non-exclusive inclusions.

[0055] Furthermore, when the terms "first" and "second" are added to devices of the same type, they are only used to distinguish different devices of the same type and to facilitate the expression of relative positions. They do not imply sequential or fixed nature. In other words, "first" and "second" are interchangeable, and one device of the same type can be referred to as "first" or "second."

[0056] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, it can mean a fixed connection, a detachable connection, or an integral connection; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean internal communication between two components. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0057] The terms used herein are intended only to describe specific embodiments and are not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "a", "an", "an item" used herein are also intended to include the plural. It should also be understood that the terms "comprise" and / or "include" used herein specify the presence of stated features, integers, steps, operations, units and / or components, and do not preclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0058] To minimize the impact of the scratching process during packaging on chips with insufficient strength, this application uses a stealth dicing and grinding (SDBG) process. This process creates invisible cracks in specific locations on the chip through stealth dicing, then performs back grinding to reduce the chip to a specified thickness. The wafer or die is then pulled apart along the sides of the invisible crack to complete the dicing of the wafer or die. This process avoids mechanical damage to the chip caused by blade dicing.

[0059] To improve chip strength, SDBG (stealth dicing followed by grinding) is a future trend in 3D NAND packaging, but not limited to 3D NAND. Compared to traditional DBG (dicing before grinding), which involves half-cutting the chip and then back-grinding it to separate the die), SDBG significantly improves chip strength requirements.

[0060] However, the present applicant has discovered through research that as the number of 3D NAND layers increases, the total thickness of the film in the Z direction of the stack becomes increasingly thicker. Furthermore, there are some tiny array test keys distributed on the cutting paths. These test keys contain a large amount of wordline metal, which can cause SDBG to be difficult to cut, thereby affecting product yield.

[0061] SDBG is a stealth cutting method that uses laser light from the backside of the substrate. Focusing the laser heat melts the silicon material, generating a thermal expansion force that cracks the substrate along the cutting path generated by this expansion force, thus achieving wafer dicing. However, if the wafer contains a large amount of continuous metal film, the metal's ductility and strong fracture toughness will affect the SDBG cutting effect, and in severe cases, the wafer may not be cut at all. Moreover, the thickened metal layer prevents the chip from cracking in the desired direction during stealth cutting, resulting in damage to the die or chip. Even if SDBG laser cutting is increased, there is a certain limit to the laser energy, and the cost of this solution will increase accordingly.

[0062] In storage arrays such as 3D NAND, a gate line isolation structure is usually provided. This application, through the design of a new special gate line isolation structure, not only significantly increases the success range (Window) of the SDBG cutting process without increasing costs, but also improves the product cutting yield.

[0063] The following will disclose the semiconductor device and its manufacturing method as well as the memory and storage system provided by the present application through some embodiments.

[0064] First, as shown in FIG. 1a to FIG. 1b , semiconductor devices according to some embodiments of the present application are disclosed, and in particular, various structures that are conducive to using the SDBG (Stealth Dicing Before Grinding) process to cut wafers are disclosed.

[0065] According to some embodiments of the present application, a basic semiconductor device is first provided. As shown in Figure 1a, the semiconductor device disclosed according to the embodiment of the present application includes: a first semiconductor structure 10, the first semiconductor structure includes a first device block 12 and a first cutting road block 13 adjacent to the first device block in a first direction; wherein, the first cutting road block 13 includes at least one crack surface guide structure 14 extending along a second direction, the second direction intersects with the first direction, and the crack surface guide structure 14 includes a first portion 14a and a second portion 14b extending along the second direction and at least partially parallel, and the second portion 14b has stronger crack surface passability than the first portion 14a.

[0066] Specifically, as shown in FIG1a , the first device block 12 and the first scribe line block 13 adjacent to the first device block in a first direction Y may include a common substrate 11. The first device block 12 is any possible device structure formed on region A of the substrate, while the first scribe line block 13 is any possible scribe line structure formed on region B of the substrate to coordinate with the device structure in region A. Furthermore, the first scribe line block 13 includes a crack surface guide structure 14 that extends along a second direction Z, through the scribe line structure, and along a third direction X. The crack surface guide structure 14 includes a first portion 14a formed from a first material, and the first material includes, but is not limited to, one of a polymer, silicon carbide (NDC), silicon nitride (SiN), ceramic (SiCN), and silicon oxide (SiO2).

[0067] The aforementioned crack surface refers to the laser beam applied to the focal point 15 in Figure 1a from the side of substrate 11 facing away from the scribe line structure in first scribe line block 13. The laser's focus heats and melts the silicon material of the substrate, generating a thermal expansion force. This thermal expansion force creates an invisible crack. In subsequent processing, the substrate then breaks along the scribe line CC of guide structure 14, starting from this invisible crack, thereby achieving wafer dicing. Cross-section line CC is the expected location of the crack surface corresponding to the laser focus position, and the cracked portion is the crack surface.

[0068] In the embodiment shown in FIG. 1 a , the second portion 14 b is an air gap, which is formed simultaneously with the first portion 14 a of the crack-guiding structure 14. In other words, by appropriately adjusting the deposition rate of the material in the first portion 14 a , an air gap serving as the second portion 14 b can be formed within the first portion 14 a .

[0069] It should be noted that in actual products, the substrate 11 may be replaced with other film layers in subsequent manufacturing processes, or the substrate 11 may be removed so that the final semiconductor device does not have the substrate 11. Therefore, the first device block 12 and the first cutting street block 13 may also not include the substrate 11. When a substrate is included, the material of the substrate 11 may include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials or other semiconductor materials. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si / SiGe, silicon on insulator (SOI) or germanium on insulator (GOI). Therefore, the substrate 11 may be a single-layer structure or a multi-layer composite structure, which is not specifically limited here.

[0070] Furthermore, the first device block 12 may be various semiconductor structures, such as various memory arrays or semiconductor structures composed of digital circuits. The semiconductor structures composed of the memory arrays may include, but are not limited to, 2D or 3D memory array semiconductor structures such as NAND, DRAM, FeRAM, PCRAM, and MRAM. The digital circuits may include, but are not limited to, analog integrated circuit devices such as controllers, power amplifiers, and power management circuits; or semiconductor structures composed of digital integrated circuit devices such as programmable logic devices (PLDs), microprocessors (MPUs), microcontrollers (MCUs), and digital signal processors (DSPs).

[0071] The scribe line structure in the first scribe line block 13 may include various possible test key structures, or may be a scribe line structure accumulated in the scribe line in accordance with the structure of the first device block 12 .

[0072] It should be further explained that the semiconductor device referred to in this application can refer to a wafer, a die or a crystal after the wafer has been diced, or a chip after packaging. However, for the sake of convenience and explanation, only the portion of the wafer, die, or chip related to the scribe line is used for reference. Most of the icons shown show a wafer containing two adjacent device blocks and a scribe line block. However, those skilled in the art will readily understand that when two adjacent die in a wafer are cleaved along the cleavage plane in the scribe line, a single die will be located on one of the two sides of the cleavage plane. Therefore, when a semiconductor device refers to a wafer, it refers to a semiconductor device including at least one first device block 12 and a complete first scribe line block 13. However, when the semiconductor device refers to a die or chip after dicing, the semiconductor device will only include one first device block 12 and a portion of the first scribe line block 13, i.e., the portion of the first scribe line block 13 cut along the cross-sectional line CC.

[0073] Therefore, in the embodiment shown in FIG1a , when the second portion 14b is an air gap, if the semiconductor device is a single die or chip, only region A and a portion of region B will be present, that is, only a first device block 12 and a portion of the first scribe line block 13 will be present, and the portion of the first scribe line block 13 will only include a portion of the first portion 14a and a portion of the second portion 14b. For example, the first portion 14a may include two end portions (not numbered) in the second direction Z, and the portion of the first portion 14a will only include a portion of the first portion 14a on the side of the interface indicated by the cross-sectional line CC near the first device block 12. The air gap as the second portion 14b will only be displayed or represented by a first curved surface 14a1 located on the first portion 14a and intersecting with the first portion 14a, and the first curved surface 14a1 is recessed toward the first portion 14a relative to the two end portions in the first direction Y. In other words, when the semiconductor device is a single bare die or chip, the existence of "part of the first part" represents the existence of the first part, that is, the first part includes "part of the first part"; the existence of "part of the second part" represents the existence of the second part, that is, the second part includes "part of the second part", and the first curved surface 14a1 is concave toward the first part 14a relative to the two end parts in the first direction Y.

[0074] In addition, the existence of the invisible second portion 14b can be said to be that the first portion 14a includes two end portions (unnumbered) in the second direction, and the second portion 14b includes a gap between a virtual section (i.e., section line CC) formed by the two end portions of the first portion 14a and the first portion 14a, i.e., the space between the section line CC and the first curved surface 14a1.

[0075] Furthermore, in some embodiments, as shown in FIG1b , the crack surface guiding structure 14′ includes a first portion 14a′ and a second portion 14b′ extending along the second direction and at least partially parallel to each other, the first portion 14a′ includes a first material, the second portion 14b′ includes a second material, and the Young's modulus of the second material is smaller than the Young's modulus of the first material.

[0076] Specifically, the Young's modulus E shown is also called the elastic modulus, which is a term in material mechanics. When an elastic material is subjected to positive stress, it will produce positive strain. When the deformation does not exceed a certain elastic limit of the corresponding material, the ratio of positive stress to positive strain is defined as the Young's modulus of this material. Moreover, the Young's modulus depends on the composition of the material. For example, most metals have different alloy compositions and different heat treatments during processing, and their Young's modulus values ​​will fluctuate by 5% or more. The first material and the second material can each include, but are not limited to, one of polymers, silicon carbide (NDC), silicon nitride, ceramics (SiCN), and silicon oxide, and are different materials.

[0077] Specifically, the Young's modulus E of ceramic (SiCN) is approximately 450 GPa, the Young's modulus E of silicon carbide (SiC) is approximately 330 GPa, the Young's modulus E of silicon nitride is approximately 300 GPa, the Young's modulus E of silicon oxide is approximately 72 GPa, and the Young's modulus E of polymer is approximately less than 10 GPa. Therefore, when the air gap shown in FIG. 1a is not used as the second portion, and instead a first material and a second material of different materials are used as the first portion and the second portion, respectively, for example, a polymer is used as the material of the second portion and silicon nitride is used as the material of the first portion, a combination can be obtained in which the Young's modulus of the second material is lower than that of the first material, or, as mentioned above, a combination in which the second portion has a higher crack surface permeability than the first portion.

[0078] Based on the above basic design, some other embodiments of the present application are further described below. First, as shown in Figure 2a, the semiconductor device shown in the embodiment of the present application includes a first semiconductor structure 100, and the first semiconductor structure 100 includes a first device block A1, and a first cutting street block B1 adjacent to the first device block A1 in the first direction (compared to Figure 1a, A1 and B1 are used to represent the blocks). The first device block A1 and the first cutting street block B1 are formed on a substrate 111. The material of the substrate is as described above and will not be described in detail. The structure shown in Figure 2a is illustrated by an example of the first semiconductor structure being applied to 3D NAND. In this example, the first device block A1 includes a first gate line isolation structure 130, and the first cutting street block B1 includes a second gate line isolation structure 140 extending along the second direction Z as a crack surface guide structure. The second gate line isolation structure 140 includes a first portion 141 and a second portion 142 corresponding to the aforementioned first portion 14a and second portion 14b, respectively, and a width W2 of the second gate line isolation structure 140 in a cross section along the first direction Y is greater than a width W1 of the first gate line isolation structure in the cross section.

[0079] Specifically, the first device block A1 in the first semiconductor structure 100 includes a stacked structure 110 and multiple channel structures 120 extending through the stacked structure 110, multiple first gate line isolation structures 130, and a top gate isolation structure 112. The stacked structure 110 includes alternating gate layers and interlayer insulating layers (not numbered). The gate layer 101 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, and the interlayer insulating layer includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The number of gate layers and insulating layers can be any number and is not limited.

[0080] The channel structure 120 penetrates the gate layer and the insulating layer along the stacking direction (Z) (i.e., the second direction). The channel structure 120 may include, from the inside out, a channel filling layer, a channel layer arranged around the channel filling layer, and a storage medium layer arranged around the channel layer (the above layers are not numbered in detail because they are not the focus of this case). The storage medium layer may include a tunnel layer arranged around the channel layer, a charge storage layer arranged around the tunnel layer, and a charge blocking layer arranged around the charge storage layer (also because the layers are not the focus of this case, they are not shown in the figure). Among them, the channel filling layer may be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride, the channel layer may be a semiconductor layer such as polycrystalline silicon, the tunnel layer may be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride, the charge storage layer may be an insulating layer including quantum dots or nanocrystals or a compound containing nitrogen and silicon, and the charge blocking layer may be an oxide such as silicon oxide.

[0081] The first gate line isolation structure 130 is a gate line isolation structure formed in a gate gap (unnumbered) formed in the stacked structure 110 through a thin film deposition process. The first gate line isolation structure 130 may include a filling layer 130a and a barrier layer 130b. The filling layer 130a extends from the side of the stacked structure 110 facing away from the base 111 into the substrate 111, and the barrier layer 130b is arranged around the filling layer 130a. The material of the barrier layer 130b may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, and the like. The material of the filling layer 130a may include, but is not limited to, a polymer material such as polysilicon. When the filling layer 130a is a polymer layer, it has a conductive effect and can serve as a common source lead structure. In addition, a cross-section of the first gate line isolation structure 130 taken at any position in the second direction Z in the first direction Y has a first width W1.

[0082] The top gate isolation structure 112 is distributed in the top gate layer and is used to perform memory array paging for the channel structure 130. The material of the top gate isolation structure 112 may include but is not limited to dielectric insulating materials such as silicon oxide and silicon nitride.

[0083] In addition, the first semiconductor structure 100 may also include an interconnection layer 150. The interconnection layer 150 is mainly distributed on the first device block A1, but can also be distributed on the first cutting street block B1, and the interconnection layer 150 includes a dielectric layer 151 and a conductive line or conductor 152 located in the dielectric layer 151. The material of the dielectric layer 151 may include but is not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, etc. The material of the conductive line or conductor 152 may include at least one of tungsten, cobalt, copper, aluminum, etc. The interconnection layer 150 can connect the first gate line isolation structure 130 and the channel structure 120 to other external devices under appropriate arrangement.

[0084] In the first scribe block B1, in conjunction with the formation of the stacked structure 110 in the first device block A1, a similar stacked structure 110' is also formed in the first scribe block B1. In this embodiment, although the stacked structures 110 and 110' are both formed of alternating gate layers and interlayer insulating layers, it should be understood that in some embodiments, the gate layer in the first scribe region B1 may be a sacrificial dielectric layer that is not replaced with a gate layer. Therefore, the stacked structure in the first scribe block B1 is labeled 110' here. The second gate line isolation structure 140, which serves as a crack surface guide structure in the first scribe block B1, is formed in the stacked structure 110'. The second portion 142 of the second gate line isolation structure 140, like the second portion 14b shown in FIG. 1a, is an air gap. The first portion 141 has the same structure as the first gate line isolation structure 130 and includes a filler layer 141a, as well as an isolation filler layer 141a and an oxide layer 141b of the stacked structure 110'. The material of the first portion 141 can be the same as that of the first gate line isolation structure 130, but the material of the filling layer 141a within the oxide layer 141b can include, but is not limited to, one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide. In other words, the first portion 141 can be formed simultaneously with the first gate line isolation structure 130 using the same material as the first gate line isolation structure 130, or can be formed separately using a material different from that of the first gate line isolation structure 130.

[0085] In addition, a cross-section of the second gate line isolation structure 140 in the first direction Y obtained at any portion in the second direction Z has a second width W2, and the second width W2 is greater than the first width W1. In some embodiments, the width range of the second gate line isolation structure 140, that is, the second width, can be between 200nm and 2um. By setting the second width W2 greater than the first width W1, when the second gate line isolation structure 140 and the first gate line isolation structure 130 are formed simultaneously, in addition to filling the first gate line isolation structure 130, an air gap serving as the second portion 142 can also be formed within the first portion 141 of the second gate line isolation structure 140. Obviously, since the second portion 142 is an air gap, the second portion 142 will be more crack-surface-permeable than the first portion 141.

[0086] Through the second gate line isolation structure 140 as a crack surface guide structure described above, when an external laser is applied from the side of the substrate 111 away from the stacked structure 110' in the first cutting street block B1 to a position similar to the focus 15 corresponding to the air gap in Figure 1a, the focusing of the laser will heat and melt the silicon material serving as the substrate, generating a thermal expansion force, causing the substrate to cleave through the air gap along the cutting route CC in the subsequent process, thereby achieving wafer cutting.

[0087] The second gate line isolation structure 140 described above can be described as a special gate line isolation structure. When this special second gate line isolation structure 140 is formed simultaneously with the first gate line isolation structure 130 in the first device block A1, process costs are not increased. Furthermore, since there is no need to reserve a 15 μm cutting channel area, for example, between the stacked structure or test key structure of the first device block A1 and the first scribe line block B1, the air gap in the second gate line isolation structure 140 is used to guide the direction and location of the laser crack extension. This ensures that during the final SDBG dicing process, crack propagation preferentially occurs along the weakest air gap, avoiding die damage and achieving good wafer or die dicing. Therefore, the structural design shown in the embodiment of the present application will not affect the testing requirements of the mini-array test key (Mini Array TSK). Furthermore, as device blocks become increasingly wider in the future, the Mini Array TSK will have a certain number of testing requirements, making it more difficult to reserve a 15 μm area. The second gate line isolation structure 140 shown in the embodiment of the present application, as a crack surface guide structure, will better address this problem.

[0088] In this embodiment, similar to the embodiment shown in FIG. 1 a , since the second portion 142 is an air gap, if the semiconductor device is a single die or chip, only a portion of the first scribe line block B1 will be present, and the portion of the first scribe line block B1 will only include a portion of the first portion 141 and a portion of the second portion 142. For example, the first portion 141 may include two end portions (not numbered) in the second direction Z, and the portion of the first portion 141 will only include the portion of the first portion 141 on the side of the interface indicated by the cross-sectional line CC near the first device block A1. The air gap as the second portion 142 will only be present through a first curved surface 141 c located on the first portion 141 and intersecting with the first portion 141, and the first curved surface 141 c is recessed toward the first portion 141 relative to the two end portions in the first direction Y. Similarly, when the semiconductor device is a single bare die or chip, the existence of "part of the first part" represents the existence of the first part, that is, the first part includes "part of the first part"; the existence of "part of the second part" represents the existence of the second part, that is, the second part includes "part of the second part", and the first curved surface 14a1 is concave toward the first part 14a relative to the two end parts in the first direction Y.

[0089] Similarly, the existence of the invisible partial second portion 142 can also be said to be that the first portion 141 includes two end portions (unnumbered) in the second direction, and the second portion 142 includes a gap between a virtual section (i.e., section line CC) formed by the two end portions of the first portion 141 and the first portion 141, i.e., the space between the section line CC and the first curved surface 141c.

[0090] It should be mentioned here that the first device block A1 described above, using the 3D NAND array as an example, may also include a connection region structure. The connection region structure may include multiple gate layer lead contacts for leading out each gate layer. The connection region structure may have various known structural designs, including a stepped structure in which stacked layers are in a stepped shape, or a stepped contact connection (SCT) structure in which only the lead contacts are in a stepped shape. Since these are not the focus of this case, they will not be described in detail here.

[0091] Next, referring to FIG. 2 b , FIG. 2 b discloses another semiconductor device formed according to some embodiments of the present application, and the semiconductor device includes a first semiconductor structure 101. The first semiconductor structure 101 is similar to the first semiconductor structure 100 shown in FIG. 2 a , and also includes a first device block A1 and a first sawing block B11 adjacent to the first device block A1 in the first direction. However, the first sawing block B11 differs from the aforementioned first sawing block B1 in that, in addition to including a second gate line isolation structure 140 extending along the second direction Z as a crack surface guide structure, the first sawing block B11 also includes a channel structure or dummy channel structure 120 ' formed in the stacked structure 110 ' and spaced apart from the second gate line isolation structure 140 in the first direction Y. Moreover, the number of rows of the channel structures or dummy channel structures 120 ' in the third direction X can be at least one or more.

[0092] The channel structure or dummy channel structure 120' can be formed simultaneously with the channel structure 120 in the first device block A1 and can include the same structure as the channel structure 120, but can also be a different structure, for example, without the channel layer and the storage medium layer in the aforementioned channel structure 120, but only with the filling layer. When the channel structure or dummy channel structure 120' has the same structure as the channel structure 120, it can be called a channel structure. When it only includes the filling layer, it can be called a dummy channel structure. The first saw street block B11 in the first semiconductor structure 101 shown in Figure 2b has a channel structure or dummy channel structure 120' added to match the configuration of the first device block A1. When the first saw street block B11 is wider, it can match the configuration of the first device block A1 to obtain a better process window.

[0093] Next, referring to FIG. 2 c , FIG. 2 c discloses another semiconductor device formed according to some embodiments of the present application, and the semiconductor device includes a first semiconductor structure 102. The first semiconductor structure 102 is similar to the first semiconductor structure 101 shown in FIG. 2 b , and also includes a first device block A1 and a first cutting street block B111 adjacent to the first device block A1 in the first direction. However, the difference between the first cutting street block B111 and the aforementioned first cutting street block B11 is that, in addition to including a second gate line isolation structure 140 extending along the second direction Z as a crack surface guide structure and a channel structure or a dummy channel structure 120 ′, the first cutting street block B111 also includes a plurality of second gate line isolation structures 140. That is, the difference between the first cutting street block B111 and the first cutting street block B11 is the number of second gate line isolation structures 140.

[0094] In addition, in the embodiment shown in FIG2c, the number of columns of the channel structure or the dummy channel structure 120' in the third direction X is also greater than the number of columns in the first cutting line block B11, and the multiple columns of channel structures or dummy channel structures are alternately spaced with the multiple second gate line isolation structures 140 in the first direction Y.

[0095] The semiconductor device or first semiconductor structure 102 shown in FIG. 2c not only accommodates wider scribe line designs but also increases the selectivity of the cleavage plane. Specifically, during the cleavage process of the semiconductor device, it may be necessary to fine-tune the cleavage position in both the X and Y directions. In this case, providing multiple second gate line isolation structures 140 that serve as cleavage plane guides enhances adjustability.

[0096] 3a and 3b further illustrate the distribution of the cleave surface guiding structures from different perspectives. Figures 3a and 3b illustrate the distribution of the cleave surface guiding structures 14 of Figures 1a and 1b, or the cleave surface guiding structures 140 of Figures 2a to 2c, on a plane defined by the first direction Y and the third direction X.

[0097] As shown in Figure 3a, A1 represents the first device blocks 12 and A1 of the aforementioned embodiments, B1 represents the first scribe line blocks B1 and B11 of the aforementioned embodiments, and 140 represents the crack surface guiding structures 14 and 140 of the aforementioned embodiments. Typically, the first gate line isolation structure 130 in the first device block A1 extends along the third direction X. Therefore, the second gate line isolation structure 140, serving as a crack surface guiding structure, also extends along the third direction X in the first scribe line block B1. Herein, the first scribe line blocks B1 extending along the third direction X but arranged at intervals in the first direction Y are referred to as first X scribe line blocks, and the first scribe line blocks B2 extending along the first direction Y but arranged at intervals in the third direction X are referred to as first Y scribe line blocks.

[0098] As shown in FIG3b , the second gate line isolation structure 140, serving as a cleave plane guiding structure, not only extends along the third direction X in the first scribe line block B1, but also extends along the first direction Y in the first Y scribe line block B2, which is the first direction Y. In other words, the first scribe line block includes the first X scribe line block B1, which is adjacent to the first device block in the first direction Y, and the first Y scribe line block B2, which is adjacent to the first device block in the third direction X, where the third direction intersects the first direction. The cleave plane guiding structure 140 includes a first X cleave plane guiding structure located in the first X scribe line block and a first Y cleave plane guiding structure located in the first Y scribe line block. The first X cleave plane guiding structure and the first Y cleave plane guiding structure have the same structure, except for their different orientations. Therefore, they are still labeled with the same reference numeral 140, rather than with different reference numerals.

[0099] The above details some of the basic structures of the crack surface guiding structures disclosed in some embodiments of the present application. Next, please refer to FIG4 a, which illustrates a schematic cross-sectional structure of another semiconductor device provided in some embodiments of the present application. The semiconductor device 300 disclosed in FIG4 a includes, in addition to the first semiconductor structure 101 described above, a second semiconductor structure 201. The second semiconductor structure 201 includes a second device block A2 and a second scribe line block B2. The first device block A1 and the second device block A2 are stacked and bonded together in the second direction Z.

[0100] Specifically, the first semiconductor structure 101 is the first semiconductor structure 101 shown in FIG. 2 a , and therefore will not be repeated here. In this embodiment, the second device block A2 in the second semiconductor structure 201 includes a substrate 211 and second devices 220 located on the substrate 211 , a conductive path 230 connecting the second devices 220 , and a dielectric layer 240 covering the second devices 220 and serving as an interlayer isolation between the conductive paths. The material of the substrate 211 is the same as that of the substrate in the first semiconductor structure 101 , and may include single crystal silicon, polycrystalline silicon, single crystal germanium, a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials, and will not be repeated here. The substrate 211 may extend into the second device block A2 and the second scribe line block B2 .

[0101] In addition, the first semiconductor structure 101 and the second semiconductor structure 201 are bonded together via a bonding structure 250. The bonding structure 250 may include bonding layers located on the first semiconductor structure 101 and the second semiconductor structure 201, respectively. Each bonding layer includes a bonding contact 251 and a dielectric layer 252 (in the figure, only one reference numeral is used to indicate both bonding layers).

[0102] The second device block A2 constitutes a device with a specific function, which can be a peripheral circuit for controlling the memory array in the first semiconductor structure 101, or a semiconductor structure composed of other digital circuits. The digital circuits may include but are not limited to analog integrated circuit devices such as controllers, power amplifiers, and power management circuits; or semiconductor structures composed of digital integrated circuit devices such as memory controllers, microprocessors, and digital signal processors (DSPs), without limitation.

[0103] The second scribe line block B2 also includes the aforementioned substrate 211 and dielectric layer 240. The substrate 211 and dielectric layer 240 in the second scribe line block B2 can be structures extending into the second scribe line block B2 to match the design of the second device block A2, or can alternatively be specially formed structures, such as the test key structure shown above. It will be appreciated that in some embodiments, the structure of the second scribe line block B2 can also be provided with a crack surface guiding structure 14 or 14' similar to that shown in Figures 1a or 1b above, which will not be repeated here.

[0104] With the aforementioned semiconductor device 300, as shown in FIG4a , an external laser can be applied to substrate 111 or 211 from the side of substrate 111 or 211 facing away from first scribe line block B11 or B2, respectively. For example, at the location of focus 215, the laser's focus heats and melts the silicon material of the substrate, generating a thermal expansion force that, under subsequent tension, causes the substrate and first and second scribe line blocks B11 and B2 to cleave along cleavage line CC, thereby achieving wafer dicing. Cross-section line CC represents the location of the crack (or cleavage) plane expected to be generated at the location of the laser focus.

[0105] In some embodiments, as shown in FIG. 4 a , the crack surface guiding structure 140 may include a first end D in the second direction Z and a recessed portion E distal to the first end D. The cross-sectional area of ​​the crack surface guiding structure 140 in the first direction Y gradually increases from the recessed portion E toward the first end D. The first end D is closer to the second scribe line area B2 of the second semiconductor device 201 than the recessed portion E. The distance between the first end D and the recessed portion E may vary depending on the actual situation.

[0106] By gradually widening the opening of the crack surface guiding structure 140 near the laser incident side toward the laser incident side, the cracking path of the thermal expansion force generated by the laser focusing on the substrate can more easily enter the crack surface guiding structure 140, thereby achieving the cutting purpose through the air gap.

[0107] It will be appreciated that, in the embodiment shown in FIG. 4 a , while the enlarged opening of the crack-plane guiding structure 140 faces the second semiconductor structure 201 , the present application is not limited thereto, and the enlarged opening can be designed based on the actual structure. For example, when the semiconductor device does not include the second semiconductor structure, the enlarged opening of the crack-plane guiding structure 140 can face the substrate of the first semiconductor structure itself, thereby facilitating the cracking path of the thermal expansion force generated by the laser focused on the substrate to more easily enter the crack-plane guiding structure 140 .

[0108] Continuing with reference to FIG4b , FIG4b illustrates a schematic cross-sectional structure of another semiconductor device provided in some embodiments of the present application. The semiconductor device 301 shown in FIG4b is similar to the semiconductor device 300 shown in FIG4a , except that the semiconductor device 301 is inverted and the substrate 111 in the first scribe line block B11 of the first semiconductor structure 101 in FIG4a is thinned to form a first semiconductor structure 101′ having a first scribe line block B11′. Furthermore, the thinned end face or back face of the first scribe line block B11′, facing away from the second scribe line block B2, is recessed relative to the end face of the first device block A1 on the same side as the back face.

[0109] Specifically, as shown in FIG4b , the semiconductor device 301 includes the aforementioned first semiconductor structure 101′ and a second semiconductor structure 201. The first semiconductor structure 101′ includes a first device block A1 and a first scribe line block B11′. The second semiconductor structure 201 includes a second device block A2 and a second scribe line block B2. The first device block A1 and the second device block A2 are stacked and bonded together in the second direction. The substrate 111 located in the first scribe line block B11 of FIG4a is partially thinned to form a first scribe line block B11′ having a thinned end surface. The height H1 of the first scribe line block B11′ is smaller than the height H2 of the first device block A1. Due to this height difference, the back end surface, or thinned end surface, of the first scribe line block B11′, facing away from the second scribe line block B2, is recessed relative to the end surface of the first device block A1 on the same side as the back end surface.

[0110] With the semiconductor device 301 shown in FIG4b , since the substrate 111 where the first cutting street block B11′ is located has been thinned or removed, when an external laser is applied to the substrate 211 from the side of the substrate 211 away from the first cutting street block B11′, such as the position of the focus 215 shown in the figure, the substrate 211 will melt due to the focused heating of the laser and generate a thermal expansion force, so that the substrate, the second cutting street block B2 and the first cutting street block B11′ are subjected to tension in different directions on both sides thereof, that is, they can be cracked along the cutting route CC. Moreover, when the cracking reaches the cross section where the substrate 111 is located, since the substrate 111 has been thinned or removed, the cutting route CC will be easier to crack, thereby achieving wafer cutting.

[0111] It should be noted that, although not specifically illustrated, the substrate 111 in the embodiment shown in FIG. 4b may, in some embodiments, be a material layer that is removed and then formed. That is, after the original substrate used to form the stacked structure is removed, a new material layer is deposited on the bottom surface of the stacked structure where the original substrate was located. This material layer may be, for example, a semiconductor layer formed of polycrystalline silicon. In particular, when the first device block A1 is a memory array, this semiconductor material layer may be or serve as a common source layer. Therefore, in some embodiments of the present application, the substrate 11 / 111 / 211 described may be the original substrate described above, or a base / material layer / semiconductor layer formed after the original substrate is removed. That is, the substrate 111 shown in FIG. 4b may also be a polycrystalline silicon semiconductor layer formed after the original substrate is removed. Therefore, the substrates described in this application include, but are not limited to, substrates, bases, deposited material layers, etc. Because the substrates shown may be removed to accommodate different designs, the semiconductor devices or semiconductor structures described in this application may or may not include a substrate.

[0112] The above embodiments illustrate the semiconductor device disclosed in this application. The following further illustrates the method for fabricating the semiconductor device disclosed in this application. Referring to Figures 5a and 5b, Figures 5a and 5b are schematic flow charts illustrating the method for fabricating the semiconductor device provided in some embodiments of this application.

[0113] First, as shown in FIG5a , a method for manufacturing a semiconductor device according to some embodiments of the present application mainly includes the following steps:

[0114] Step S400: providing a first semiconductor structure, wherein the first semiconductor structure includes a first device block and a first scribe line block adjacent to the first device block in a first direction;

[0115] Step S500: forming at least one crack surface guiding structure extending along the second direction in the first cutting street structure, wherein the second direction intersects the first direction, and the crack surface guiding structure includes a first portion and a second portion extending along the second direction, and the second portion has a stronger crack surface passability than the first portion.

[0116] Specifically, referring to step S400 of FIG. 5a and FIG. 1a , a first device block 12 and a first scribe line block 13 adjacent to the first device block 12 in a first direction Y are formed on region A of the substrate. The first device block 12 can be any possible device structure, and the first scribe line block 13 can be any possible scribe line structure formed on region B of the substrate to coordinate with the device structure on region A.

[0117] Specifically, in some embodiments, step S500 may include:

[0118] Step S510 : forming the first portion, and forming the second portion within the first portion, wherein the second portion includes an air gap.

[0119] Referring to step S500 in FIG. 5a and FIG. 1a , a crack surface guiding structure 14 is formed in the first scribe line block 13. The structure extends along a second direction Z, through the scribe line structure, and along a third direction X. The crack surface guiding structure 14 includes a first portion 14a formed from a first material, including but not limited to a polymer, silicon carbide (NDC), silicon nitride (SiN), ceramic (SiCN), or silicon oxide (SiO2). The second portion 14b is an air gap, which is formed simultaneously with the formation of the first portion 14a of the crack surface guiding structure 14. By appropriately adjusting the material deposition rate of the first portion 14a, an air gap serving as the second portion 14b can be formed within the first portion 14a. This method forms the crack surface guiding structure 14 described in the present embodiment.

[0120] In some other embodiments, step S500 may include:

[0121] Step S510': firstly form the first portion with a first material,

[0122] Step S520 : forming the second portion on the inner surface of the first portion with a second material, wherein the Young's modulus of the second material is smaller than that of the first material.

[0123] In the step S510', in some embodiments, the first portion is formed using one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide; in the step S520, the second portion is formed using a material selected from one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide, and the second material is different from the first material, and the Young's modulus of the second material is smaller than the Young's modulus of the first material.

[0124] Specifically, referring to FIG1b , a first device block 12 and a first scribe line block 13 adjacent to the first device block 12 in a first direction Y are formed on region A of the substrate. The first device block 12 can be any possible device structure, and the first scribe line block 13 can be any possible scribe line structure formed on region B of the substrate to coordinate with the device structure on region A.

[0125] Referring again to step S510' in FIG. 5a and FIG. 1b , a first portion 14a' formed of a first material is formed in the first scribe line block 13. The portion extends along the second direction Z, passes through the scribe line structure, and extends along the third direction X. Referring again to FIG. 1b and step S520, a second portion 14b' is formed on the inner surface of the first portion 14a' using a second material. The second material has a Young's modulus that is lower than that of the first material. The first material or the second material includes, but is not limited to, one of a polymer, silicon carbide (NDC), silicon nitride (SiN), ceramic (SiCN), or silicon oxide (SiO2). This forms a crack surface guiding structure 14 according to an embodiment of the present application.

[0126] The following will further illustrate the method for preparing the semiconductor device 101 by taking the preparation of the semiconductor device 101 as an example, with reference to Figures 5b and 6a to 6d. That is, in some embodiments, as shown in Figure 5b, the aforementioned step S400 may include:

[0127] Step S410: forming a plurality of stacked layers formed by alternately stacking sacrificial dielectric layers and interlayer insulating layers in the second direction, and a channel structure or a dummy channel structure located in the stacked layers and spaced apart from a preset position of the second gate line isolation structure, thereby forming a first cutting street block.

[0128] In some embodiments, step S500 may include:

[0129] Step S513: forming a first gate line isolation structure in the first device block, and forming a second gate line isolation structure in the first cutting road block as the crack surface guide structure and including the first portion and the second portion, and setting the width of the second gate line isolation structure on a cross section in the first direction to be greater than the width of the first gate line isolation structure on the cross section.

[0130] Since the width of the second gate line isolation structure in a cross section in the first direction is greater than the width of the first gate line isolation structure in the cross section, in the process of forming the gate line isolation structure, the first gate line isolation structure in the device will be filled, but the special second gate line isolation structure in the cutting channel area will fill out a clear air gap, that is, the air gap described in step S510 is formed in the second gate line isolation structure.

[0131] In some embodiments, the step S513 may further include: forming a plurality of second gate line isolation structures, and arranging the plurality of second gate line isolation structures spaced apart from the channel structure or the dummy channel structure in the first direction.

[0132] Specifically, first, as shown in step S410 of Figure 5b and Figure 6a, a stacked structure 110 and a stacked structure 110', a plurality of channel structures 120 passing through the stacked structure 110, a channel structure or a virtual channel structure 120' passing through the stacked structure 110', a top gate isolation structure 112, a first gate line gap 130', and a second gate line gap 140' are formed on the first device region A on the substrate 111 and the first cutting road region B adjacent to the first device region A in the first direction Y. The stacked structure 110 includes alternatingly stacked gate layers and interlayer insulating layers (unnumbered), wherein the gate layer includes but is not limited to tungsten, cobalt, copper, aluminum, doped silicon or doped silicide, and the interlayer insulating layer includes but is not limited to any one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. The number of gate layers and insulating layers can be any number and is not limited.

[0133] It should be noted that the stacked structure 110 is formed by first forming a stack of alternating sacrificial dielectric layers and interlayer insulating layers on regions A and B of the substrate 111, then completing the channel structures 120 and 120' and the top gate isolation structure 112 in the stacked layer, then excavating the first gate line gap 130' and the second gate line gap 140', and then replacing the sacrificial dielectric layer with the gate layer through the first gate line gap 130' and the second gate line gap 140'. Therefore, the channel structure or dummy channel structure is formed in a position in the stacked layer that is spaced apart from the predetermined position of the second gate line isolation structure.

[0134] Furthermore, the channel structure 120 that penetrates the stacked layers along the stacking direction (Z) (i.e., the second direction) is formed, for example, by first forming a channel hole in the stacked layers, and then forming a storage dielectric layer, a channel layer located within the storage dielectric layer, and a channel filling layer located within the channel layer in the channel hole. The storage dielectric layer may include a tunnel layer disposed around the channel layer, a charge storage layer disposed around the tunnel layer, and a charge blocking layer disposed around the charge storage layer. The channel filling layer may be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride; the channel layer may be a semiconductor layer such as polycrystalline silicon; the tunnel layer may be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride; the charge storage layer may be an insulating layer containing quantum dots or nanocrystals or a compound containing nitrogen and silicon; and the charge blocking layer may be an oxide such as silicon oxide. A top gate isolation structure 112 is distributed in the top gate layer to perform paging for the channel structure 120. The material of the top gate isolation structure 112 may include, but is not limited to, dielectric insulating materials such as silicon oxide and silicon nitride.

[0135] In addition, although in some embodiments the stacked structures 110 and 110' are both formed by alternatingly stacked gate layers and interlayer insulating layers, it should be understood that the sacrificial dielectric layer in the first cutting street block B11 may not be replaced by a conductive gate layer. In particular, when no channel structure is provided in the first cutting street block B1 as shown in the example of FIG2a, or when the cutting street is wider, part of the sacrificial dielectric layer may still be retained. Therefore, the gate layer here should be interpreted as including a sacrificial dielectric layer or a replaced conductive gate layer.

[0136] It should also be noted that the width of the second gateline slit 140' in a cross section along the first direction Y is set to be greater than the width of the first gateline slit 130' in the cross section. This is the first width W1 and the second width W2 shown in FIG2a . This setting allows, when the second gateline isolation structure 140 is subsequently formed, to form the second gateline isolation structure 140 including an air gap within the second gateline slit 140' while also filling the first gateline slit 130' to form the first gateline isolation structure 130.

[0137] Next, as shown in Figure 6b, the first gate line isolation structure 130 and the second gate line isolation structure 140 are filled in the first gate line gap 130' and the second gate line gap 140' respectively. The first gate line isolation structure 130 may include a filling layer 130a and a barrier layer 130b. The material of the barrier layer 130b may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass and the like. The material of the filling layer 130a may include but is not limited to polymer materials such as polysilicon. The second gate line isolation structure 140 includes a first portion 141 and a second portion 142, and the second portion 142 is an air gap. The first portion 141 is the same as the first gate line isolation structure 130 and includes a filling layer 141a, as well as an isolation filling layer 141a and an oxide layer 141b of the stacked structure 110'. The material of the first portion 141 can be the same as that of the first gate line isolation structure 130, but the material of the filling layer 141a within the oxide layer 141b can also include, but is not limited to, one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide. In other words, the first portion 141 can be formed simultaneously with the first gate line isolation structure 130 using the same material as the first gate line isolation structure 130, or can be formed separately using a material different from that of the first gate line isolation structure 130.

[0138] Next, as shown in FIG6c , an interconnect layer 150 is formed on the stacked structures 110 and 110 ′, thereby forming the semiconductor device 101 including the first device block A1 and the first scribe line block B11 as shown in FIG2b . The interconnect layer 150 is primarily located on the first device block A1, but may also be located on the first scribe line block B11. The interconnect layer 150 includes a dielectric layer 151 and conductive lines or conductors 152 located within the dielectric layer 151. The materials and functions of the interconnect layer 150 have been previously described and will not be repeated here.

[0139] In some embodiments, as described above, step S513 may further include forming a plurality of second gate line isolation structures, and spacing the plurality of second gate line isolation structures from the channel structure or dummy channel structure in the first direction. Specifically, the second gate line slits 140' shown in FIG6a are formed into a plurality and spaced apart from the channel structure or dummy channel structure in the first direction Y. This structure can be achieved, which is equivalent to the structure shown in FIG2c. Therefore, the structure formed in this step is not shown in the figure.

[0140] In addition, as shown in FIG5 b , the method for manufacturing a semiconductor device according to some embodiments of the present application further includes:

[0141] Step S600: providing a second semiconductor structure, wherein the second semiconductor structure includes a second device block and a second scribe line block; and stacking and bonding the first device block and the second device block together in the second direction.

[0142] In some embodiments, the step S600 further includes providing a silicon substrate, and the second scribe line area includes the silicon substrate.

[0143] Specifically, in step S600, a second semiconductor structure 201 as shown in FIG6d is first provided. The step of providing the second semiconductor structure 201 includes forming a second device 220 on a substrate 211, and alternately depositing dielectric layers 240 and conductive paths 230 to form a second device block A2 and a second saw street block B2. The dielectric layer 240 covers the second devices 220 and serves as interlayer isolation. The conductive paths 230 are arranged in the dielectric layer 240 to connect the second devices 220. The material of the substrate 211 is the same as that of the substrate in the first semiconductor structure 101, and can include single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials, and will not be repeated here. The substrate 211 extends into the second device block A2 and the second saw street block B2.

[0144] After forming the second semiconductor structure 201, bonding layers are formed on the first semiconductor structure 101 and the second semiconductor structure 201, respectively. Each bonding layer includes bonding contacts 251 and a dielectric layer 252. Then, through a bonding process, the second semiconductor structure 201 is placed upside down on the first semiconductor structure 101 and pressurized and heat-fused. This forms a bonding structure 250 located between the first semiconductor structure 101 and the second semiconductor structure 201, bonding the first semiconductor structure 101 and the second semiconductor structure 201 together. This results in the semiconductor device 300 shown in FIG6d (also FIG4a).

[0145] Next, the method for manufacturing a semiconductor device according to some embodiments of the present application may further include:

[0146] Step S700: removing the end portion of the first cutting street block away from the second cutting street block to form a first cutting street block with a thinned end face, wherein the thickness of the first cutting street block with the thinned end face in the second direction is smaller than the thickness of the first device block in the second direction.

[0147] Specifically, in step S700, the end portion of the first scribe block B11 in FIG. 4a that faces away from the second scribe block B2 is removed to form a first scribe block B11' having a thinned end face, as shown in FIG. 4b (because the structure at this point is identical to FIG. 4b , FIG. 4b is referenced directly and not separately shown). Thus, the thickness of the first scribe block B11' having a thinned end face in the second direction Z is less than the thickness of the first device block A1 in the second direction Z. This step can be achieved by masking the substrate in the first device block A1 region and using anisotropic etching to remove the substrate or a portion of the substrate in the first scribe block B11 facing away from the second scribe block B2, thereby achieving the purpose of thinning and forming the first scribe block B11' having a thinned end face.

[0148] It should be noted that the substrate shown can also be removed as described in the previous structural description, and then a semiconductor layer can be deposited to serve as the common source layer. Therefore, the thinned substrate can also be a later-deposited semiconductor layer. Furthermore, when the semiconductor device does not include the second semiconductor structure, the thinned substrate can also be the substrate in the first semiconductor structure. In other words, the substrate is thinned to a thickness that is easily cracked after laser irradiation.

[0149] Following the semiconductor device fabrication methods described in the preceding embodiments, an external laser is applied to the substrate 211 from a side of the substrate 211 facing away from the first scribe line block B11 / B11', such as at the location of the focal point 215 shown in Figures 4a and 4b. The focused heating of the laser causes the substrate 211 to melt, generating a thermal expansion force. Subsequently, by subjecting the substrate 211, the second scribe line block B2, and the first scribe line block B11 / B11' to tension in different directions, the substrate 211, the second scribe line block B2, and the first scribe line block B11 / B11' can be cleaved along the scribe line CC, thereby dicing the wafer and fabricating the semiconductor devices.

[0150] According to some embodiments of the present application, the present application further provides a memory, comprising:

[0151] A memory array comprising the first semiconductor structure or the second semiconductor structure in the aforementioned semiconductor device; and a peripheral circuit comprising the first semiconductor structure or the second semiconductor structure in the aforementioned semiconductor device.

[0152] Finally, according to some embodiments of the present application, the present application further provides a storage system, including:

[0153] The aforementioned memory; and a control device that controls the operation of the memory.

[0154] Specifically, please refer to Figure 7, which is a schematic block diagram of a memory provided in some embodiments of the present application. The memory 400 may be a three-dimensional memory, such as a 3D NAND, 3D NOR, or 3D DRAM memory.

[0155] The memory 400 includes a semiconductor device 401 and a peripheral circuit 402. The semiconductor device 401 can be the first semiconductor structure 100 / 101 / 102 or the second semiconductor structure 201 (when the memory is a 2D structure) in the above-mentioned embodiment, and the peripheral circuit 402 can be the first semiconductor structure 10 / 10' or the second semiconductor structure 201 in the above-mentioned embodiment, which is usually a CMOS (complementary metal oxide semiconductor) structure. The peripheral circuit 402 is electrically connected to the semiconductor device 401 to transmit signals to the semiconductor device 401. The peripheral circuit 402 can be used for logical operations and to control and detect the switching state of each storage unit in the above-mentioned semiconductor device 401 through metal wiring to realize data storage and reading. Therefore, the memory 400 can also be the aforementioned semiconductor device 300 / 301 including the first semiconductor structure 100 / 101 / 102 and the second semiconductor structure 201.

[0156] In the aforementioned memory 400, the semiconductor device 401 includes a first device block and a first cutting road block adjacent to the first device block in a first direction; moreover, the first cutting road block includes at least one crack surface guide structure extending along a second direction, the second direction intersects with the first direction, and the crack surface guide structure includes a first portion and a second portion extending along the second direction and at least partially parallel, and the second portion has stronger crack surface passability than the first portion, so that the memory has a good cutting surface.

[0157] Please refer to Figure 8, which is a schematic block diagram of a storage system provided in some embodiments of the present application. The storage system 500 includes a memory 400 and a controller 502. The memory 400 may be the memory described in the aforementioned embodiments and may include any of the semiconductor devices described in the aforementioned embodiments. In other words, the memory 400 may be the memory 400 shown in Figure 7. The controller 502 is electrically connected to the memory 400 and is configured to control the memory 400 to store data. The memory 400 may perform data storage operations based on the control of the controller 502.

[0158] In some embodiments, the storage system may be implemented as a storage device such as a Universal Flash Storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card or a memory stick, etc.

[0159] Through the semiconductor devices and their preparation methods, as well as the memory and storage systems disclosed in some embodiments of the present application as described above, a crack surface guide structure is designed on the cutting path, and two first and second parts with different cracking easiness are set in the crack surface guide structure, and the second part has a stronger crack surface passability than the first part. Through such a configuration, during the stealth dicing before grinding (SDBG) process, the cracks in the cutting path block will preferentially pass through the second part, avoiding the situation where a large amount of metal located in the cutting path block cannot be disconnected under the traditional solution, thereby improving the product cutting yield without increasing the cost.

[0160] In summary, although the semiconductor devices and their manufacturing methods, as well as the memory and storage systems disclosed in some embodiments of the present application have been disclosed above, the above embodiments are not intended to limit the present application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. In addition to the above embodiments, the present application can also have other implementation methods. Any technical solution formed by equivalent replacement or equivalent replacement falls within the scope of protection required by this application. Therefore, the scope of protection of this application shall be based on the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor structure, the first semiconductor structure comprising a first device block and a first scribe line block adjacent to the first device block in a first direction; The first cutting path block includes at least one crack surface guiding structure extending along a second direction, the second direction intersects the first direction, and the crack surface guiding structure includes a first portion and a second portion extending along the second direction, and the second portion has a stronger crack surface passability than the first portion.

2. The semiconductor device according to claim 1, wherein: The second portion includes an air gap.

3. The semiconductor device according to claim 2, characterized in that The first portion includes two end portions in the second direction, and the first portion includes a first curved surface bordering the second portion, and the first curved surface is concave toward the first portion relative to the two end portions in the first direction.

4. The semiconductor device according to claim 2, characterized in that The first portion includes two ends in the second direction, and the second portion includes a gap between the first portion and a virtual cross section formed by the two ends of the first portion.

5. The semiconductor device according to claim 2, wherein: The first portion includes a first material, and the first material includes one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

6. The semiconductor device according to claim 1, wherein: The first portion includes a first material, the second portion includes a second material, and the Young's modulus of the second material is smaller than that of the first material.

7. The semiconductor device according to claim 6, characterized in that The first material or the second material includes one of polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

8. The semiconductor device according to claim 1, wherein: The first device block includes a first gate line isolation structure, the crack surface guiding structure includes a second gate line isolation structure, the second gate line isolation structure includes the first portion and the second portion, and the width of the second gate line isolation structure on a cross section in the first direction is greater than the width of the first gate line isolation structure on the cross section.

9. The semiconductor device according to claim 8, characterized in that The first scribe line block includes a plurality of stacked structures formed by alternately stacking gate layers and interlayer insulating layers in the second direction, and a channel structure or a virtual channel structure located in the stacked structure and spaced apart from the second gate line isolation structure.

10. The semiconductor device according to claim 9, characterized in that The first cutting path block includes a plurality of the channel structures or virtual channel structures and a plurality of the second gate line isolation structures, and the plurality of channel structures or virtual channel structures are alternately and spaced apart from the plurality of second gate line isolation structures in the first direction.

11. The semiconductor device according to claim 1, wherein: The first scribe line block includes a first X scribe line block adjacent to the device block in the first direction, and a first Y scribe line block adjacent to the device block in a third direction, wherein the third direction intersects with the first direction; The cleave plane guiding structure includes a first X cleave plane guiding structure located on the first X cleave street block and a first Y cleave plane guiding structure located on the first Y cleave street block.

12. The semiconductor device according to claim 1, wherein: The split surface guiding structure includes a first end in the second direction and a retracted portion away from the first end, and a transverse cross-sectional area of ​​the split surface guiding structure in the first direction gradually increases from the retracted portion toward the first end.

13. The semiconductor device according to claim 1, wherein: The semiconductor device also includes a second semiconductor structure, the second semiconductor structure includes a second device block and a second cutting road block, and the first device block and the second device block are stacked and bonded together in the second direction.

14. The semiconductor device according to claim 13, characterized in that The second scribe line block includes a silicon substrate.

15. The semiconductor device according to claim 13, wherein: The crack surface guide structure includes a first end in the second direction and a retracted portion away from the end, and a lateral cross-sectional area of ​​the crack surface guide structure in the first direction gradually expands from the retracted portion toward the first end, and the first end is closer to the second cutting path block of the second semiconductor device than the retracted portion.

16. The semiconductor device according to claim 13, wherein: The first cutting road block has a first thickness, the first device block has a second thickness, the second thickness is greater than the first thickness, and the back end surface of the first cutting road block away from the second cutting road block is concave relative to the end surface of the first device block on the same side as the back end surface.

17. A method for preparing a semiconductor device, characterized in that: include: Providing a first semiconductor structure, the first semiconductor structure comprising a first device block and a first scribe line block adjacent to the first device block in a first direction; At least one crack surface guiding structure extending along the second direction is formed in the first cutting line structure. The second direction intersects the first direction, and the crack surface guiding structure includes a first portion and a second portion extending along the second direction. The second portion has a stronger crack surface passability than the first portion.

18. The method for preparing a semiconductor device according to claim 17, characterized in that: The step of forming the crack surface guiding structure includes forming the first portion, and forming the second portion in the first portion, wherein the second portion includes an air gap.

19. The method for preparing a semiconductor device according to claim 18, characterized in that: The step of forming the crack surface guiding structure includes forming the first portion with a first material, and the first material includes one of polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

20. The method for preparing a semiconductor device according to claim 17, wherein: The step of forming the crack surface guiding structure includes first forming the first part with a first material, and then forming the second part with a second material inside the first part, wherein the Young's modulus of the second material is smaller than that of the first material.

21. The method for preparing a semiconductor device according to claim 20, characterized in that: The step of forming the first portion with a first material includes forming the first portion with one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide, and the step of forming the second portion with a second material includes forming the second portion with one of a polymer, silicon carbide (NDC), silicon nitride, ceramic (SiCN), and silicon oxide.

22. The method for preparing a semiconductor device according to claim 17, characterized in that: The step of forming a crack surface guiding structure includes forming a first gate line isolation structure in the first device block, and forming a second gate line isolation structure as the crack surface guiding structure in the first cutting road block and including the first part and the second part, and the width of the second gate line isolation structure on a cross section in the first direction is set to be greater than the width of the first gate line isolation structure on the cross section.

23. The method for preparing a semiconductor device according to claim 22, characterized in that: The step of forming the first cutting road block includes forming a plurality of stacked layers formed by alternately stacking sacrificial dielectric layers and interlayer insulating layers in the second direction, and a channel structure or a virtual channel structure located in the stacked layer and spaced from a preset position of the second gate line isolation structure.

24. The method for preparing a semiconductor device according to claim 23, characterized in that: The step of forming the crack surface guiding structure includes forming a plurality of the second gate line isolation structures, and arranging the plurality of the second gate line isolation structures in a spaced relationship from the channel structure or the virtual channel structure in the first direction.

25. The method for preparing a semiconductor device according to claim 17, characterized in that: The method further includes providing a second semiconductor structure, wherein the second semiconductor structure includes a second device block and a second scribe line block; And, the first device block and the second device block are stacked and bonded together in the second direction.

26. The method for preparing a semiconductor device according to claim 25, characterized in that: The step of providing a second semiconductor structure includes providing a silicon substrate, and the second scribe line block includes the silicon substrate.

27. The method for preparing a semiconductor device according to claim 25, characterized in that: The method also includes removing the end of the first cutting road block on the side away from the second cutting road block to form a first cutting road block with a thinned end face, and the thickness of the first cutting road block with the thinned end face in the second direction is less than the thickness of the first device block in the second direction.

28. A memory comprising: A memory array, wherein the memory array comprises the first semiconductor structure or the second semiconductor structure in the semiconductor device according to any one of claims 1 to 16, A peripheral circuit, wherein the peripheral circuit includes the first semiconductor structure or the second semiconductor structure in the semiconductor device according to any one of claims 1 to 7 and 13 to 16.

29. A storage system comprising: The memory as claimed in claim 28; as well as, A control device controls the operation of the memory.

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