Method of manufacturing semiconductor device and corresponding device

Abstract

The invention relates to a method of manufacturing a semiconductor device and a corresponding device. The semiconductor chip is covered by a non-LDS encapsulation material (i.e., an encapsulation material that does not include an LDS-activatable additive). One or more first vias are opened through the non-LDS encapsulation material toward the semiconductor chip. An LDS encapsulation material (i.e., an encapsulation material including an LDS-activatable additive) is molded on the non-LDS encapsulation material to fill the first via. One or more second vias aligned with the first vias are opened through the LDS encapsulation material toward the semiconductor chip. The second via has a liner of LDS encapsulation material. An electrical coupling formation for the semiconductor chip is provided via a laser direct structuring process of the LDS encapsulation material including a liner in the second via.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000020505, filed on October 4, 2023, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The specification relates to manufacturing semiconductor devices.

[0004] One or more embodiments may be applied to, for example, a micro-electromechanical system (MEMS) thermocouple generator including a fragile suspended membrane over a sealed cavity. Background Art

[0005] U.S. Patent Application Publication Nos. 2021 / 0305191 and 2023 / 035470, which are incorporated herein by reference, are examples of possible applications of laser direct structuring (LDS) technology in the manufacture of integrated circuit (IC) semiconductor devices.

[0006] Laser Direct Structuring (LDS), sometimes also referred to as Direct Copper Interconnect (DCI), is a technology based on the structuring of a plastic material by a laser source. The laser processed traces are then plated with a conductive material in order to provide a conductive pattern.

[0007] Laser induced stripe interconnect (LISI) is another name sometimes applied to this technology.

[0008] LISIPACK in STMicroelectronics TM In the product line, LDS mold compound is used to cover (encapsulate) the die, and the electrically conductive lines (vias, traces) are "molded" in the LDS mold compound.

[0009] In some specific applications, there may already be a non-LDS coating layer (tape, molded film, thick passivation, etc.) that is inherently incompatible with the LDS processing flow because that layer does not contain any LDS additives.

[0010] There is a need in the art to make contributions in solving the above-mentioned problems. Summary of the invention

[0011] One or more embodiments are directed to methods.

[0012] One or more embodiments relate to corresponding (integrated circuit, IC) semiconductor devices.

[0013] In one embodiment, the method includes: opening a via, e.g., via laser drilling, in a first non-LDS layer toward a metal (e.g., copper) pad in the die; filling the opened via in the non-LDS layer with an LDS molding compound (thus also closing the die package); reopening the via that was opened during the first step and then filled with the LDS molding compound, such that the via is lined with LDS material; and placing a standard LDS (e.g., LISIPACK) TM ) processing is applied to the LDS material to provide connection formations such as vias on leads and traces.

[0014] The solution described herein may be advantageously applied to, for example, a micro-electromechanical system (MEMS) thermocouple generator comprising a fragile suspended membrane over a sealed cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which Figures 1 to 5 is an example of a possible sequence of steps in a process for manufacturing an (integrated circuit, IC) semiconductor device. DETAILED DESCRIPTION

[0016] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0017] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the extent of the features.

[0018] In the following description, various specific details are illustrated to provide a deep understanding of various examples of the embodiments according to the description. The embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured.

[0019] Reference to "an embodiment" or "an embodiment" in the framework of this specification is intended to indicate that a specific configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment," "in an embodiment," and the like that may be present in various points of this specification do not necessarily refer to exactly one embodiment and the same embodiment. Furthermore, specific configurations, structures, or features may be combined in any appropriate manner in one or more embodiments.

[0020] The headings / references used herein are provided for convenience only and therefore do not define the extent of protection or the scope of the embodiments.

[0021] Recently, laser direct structuring (LDS), also often referred to as direct copper interconnect (DCI), has been added to the conventional scheme for providing interconnections in integrated circuit (IC) semiconductor devices, as exemplified by documents such as U.S. Patent Nos. 9,171,739 and 10,796,981 or U.S. Patent Application Publication No. 2016 / 0324009, all of which are incorporated herein by reference.

[0022] As discussed in the introductory part of this specification, LDS is a technology based on the shaping of plastic material by means of a laser source.

[0023] LDS is now widely used in a variety of industries in both the industrial and consumer electronics markets, for example for high-performance antenna integration, where antenna designs can be formed directly onto molded plastic parts.

[0024] In an exemplary process, molded parts can be produced using a commercially available insulating resin that includes additives suitable for LDS processing; currently a wide range of resins (such as polymer resins like PC, PC / ABS, ABS, LCP) and LDS additives (such as copper-based additives, copper-chromite seed-forming additives) can be used for that purpose.

[0025] A laser beam may be used to transfer ("shape" or "activate") a desired electrically conductive pattern onto an LDS mold compound, which may then undergo metallization to finalize the desired conductive pattern.

[0026] Metallization can involve electroless plating followed by electrolytic plating. Electroless plating, also known as chemical plating, is a class of industrial chemical processes that produce metal coatings on various materials by autocatalytic chemical reduction of metal cations in a liquid bath. In electrolytic plating, an electric field between an anode and a workpiece, which acts as a cathode, forces positively charged metal ions to move to the cathode, where they give up their charge and deposit themselves as metal on the surface of the workpiece.

[0027] LDS can be applied to IC packaging families where conventional wire bonds are replaced by copper plated vias and lines (traces).

[0028] Refer to U.S. Patent Application Publication Nos. 2021 / 0305191, 2023 / 0035470, 2018 / 0342453, 2019 / 0115287, 2020 / 0203264, 2020 / 0321274, 2021 / 0050226, 2021 / 0050299, 2021 / 0183748 or 2021 / 0305203A1 (all incorporated herein by reference), which are possible examples of applying LDS technology in manufacturing semiconductor devices.

[0029] For example, LDS technology facilitates replacing leads, clips or straps with lines / vias produced by laser beam processing of the LDS material followed by metallization (eg, growth of a metal such as copper via a plating process).

[0030] Electrically conductive couplings may be provided in the LDS material (e.g., once cured via thermal curing): such as through molded vias (TMVs) extending through the LDS package between electrically conductive pads at the front or top surface of the chip or die and / or corresponding leads in the lead frame; and such as electrically conductive lines or traces extending between the electrically coupled molded vias and the front or top surface of the LDS package to provide a desired electrical connection (routing) pattern.

[0031] Electrical components (eg, passive components such as resistors) may possibly be arranged along one or more lines or traces.

[0032] Providing such electrically conductive formations using LDS material therefore essentially involves: forming these formations in the LDS material at the desired locations (e.g. by laser drilling); and growing electrically conductive material (e.g. a metal such as copper) at the previously formed (activated) locations.

[0033] The associated back-end manufacturing may therefore involve a combination of laser machining, molding and plating processing steps in dedicated combinations using an LDS mold compound for covering and encapsulating the die.

[0034] Certain specific applications may involve specific non-LDS coatings, tapes, molded films, thick passivations, etc., which are already present on the semiconductor chip or die: this may be the case, for example, of a micro-electromechanical system (MEMS) thermocouple generator comprising a fragile suspended membrane over a sealed cavity.

[0035] In these applications, the protective layer may already exist as a thin layer of protective material that does not contain LDS additives that can be activated by the laser and therefore cannot be plated with metal (eg, copper) after laser drilling as specified in conventional LDS processing flows.

[0036] That is, these applications appear to be inherently incompatible with LDS processing because the encapsulation layer does not contain any LDS additives that can be activated (formed) and plated with an electrically conductive material such as copper.

[0037] The solution as described herein facilitates the application of LDS processing to these applications as well by "converting" other products that are not compatible with LDS processing into products to which LDS processing can be applied.

[0038] This may involve a dual drilling approach using a “bond” metal (e.g. Cu) deposition to integrate non-LDS layers into the LDS process (e.g. LISIPACK TM ).

[0039] In a solution as described herein, a (continuous) patch may be provided between the lead frame and the die pad which may be (copper) plated by forming one or more openings in the first non-LDS protective layer which are filled with LDS molding compound (in which “plateable” vias are formed).

[0040] Figures 1 to 5 is an example of a possible sequence of steps in a process for manufacturing an (integrated circuit, IC) semiconductor device.

[0041] in addition, Figures 1 to 5 The sequence of steps is exemplary only, to some extent: Figures 1 to 5 One or more of the steps illustrated in the drawings may be omitted, performed in a different manner (eg, with other tools) and / or replaced by other steps; and / or additional steps may be added.

[0042] In conjunction with the manufacture of an integrated circuit (IC) semiconductor device 10, Figures 1 to 5 An exemplary sequence of steps is provided for an integrated circuit (IC) semiconductor device 10 comprising a lead frame 12 having one or more (integrated circuit) chips or dies 14 attached to one or more die pads 12A in the lead frame 12, wherein electrically conductive leads 12B are wound around the die pads 12A, the die pads 12A having the die / dies 14 mounted thereon, wherein a metal (e.g., copper) pad 14A is provided at a front or top surface of the chip 14.

[0043] The designation lead frame or leadframe is currently used (see, e.g., the USPC Uniform Glossary of Terms by the U.S. Patent and Trademark Office) to indicate a metal frame that provides support (here at 12A) for a semiconductor chip or die (here 14) and electrical leads (here 12B) that are used to couple the semiconductor chip or die to other electrical components or contacts.

[0044] Essentially, the leadframe includes an array of electrically conductive formations, such as leads 12B, extending inwardly from a peripheral position in the direction of the semiconductor chip or die 14, thereby forming an array of electrically conductive formations originating from a die pad 12A that is configured to have at least one semiconductor chip or die attached thereto. This may be via a die attach adhesive, such as a die attach film (DAF).

[0045] For simplicity, a single chip or die 14 and a single lead 12B are shown in the drawings as mounted on a single die pad 12A; as used herein, the terms chip(s) and die / dies are considered synonymous.

[0046] As Figures 1 to 5 At the starting point of the exemplary sequence, the “intermediate” product is considered to include, in response to (otherwise conventional) manufacturing steps, a die 14 mounted on a die pad 12A in a lead frame 12, with a protective package 16 (already) molded thereon.

[0047] As illustrated, chip 14 includes electrically conductive pads 14A at a front or top surface thereof.

[0048] Package 16 includes non-LDS coating layers, tapes, mold films, thick passivation, etc., that are already present on the semiconductor chip or die.

[0049] Such non-LDS encapsulation material 16 (eg, epoxy) is readily identifiable and, therefore, distinguishable from LDS encapsulation material because it is essentially free of LDS additives such as, for example, copper-based additives, copper-chromite nucleating additives, and the like.

[0050] More generally, such non-LDS encapsulation materials are easily identifiable because they cannot be activated (molded) and plated with a metal such as copper due to the absence (or low content) of the LDS activatable additive.

[0051] A package 16 of non-LDS material covering the chip or die 14, 14A may be provided for various reasons, which are not specifically addressed in this discussion. By way of example, this may be the case of a micro-electromechanical system (MEMS) thermocouple generator comprising a fragile suspended membrane on a sealed cavity.

[0052] Figure 1The (otherwise conventional) structure of the product illustrated in is therefore an example of an application in which a (first) encapsulation 16 may already be present (as a thin layer of protective material), which (first) encapsulation 16 does not contain the LDS additive and therefore cannot be plated with metal (e.g. copper) after laser drilling as specified in a conventional LDS processing flow.

[0053] Figure 2 Yes Figure 1 An example of the product shown in FIG. 1 performing the first drilling step.

[0054] The purpose of this first drilling step (which may be performed via laser beam energy LB1, as is conventional in the art) is to open ("drill") the non-LDS package layer 16 and form therein one or more (first) vias 18 (also referred to as "openings" for simplicity), which extend from the front surface of the package 16 (opposite the lead frame 12) toward the front surface or top surface of the chip 14 (i.e., in the example illustrated here, toward the pad 14A).

[0055] Figure 2 The drilling step thus results in "opening" the protective layer 16 by forming one or more openings 18 therein (a single opening, essentially a hole, is shown for simplicity and ease of explanation).

[0056] Advantageously, these first vias 18 are opened through the non-LDS package 16 to as close as possible to the total actual metal pad area on the chip 14 (as represented here by pads 14A).

[0057] Figure 3 is molded in Figure 2 An example of a (second) package 20 of LDS material (of any type known to those skilled in the art) on a component of FIG.

[0058] That the package 20 is of LDS material means that, in contrast to the non-LDS package 16 , the package 20 contains an LDS activatable additive (a copper-based additive, a copper-chromite nucleating additive may again be indicated by way of example).

[0059] Due to the presence of the LDS activatable additive, the LDS package 20 can be activated (formed) and plated with a metal such as copper after laser drilling as specified in a conventional LDS processing flow.

[0060] Figure 3 The molding step (as discussed below, this step is Figure 2 and Figure 4) results in the LDS mold compound 20 being filled into the openings (vias) 18 opened in the non-LDS layer 16 .

[0061] The LDS molding compound 20 (which may be molded using any molding technique known to those skilled in the art for that purpose) thus closes the package and fills the openings 18 previously opened in the non-LDS layer 16 .

[0062] Figure 4 Yes Figure 3 An example of the product shown in FIG. 1 performing the second drilling step.

[0063] Figure 4 The second drilling step has the purpose of (partially) reopening the same passage 18 which was Figure 2 is opened (in the non-LDS layer 16) during the step of Figure 3 During the molding step of the via 18 is filled with LDS material 20 (suitable for plating within the framework of the LDS process). This second drilling step forms a (second) via 18 ′ (also referred to as “opening” for simplicity) through the LDS material 20 .

[0064] Application Figure 4 The wording "partially" in the second drilling step highlights the fact that the opening 18' is narrower (radially smaller) than the opening 18, which is Figure 4 During the second drilling step of the LDS material 20, the opening 18 is (re)opened. Figure 2 is formed in the non-LDS material during the first drilling step.

[0065] In that way, in Figure 4 The openings 18' which are (re)opened during the second drilling step have their inner walls lined (as indicated by reference numeral 200) with LDS material 20 (containing an LDS additive) in the Figure 3 is molded during the molding step.

[0066] In summary, in the method as described herein:

[0067] One or more vias 18 are opened in the non-LDS encapsulation material 16 (e.g., via a laser beam LB1) toward the semiconductor chip or chips 14, 14A: the exemplary semiconductor chip illustrated in the figure includes an electrically conductive front pad 14A, which is covered (encapsulated) by the non-LDS encapsulation material 16. As in Figure 2 Visible in, for example, opening (e.g. via laser beam drilling LB1) via 18 towards and down to the electrically conductive front pad 14A;

[0068] LDS encapsulation material 20 (i.e., material including an LDS-activatable additive) is molded onto the semiconductor chip(s) 14, 14A covered by the non-LDS encapsulation material 16 having the via(s) 18 opened therein toward the semiconductor chip(s) 14, 14A. In that manner, Figure 3 As illustrated in FIG. 1 , an LDS encapsulation material 20 including an LDS-activatable additive is filled into the via(s) 18 toward the semiconductor chip 14 , 14B; and

[0069] The via(s) 18 with the LDS encapsulation material (20) filled therein towards the semiconductor chip 14, 14A is partially reopened (eg via the laser beam LB2: see Figure 4 18' in the figure), and thus represents the liner 200 of the LDS encapsulation material.

[0070] Stated further, reopening the via(s) having the LDS encapsulation material 20 filled therein toward the semiconductor chip 14, 14A involves forming an opening(s) 18' in such LDS encapsulation material 20 that is larger than the via(s) 18 opened in the non-LDS material 16 (e.g., Figure 2 ) is narrower (having a smaller diameter size / cross-section).

[0071] Advantageously, similar Figure 2 The drilling step can be performed via the laser beam energy LB2 Figure 4 Another drilling step is performed as is conventional in the art.

[0072] At least in principle, it can be implemented in other ways Figure 2 A first "opening" step of the LDS material where the via is formed with a process other than laser drilling: etching for example is an example of those other processes. The first opening of the non-LDS material can be achieved with different techniques, since no activation is required in this case.

[0073] Figure 4 The second "opening" performed by laser drilling is advantageous because this also activates the LDS layer in the first opening ("well"): Figure 4 In the case of a step, laser beam drilling to reopen passage 18' is therefore advantageous, to the extent that laser beam energy LB2 can achieve the purpose of reopening ("re-drilling") passage 18' while activating the LDS material of liner 200 without the need for a different laser treatment to activate the LDS additive in the LDS material.

[0074] Although in Figure 2 and Figure 4 Different reference numerals are used (i.e., LB1 and LB2), but in Figure 4 The laser beam source used in the step may be Figure 2 The same laser beam source as in the steps.

[0075] This represents an advantageous option, to the extent that the same alignment of the same laser source with respect to the chip 14 / pad 16 can be employed with different focus adjustments (drill hole sizes).

[0076] Even if the first drilling step is performed on a non-molded leadframe and the second drilling step on a molded leadframe, the alignment datums can be the same in both instances. For example, they can be "ovals" on the edge of the leadframe in the area not reached by the molding compound.

[0077] The laser beam energy may be provided by the first beam LB1 during the opening of the via(s) 18 in the non-LDS encapsulation material 16, and by the second beam LB2 during the reopening of the via(s) 18' having the LDS encapsulation material 20 filled therein. Advantageously, the second beam LB2 is narrower than the first beam LB1, so that the reopened via(s) 18' is narrower than the via(s) 18 opened in the non-LDS encapsulation material 16 to form the liner 200.

[0078] As in a standard LDS process flow, the substrate may be processed (e.g., by plating via electroless / electrolytic plating) (e.g., by Figure 4 The lining 200 of LDS material is “activated” by the laser beam LB2) during the drilling in the second drilling step.

[0079] deal with Figure 2 and Figure 4 A combination of two steps (with Figure 3 The molding step) thus helps to convert similar Figure 1 Products shown in the figure are "recovered" for LDS processing, which would otherwise appear unsuitable for LDS processing.

[0080] Figure 2 and Figure 4 A combination of two steps (with Figure 3 The molding step) helps to provide electrical coupling for the semiconductor chips 14, 14A through laser direct molding, i.e., LDS processing of the LDS packaging material (i.e., packaging material including LDS-activatable additives) when the semiconductor chip is (already) covered by a non-LDS packaging material (i.e., packaging material that is not suitable for plating and is essentially free of LDS-activatable additives).

[0081] For example (such as Figure 5 ) may provide an electrically conductive formation to electrically couple the semiconductor chip(s) 14 to selected ones of the leads (outer pads) 12B in the lead frame 12.

[0082] like Figure 5 As illustrated in , electrical coupling formations 221, 222, 223 for semiconductor chips 14, 14A may be produced via laser direct structuring, ie, LDS processing of LDS encapsulation material 20. This includes applying the LDS treatment to the liner 200 of the reopened via(s) 18'.

[0083] like Figure 5 As shown in the figure, these coupling formations may include:

[0084] a first through molded via (TMV) 221 comprising a conductive material, such as copper, grown into the reopened via or vias 18 ′ extending between the top (front) surface 20A of the LDS encapsulation material 20 and an electrically-conductive pad 14A at the front or top surface of the chip or die 14 ;

[0085] A second through molded via (TMV) 222, comprising a conductive material grown into the (another) via 180, may be formed with Figure 4 The step of simultaneously forming the via 180 extending between the top (front) surface 20A of the LDS package 20 and the corresponding lead 12B in the lead frame 12; and

[0086] Electrically conductive lines or traces 223 include conductive material grown at the front or top surface 20A of the LDS package 20 and electrically coupling selected first vias 221 among the first vias 221 with selected second vias 222 among the second vias 222 to provide a desired electrical connection (routing) pattern between the chip or die 14 and the leads 12B.

[0087] Providing electrically conductive formations 221, 222, 223 essentially involves molding these formations (including an LDS "liner" 200 molding the vias 18', such as Figure 4 As illustrated in FIG. 1 , the via 18 ′ is partially reopened via laser beam energy), and electrically conductive material (eg, a metal such as copper) grows at the previously activated (formed) location.

[0088] For example, the electrical coupling formations for the semiconductor chips 14, 14A, such as molded through vias TMV 221, may be formed by laser activation (see Figure 4and growing an electrically conductive material (e.g., electroless plus electrolytic copper) in the reopened via 18' having an LDS additive activated (formed) by laser beam energy in the lining 200 of the LDS encapsulation material.

[0089] The relevant LDS processing may be along the lines of the solutions exemplified in the patent references cited at the beginning of this specification.

[0090] Without prejudice to the essential principles, the details and embodiments may vary, even significantly, with respect to those described above purely by way of example, without departing from the scope of protection.

[0091] The claims are an integral part of the technical teaching of the embodiments as provided herein.

[0092] The scope of protection is determined by the appended claims.

Claims

1. A method comprising: providing a semiconductor chip, wherein the semiconductor chip is covered by a first packaging material; Wherein, the first packaging material does not include a laser direct structuring (LDS) additive; opening a first via through the first encapsulation material to reach a conductive structure; molding a second encapsulation material on the first encapsulation material and filling the first via; wherein the second packaging material includes an LDS additive; opening a second via, the second via being aligned with the first via, the second via passing through the second packaging material to reach the conductive structure; wherein the second passage has an inner lining made of the second packaging material; and Electrical coupling to the conductive structure is provided via laser direct structuring of the second encapsulation material including the lining of the second via.

2. The method of claim 1, wherein opening the second passageway comprises applying laser beam energy, and wherein the liner is laser formed by the laser beam energy. The method of claim 1 , wherein the second passage is narrower than the first passage.

4. The method of claim 1, wherein opening the first pathway comprises applying laser beam energy, and wherein opening the second pathway comprises applying laser beam energy.

5. The method of claim 4, wherein the liner is laser formed by the laser beam energy.

6. The method of claim 4, wherein applying laser beam energy for opening the first passage comprises using a first laser beam, and wherein applying laser beam energy for opening the second passage comprises using a second laser beam, and wherein the second laser beam is narrower than the first laser beam.

7. The method of claim 6, wherein the first laser beam and the second laser beam have the same alignment and different focus adjustments. The method of claim 1 , wherein the conductive structure is a conductive pad on the semiconductor chip.

9. The method according to claim 1, wherein the second packaging material covers a lead frame, the semiconductor chip is mounted to the lead frame, the method further comprising: opening a third via through the second packaging material to reach the lead frame; as well as The second encapsulation material is processed via laser direct structuring to provide electrical coupling to the lead frame.

10. The method of claim 1, wherein providing an electrical coupling for the semiconductor chip comprises: laser activating the second encapsulating material in the lining of the second via; as well as An electrically conductive material is grown in the laser activated second via lined with a second encapsulation material to form an electrical coupling formation therein for the semiconductor chip.

11. An apparatus comprising: Semiconductor chips; a first packaging material, wherein the first packaging material covers the semiconductor chip; Wherein, the first packaging material does not include a laser direct structuring (LDS) additive; a first via extending in the first packaging material toward the semiconductor chip; a second encapsulating material molded over the first encapsulating material and present within the first via; wherein the second packaging material includes an LDS additive; a second via aligned with the first via, the second via extending through the second encapsulation material; wherein the second passage has an inner lining made of the second packaging material; and An electrical coupling for the semiconductor chip is provided via a laser directly structured electrically conductive structure at the lining of the second via.

12. The device according to claim 11, wherein the semiconductor chip includes an electrically conductive front pad, the electrically conductive front pad is covered by the first packaging material, wherein the first via extends toward the semiconductor chip and reaches the electrically conductive front pad, and wherein the second via extends toward the semiconductor chip and reaches the electrically conductive front pad.

13. The apparatus according to claim 11, further comprising: a lead frame to which the semiconductor chip is mounted; wherein the second packaging material covers the lead frame; a third via extending through the second packaging material to the lead frame; as well as An electrical coupling to the lead frame is provided via a laser directly structured electrically conductive structure at the third via.

14. The apparatus of claim 11, wherein the electrical coupling for the semiconductor chip comprises: a laser activated second encapsulating material lining the second via; as well as An electrically conductive material is grown in the second via at the laser activated second encapsulation material.

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