T-type three-level circuit test system, method, equipment and medium

Abstract

The present application relates to the field of device testing technology, and provides a testing system, method, device and medium for a T-type three-level circuit, wherein an upper vertical bridge unit and a lower vertical bridge unit are connected in series and then connected in parallel to two ends of an adjustable high-voltage direct current source, one end of a right bridge arm unit and a left bridge arm unit connected in series is connected to a reference ground, and the other end of the right bridge arm unit and the left bridge arm unit connected in series is connected to a series connection point of the upper vertical bridge unit and the lower vertical bridge unit; a driving circuit is used to send a double pulse test signal to one of the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit according to a double pulse test parameter; and other driving circuits are used to send driving signals to the remaining three of the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit respectively according to a driving control signal. Thus, the system can realize double pulse testing of the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit, and reduce the complexity of power device testing.

Description

Technical Field

[0001] The present application relates to the field of device testing technology, and in particular to a testing system, method, equipment and medium for a T-type three-level circuit. Background Art

[0002] As the demand for energy storage increases. The inverter (Power Conversion System, PCS) is an important component of the energy storage system, and most PCS use a T-type three-level topology. Compared with the traditional two-level converter, the T-type three-level topology has the advantages of small output harmonics, low device voltage stress, low electromagnetic interference, low loss and high efficiency. However, in the prior art, the test process for the power device of the T-type three-level topology is complicated. Summary of the invention

[0003] In view of this, the purpose of the present invention is to overcome the deficiencies in the prior art and provide a test system, method, device and medium for a T-type three-level circuit. The present invention provides the following technical solutions:

[0004] In a first aspect, the present invention provides a test system for a T-type three-level circuit, comprising: a T-type three-level main circuit and a plurality of drive circuits; the T-type three-level main circuit comprises: an adjustable high-voltage direct current source, a first bus capacitor, a second bus capacitor, a vertical bridge subcircuit, a horizontal bridge subcircuit and an inductor, the vertical bridge subcircuit comprises an upper vertical bridge unit and a lower vertical bridge unit, the upper vertical bridge unit and the lower vertical bridge unit are connected in series and then connected in parallel to the two ends of the adjustable high-voltage direct current source, the horizontal bridge subcircuit comprises a right bridge arm unit and a left bridge arm unit, one end of the right bridge arm unit and the left bridge arm unit connected in series is connected to a reference ground, the other end of the right bridge arm unit and the left bridge arm unit connected in series is connected to a series connection point of the upper vertical bridge unit and the lower vertical bridge unit, the adjustable high-voltage direct current source is connected to the first The bus capacitor is connected to the reference ground, and the adjustable high-voltage DC source is connected to the reference ground through the second bus capacitor; the inductor is connected in parallel with any one of the horizontal bridge sub-circuit, the upper vertical bridge unit and the lower vertical bridge unit; one driving circuit is used to send a double pulse test signal to the unit to be tested according to the double pulse test parameters; the unit to be tested is determined from the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit according to the parallel position of the inductor; the other driving circuits are used to send driving signals to each remaining unit according to the driving control signal, wherein the remaining units include the units in the vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit except the unit to be tested.

[0005] In a second aspect, the present invention provides a method for testing a T-type three-level circuit, which is applied to the testing system for the T-type three-level circuit described in the first aspect, and the method comprises:

[0006] Controlling a driving circuit to send a double pulse test signal to the unit under test according to the double pulse test parameters;

[0007] Control other driving circuits to send driving signals to the remaining units respectively according to the driving control signal;

[0008] The oscilloscope is controlled to receive test data from the unit under test, and output a pulse test result of the unit under test according to the test data.

[0009] In a third aspect, the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is run on the processor, the test method of the T-type three-level circuit described in the second aspect is executed.

[0010] In a fourth aspect, the present invention provides a computer storage medium storing a computer program, wherein when the computer program is executed on a processor, the test method of the T-type three-level circuit described in the second aspect is implemented.

[0011] The present invention provides a test system, method, device and medium for a T-type three-level circuit, wherein a driving circuit sends a double-pulse test signal to the unit to be tested according to a double-pulse test parameter; other driving circuits send driving signals to the remaining units according to a driving control signal. The driving circuit electrically connected to the remaining units sends driving signals to the remaining units according to the driving control signal. Thus, a double-pulse test of the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit can be implemented through a testing system, and the performance parameters of the power device under actual operation can be obtained. Multiple models of power devices can be tested synchronously, reducing the complexity of power device testing, providing a convenient and flexible testing solution, improving testing efficiency, and saving testing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope of protection of the present application. For ordinary technicians in this field, other related drawings can also be obtained based on these drawings without creative work.

[0013] Figure 1 A structural schematic diagram of an existing T-type three-level test platform is shown;

[0014] Figure 2 A structural schematic diagram of an existing T-type three-level main circuit is shown;

[0015] Figure 3A schematic diagram of the structure of a test system for a T-type three-level circuit provided by an embodiment of the present invention is shown;

[0016] Figure 4 A schematic diagram of the structure of a T-type three-level main circuit provided by an embodiment of the present invention is shown;

[0017] Figure 5 Another structural schematic diagram of a T-type three-level main circuit provided by an embodiment of the present invention is shown;

[0018] Figure 6 Another structural schematic diagram of a T-type three-level circuit test system provided by an embodiment of the present invention is shown;

[0019] Figure 7 A schematic diagram of a setting process of a host computer provided by an embodiment of the present invention is shown;

[0020] Figure 8 A schematic diagram of an interface of a host computer provided by an embodiment of the present invention is shown;

[0021] Fig. 9 A control logic schematic diagram of a switch tube provided by an embodiment of the present invention is shown;

[0022] Fig.10 A schematic diagram of a current path of a T-type three-level main circuit provided by an embodiment of the present invention is shown;

[0023] Fig.11 Another current path schematic diagram of a T-type three-level main circuit provided by an embodiment of the present invention is shown;

[0024] Fig.12 Another structural schematic diagram of a T-type three-level main circuit provided by an embodiment of the present invention is shown;

[0025] Fig.13 A schematic diagram of a driving current structure provided by an embodiment of the present invention is shown;

[0026] Fig.14 A schematic diagram of a power supply circuit provided by an embodiment of the present invention is shown;

[0027] Fig.15 Another structural schematic diagram of a T-type three-level main circuit provided by an embodiment of the present invention is shown;

[0028] Fig.16 A schematic diagram of a measured waveform provided by an embodiment of the present invention is shown;

[0029] Fig.17 Another schematic diagram of a measured waveform provided by an embodiment of the present invention is shown;

[0030] Fig.18A schematic flow chart of a method for testing a T-type three-level circuit provided in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0032] In power electronic systems, designers often need to select the best power device or design the best drive circuit parameters according to different power device models, or need to match different drive circuits for the same power device model, and evaluate the switching performance of the power device. However, the parameters in the specifications of power devices such as insulated gate bipolar transistor (IGBT) with reverse resistance, metal-oxide-semiconductor field-effect transistor (MOS), and silicon carbide (SiC) MOS, the third generation of wide bandgap semiconductor materials, are data tested under specific conditions and may not represent the actual performance in actual applications, so these parameters cannot be used directly. Therefore, performance testing of power devices such as IGBT, MOS, and SiC MOS is particularly important. There are many performance parameters describing power devices such as IGBT, MOS, SiC MOS, such as the recovery time and recovery loss of the freewheeling diode, di / dt, dv / dt, Eon, Eoff, td(on), tr, td(off), tf, etc. of IGBT, MOS, SiC MOS. The double pulse test method is a relatively effective method to observe the performance parameters of power devices in actual applications.

[0033] The traditional double pulse test method for power devices only provides a test circuit or test pulse in a certain situation. For example, the existing T-type three-level topology structure is composed of multiple power devices with the same package type, and it is impossible to fully test the power devices in the T-type three-level topology structure according to the actual operating status. Figure 1 , Figure 1It is a structural diagram of an existing T-type three-level double pulse test platform. The DUT-T type three-level circuit 2 is electrically connected to the driving module 9 and the DC high voltage source 1 respectively. The driving module 9 is also electrically connected to the DC low voltage source 6 and the signal generator 8. The DC low voltage source 6 is also electrically connected to the mains equipment 7. The mains equipment 7 is also electrically connected to the DC high voltage source 1 and the signal generator 8. The signal generator 8 is an external device for providing a PWM pulse signal. The driving module 9 needs to be powered by an external DC low voltage source 6, and there is no size adjustment function and limit protection function for the driving voltage of the driving module 9 in the existing T-type three-level double pulse test platform. When the driving voltage needs to be debugged, it can only be adjusted by adjusting the external DC low voltage source 6, which is easy to cause the driving voltage to be artificially adjusted too high, resulting in exceeding the limit of the power device of the DUT-T type three-level circuit 2, and damaging the power device.

[0034] See also Figure 2 , is a structural schematic diagram of an existing DUT-T type three-level circuit 2, the DUT-T type three-level circuit 2 includes a first DC high-voltage source B0, a bridge arm to be measured, and a first voltage-dividing capacitor C1a and a second voltage-dividing capacitor C2a, the bridge arm to be measured includes a vertical bridge and a horizontal bridge, the upper bridge arm switch tube S1a of the vertical bridge is connected in series with the lower bridge arm switch tube S2a and then connected in parallel to the two ends of the first DC high-voltage source B0, one end of the right bridge arm switch tube S3a and the left bridge arm switch tube S4a of the horizontal bridge is connected in series to the reference ground P11, the other end of the right bridge arm switch tube S3a and the left bridge arm switch tube S4a is connected in series to the series connection point P33 of the upper bridge arm S1a and the lower bridge arm S2a of the vertical bridge, the positive electrode of the first DC high-voltage source B0 is connected to the reference ground P11 through the first voltage-dividing capacitor C1a, and the negative electrode of the first DC high-voltage source B0 is connected to the reference ground P11 through the second voltage-dividing capacitor C2a. The upper bridge arm switch tube S1a is connected in parallel with the first voltage-dividing capacitor C1a at the parallel connection point P22, and the lower bridge arm switch tube S2a is connected in parallel with the second voltage-dividing capacitor C2a at the parallel connection point P44. As required, the inductor L0 can be connected in parallel between the parallel connection point P22 and the series connection point P33, or the inductor L0 can be connected in parallel between the series connection point P33 and the parallel connection point P44, or the inductor L0 can be connected in parallel between the reference ground P11 and the series connection point P33. The upper bridge arm switch tube S1a is connected in parallel with the freewheeling diode D1, the lower bridge arm switch tube S2a is connected in parallel with the freewheeling diode D2, the right bridge arm switch tube S3a is connected in parallel with the freewheeling diode D3, and the left bridge arm switch tube S4a is connected in parallel with the freewheeling diode D4. The upper bridge arm switch tube S1a, the lower bridge arm switch tube S2a, the right bridge arm switch tube S3a and the left bridge arm switch tube S4a can only be of the same package model, and the compatibility is relatively low. When testing a power device of another package model, additional circuit design is required.

[0035] To solve the above problems, the present application provides a T-type three-level circuit testing system, which is used for the selection of power devices, tests the performance of power devices in actual applications, obtains more realistic test data, and reduces the testing complexity of the T-type three-level circuit.

[0036] See also Figure 3 The test system of the T-type three-level circuit provided in this embodiment includes: a T-type three-level main circuit 310 and a plurality of driving circuits 320. The T-type three-level main circuit includes: an adjustable high-voltage DC source B1, a first bus capacitor C1, a second bus capacitor C2, a vertical bridge subcircuit Q12, a horizontal bridge subcircuit Q34 and an inductor L1. The vertical bridge subcircuit Q12 includes an upper vertical bridge unit Q1 and a lower vertical bridge unit Q2, the upper vertical bridge unit Q1 and the lower vertical bridge unit Q2 are connected in series and then connected in parallel to the two ends of the adjustable high-voltage DC source B1, and the horizontal bridge subcircuit Q34 includes a right bridge arm unit Q3 and a left bridge arm unit Q4, one end of the right bridge arm unit Q3 and the left bridge arm unit Q4 connected in series is connected to the reference ground P1, and the other end of the right bridge arm unit Q3 and the left bridge arm unit Q4 connected in series is connected to the series connection point P3 of the upper vertical bridge unit Q1 and the lower vertical bridge unit Q2. The adjustable high-voltage DC source B1 is connected to the reference ground P1 through the first bus capacitor C1, and the adjustable high-voltage DC source B1 is connected to the reference ground P1 through the second bus capacitor C2. The inductor L1 is connected in parallel with any one of the cross bridge sub-circuit Q34, the upper vertical bridge unit Q1 and the lower vertical bridge unit Q2. Figure 3 In the circuit, the inductor L1 and the upper vertical bridge unit Q1 are connected in parallel. Figure 4 In the circuit, the inductor L1 and the lower vertical bridge unit Q2 are connected in parallel. Figure 5 In the embodiment, the inductor L1 and the cross-bridge sub-circuit Q34 are connected in parallel.

[0037] In this embodiment, the number of the driving circuits 320 is determined according to the vertical bridge subcircuit Q12 and the horizontal bridge subcircuit Q34. For example, the number of the driving circuits 320 is 4, and one driving circuit 320 is electrically connected to the upper vertical bridge unit Q1, the lower vertical bridge unit Q2, the left bridge arm unit Q4, and the right bridge arm unit Q3, respectively.

[0038] In this embodiment, the inductor L1 can be connected in parallel with any one of the horizontal bridge subcircuit Q34, the upper vertical bridge unit Q1 and the lower vertical bridge unit Q2 according to the test requirements, and a unit to be tested is determined from the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit according to the positional relationship of the parallel connection between the inductor L1 and any one of the horizontal bridge subcircuit Q34, the upper vertical bridge unit Q1 and the lower vertical bridge unit Q2. The units other than the unit to be tested in the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit are determined as the remaining units. That is, based on the three different parallel positions of the inductor L1, the unit to be tested and the remaining units correspond to three situations respectively.

[0039] The first case, such as Figure 3 As shown, the inductor L1 and the upper vertical bridge unit Q1 are connected in parallel, the unit to be tested includes the left bridge arm unit Q4, and the remaining units include the upper vertical bridge unit Q1, the lower vertical bridge unit Q2 and the right bridge arm unit Q3. Among them, the upper vertical bridge unit Q1 includes at least two upper bridge arm switch tubes (for example, Figure 3 The upper bridge arm switch tubes Q1A and Q1B in the embodiment of the present invention are provided. The lower vertical bridge unit Q2 includes at least two lower bridge arm switch tubes (for example, Figure 3 The right bridge arm unit Q3 includes at least two right bridge arm switch tubes (for example, Figure 3 The left bridge arm unit Q4 includes at least two left bridge arm switch tubes (for example, Figure 3 The left bridge arm switch tubes Q4A and Q4B in the figure). The upper bridge arm switch tubes are of different models, the lower bridge arm switch tubes are of different models, the left bridge arm switch tubes are of different models, and the right bridge arm switch tubes are of different models.

[0040] It should be noted that the first drive circuit 320 is electrically connected to the control ends of the upper bridge arm switch tubes Q1A and Q1B, the second drive circuit 320 is electrically connected to the control ends of the lower bridge arm switch tubes Q2A and Q2B, the third drive circuit 320 is electrically connected to the control ends of the right bridge arm switch tubes Q3A and Q3B, and the fourth drive circuit 320 is electrically connected to the left bridge arm switch tubes Q4A and Q4B. In this way, one drive circuit 320 can realize the drive control of multiple switch tubes, reduce the complexity of the test circuit, reduce costs, and improve test efficiency.

[0041] For example, the upper bridge arm switch tube Q1A, the lower bridge arm switch tube Q2A, the right bridge arm switch tube Q3A, and the left bridge arm switch tube Q4A are of the same package model TO-247-3. The upper bridge arm switch tube Q1B, the lower bridge arm switch tube Q2B, the right bridge arm switch tube Q3B, and the left bridge arm switch tube Q4B are of the same package model TO-247-4. The switch tube can also be of other package models, which is not limited here. In this way, the test system of the T-type three-level circuit can realize the test of power devices of various different package models, with high compatibility, no need for additional circuit design, and reduce test cost and test complexity.

[0042] In the second case, see Figure 4When the inductor L1 and the lower vertical bridge unit Q2 are connected in parallel, the unit to be tested includes the right bridge arm unit Q3, and the remaining units include the upper vertical bridge unit Q1, the lower vertical bridge unit Q2 and the left bridge arm unit Q4. Among them, the upper vertical bridge unit Q1 includes at least two upper bridge arm switch tubes Q1A and Q1B connected in parallel, the lower vertical bridge unit Q2 includes lower bridge arm switch tubes Q2A and Q2B connected in parallel, the right bridge arm unit Q3 includes right bridge arm switch tubes Q3A and Q3B connected in parallel; the left bridge arm unit Q4 includes left bridge arm switch tubes Q4A and Q4B connected in parallel. Each switch tube is connected in parallel with a corresponding freewheeling diode.

[0043] Specifically, the upper bridge arm switch tube Q1A is connected in parallel with the freewheeling diode D1A, the lower bridge arm switch tube Q2A is connected in parallel with the freewheeling diode D2A, the right bridge arm switch tube Q3A is connected in parallel with the freewheeling diode D3A, and the left bridge arm switch tube Q4A is connected in parallel with the freewheeling diode D4A. The upper bridge arm switch tube Q1B is connected in parallel with the freewheeling diode D1B, the lower bridge arm switch tube Q2B is connected in parallel with the freewheeling diode D2B, the right bridge arm switch tube Q3B is connected in parallel with the freewheeling diode D3B, and the left bridge arm switch tube Q4B is connected in parallel with the freewheeling diode D4B.

[0044] For the third case, see Figure 5 When the inductor L1 and the cross-bridge subcircuit Q34 are connected in parallel, the unit to be tested includes the upper vertical bridge unit Q1 or the lower vertical bridge unit Q2. The remaining units include the lower vertical bridge unit Q2, the right bridge arm unit Q3 and the left bridge arm unit Q4. Alternatively, the remaining units include the upper vertical bridge unit Q1, the right bridge arm unit Q3 and the left bridge arm unit Q4.

[0045] In this embodiment, a driving circuit 320 electrically connected to the unit to be tested is used to send a double pulse test signal to the unit to be tested according to the double pulse test parameters; other driving circuits electrically connected to the remaining units are used to send drive signals to the remaining units according to the drive control signal. Thus, a double pulse test of the upper vertical bridge unit Q1, the lower vertical bridge unit Q2, the right bridge arm unit Q3 and the left bridge arm unit Q4 can be implemented through a test system, the performance parameters of the power device under actual operation can be obtained, and multiple models of power devices can be tested simultaneously, reducing the complexity of power device testing, providing a convenient and flexible test solution, improving test efficiency, and saving test time.

[0046] In addition, in the prior art, before performing dual pulse tests on IGBT, MOS, SiC MOS and other switch tubes, it is necessary to debug and obtain the turn-on current and turn-off current of the simulated switch tube in the actual circuit. During the adjustment process of the existing T-type three-level dual pulse test platform, the duty cycle of the first pulse is continuously adjusted by an external signal generator so that the turn-on current value of the power device reaches the required test value, and the turn-off current of the power device is adjusted by adjusting the duty cycle of the second pulse to reach the required test value.

[0047] The prior art adjustment method needs to adjust the signal generator, which is cumbersome, inflexible, and time-consuming. It requires familiarity with the use of the signal generator, and the user has high requirements. When the different operating states of the T-type three-level need to be tested, the driving signal of the signal generator needs to be re-matched or the corresponding driving circuit needs to be built, which brings inconvenience to the tester. At the same time, the signal generator also needs to be purchased additionally, which brings huge economic pressure to the company or individual. The driving voltage of the driving circuit is not adjustable or needs to be adjusted by an external power supply, and the driving circuit has no clamping circuit (that is, no voltage limit is set). During the test, it is easy to damage the power devices such as IGBT, MOS and SiC MOS under test due to artificial misadjustment of the driving voltage (especially SiC MOS is sensitive to the driving voltage, and the driving voltage cannot exceed the limit, otherwise it will be damaged).

[0048] In this regard, the present application is further improved to provide Figure 6 The test system of the T-type three-level circuit shown in FIG. Figure 3 The test system for T-type three-level circuits provided is different in that: Figure 6 The test system for the T-type three-level circuit further includes a control circuit 330 , a host computer 340 , a power supply circuit 350 , a mains device 360 ​​, an external DC voltage source 370 , an oscilloscope 380 , a voltage probe 381 and a current probe 382 .

[0049] The host computer 340 is electrically connected to the control circuit 330, and the control circuit 330 is also electrically connected to the power supply circuit 350 and each drive circuit 320, and the power supply circuit 350 is also electrically connected to the external DC voltage source 370, and the external DC voltage source 370 is also electrically connected to the mains device 360. The oscilloscope 380 is electrically connected to the T-type three-level main circuit 310 through a voltage probe 381 and a current probe 382.

[0050] It is further explained that the host computer 340 is used to set the working state of the T-type three-level main circuit 310, and to set the double pulse test parameters and drive control signals in the working state, and to send the double pulse test parameters and drive control signals to the control circuit 330. Among them, the host computer 340 can be an RS232 host computer, which is not limited here. By issuing corresponding control instructions to the host computer 340, different working states and different test requirements of the power devices of the T-type three-level main circuit 310 can be met, without the need for an additional signal generator, and the control is more flexible and convenient.

[0051] The double pulse test parameters include the switching frequency and pulse dead zone of the double pulse test signal, the first duty cycle of the first pulse signal of the double pulse test signal, and the second duty cycle of the second pulse signal of the double pulse test signal. The first duty cycle is the duty cycle that makes the turn-on current of the switch tube on the main test loop path where the unit to be tested is located reach the first preset current range; the second duty cycle is the duty cycle that makes the turn-off current of the switch tube on the main test loop path where the unit to be tested is located reach the second preset current range. The first preset current range and the second preset current range can be determined according to actual conditions and are not limited here.

[0052] Combine the following Figure 7-Figure 8 The setting process of the host computer 340 is described.

[0053] See also Figure 7 , Figure 7 FIG. 1 is a schematic diagram of a setting process of a double pulse test signal provided in this embodiment, including:

[0054] Step S701 , adjusting the driving voltage by adjusting the driving circuit 320 .

[0055] In this embodiment, combined with Figure 6 After the power supply circuit 350 provides a +12V power supply to the driving circuit 320, the required driving voltage value is obtained by adjusting the adjustable resistance positioner of the driving circuit 320, thereby obtaining the driving voltage.

[0056] Step S702, determining whether the driving voltage reaches a required value.

[0057] Specifically, if yes, execute step S703, if no, return to step S701.

[0058] Step S703: the host computer 340 sets the switching frequency.

[0059] Step S704: the host computer 340 sets a duty dead zone.

[0060] Step S705: the host computer 340 adjusts the first pulse duty cycle.

[0061] Step S706, determining whether the turn-on current reaches a required value.

[0062] Specifically, if yes, execute step S707, if no, return to step S705.

[0063] In this way, the switching frequency fs and driving dead zone required for the test are set by the host computer 340, and then the duty cycle of the first pulse is adjusted by the host computer 340 so that the turn-on current value of the power device on the main test loop path where the unit under test is located reaches the required test value.

[0064] Step S707: the host computer 340 adjusts the second pulse duty cycle.

[0065] Step S708, determining whether the shutdown current reaches a required value.

[0066] Specifically, if yes, execute step S709, if no, return to step S707.

[0067] Step S709, start double pulse test.

[0068] In this way, by adjusting the duty cycle of the second pulse, the off current of the switch tube on the main test loop path where the unit under test is located reaches the required test value. When testing different working states of the switch tube, it is only necessary to set the corresponding state in the status bar of the host computer 340, which makes the control more flexible and the test more convenient.

[0069] See also Figure 8 The control interface diagram of the host computer 340 includes multiple status bars that can be set, status bar 1: switch 1 / 0. Status bar 2: first pulse duty cycle setting, status bar 3: first pulse dead zone setting, status bar 4: second pulse duty cycle setting, status bar 5: second pulse dead zone setting, status bar 11: operation working state setting ("1", "2", "3", "4"), status bar 12: switch frequency setting. The control display interface of the host computer 340 can directly set parameter information, avoiding the tedious process of manually adjusting pulse parameters.

[0070] See also Fig. 9 , is the double pulse drive logic diagram for testing the left bridge arm switch tube Q4A. The two PWM pulse wave signals of the left bridge arm switch tube Q4A (Q4B) are complementary to the drive signal of the upper bridge arm switch tube Q1A (Q1B); the drive signal of the lower bridge arm switch tube Q2A (Q2B) is normally low; the drive signal of the right bridge arm switch tube Q3A (Q3B) is normally high. The high level duration t1 of the first PWM pulse wave signal of the left bridge arm switch tube Q4A (Q4B), the dead time tx, the low level duration t2 of the first PWM pulse wave signal of the left bridge arm switch tube Q4A (Q4B). The high level duration t3 of the second PWM pulse wave signal of the left bridge arm switch tube Q4A (Q4B), the high level duration t2-2·tx of the first PWM pulse wave signal of the upper bridge arm switch tube Q1A (Q1B). The following takes the test of the left bridge arm switch tube Q4A (Q4B) as an example for explanation.

[0071] See also Fig.10, inductor L1 is connected in parallel between the parallel connection point P2 and the series connection point P3. The first drive circuit 320 provides two PWM pulse wave signals to the left bridge arm switch tube Q4A (Q4B). The drive signal provided by the second drive circuit 320 to the upper bridge arm switch tube Q1A (Q1B) is complementary to the pulse wave signal of the left bridge arm switch tube Q4A (Q4B). The drive signal provided by the third drive circuit 320 to the lower bridge arm switch tube Q2A (Q2B) is normally low. The drive signal provided by the fourth drive circuit 320 to the right bridge arm switch tube Q3A (Q3B) is normally high (such as Fig. 9 shown).

[0072] When the left bridge arm switch tube Q4A is used as the switch tube to be tested, when the left bridge arm switch tube Q4A inputs the first pulse wave, the left bridge arm switch tube Q4A is turned on, and the current of the inductor L1 rises. When the first pulse wave is turned off, the left bridge arm switch tube Q4A is turned off, and the inductor L1 slowly decays through the upper bridge arm switch tube Q1A. When the second pulse wave arrives, the left bridge arm switch tube Q4A is turned on again, the current of the inductor L1 continues to rise, and the freewheeling diode D1A of the upper bridge arm switch tube Q1A enters the reverse recovery state. In this way, the double pulse test signal can be set through the host computer without a signal generator, which simplifies the setting process and makes the test more flexible and convenient. At the same time, the host computer can be set to quickly test different operating states to meet different test requirements.

[0073] It should be noted that since the left bridge arm switch tube Q4A and the left bridge arm switch tube Q4B are connected in parallel and receive the drive control of the same drive circuit 320, the upper bridge arm switch tube Q1A (Q1B) is connected in parallel and receives the drive control of the same drive circuit 320, the lower bridge arm switch tube Q2A (Q2B) is connected in parallel and receives the drive control of the same drive circuit 320, and the right bridge arm switch tube Q3A (Q3B) is connected in parallel and receives the drive control of the same drive circuit 320, therefore, when testing the left bridge arm switch tube Q4A, the left bridge arm switch tube Q4B is tested synchronously, and the test process of the left bridge arm switch tube Q4B is the same as that of the left bridge arm switch tube Q4A, which will not be repeated here.

[0074] See also Fig.11, the following is an example of testing the right bridge arm switch tube Q3A (Q3B). The inductor L1 is connected in parallel between the series connection point P3 and the parallel connection point P4. The first drive circuit 320 provides two PWM pulse wave signals to the left bridge arm switch tube Q3A (Q3B). The second drive circuit 320 provides a drive signal to the lower bridge arm switch tube Q2A (Q2B) that is complementary to the pulse wave signal of the right bridge arm switch tube Q4A (Q4B). The third drive circuit 320 provides a drive signal to the upper bridge arm switch tube Q1A (Q1B) that is normally low. The fourth drive circuit 320 provides a drive signal to the left bridge arm switch tube Q4A that is normally high. When the right bridge arm switch tube Q3A is used as the unit to be tested, when the first pulse wave is input to the right bridge arm switch tube Q3A, the right bridge arm switch tube Q3A is turned on, and the current of the inductor L1 rises. When the first pulse wave is turned off, the right bridge arm switch tube Q3A is turned off, and the inductor L1 slowly decays through the lower bridge arm switch tube Q2A. When the second pulse wave arrives, the right bridge arm switch tube Q3A is turned on again, the current of the inductor L1 continues to rise, and the freewheeling diode D2A of the lower bridge arm switch tube Q2A enters the reverse recovery state. When testing the right bridge arm switch tube Q3A, the right bridge arm switch tube Q3B is tested synchronously. The test process of the right bridge arm switch tube Q3B is the same as that of the right bridge arm switch tube Q3A, so it will not be repeated here.

[0075] See also Fig.12 When testing the upper bridge arm switch tube Q1A (Q1B), the inductor L1 is connected in parallel between the series connection point P3 and the reference ground P1, and the first drive circuit 320 provides two PWM pulse wave signals to the upper bridge arm switch tube Q1A (Q1B), and the other drive circuits 320 provide corresponding drive signals to the lower bridge arm switch tube Q2A (Q2B), the right bridge arm switch tube Q3A (Q3B), and the left bridge arm switch tube Q4A (Q4B) according to the test requirements. In addition, when testing the lower bridge arm switch tube Q2A (Q2B), the inductor L1 is also connected in parallel between the series connection point P3 and the reference ground P1, and the first drive circuit 320 provides two PWM pulse wave signals to the lower bridge arm switch tube Q2A (Q2B), and the other drive circuits 320 provide corresponding drive signals to the upper bridge arm switch tube Q1A (Q1B), the right bridge arm switch tube Q3A (Q3B), and the left bridge arm switch tube Q4A (Q4B) according to the test requirements. When testing the upper bridge arm switch tube Q1A, the upper bridge arm switch tube Q1B is tested synchronously, and when testing the lower bridge arm switch tube Q2A, the lower bridge arm switch tube Q2B is tested synchronously.

[0076] See also Fig.13The driving circuit 320 includes: a boost isolation subcircuit 321, an adjustable linear voltage stabilization subcircuit 322 and a driving isolation subcircuit 323; a power supply circuit 350 is electrically connected to the boost isolation subcircuit 321 and is used to input an initial voltage to the boost isolation subcircuit 321; the boost isolation subcircuit 321 is also electrically connected to the adjustable linear voltage stabilization subcircuit 322 and is used to boost the initial voltage to obtain a boost voltage and send the boost voltage to the adjustable linear voltage stabilization subcircuit 322; the adjustable linear voltage stabilization subcircuit 321 is also electrically connected to the driving isolation subcircuit 323 The drive isolation subcircuit 323 is electrically connected to adjust the boost voltage to obtain a target voltage and send the target voltage to the drive isolation subcircuit 323; the drive isolation subcircuit 323 is also electrically connected to the control circuit 330 to receive a double pulse test parameter or a drive signal from the control circuit 330; the drive isolation subcircuit 323 is also electrically connected to a target unit among the upper vertical bridge unit Q1, the lower vertical bridge unit Q2, the right bridge arm unit Q3 and the left bridge arm unit Q4 to send a double pulse test signal or a drive control signal to the target unit according to the double pulse test parameter or the drive signal.

[0077] Exemplarily, in the first case described above, the inductor L1 is connected in parallel with the upper vertical bridge unit Q1, the unit to be tested includes the left bridge arm unit Q4, and the remaining units include the upper vertical bridge unit Q1, the lower vertical bridge unit Q2 and the right bridge arm unit Q3. If a driving circuit 320 is electrically connected to the left bridge arm unit Q4, the driving circuit 320 provides a double pulse test signal to the left bridge arm switch tubes Q4A and Q4B of the left bridge arm unit Q4. If a driving circuit 320 is electrically connected to one of the upper vertical bridge unit Q1, the lower vertical bridge unit Q2 and the right bridge arm unit Q3, the driving circuit 320 provides a corresponding driving signal to one of the upper vertical bridge unit Q1, the lower vertical bridge unit Q2 and the right bridge arm unit Q3. The oscilloscope 380 is electrically connected to the unit to be tested through a voltage probe and a current probe, and the oscilloscope 380 is used to receive test data from the unit to be tested and output the pulse test result of the unit to be tested according to the test signal. For example, the oscilloscope 380 is electrically connected to the left bridge arm unit Q4 through a voltage probe and a current probe, and is used to detect the test signals of each switch tube of the left bridge arm unit Q4, and obtain the pulse test results of the left bridge arm switch tubes Q4A and Q4B. The oscilloscope 380 can also be electrically connected to the corresponding freewheeling diode through a voltage probe and a current probe, and the recovery time and recovery loss of the corresponding freewheeling diode can be detected through the oscilloscope 380.

[0078] The test system for the T-type three-level circuit provided in this embodiment is more flexible and convenient to test, has wider compatibility, higher efficiency, and more authentic test data. In addition, the test system for the T-type three-level circuit provided in this embodiment can test a more comprehensive working state, which is of great significance for designers to select or verify whether the designed circuit is correct and to ensure the long-term reliable operation of the inverter PCS.

[0079] Please see again Fig.13 , the boost isolation sub-circuit 321 includes a boost isolation chip U1 and an input filter capacitor C10. The input terminal VIN of the boost isolation chip U1 is electrically connected to the output terminal of the power supply circuit 350, and the boost isolation chip U1 receives the 12V DC voltage input by the power supply circuit 350. The input terminal VIN of the boost isolation chip U1 and the ground terminal GND and the input filter capacitor C10 are connected in parallel, and the first output terminal VO of the boost isolation chip U1 is electrically connected to the input terminal of the adjustable linear voltage stabilization sub-circuit 322. The boost isolation chip U1 is used to isolate the initial voltage input by the boost power supply circuit 350. It can be understood that when the initial voltage fluctuates, it will have an adverse effect on the subsequent circuit, such as overvoltage damage, etc. The boost isolation chip U1 can improve the test safety of the power device.

[0080] The adjustable linear voltage regulator sub-circuit 322 includes an adjustable linear voltage regulator chip U2, an adjustable resistor RP1 and a fixed resistor R2; the adjustable linear voltage regulator chip U2 is electrically connected to the boost isolation sub-circuit 321, the active end of the adjustable resistor RP1, the first end of the fixed resistor R2 and the drive isolation sub-circuit 323. Exemplarily, the IN pin of the adjustable linear voltage regulator chip U2 is electrically connected to the first output end VO of the boost isolation chip U1, and the VJDJ pin of the adjustable linear voltage regulator chip U2 is electrically connected to the second output end OV of the boost isolation chip U1 and the active end of the adjustable resistor RP1. The OUT pin of the adjustable linear voltage regulator chip U2 is electrically connected to the first end of the fixed resistor R2 and the drive isolation sub-circuit 323 respectively. The second end of the fixed resistor R2 is electrically connected to the first fixed end of the adjustable resistor RP1, and the second fixed end of the adjustable resistor RP1 is electrically connected to the boost isolation sub-circuit 321; the adjustable linear voltage regulator chip U2 is used to output the target voltage to the drive isolation sub-circuit 323 by adjusting the resistance value of the adjustable resistor RP1.

[0081] Please see again Fig.13 The adjustable linear voltage regulator sub-circuit 322 also includes: a voltage regulator diode DZ1; an input end of the voltage regulator diode DZ1 is electrically connected to the adjustable linear voltage regulator chip; an output end of the voltage regulator diode DZ1 is electrically connected to the second fixed end of the adjustable resistor RP1; and the voltage regulator diode DZ1 is used to clamp the target voltage.

[0082] The adjustable linear voltage regulator subcircuit 322 also includes a first filter capacitor C11 and a second filter capacitor C12, and the first filter capacitor C11 and the second filter capacitor C12 are respectively connected in parallel to the IN pin and the VJDJ pin of the adjustable linear voltage regulator chip U2. The VJDJ pin of the adjustable linear voltage regulator chip U2 is electrically connected to the active end of the adjustable resistor RP1 and the output end of the voltage regulator diode DZ1, respectively. The input end of the voltage regulator diode DZ1 is electrically connected to the second output end OV of the boost isolation subcircuit 321. In this embodiment, the voltage regulator diode DZ1 is used to clamp the target voltage to prevent the output target voltage from being too high and causing damage to the subsequent circuit. Due to the clamping of the voltage regulator diode DZ1, the maximum value of the target voltage output by the boost isolation chip U1 is the voltage regulation value of the voltage regulator diode DZ1.

[0083] The adjustable linear voltage stabilization sub-circuit 322 further includes a third filter capacitor C13 and a fourth filter capacitor 14. The third filter capacitor C13 and the fourth filter capacitor 14 are respectively connected in parallel to the series branch of the fixed resistor R and the adjustable resistor RP1.

[0084] The adjustable linear voltage regulator sub-circuit 322 also includes a first voltage-dividing resistor R3 and a secondary voltage-regulating diode DZ2, one end of the first voltage-dividing resistor R3 is electrically connected to the OUT pin of the adjustable linear voltage-regulating chip U2, the other end of the first voltage-dividing resistor R3 is electrically connected to the output end of the secondary voltage-regulating diode DZ2, and the input end of the secondary voltage-regulating diode DZ2 is electrically connected to the second fixed end of the adjustable resistor RP1.

[0085] The adjustable linear voltage stabilization sub-circuit 322 further includes a fifth filter capacitor C15 and a sixth filter capacitor C16. The fifth filter capacitor C15 is connected in parallel with the voltage dividing resistor R3, and the sixth filter capacitor C16 is connected in parallel with the secondary voltage stabilization diode DZ2.

[0086] The drive isolation sub-circuit 323 includes a drive isolation chip U3, the ANODE pin of the drive isolation chip U3 is electrically connected to the control circuit 330 through the first pull-up resistor R4, the NC pin and the CATHODE pin of the drive isolation chip U3 are connected in parallel and then grounded, one end of the second voltage-dividing resistor R5 is electrically connected to the ANODE pin of the drive isolation chip U3, and the other end of the second voltage-dividing resistor R5 is grounded. The VCC pin of the drive isolation chip U3 is electrically connected to the OUT pin of the adjustable linear voltage regulator chip U2. The VEE pin of the drive isolation chip U3 is electrically connected to the input end of the secondary voltage regulator diode DZ2. The VOUT pin of the drive isolation chip U3 is used to output a double pulse test signal or a drive signal DRV.

[0087] The driving isolation sub-circuit 323 also includes a third voltage-dividing resistor R6, a fourth voltage-dividing electron R7 and a diode D10. The VOUT pin of the driving isolation chip U3 is electrically connected to one end of the third voltage-dividing resistor R6 and one end of the fourth voltage-dividing electron R7, respectively. The other end of the fourth voltage-dividing electron R7 is electrically connected to the cathode of the diode D10. The parallel connection point between the anode of the diode D10 and the other end of the third voltage-dividing resistor R6 serves as an output end, and is electrically connected to the control end of the corresponding left bridge arm switch tube Q3A (Q3B), right bridge arm switch tube Q4A (Q4B), upper bridge arm switch tube Q1A (Q1B), and lower bridge arm switch tube Q2A (Q2B).

[0088] The drive isolation subcircuit 323 also includes a seventh filter capacitor C17, a parallel connection point between the anode of the diode D10 and the other end of the third voltage-dividing resistor R6, and one end of the seventh filter capacitor C17 is electrically connected. A series connection point between the fifth filter capacitor C15 and the sixth filter capacitor C16 is electrically connected to the other end of the seventh filter capacitor C17.

[0089] The drive isolation subcircuit 323 also includes a resistor R8, a first transient voltage suppression diode TVS1, and a second transient voltage suppression diode TVS2. The resistor R8 and the seventh filter capacitor C17 are connected in parallel. The input end of the first transient voltage suppression diode TVS1 is electrically connected to the output end of the second transient voltage suppression diode TVS2, the input end of the first transient voltage suppression diode TVS2 is electrically connected to one end of the resistor R8, and the output end of the second transient voltage suppression diode TVS2 is electrically connected to the other end of the resistor R8.

[0090] In this way, the input voltage +12V of the power supply circuit is isolated and boosted by the boost isolation sub-circuit 321, and then input to the adjustable linear voltage regulator sub-circuit 322. The output voltage Vout of the adjustable linear voltage regulator sub-circuit 322 is Vout=1.25×(1+RP1 / R2), the resistor R2 is a fixed value, and RP1 is an adjustable resistor positioner, that is, the output voltage Vout of the adjustable linear voltage regulator sub-circuit 322 can be adjusted by adjusting the resistance value of RP1 to obtain different output voltage values. In this way, there is no need to adjust the drive voltage by adjusting the external power supply, and it can be achieved by adjusting the resistance value of RP1, thereby reducing the operation complexity and improving the operation efficiency. At the same time, the output Vout voltage is limited by the voltage regulator diode DZ1 (that is, the maximum output Vout voltage is the voltage regulator value of the voltage regulator diode DZ1) to prevent the drive voltage from being too high and thus damaging the power device under test.

[0091] See also Fig.14The power supply circuit 350 includes a step-down conversion sub-circuit 351 and a low-dropout linear voltage regulator sub-circuit 352; the step-down conversion sub-circuit 351 and the low-dropout linear voltage regulator sub-circuit 352 are used to step down and convert the first voltage into a second voltage, and input the second voltage to the low-dropout linear voltage regulator sub-circuit 352; the low-dropout linear voltage regulator sub-circuit 352 is electrically connected to the control circuit 330, and is used to stabilize the second voltage and input the stabilized voltage to the control circuit 330.

[0092] The buck conversion subcircuit 351 includes a buck conversion chip U4, an eighth filter capacitor C18, a ninth filter capacitor C19, a fourth voltage-dividing resistor R9, a fifth voltage-dividing resistor R10, a sixth voltage-dividing resistor R11, a seventh voltage-dividing resistor R12, an inductor L3 and a diode D11. The low-dropout linear voltage regulator subcircuit 352 includes a low-dropout linear voltage regulator U5, a tenth filter capacitor C20, an eleventh filter capacitor C21, an eighth voltage-dividing resistor R13 and a twelfth filter capacitor C22.

[0093] Among them, the BOOT pin of the buck converter chip U4 is electrically connected to the PH pin through the eighth filter capacitor C18. The VIN pin of the buck converter chip U4 is electrically connected to one end of the ninth filter capacitor C19, and the other end of the ninth filter capacitor C19 is grounded GND. The VIN pin of the buck converter chip U4 receives a 12V power supply voltage. The G1 pin of the buck converter chip U4 is electrically connected to the anode of the diode D11, and the PH pin of the buck converter chip U4 is electrically connected to the cathode of the diode D11. The PH pin of the buck converter chip U4 is electrically connected to the VIN pin of the low-dropout linear regulator U5 through the inductor L3. The BNA pin of the buck converter chip U4 is electrically connected to one end of the fourth voltage-dividing resistor R9 and one end of the fifth voltage-dividing electronic R10, respectively. The other end of the fourth voltage-dividing resistor R9 is used to receive a 12V voltage, and the other end of the fifth voltage-dividing electronic R10 is grounded GND. The VS pin of the buck converter chip U4 is electrically connected to one end of the sixth voltage-dividing resistor R11 and one end of the seventh voltage-dividing resistor R12, respectively, and the other end of the sixth voltage-dividing resistor R11 is electrically connected to the VIN pin of the low-dropout linear regulator U5. One end of the tenth filter capacitor C20 and one end of the eleventh filter capacitor C21 are electrically connected to the VIN pin of the low-dropout linear regulator U5, respectively, and the other end of the tenth filter capacitor C20 and the other end of the eleventh filter capacitor C21 are grounded. One end of the twelfth filter capacitor C22 is electrically connected to the VOUT pin of the low-dropout linear regulator U5, the other end of the twelfth filter capacitor C22 is grounded, and the GND pin of the low-dropout linear regulator U5 is grounded. One end of the eighth voltage-dividing resistor R13 is electrically connected to the VOUT pin of the low-dropout linear regulator U5, and the other end of the eighth voltage-dividing resistor R13 is electrically connected to the control circuit 330, so that the low-dropout linear regulator U5 supplies power to the control circuit 330. In this way, the entire T-type double-pulse test platform only needs a +12V power supply to supply the control circuit and the drive circuit. The power supply of the entire test platform system is simple. Even if the external power supply is misadjusted artificially, it will not affect or damage the entire T-type three-level double-pulse test platform system, and the safety is more reliable.

[0094] In addition, in the prior art, any PCB routing loop will have different parasitic parameters (parasitic inductance). If the parasitic parameters in the loop are too large, it will directly affect the test results of the power device, thereby affecting the design judgment. If the parasitic parameters in the loop are too large, the peak voltage is relatively high, exceeding the voltage limit of the power device, and directly damaging the device. The main circuit of the existing T-type three-level double-pulse test platform does not have any circuit or measures to reduce the parasitic parameters of the loop. If the parasitic parameters of the PCB routing loop are relatively large, the loop peak voltage is relatively high, and the test data will also have a relatively large deviation. When the loop peak voltage exceeds the withstand voltage value of the power device, the peak voltage may even directly break down power devices such as IGBT / MOS / SiC MOS.

[0095] The passive clamping absorption method and active clamping absorption method of the traditional half-bridge two-level dual pulse test platform, these two methods, do not fundamentally reduce the parasitic parameters in the circuit, but simply build a circuit to absorb or clamp the excessively high peak voltage, so as to achieve the effect of protecting the power tube under test. The test results are still greatly affected by the parasitic parameters of the circuit, and there will be certain errors in the parameter data obtained. Secondly, when testing different IGBT, MOS, SiC MOS and other power devices, or when the specifications of the power devices are different, the voltage regulator diode TVS3 and the external clamping DC source of the absorption circuit need to be changed or set to different values, and the adjustment is cumbersome and complicated. At the same time, the T-type three-level topology needs to test more power devices in different positions and in many operating states. Therefore, the peak voltage absorption method in the traditional two-level topology is no longer applicable to the T-type three-level topology. In order to solve the problems of large stray inductance (parasitic parameters) and large peak voltage in the circuit, this real-time example further provides the following Fig.15 The T-type three-level main circuit shown can effectively absorb the peak voltage of the T-type three-level topology.

[0096] See also Fig.15 The T-type three-level main circuit also includes: a first spike voltage absorbing branch W1, a second spike voltage absorbing branch W2 and a third spike voltage absorbing branch W3; one end of the first spike voltage absorbing branch W1 is connected to the reference ground P1, and the other end of the first spike voltage absorbing branch W1 is connected to the parallel connection point P2 of the upper vertical bridge unit Q1 and the first bus capacitor C1; one end of the second spike voltage absorbing branch W2 is connected to the reference ground P1, and the other end of the second spike voltage absorbing branch W2 is connected to the parallel connection point P4 of the lower vertical bridge unit Q2 and the second bus capacitor C2; one end of the third spike voltage absorbing branch W3 is connected to the parallel connection point P2 of the upper vertical bridge unit Q1 and the first bus capacitor C1, and the other end of the third spike voltage absorbing branch W3 is connected to the parallel connection point P4 of the lower vertical bridge unit Q2 and the second bus capacitor C2. The first peak voltage absorption branch W1 includes a capacitor C3, one end of the capacitor C3 is electrically connected to the reference ground P1, and the other end of the capacitor C3 is electrically connected to the parallel connection point P2. The second peak voltage absorption branch W2 includes a capacitor C4, one end of the capacitor C4 is electrically connected to the reference ground P1, and the other end of the capacitor C4 is electrically connected to the parallel connection point P4. The third peak voltage absorption branch W3 includes a capacitor C5 and a capacitor C6, one end of the capacitor C5 is electrically connected to one end of the capacitor C6, the other end of the capacitor C5 is electrically connected to the parallel connection point P2, and the other end of the capacitor C6 is electrically connected to the parallel connection point P4.

[0097] Combination Fig. 9From the control logic, it can be seen that when the second double pulse is turned off, due to the existence of stray inductance (parasitic parameters) in the loop, it will prevent the current from changing, produce an opposite voltage drop, and superimpose on the left bridge arm switch tube Q4A (Q4B) together with the bus voltage to form a spike voltage. If no measures are taken to absorb the spike voltage, the spike voltage will affect the test results. When it is too large, it will directly break down the power device under test. When testing other switch tubes, there will also be corresponding spike voltages. By connecting a suitable capacitor C3 in parallel between the reference ground P1 and the parallel connection point P2, connecting a suitable capacitor C4 in parallel between the reference ground P1 and the parallel connection point P4, and adding suitable capacitors C5 and C6 between the parallel connection point P2 and the parallel connection point P4 (C5 and C6 are connected in series to achieve a higher withstand voltage, and a higher platform voltage can be tested). Capacitor C3, capacitor C4, capacitor C5 and capacitor C6 can be divided into thin film capacitors. Film C3 and film C4 can effectively reduce the commutation stray parasitic inductance. Film capacitor C5 and film capacitor C6 can absorb the stray inductance of the main circuit, protect the switching tubes Q1A and Q2A (or Q1B and Q2B), avoid overvoltage, suppress oscillation and reduce peak voltage. At the same time, through more suitable PCB layout and wiring, the parasitic parameters in the loop are further reduced, thereby reducing the stray inductance (parasitic parameters) and the data error when performing double pulse testing on the power device under test (i.e., the switching tube), so as to obtain more realistic test results.

[0098] Fig.16 The waveform diagram of the double pulse test on the power device with a peak voltage absorption branch (i.e., capacitors C3, C4, C5 and C6) is shown below. Fig.17 This is the waveform diagram of the double pulse test without the spike voltage absorption branch (that is, after removing capacitors C3, C4, C5 and C6). After comparison, the Fig.16 The VDS voltage waveform in the first waveform area of ​​K1 waveform and Fig.17 From the VDS voltage waveform K2 in the second waveform area, it can be seen that when the second pulse is turned off, Fig.17 The turn-off peak voltage of VDS voltage waveform K2 is obviously higher than Fig.16 The peak voltage of the VDS voltage waveform K1 in the first waveform area is much larger, and Fig.17 The peak voltage oscillation is very long. Fig.17 The turn-off loss tested is obviously Fig.16 Therefore, the peak voltage absorption branch designed in this embodiment can effectively reduce the peak voltage, thereby protecting the power device under test, and the error of the data obtained by the test is smaller, which is of great significance for verifying the real performance of the power device in the actual circuit.

[0099] The embodiment of the present invention also provides a test method for a T-type three-level circuit, which is applied to a test system for a T-type three-level circuit, see Fig.18, the method includes steps S211-S213.

[0100] Step S211, controlling a driving circuit to send a double pulse test signal to the unit under test according to the double pulse test parameters.

[0101] Step S212, controlling other driving circuits to send driving signals to the remaining units respectively according to the driving control signal.

[0102] Step S213, controlling the oscilloscope to receive test data from the unit under test, and outputting a pulse test result of the unit under test according to the test signal.

[0103] The testing method of the T-type three-level circuit provided in the embodiment of the present invention is applied to the testing system of the T-type three-level circuit provided, and can realize the corresponding functions of the testing system of the T-type three-level circuit. To avoid repetition, it will not be described here.

[0104] The present application also provides a computer device including a memory and a processor, wherein the memory stores a computer program, and when the computer program is run on the processor, the test method of the T-type three-level circuit provided in the embodiment is executed.

[0105] The present application also provides a computer-readable storage medium for storing the computer program used in the above-mentioned computer device. For example, the computer-readable storage medium may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0106] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A test system for a T-type three-level circuit, characterized in that: include: T-type three-level main circuit and multiple drive circuits; The T-type three-level main circuit includes: an adjustable high-voltage DC source, a first bus capacitor, a second bus capacitor, a vertical bridge subcircuit, a horizontal bridge subcircuit and an inductor. The vertical bridge subcircuit includes an upper vertical bridge unit and a lower vertical bridge unit. The upper vertical bridge unit and the lower vertical bridge unit are connected in series and then connected in parallel to the two ends of the adjustable high-voltage DC source. The horizontal bridge subcircuit includes a right bridge arm unit and a left bridge arm unit. One end of the right bridge arm unit and the left bridge arm unit connected in series is connected to a reference ground. The other end of the right bridge arm unit and the left bridge arm unit connected in series is connected to a series connection point of the upper vertical bridge unit and the lower vertical bridge unit. The adjustable high-voltage DC source is connected to the reference ground through the first bus capacitor, and the adjustable high-voltage DC source is connected to the reference ground through the second bus capacitor. The inductor is connected in parallel with any one of the horizontal bridge subcircuit, the upper vertical bridge unit and the lower vertical bridge unit. The driving circuit is used to send a double pulse test signal to the unit under test according to the double pulse test parameters; the unit under test is determined from the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit according to the parallel connection position of the inductor; The other driving circuits are used to send driving signals to each remaining unit according to the driving control signal, wherein the remaining units include the vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit except the unit to be tested.

2. The test system for a T-type three-level circuit according to claim 1, characterized in that: When the inductor and the upper vertical bridge unit are connected in parallel, the unit to be tested includes a left bridge arm unit, and the remaining units include the upper vertical bridge unit, the lower vertical bridge unit and the right bridge arm unit; When the inductor and the lower vertical bridge unit are connected in parallel, the unit to be tested includes a right bridge arm unit, and the remaining units include the upper vertical bridge unit, the lower vertical bridge unit and the left bridge arm unit; When the inductor and the cross-bridge subcircuit are connected in parallel, the unit to be tested includes the upper vertical bridge unit or the lower vertical bridge unit; the remaining units include the lower vertical bridge unit, the left bridge arm unit and the right bridge arm unit; or, the remaining units include the upper vertical bridge unit, the left bridge arm unit and the right bridge arm unit.

3. The test system for a T-type three-level circuit according to claim 2, characterized in that: The upper vertical bridge unit includes at least two upper bridge arm switching tubes connected in parallel, the lower vertical bridge unit includes at least two lower bridge arm switching tubes connected in parallel, each left bridge arm unit includes at least two left bridge arm switching tubes connected in parallel, and each right bridge arm unit includes at least two right bridge arm switching tubes connected in parallel; the models of the upper bridge arm switching tubes are different, the models of the lower bridge arm switching tubes are different, the models of the left bridge arm switching tubes are different, and the models of the right bridge arm switching tubes are different.

4. The test system for a T-type three-level circuit according to claim 3, characterized in that: Also includes: Power supply circuit and control circuit; The driving circuit comprises: a boost isolation subcircuit, an adjustable linear voltage stabilization subcircuit and a driving isolation subcircuit; The power supply circuit is electrically connected to the boost isolation sub-circuit and is used to input an initial voltage to the boost isolation sub-circuit; The boost isolation subcircuit is also electrically connected to the adjustable linear voltage stabilization subcircuit, and is used to boost the initial voltage to obtain a boosted voltage, and send the boosted voltage to the adjustable linear voltage stabilization subcircuit; The adjustable linear voltage stabilization sub-circuit is also electrically connected to the drive isolation sub-circuit, and is used to adjust the boost voltage to obtain a target voltage, and send the target voltage to the drive isolation sub-circuit; The drive isolation sub-circuit is electrically connected to the upper vertical bridge unit, the lower vertical bridge unit, one of the right bridge arm unit and the left bridge arm unit and the control circuit, respectively, and is used to receive the double pulse test parameter or the drive control signal from the control circuit, and send the double pulse test signal or the drive control signal to one of the upper vertical bridge unit, the lower vertical bridge unit, the right bridge arm unit and the left bridge arm unit according to the double pulse test parameter or the drive control signal.

5. The test system for a T-type three-level circuit according to claim 4, characterized in that: The adjustable linear voltage stabilization subcircuit includes an adjustable linear voltage stabilization chip, an adjustable resistor and a fixed resistor; The adjustable linear voltage stabilization chip is electrically connected to the boost isolation subcircuit, the active end of the adjustable resistor, the first end of the fixed resistor and the drive isolation subcircuit respectively; The second end of the fixed resistor is electrically connected to the first fixed end of the adjustable resistor, and the second fixed end of the adjustable resistor is electrically connected to the boost isolation sub-circuit; The adjustable linear voltage stabilizing chip is used to output the target voltage to the driving isolation sub-circuit by adjusting the resistance value of the adjustable resistor.

6. The test system for a T-type three-level circuit according to claim 5, characterized in that: The adjustable linear voltage stabilization subcircuit also includes: a voltage stabilization diode; The input end of the voltage stabilizing diode is electrically connected to the adjustable linear voltage stabilizing chip; The output end of the voltage zener diode is electrically connected to the second fixed end of the adjustable resistor; The voltage stabilizing diode is used to clamp the target voltage.

7. The test system for a T-type three-level circuit according to claim 4, characterized in that: The power supply circuit includes a step-down conversion subcircuit and a low-dropout linear voltage stabilization subcircuit; The step-down conversion subcircuit is electrically connected to the low-dropout linear voltage stabilization subcircuit, and is used to step-down the first voltage into a second voltage, and input the second voltage to the low-dropout linear voltage stabilization subcircuit; The low voltage drop linear voltage stabilization sub-circuit is electrically connected to the control circuit, and is used for stabilizing the second voltage and inputting the regulated voltage into the control circuit.

8. The test system for a T-type three-level circuit according to claim 4, characterized in that: Also includes: The host computer is electrically connected to the control circuit, and is used to set the working state of the T-type three-level main circuit, and to set the double pulse test parameters and the drive control signal under the working state, and to send the double pulse test parameters and the drive control signal to the control circuit.

9. The test system for a T-type three-level circuit according to claim 8, characterized in that: The double pulse test parameters include the switching frequency and pulse dead zone of the double pulse test signal, the first duty cycle of the first pulse signal of the double pulse test signal and the second duty cycle of the second pulse signal of the double pulse test signal, wherein the first duty cycle is a duty cycle that makes the turn-on current on the main test loop path where the unit under test is located reach a first preset current range; The second duty cycle is a duty cycle that enables the shutdown current on the main test loop path where the unit under test is located to reach a second preset current range.

10. The test system for a T-type three-level circuit according to claim 1, characterized in that: The T-type three-level main circuit also includes a first peak voltage absorption branch, a second peak voltage absorption branch and a third peak voltage absorption branch; One end of the first peak voltage absorption branch is connected to the reference ground, and the other end of the first peak voltage absorption branch is connected to the parallel connection point of the upper vertical bridge unit and the first bus capacitor; One end of the second peak voltage absorption branch is connected to the reference ground, and the other end of the second peak voltage absorption branch is connected to the parallel connection point of the lower vertical bridge unit and the second bus capacitor; One end of the third peak voltage absorption branch is connected to the parallel connection point of the upper vertical bridge unit and the first bus capacitor, and the other end of the third peak voltage absorption branch is connected to the parallel connection point of the lower vertical bridge unit and the second bus capacitor.

11. The test system for a T-type three-level circuit according to claim 1, characterized in that: Also includes: The oscilloscope is electrically connected to the unit under test and is used to receive test data from the unit under test and output a pulse test result of the unit under test according to the test data.

12. A method for testing a T-type three-level circuit, characterized in that: A test system for a T-type three-level circuit according to any one of claims 1 to 11, the method comprising: Controlling a driving circuit to send a double pulse test signal to the unit under test according to the double pulse test parameters; Control other driving circuits to send driving signals to the remaining units respectively according to the driving control signal; The oscilloscope is controlled to receive test data from the unit under test, and output a pulse test result of the unit under test according to the test data.

13. A computer device, characterized in that: The invention comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is run on the processor, the test method of the T-type three-level circuit according to claim 12 is executed.

14. A computer storage medium, characterized in that: The computer program is stored therein, and when the computer program is executed on a processor, the testing method of the T-type three-level circuit according to claim 12 is implemented.

Images