Chip testing method, device, system, computer equipment and storage medium

Abstract

In the embodiments of the present application, a chip testing method, a chip testing device, a chip testing system, a computer device and a computer storage medium are provided, which relate to the field of chip security testing technology. The method comprises: in response to the power-on operation of the target development board, controlling the first chip to be tested to start the first test program based on the test selection program pre-configured in the switching circuit; testing one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; in response to the first test result being a successful test, controlling the first chip to be tested to start the second test program based on the test selection program; testing one or more second target test instances in each test instance circuit according to the second test program to obtain a second test result. The present application can improve the efficiency of chip testing.

Description

Technical Field

[0001] The present application relates to the field of chip security testing technology, and in particular, to a chip testing method, a chip testing device, a chip testing system, a computer device, and a computer storage medium. Background Art

[0002] As the requirements for chip integration continue to increase, the number of existing chip pins continues to increase, power consumption continues to increase, and the packaging requirements for integrated circuits are becoming more stringent. In existing integrated circuit packaging technologies, such as ball grid array packaging (BGA) technology, the packaging pins are led out from the center of the chip, thereby effectively shortening the signal transmission distance and reducing signal attenuation. However, existing chip substrates have high wiring density, narrow spacing, and many through holes, and other high integration characteristics. Accordingly, reliability testing of chips is also very challenging.

[0003] The existing chip testing method usually adopts a manual method to replace and test a large number of sample chips (ie, the first chips to be tested) one by one, which makes the testing process of the sample chips time-consuming and labor-intensive, thereby resulting in low chip testing efficiency. Summary of the invention

[0004] In the embodiments of the present application, a chip testing method, a chip testing device, a chip testing system, a computer device and a computer storage medium are provided, thereby overcoming, at least to a certain extent, the technical problem that, due to the limitations and defects of the relevant technologies, a large number of sample chips need to be manually replaced and tested one by one, making the testing process of the sample chips time-consuming and labor-intensive, thereby leading to low efficiency of chip testing.

[0005] A first aspect of an embodiment of the present application provides a chip testing method, which is applied to a target development board, wherein at least a first chip to be tested, test instance circuits connected to the first chip to be tested, and a switching circuit are installed in the board circuit of the target development board. The method comprises: in response to a power-on operation on the target development board, controlling the first chip to be tested to start a first test program based on a test selection program pre-configured in the switching circuit; testing one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; in response to the first test result being a test success, controlling the first chip to be tested to start a second test program based on the test selection program; and testing one or more second target test instances in each test instance circuit based on the second test program to obtain a second test result.

[0006] In an optional embodiment of the present application, the first test program is a test program corresponding to the packaged finished product test FT; the second test program is a test program corresponding to the system-level test SLT; based on the test selection program pre-configured in the switching circuit, the first chip to be tested is controlled to start the first test program, and / or, according to the test selection program, the first chip to be tested is controlled to start the second test program, including: based on the test selection program, the first chip to be tested is controlled to start the first test program from the flash memory circuit; and / or, according to the test selection program, the first chip to be tested is controlled to start the second test program from the embedded storage controller EMMC circuit.

[0007] In an optional embodiment of the present application, each test instance circuit includes at least a target test instance circuit; one or more first target test instances in each test instance circuit are tested based on a first test program to obtain a first test result, including: constructing a loopback circuit of the first test instance circuit based on a functional interface in the target test instance circuit; performing a loopback test on the first target test instance corresponding to the loopback circuit of the first test instance circuit based on the first test program to obtain a first test result.

[0008] In an optional embodiment of the present application, the target test instance circuit includes a first target test instance circuit, and / or a second target test instance circuit; based on the functional interface of the first test instance circuit, a loopback circuit of the first test instance circuit is constructed, including: when the target test instance circuit includes at least the first target test instance circuit, the first target test instance circuit is directly connected to the first functional interface and the second functional interface of the chip to be tested to construct a loopback circuit of the first target test instance circuit; when the target test instance circuit includes at least the second target test instance circuit, multiple second target test instance circuits are connected to the pin interface of the chip to be tested based on resistors with preset resistance values ​​to construct a loopback circuit of the second target test instance circuit.

[0009] In an optional embodiment of the present application, the method further includes: installing a socket base on the target development board, and inserting the chip to be tested into the socket base.

[0010] In an optional embodiment of the present application, the method also includes: in response to a test completion instruction for the first chip to be tested, controlling a power-off operation for the target development board; controlling the robotic arm to unload the first chip to be tested from the socket base, and controlling the robotic arm to press the second chip to be tested against the socket base, in response to a power-on operation on the target development board, until a test completion instruction for the second chip to be tested is received.

[0011] According to a second aspect of an embodiment of the present application, a chip testing device is provided, which is applied to a target development board, wherein at least a first chip to be tested, test instance circuits connected to the first chip to be tested, and a switching circuit are installed in the board circuit of the target development board, and the device comprises: a first program starting module, which is used to control the first chip to be tested to start a first test program based on a test selection program pre-configured in the switching circuit in response to a power-on operation of the target development board;

[0012] A first test module, configured to test one or more first target test instances in each test instance circuit based on a first test program to obtain a first test result;

[0013] A second program starting module is used for controlling the first chip to be tested to start a second test program based on the test selection program in response to the first test result being a test success;

[0014] The second test module is used to test one or more second target test instances in each test instance circuit according to a second test program to obtain a second test result.

[0015] In an optional embodiment of the present disclosure, the first test program is a test program corresponding to the packaged finished product test FT; the second test program is a test program corresponding to the system-level test SLT; the first program startup module controls the first chip to be tested to start the first test program from the flash memory circuit based on the test selection program; and / or the second program startup module is used to control the first chip to be tested to start the second test program from the embedded storage controller EMMC circuit according to the test selection program.

[0016] In an optional embodiment of the present disclosure, each test instance circuit includes at least a target test instance circuit and a first test module, which is used to construct a loopback circuit of the first test instance circuit based on a functional interface in the target test instance circuit; and perform a loopback test on a first target test instance corresponding to the loopback circuit of the first test instance circuit based on a first test program to obtain a first test result.

[0017] In an optional embodiment of the present disclosure, the target test instance circuit includes a first target test instance circuit, and / or a second target test instance circuit; a first test module is used to directly connect the first target test instance circuit with the first functional interface and the second functional interface of the chip to be tested to construct a loop circuit of the first target test instance circuit when the target test instance circuit includes at least the first target test instance circuit; and a first test module is used to connect multiple second target test instance circuits with pin interfaces of the chip to be tested based on resistors with preset resistance values ​​to construct a loop circuit of the second target test instance circuit when the target test instance circuit includes at least the second target test instance circuit.

[0018] In an optional embodiment of the present disclosure, the device may further include a chip insertion module, and the chip insertion module is used to install a socket base on the target development board and insert the chip to be tested into the socket base.

[0019] In an optional embodiment of the present disclosure, the device may also include a control module, which is used to control a power-off operation on a target development board in response to a test completion instruction for a first chip to be tested; control a robotic arm to unload the first chip to be tested from a socket base, and control the robotic arm to press the second chip to be tested against the socket base in response to a power-on operation on the target development board, until a test completion instruction for the second chip to be tested is received.

[0020] According to a third aspect of an embodiment of the present application, a chip testing system is provided, the system comprising a terminal testing device and a target development board, wherein at least a first chip to be tested, test instance circuits connected to the first chip to be tested, and a switching circuit are installed in the board circuit of the target development board, the system comprising: a terminal testing device, for pre-configuring a test selection program in the switching circuit, and configuring a first test program and a second test program in the target development board; a target development board, for controlling the first chip to be tested to start a first test program based on the test selection program pre-configured in the switching circuit in response to a power-on operation on the target development board; testing one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; in response to the first test result being a test success, controlling the first chip to be tested to start a second test program based on the test selection program; and testing one or more second target test instances in each test instance circuit according to the second test program to obtain a second test result.

[0021] According to a fourth aspect of an embodiment of the present application, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of any of the above chip testing methods are implemented.

[0022] According to a fifth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above chip testing methods are implemented.

[0023] According to a sixth aspect of an embodiment of the present application, a computer program product is provided, including a computer program, which is executed by a processor to implement the steps of any one of the above chip testing methods.

[0024] The technical solution of this application has the following beneficial effects:

[0025] Based on the above chip testing method, the target development board controls the first chip to be tested to start a first test program based on a test selection program pre-configured in the switching circuit in response to a power-on operation on the target development board; tests one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; in response to the first test result being a successful test, controls the first chip to be tested to start a second test program based on the test selection program; tests one or more second target test instances in each test instance circuit based on the second test program to obtain a second test result.

[0026] The chip testing method adds a switching circuit to the board circuit of the target development board. The switching circuit is pre-configured with a test selection program. When the system detects that the target open board is powered on, it can select a test program corresponding to a test mode through the test selection program to start the test process; and automatically switch to the test program corresponding to the next test mode to start the test process after detecting that the test is successful. On the one hand, the method can complete multiple test processes for the first chip to be tested when the target development board is powered on once by executing program switching through the switching circuit, thereby solving the technical problems of time-consuming and labor-intensive work, high labor costs, and low chip testing efficiency caused by the need to manually switch multiple test processes in the related technical solutions, thereby achieving the technical effect of reducing labor costs and improving chip testing efficiency. On the other hand, the method only requires one power-on operation on the target development board to realize the switching process of multiple test processes, which solves the problem that the chip testing in the related technical solutions needs to be time-consuming after manually powering off the target development board and then switching to the next test process and powering it on again, especially when batch screening of a large number of chips to be tested wastes more time, which seriously affects the efficiency of chip testing and batch screening, and the technical problem that multiple power offs and restarts seriously affect the service life of each device in the target development board, thereby achieving the technical effect of improving the efficiency of chip testing and batch screening, and reducing the loss of service life of each device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0028] Figure 1 An architectural diagram of a chip testing system provided in one embodiment of the present application;

[0029] Figure 2 A flowchart of a chip testing method provided in one embodiment of the present application;

[0030] Figure 3A schematic diagram of a board circuit of a base station processor UCP4008 chip provided in one embodiment of the present application;

[0031] Figure 4 A top view of a board circuit of a base station processor UCP4008 chip provided in one embodiment of the present application;

[0032] Figure 5 A physical diagram of a board circuit of a base station processor UCP4008 chip provided in one embodiment of the present application;

[0033] Figure 6 A schematic diagram of the structure of a chip testing device provided in one embodiment of the present application;

[0034] Figure 7 A schematic diagram of a computer device structure provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present application will be more comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical solutions of the present application may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present application.

[0036] In addition, the accompanying drawings are only schematic illustrations of the present application and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0037] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0038] In the relevant technical background, as the market's requirements for chip integration continue to increase, the number of chip pins has increased dramatically, power consumption has also increased, and the requirements for integrated circuit packaging technology have become more stringent. In order to meet the needs of social development and the continuous advancement of integration technology, BGA integrated circuit packaging technology has begun to be widely used in actual production. Compared with the traditional thin small outline package (TSOP) technology, the BGA package pins are led out from the center of the chip. This method effectively shortens the signal transmission distance, and the length of the signal transmission line is only 1 / 4 of the traditional TSOP technology, so the signal attenuation is also reduced. And the BGA packaging method not only greatly improves the anti-interference and anti-noise performance of the chip, but also has a smaller volume, better heat dissipation and electrical performance.

[0039] Since the existing highly integrated chip substrates have high wiring density, narrow spacing, many through holes, and high requirements for the coplanarity of the substrate, the chip must undergo relevant reliability board-level testing after production to verify whether the sample chip is a qualified chip, thereby avoiding defective products and rework, etc. Among them, the above-mentioned board-level test can, for example, be a packaged finished product test (Final Test, referred to as FT test), a system level test (System Level Test, SLT test), an aging test, a limit capability test (such as avalanche energy test, surge current test, etc.) for multiple sample chips, and the embodiments of the present application do not impose any special restrictions on this.

[0040] Among them, FT testing is carried out after the chip to be tested is packaged. Through the cooperation of the sorting machine and the testing machine, a series of tests are performed on the function and electrical parameter performance of the chip to be tested. SLT testing is to put the chip to be tested into the actual system for testing to verify the performance of the chip to be tested in the system. This test usually includes aging testing, that is, placing the chip to be tested in a high temperature environment for high voltage testing to simulate the actual use environment to detect the stability and reliability of the chip.

[0041] It should be explained that the reason why FT test and SLT test must be separated and the startup mode needs to be switched is that the FT test program is a uboot program. After the chip is started, the processor core and system cannot be loaded when the FT test program is executed, and SLT test cannot be performed because SLT test must be performed under the operating system.

[0042] In the relevant technical solutions, when a large number of sample chips are subjected to board-level tests one by one, manual intervention is usually required to complete the test. For example, taking the board-level test of a large number of sample chips for FT test and SLT test as an example, the relevant technical solutions require manual power-off of the sample chip after confirming that the FT test is completed, and then reload the SLT test program, and power on the sample chip to start the SLT test for the sample chip. And after completing multiple board-level tests of a sample chip, it is necessary to manually remove the sample chip from the test substrate to replace other sample chips for board-level tests of FT test and SLT test again, and repeat the cycle until the board-level test of all sample chips is completed.

[0043] The above-mentioned related technical solutions, on the one hand, are to manually perform FT test and SLT test on sample chips respectively, and to manually unload a sample chip from the test board and replace another sample chip to continue testing, which makes the labor cost of testing chips high, time-consuming and labor-intensive, and thus leads to low efficiency of chip testing and screening of a large number of sample chips. On the other hand, after completing the FT test on a sample chip, it is necessary to power off the board, and then power on the board again to continue the SLT test, which will make the chip test time-consuming, especially when a large number of chips to be tested are screened in batches, more time is wasted. For example, it usually takes 30-40 seconds to power on and off the target development board once. When screening in batches, usually thousands or even more single chips to be tested are tested multiple times, which will seriously affect the efficiency of chip testing and batch screening, and multiple power offs and restarts seriously affect the service life of each device in the target development board, and thus affect the stability of the system.

[0044] Taking the above problems into consideration, the exemplary embodiment of the present application proposes a chip testing method, in which a switching circuit is newly added to the board circuit of the target development board, and a test selection program is pre-configured in the switching circuit. When the system detects that the target open board is powered on, it can select a test program corresponding to a test mode through the test selection program to start the test process; and automatically switch to the test program corresponding to the next test mode to start the test process after detecting that the test is successful. On the one hand, the method can complete multiple test processes for the chip to be tested when the target development board is powered on once by executing program switching through the switching circuit, thereby solving the technical problems of time-consuming and labor-intensive work, high labor costs, and low chip testing efficiency caused by the need to manually switch multiple test processes in the related technical solutions, thereby achieving the technical effect of reducing labor costs and improving chip testing efficiency. On the other hand, the method only requires one power-on operation on the target development board to realize the switching process of multiple test processes, which solves the problem that the chip testing in the related technical solutions needs to be time-consuming after manually powering off the target development board and then switching to the next test process and powering it on again, especially when batch screening of a large number of chips to be tested wastes more time, which seriously affects the efficiency of chip testing and batch screening, and the technical problem that multiple power offs and restarts seriously affect the service life of each device in the target development board, thereby achieving the technical effect of improving the efficiency of chip testing and batch screening and reducing the loss of service life of each device.

[0045] This method can automatically switch the circuit to test a large number of sample chips separately without manual intervention to complete the screening, thereby improving the chip testing and screening efficiency. On the other hand, this method can continue the SLT test without powering off the board after the FT test is completed, so that the FT test and SLT test of the chip can be completed at one power-on through a simple program switch, thereby reducing the power consumption of the chip test and improving the stability of the system.

[0046] The following will be combined Figure 1 , a chip testing method proposed in this application is applied to Figure 1 The embodiments are described in the system architecture of the exemplary application environment shown.

[0047] like Figure 1As shown, a schematic diagram of an application scenario provided by an embodiment of the present application, in which a terminal test device 101 and a development board 102 with specific business functions may be included, and the development board 102 is connected to the terminal test device 101. Exemplarily, the terminal test device 101 and the development board 102 may be connected via a UART (Universal Asynchronous Receiver / Transmitter) interface or other interfaces, and the embodiments of the present application do not impose any special restrictions on this. The chip to be tested 103 is electrically operated on the development board 102.

[0048] The terminal test device 101 can be, for example, a mobile phone, a tablet computer (PAD), a laptop computer, a desktop computer, a smart TV, a smart vehicle-mounted device, a smart wearable device, a smart TV, an aircraft, or any other device involved in chip testing. The terminal test device 101 is installed with test management software and provides a user interaction interface, so that the user can perform chip testing and display test results through the user interaction interface, and the development board 102 is installed with at least a chip to be tested 103. Taking the chip test including FT test and SLT test as an example, the test program runs on the operating system of the chip to be tested, the test management software is connected to the test program through an interface, and the SLT test software tests each test object in the chip to be tested separately, obtains the test results, and returns the test results to the test management software, and displays the test results to the user in the user interaction interface.

[0049] For example, in an optional embodiment, the board circuit of the development board 102 (i.e., the target development board) is installed with at least a chip to be tested 103, test instance circuits connected to the chip to be tested 103, and a switching circuit. The user can pre-configure a test selection program into the switching circuit through the terminal test device 101, and inject a first test program and a second test program.

[0050] In response to the power-on operation of the development board 102, the development board 102 controls the chip to be tested 103 (i.e., the first chip to be tested) to start the first test program based on the test selection program pre-configured in the switching circuit installed on the development board 102; based on the first test program, one or more first target test instances in each test instance circuit connected to the chip to be tested 103 are tested to obtain a first test result; in response to the first test result being a test success, the development board 102 controls the first chip to be tested 103 to start the second test program based on the test selection program; based on the second test program, one or more second target test instances in each test instance circuit are tested to obtain a second test result. The first test result and the second test result are respectively sent to the terminal test device 101 to display the first / second test results for the development board 102 on the user interaction interface (i.e., the software interface of the test management software) provided by the terminal test device 101. Then, the above test process is repeated for the second chip to be tested until the reliability test of all chips to be tested is completed.

[0051] Below, in combination with the application scenarios described above, the method provided by the exemplary embodiment of the present application is described with reference to the accompanying drawings. It should be noted that the above application scenarios are only shown to facilitate understanding of the spirit and principle of the present application, and the implementation of the present application is not limited in this respect. It should be noted that the following method will use the above development board 102 as the execution subject to specifically describe an embodiment of a chip testing method proposed in the embodiment of the present application.

[0052] Figure 2 For a flowchart of a chip testing method provided in an embodiment of the present application, please refer to Figure 2 The method is applied to a target development board, in which at least a chip to be tested, test instance circuits connected to the chip to be tested, and a switching circuit are installed in the board circuit of the target development board. Taking the first chip to be tested installed in the board circuit of the target development board in the current test process as an example, the chip testing method provided by the embodiment of the present disclosure includes the following steps 201 to 204:

[0053] Step 201 : In response to a power-on operation on a target development board, control a first chip to be tested to start a first test program based on a test selection program preconfigured in a switching circuit.

[0054] Step 202: Test one or more first target test instances in each test instance circuit based on a first test program to obtain a first test result.

[0055] Step 203 : In response to the first test result being a test success, control the first chip to be tested to start a second test program based on the test selection program.

[0056] Step 204 : Test one or more second target test instances in each test instance circuit according to the second test program to obtain a second test result.

[0057] In the above Figure 2 In the provided technical solution, in response to a power-on operation, the target development board controls the first chip to be tested to start a first test program based on a test selection program pre-configured in a switching circuit; based on the first test program, one or more first target test instances in each test instance circuit are tested to obtain a first test result; in response to the first test result being a successful test, the first chip to be tested is controlled to start a second test program based on the test selection program; based on the second test program, one or more second target test instances in each test instance circuit are tested to obtain a second test result.

[0058] The chip testing method adds a switching circuit to the board circuit of the target development board. The switching circuit is pre-configured with a test selection program. When the system detects that the target open board is powered on, it can select a test program corresponding to a test mode through the test selection program to start the test process; and automatically switch to the test program corresponding to the next test mode to start the test process after detecting that the test is successful. On the one hand, the method can complete multiple test processes for the chip to be tested when the target development board is powered on once by executing program switching through the switching circuit, thereby solving the technical problems of time-consuming and labor-intensive work, high labor costs, and low chip testing efficiency caused by the need to manually switch multiple test processes in the related technical solutions, thereby achieving the technical effect of reducing labor costs and improving chip testing efficiency. On the other hand, the method only requires one power-on operation on the target development board to realize the switching process of multiple test processes, which solves the problem that the chip testing in the related technical solutions needs to be time-consuming after manually powering off the target development board and then switching to the next test process and powering it on again, especially when batch screening of a large number of chips to be tested wastes more time, which seriously affects the efficiency of chip testing and batch screening, and the technical problem that multiple power offs and restarts seriously affect the service life of each device in the target development board, thereby achieving the technical effect of improving the efficiency of chip testing and batch screening, and reducing the loss of service life of each device.

[0059] The following will be combined with specific embodiments to Figure 2 The specific implementation methods of each step in the embodiment shown are described in detail:

[0060] In step 201, in response to a power-on operation on a target development board, a first chip to be tested is controlled to start a first test program based on a test selection program preconfigured in a switching circuit.

[0061] The target development board is a development board installed with the first chip to be tested, which can be a development board with any function that needs to perform reliability testing of the function. The first chip to be tested is a chip to be tested installed on the target development board. For example, the target development board can be a system on chip (SoC) development board, and the first chip to be tested can be a SOC chip; the target development board is a base station processing development board, and the first chip to be tested can be a UCP4008 chip installed on the base station processing development board.

[0062] Among them, the power-on operation of the target development board can be a power startup operation performed by the user on the target development board to provide power drive for the overall system operation of the target development board. The switching circuit is a circuit in the target development board that is connected to the first chip to be tested through a pin, which can realize the switching of different test programs for the first chip to be tested. The switching circuit can be, for example, a multiple-choice selector (i.e., multiple inputs, one output), in which a test selection program is pre-configured, which can be pre-configured by the user to the switching circuit through the terminal test device 101.

[0063] For example, the user can configure to pre-execute the SLT test and then execute the FT test; or the user can pre-execute the FT test and then execute the SLT test. The embodiments of the present application do not impose any special restrictions on this.

[0064] In an optional embodiment of the present disclosure, the first test program is a test program corresponding to the packaged finished product test FT; the corresponding second test program is a test program corresponding to the system-level test SLT; when executing the above step 201, based on the test selection program pre-configured in the switching circuit, the first chip to be tested is controlled to start the first test program from the flash memory circuit based on the test selection program.

[0065] For example, since the FT test program is a uboot program, the processor kernel and the system cannot be loaded when the first chip to be tested executes the FT test program after startup, and the SLT test cannot be performed, because the SLT test must be performed under the operating system. Therefore, the FT test program can be stored in the Flash circuit to start the FT test program in the Flash circuit.

[0066] In step 202, one or more first target test instances in each test instance circuit are tested based on a first test program to obtain a first test result.

[0067] Among them, each test instance circuit connected to the chip to be tested through pins is a circuit used to implement a specific independent function. Taking the chip to be tested as a processor UCP4008 chip as an example, each test instance circuit can be a storage circuit, a low-speed communication interface circuit, a high-speed communication interface circuit, a clock circuit, a processor UCP4008 minimum unit circuit, a general purpose input and output interface (General Purpose Input Output, referred to as GPIO) interconnection circuit, etc.

[0068] Exemplarily, each test instance circuit connected to the chip to be tested through pins may include a target test instance circuit and other test instance circuits. The target test instance circuit may be an instance circuit that can implement a specific function and directly perform a test without connecting to other external devices; on the contrary, other test instance circuits must be connected to external devices to implement the corresponding functions and perform functional tests.

[0069] In the following, in conjunction with a specific embodiment, an exemplary description is given of a situation where each test example circuit includes at least a target test example circuit:

[0070] In an optional embodiment of the present disclosure, each test instance circuit includes at least a target test instance circuit; in the above step 202, one or more first target test instances in each test instance circuit are tested based on the first test program to obtain a first test result, and a loopback circuit of the first test instance circuit can be constructed based on a functional interface in the target test instance circuit; a loopback test is performed on the first target test instance corresponding to the loopback circuit of the first test instance circuit based on the first test program to obtain a first test result.

[0071] Among them, the loop circuit does not need to be connected to external devices or chips, and can be directly connected to different pin interfaces to form a corresponding loop circuit.

[0072] The following will be combined with different embodiments to exemplarily illustrate the process of building a loopback circuit for different target test instance circuits:

[0073] Embodiment 1: In an optional embodiment of the present disclosure, the target test instance circuit includes a first target test instance circuit, and based on the functional interface of the first test instance circuit, a loopback circuit of the first test instance circuit is constructed, including: directly connecting the first target test instance circuit with the first functional interface and the second functional interface of the chip to be tested, to construct a loopback circuit of the first target test instance circuit.

[0074] In this embodiment, when the target test instance circuit only includes the first target test instance circuit, the first target test instance circuit can be directly connected to the first functional interface and the second functional interface of the chip to be tested, so as to construct a loop circuit of the first target test instance circuit. Figure 3 PCIE / TMAC loopback test, CPRI / SRIO loopback test, etc.

[0075] Embodiment 2: The target test instance circuit includes a second target test instance circuit; when the target test instance circuit includes at least the second target test instance circuit, multiple second target test instance circuits are connected to the pin interface of the chip to be tested based on resistors with preset resistance values ​​to construct a loop circuit of the second target test instance circuit.

[0076] In this embodiment, when the target test instance circuit only includes the second target test instance circuit, multiple second target test instance circuits are connected to the pin interface of the chip to be tested based on the resistors of the preset resistance value to construct a loop circuit of the second target test instance circuit. The preset resistance value can be 0Ω, for example, Figure 3 The GPIOA5-GPIOA1, GPIOB31-GPIOB29 pin interfaces.

[0077] Embodiment 3: The target test instance circuit includes a first target test instance circuit and a second target test instance circuit; the first target test instance circuit is directly connected to the first functional interface and the second functional interface of the chip to be tested to construct a loop circuit of the first target test instance circuit; and multiple second target test instance circuits are connected to the pin interfaces of the chip to be tested based on resistors with preset resistance values ​​to construct a loop circuit of the second target test instance circuit.

[0078] In this embodiment, when the target test instance circuit includes the first target test instance circuit and the second target test instance circuit, the situations of the above-mentioned Embodiment 1 and Embodiment 2 may exist at the same time.

[0079] In addition to the above embodiments, each test example circuit may also include other test example circuits. Since other test example circuits must be connected to external devices to implement corresponding functions and perform functional tests, in order to ensure the efficiency of chip testing, other test example circuits may be configured with a minimum unit external circuit. The minimum unit external circuit refers to a circuit with the smallest complexity.

[0080] In step 203, in response to the first test result being a test success, the first chip to be tested is controlled to start a second test program based on the test selection program.

[0081] Exemplarily, when the first test result obtained for the first test program is a test success, the switching program can be started based on the switching circuit to switch from the first test program to the second test program. Conversely, if the first test result obtained for the first test program is a test failure, the test is terminated directly.

[0082] In another optional embodiment of the present disclosure, the first test program is continued to be the test program corresponding to the packaged finished product test FT; the corresponding second test program is the test program corresponding to the system-level test SLT as an example, when executing the above step 203 to control the first chip to be tested to start the second test program based on the test selection program, the first chip to be tested can be controlled to start the second test program from the embedded storage controller EMMC circuit according to the test selection program.

[0083] For example, since the FT test program is a uboot program, the processor kernel and the system cannot be loaded after the first chip to be tested executes the FT test program after startup, and the SLT test cannot be performed, because the SLT test must be performed under the operating system. Therefore, the SLT test program can be stored in the system-level embedded memory controller (Embedded Multi Media Card, EMMC for short) circuit to start the SLT test program in the EMMC circuit.

[0084] In step 204, one or more second target test instances in each test instance circuit are tested according to a second test program to obtain a second test result.

[0085] The second target test instance is usually different from the first target test instance, but the same situation is not excluded, that is, the second target test instance can be the same as or different from the first target test instance. The second target test instance is the test object corresponding to the second test program.

[0086] Exemplarily, one or more second target test instances in each test instance circuit are tested according to a second test program to obtain a second test result. If the second test result is a successful test, the test result can be fed back to the terminal test device; otherwise, if the second test result obtained for the second test program is a test failure, the test is terminated directly.

[0087] Furthermore, in the implementation Figure 2 In the steps shown, in order to facilitate testing of a large number of chips to be tested, a socket base can be installed on the target development board, and the chip to be tested can be inserted into the socket base.

[0088] Through this embodiment, when replacing the chip to be tested, it is not necessary to carry a large number of pins of the chip to be tested, and only the chip to be tested on the socket base needs to be replaced, thereby improving the applicability of the target development board.

[0089] After completing the above Figure 2 In the steps shown, the target development board controls a power-off operation on the target development board in response to a test completion instruction for the first chip to be tested; controls a robotic arm to unload the first chip to be tested from the socket base, and controls the robotic arm to press the second chip to be tested against the socket base in response to a power-on operation on the target development board, until a test completion instruction for the second chip to be tested is received.

[0090] In this embodiment, the robot arm unloads the first chip to be tested that has completed the test and replaces it with the second chip to be tested that is waiting to be tested. This can avoid manual intervention and automatically complete the automated testing process of a large number of sample chips, thereby improving the efficiency of chip testing.

[0091] In addition, during the connection process between the socket base and the chip to be tested, in order to ensure good contact and user safety, it is usually necessary to fix and tighten it before powering on, which undoubtedly increases the time consumption of chip replacement. However, when using a robotic arm, there is no need to perform the above-mentioned fixing and tightening operations. It is only necessary to control the robotic arm to press the second chip to be tested to the socket base, and then the power-on test can be performed directly, thereby reducing the time consumption of chip replacement and improving the screening efficiency.

[0092] For ease of understanding, the following will take the base station processor UCP4008 as the chip to be tested as an example. Figure 3 , Figure 4 , Figure 5 The above-mentioned test process for the base station processor UCP4008 chip is exemplified.

[0093] Figure 3 A schematic diagram of a base station processor UCP4008 chip board circuit provided in one embodiment of the present application; Figure 3 As shown, the board circuit of the base station processor UCP4008 chip is mainly divided into a storage circuit, a low-speed communication interface circuit, a high-speed communication interface circuit, a clock circuit, a processor UCP4008 minimum unit circuit and a startup switching circuit, and a GPIO interconnection circuit. The following will provide exemplary descriptions of each of the above components.

[0094] The first part is the storage circuit. The storage circuit includes EMMC circuit, Flash circuit, switching circuit, DDR circuit and EPPROM circuit. 1) EMMC circuit, used to control UCP4008 to start the SLT test program from EMMC (after normal startup, verify the SLT test program);

[0095] 2) Flash circuit: used to control UCP4008 to start the FT test program from the Flash circuit (after normal startup, verify the FT test program);

[0096] 3) A switching circuit is used to control the processor UCP4008 to start from the EMMC circuit or the Flash circuit first, and the switching can be achieved by controlling this circuit with a program, thereby improving the efficiency of the test.

[0097] 4) EPPROM circuit (stores some board startup environment variables, read and write through I2C interface);

[0098] 5) DDR circuit: The board has four DDR4 chips with a particle capacity of 2Gb. The chip DDR interface can be verified by executing the SLT program;

[0099] Part 2: Low-speed interface circuit:

[0100] UART circuit (used to communicate with the host computer), SPI circuit (configure the device ADRV9026 and phase-locked loop 8A34002 on the board through SPI), I2C circuit (configure EEPROM), JTAG circuit (for internal debugging of the chip)

[0101] Part III: High-speed interface circuit:

[0102] 1) cpri / eCPRI loopback test, TMAC loopback test, PCIE loopback test, srio loopback test. (Among them, the loopback test is to connect the data sending end of the relevant high-speed interface module of the chip UCP4008 directly to the data receiving end through the PCB, without using additional devices.)

[0103] 2) JESD204B circuit: Use the peripheral device ADRV9026 and related configuration circuits to verify whether the high-speed interface is normal;

[0104] 3) Gigabit Ethernet GMAC1 / 2: Use Ethernet PHY chip 88E1512 to implement Gigabit Ethernet communication, which can communicate with the host computer or ping between the two network ports;

[0105] Part 4: Clock Circuit:

[0106] 1) Use the phase-locked loop 8A34002 to provide the working clock for the high-speed interface module (PET PMA / ECS PMA) of the board;

[0107] The PET PMA module is used to verify: PCIE interface and TMAC interface;

[0108] The ECS PMA module is used to verify: CPEI / eCPRI interface and SRIO interface;

[0109] 2) The clock generator AD9528 increases the working clock for the JESD204B communication interface;

[0110] Part 5, GPIO interconnection circuit: verify the GPIO function of UCP4008.

[0111] exist Figure 3 Based on the shown Figure 4 This is a top view of the board circuit of one of the base station processor UCP4008 chips; refer to Figure 4 As shown in the figure, the boxed part is the installation position of the socker base where the UCP4008 chip is located. The UCP4008 chip can be replaced manually or using a robotic arm.

[0112] and Figure 3 , Figure 4 The physical picture corresponding to the board picture shown is as follows Figure 5 As shown, Figure 5 A physical diagram of a base station processor UCP4008 chip board circuit provided in one embodiment of the present application, refer to Figure 5 As shown, when manually replacing the UCP4008 chip from the socket base, it is necessary to use a fixing device and screws (such as Figure 5 The position marked with a circle in the figure is a screw) to tighten it to ensure the contact between the pin and the base. If a mechanical arm is used, the mechanical arm can be controlled to press the second chip to be tested to the socket base.

[0113] It should be explained that all power / communication cables on the target development board are routed out from the bottom during PCB design, which is convenient for use on the automatic test line.

[0114] In an optional embodiment of the present application, the first chip to be tested may be a voltage-controlled oscillator output frequency control chip, which includes at least a voltage-controlled oscillator, a base station processor, and a phase-locked loop circuit. The chip test process also includes: the base station processor receives a specific fluctuation frequency signal emitted by the voltage-controlled oscillator, and records the number of clocks of the specific fluctuation frequency signal;

[0115] The base station processor reads the clock quantity when the specific fluctuation frequency signal and the second pulse sent by the GPS receiver are phase-locked in the phase-locked loop circuit;

[0116] When the number of clocks does not meet a preset value, the base station processor adjusts the control voltage of the voltage-controlled oscillator based on the number of clocks to achieve control over the output frequency until the number of clocks meets the preset value.

[0117] In an optional embodiment of the present application, when the number of clocks does not meet the preset value, the base station processor adjusts the control voltage of the voltage-controlled oscillator based on the number of clocks to achieve control of the output frequency until the number of clocks meets the preset value, including:

[0118] When the number of clocks is greater than the preset value, the base station processor dynamically controls the control voltage of the voltage-controlled oscillator to decrease until the number of clocks meets the preset value;

[0119] When the clock quantity is less than the preset value, the base station processor dynamically controls the control voltage of the voltage-controlled oscillator to increase until the clock quantity meets the preset value.

[0120] In an optional embodiment of the present application, if the clock quantity meets the preset value, the base station processor determines that there is no phase deviation between the specific fluctuation frequency output by the voltage-controlled oscillator and the second pulse.

[0121] In an optional embodiment of the present application, when the specific fluctuation frequency signal and the second pulse emitted by the GPS receiver are phase-locked in the phase-locked loop circuit, the base station processor reads the clock quantity, including:

[0122] The base station processor performs phase lock on the specific fluctuation frequency signal and the second pulse emitted by the GPS receiver through the phase detector, loop filter, and target voltage-controlled oscillator in the phase-locked loop circuit, and reads the clock quantity to lock the specific fluctuation frequency;

[0123] The base station processor reads the clock quantity.

[0124] In an optional embodiment of the present application, the voltage-controlled oscillator output frequency control chip also includes a GPS receiver, which receives GPS signals and sends second pulses to the base station processor based on an onboard receiver.

[0125] In an optional embodiment of the present application, the voltage-controlled oscillator output frequency control chip also includes a clock buffer, which receives a specific fluctuation frequency signal sent by the voltage-controlled oscillator, copies the specific fluctuation frequency signal into multiple clocks with the same frequency and phase, and sends the multiple clocks to the base station processor and the phase-locked loop circuit respectively.

[0126] In an optional embodiment of the present application, the base station processor includes a counting deviation calculation module and an output frequency adjustment module, the counting deviation calculation module is used to detect the deviation between the clock quantity and the preset value, and the output frequency adjustment module is used to adjust the control voltage of the voltage-controlled oscillator based on the clock quantity to achieve control of the output frequency when the clock quantity does not meet the preset value, until the clock quantity meets the preset value.

[0127] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0128] Furthermore, in one embodiment, an embodiment of the present application also provides a chip testing system, which includes a terminal testing device and a target development board. The target development board has at least a first chip to be tested, each test instance circuit connected to the first chip to be tested, and a switching circuit installed in the board circuit.

[0129] The terminal test device is used to pre-configure a test selection program in the switching circuit, and to configure a first test program and a second test program in the target development board.

[0130] A target development board is used to control a first chip to be tested to start a first test program based on a test selection program pre-configured in a switching circuit in response to a power-on operation on the target development board; to test one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; in response to the first test result being a test success, to control the first chip to be tested to start a second test program based on the test selection program; and to test one or more second target test instances in each test instance circuit according to the second test program to obtain a second test result.

[0131] To implement the above chip testing method, see Figure 6 An embodiment of the present application provides a chip testing device, which is applied to a target development board. The board circuit of the target development board is at least equipped with a first chip to be tested, test instance circuits connected to the first chip to be tested, and a switching circuit. The chip testing device 600 may include: a first program startup module 601, a first test module 602, a second program startup module 603, and a second test module 604.

[0132] The first program starting module 601 is used to control the first chip to be tested to start the first test program based on the test selection program pre-configured in the switching circuit in response to the power-on operation of the target development board;

[0133] A first test module 602 is used to test one or more first target test instances in each test instance circuit based on a first test program to obtain a first test result;

[0134] A second program starting module 603 is used to control the first chip to be tested to start a second test program based on the test selection program in response to the first test result being a test success;

[0135] The second test module 604 is used to test one or more second target test instances in each test instance circuit according to a second test program to obtain a second test result.

[0136] In an optional embodiment of the present disclosure, the first test program is a test program corresponding to the packaged finished product test FT; the second test program is a test program corresponding to the system-level test SLT; the first program startup module 601 controls the first chip to be tested to start the first test program from the flash memory circuit based on the test selection program; and / or the second program startup module 603 is used to control the first chip to be tested to start the second test program from the embedded storage controller EMMC circuit according to the test selection program.

[0137] In an optional embodiment of the present disclosure, each test instance circuit includes at least a target test instance circuit, and a first test module 602 is used to construct a loopback circuit of the first test instance circuit based on a functional interface in the target test instance circuit; and perform a loopback test on a first target test instance corresponding to the loopback circuit of the first test instance circuit based on a first test program to obtain a first test result.

[0138] In an optional embodiment of the present disclosure, the target test instance circuit includes a first target test instance circuit, and / or a second target test instance circuit; a first test module 602 is used to directly connect the first target test instance circuit with the first functional interface and the second functional interface of the chip to be tested to construct a loop circuit of the first target test instance circuit when the target test instance circuit includes at least the first target test instance circuit; the first test module 602 is used to connect multiple second target test instance circuits with pin interfaces of the chip to be tested based on resistors with preset resistance values ​​to construct a loop circuit of the second target test instance circuit when the target test instance circuit includes at least the second target test instance circuit.

[0139] In an optional embodiment of the present disclosure, the device may further include a chip insertion module, and the chip insertion module is used to install a socket base on the target development board and insert the chip to be tested into the socket base.

[0140] In an optional embodiment of the present disclosure, the device may also include a control module, which is used to control a power-off operation on a target development board in response to a test completion instruction for a first chip to be tested; control a robotic arm to unload the first chip to be tested from a socket base, and control the robotic arm to press the second chip to be tested against the socket base in response to a power-on operation on the target development board, until a test completion instruction for the second chip to be tested is received.

[0141] For the specific definition of the above-mentioned chip testing device, please refer to the definition of the chip testing method above, which will not be repeated here. Each module in the above-mentioned chip testing device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0142] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 7As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a chip testing method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the chip testing method as described above is implemented.

[0143] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above chip testing method can be implemented.

[0144] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0145] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0146] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1A function specified in one or more boxes.

[0147] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0148] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0149] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip testing method, characterized in that: Applied to a target development board, the board circuit of the target development board is installed with at least a first chip to be tested, each test instance circuit connected to the first chip to be tested, and a switching circuit, the method comprising: In response to a power-on operation on the target development board, controlling the first chip to be tested to start a first test program based on a test selection program preconfigured in the switching circuit; Testing one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; In response to the first test result being a test success, controlling the first chip to be tested to start a second test program based on the test selection program; One or more second target test instances in each test instance circuit are tested according to the second test program to obtain a second test result.

2. The method according to claim 1, characterized in that The first test program is a test program corresponding to the packaged finished product test FT; the second test program is a test program corresponding to the system level test SLT; based on the test selection program pre-configured in the switching circuit, the first chip to be tested is controlled to start the first test program, and / or, according to the test selection program, the first chip to be tested is controlled to start the second test program, including: Based on the test selection program, the first chip to be tested is controlled to start the first test program from the flash memory circuit; and / or, according to the test selection program, the first chip to be tested is controlled to start the second test program from the embedded memory controller EMMC circuit.

3. The method according to claim 1, characterized in that Each of the test instance circuits at least includes a target test instance circuit; and testing one or more first target test instances in each of the test instance circuits based on the first test program to obtain a first test result includes: Based on the functional interface in the target test instance circuit, construct a loopback circuit of the first test instance circuit; Based on the first test program, a loopback test is performed on a first target test instance corresponding to a loopback circuit of the first test instance circuit to obtain the first test result.

4. The method according to claim 3, characterized in that The target test instance circuit includes a first target test instance circuit and / or a second target test instance circuit; and based on a functional interface of the first test instance circuit, constructing a loopback circuit of the first test instance circuit includes: When the target test instance circuit includes at least a first target test instance circuit, directly connecting the first target test instance circuit to the first functional interface and the second functional interface of the chip to be tested to construct a loopback circuit of the first target test instance circuit; When the target test instance circuit includes at least a second target test instance circuit, multiple second target test instance circuits are connected to the pin interface of the chip to be tested based on resistors with preset resistance values ​​to construct a loop circuit of the second target test instance circuit.

5. The method according to claim 1, characterized in that The method further comprises: A socket base is installed on the target development board, and the chip to be tested is inserted into the socket base.

6. The method according to claim 5, characterized in that The method further comprises: In response to a test completion instruction for the first chip to be tested, controlling a power-off operation for the target development board; The robot arm is controlled to unload the first chip to be tested from the socket base, and the robot arm is controlled to press the second chip to be tested against the socket base in response to the power-on operation of the target development board until a test completion instruction for the second chip to be tested is received.

7. A chip testing system, characterized in that: The system includes a terminal test device and a target development board, wherein the board circuit of the target development board is installed with at least a first chip to be tested, each test instance circuit connected to the first chip to be tested, and a switching circuit, and the system includes: The terminal test device is used to pre-configure a test selection program into the switching circuit, and to configure a first test program and a second test program into the target development board; The target development board is used to control the first chip to be tested to start a first test program based on a test selection program pre-configured in the switching circuit in response to a power-on operation of the target development board; test one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; in response to the first test result being a test success, control the first chip to be tested to start a second test program based on the test selection program; and test one or more second target test instances in each test instance circuit according to the second test program to obtain a second test result.

8. A chip testing device, characterized in that: Applied to a target development board, the board circuit of the target development board is installed with at least a first chip to be tested, each test instance circuit connected to the first chip to be tested, and a switching circuit, the device comprises: A first program starting module, configured to control the first chip to be tested to start a first test program based on a test selection program preconfigured in the switching circuit in response to a power-on operation on the target development board; A first test module, configured to test one or more first target test instances in each test instance circuit based on the first test program to obtain a first test result; A second program starting module, configured to control the first chip to be tested to start a second test program based on the test selection program in response to the first test result being a test success; The second test module is used to test one or more second target test instances in each test instance circuit according to the second test program to obtain a second test result.

9. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the chip testing method according to any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip testing method according to any one of claims 1 to 6 are implemented.

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