A radar pulse signal sampling and storage method and device based on FPGA

Abstract

The present invention discloses a radar pulse signal sampling and storage method and device based on FPGA in the field of signal processing technology. The method comprises: S1: acquiring a radar pulse signal and sampling it, and obtaining radar pulse data to be stored after processing; S2: acquiring a half-power point from the radar pulse data, and starting to store data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point of the rising edge of the radar pulse data. Compared with conventional practices, this sampling and storage method can effectively avoid the influence of the pulse signal amplitude on the position of the rising edge of the detection signal, which makes the starting position of the data storage relatively stable, and further makes the position of the interference target that is delayed and forwarded later relatively stable, and has a better interference effect.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a radar pulse signal sampling and storage method and device based on FPGA. Background Art

[0002] When using an FPGA to sample, store, and delay jammer radar pulse signals, the FPGA must first store the radar pulse signal's sampled data and then generate an interference signal at a specific distance through delayed forwarding. If the radar pulse width is large, the signal must be extracted before storage. A high extraction factor results in a lower data sampling rate. Furthermore, the starting point of storage can affect the location of the interference signal, as radar determines target distance based on the arrival time of the rising edge of the echo pulse. Therefore, the timing of data storage becomes a key factor influencing the effectiveness of the jamming.

[0003] Typically, an FPGA performs an FFT on sampled data to determine whether the FFT peak exceeds a threshold. If the FFT peak exceeds the threshold, it indicates the presence of a pulse signal, and the detection signal is set to 1. If it falls below the threshold, the detection signal is set to 0. When the detection signal is 1, the sampled pulse data is stored. However, this method only works when the sampling rate of the data to be stored is high. For data with lower sampling rates, determining whether the signal should be stored based on whether the FFT peak exceeds the detection threshold is not suitable. Although the FFT IP core in the FPGA performs a sliding window FFT, the number of data points in the sliding window is the same as the number of FFT points. This means that data that has participated in one FFT will not participate in the next FFT. Since the arrival of pulse signals is random, the number of pulse data points in each FFT is also random. This makes the timing and amplitude of the FFT peak very random, and thus the starting position of the data storage also random. While multiple FFT IP cores can be used to reduce the number of data points in the sliding window, using multiple FFT IP cores also increases code complexity and resource usage.

[0004] In this case, for data with a low sampling rate, the conventional approach is to directly determine whether the signal amplitude exceeds the detection threshold. The detection threshold is manually set and is usually set to a value higher than the noise floor. This approach causes the starting position of data storage to be affected by the amplitude of the pulse signal. When the pulse signal amplitude is low, the starting position of data storage is closer to the trailing edge of the pulse signal; when the pulse signal amplitude is high, the starting position of data storage is closer to the leading edge of the pulse signal. Summary of the Invention

[0005] The present application provides an FPGA-based radar pulse signal sampling and storage method, which solves the problem of inaccurate storage starting position of pulse data with a low sampling rate in the prior art, and achieves a relatively stable starting position of data storage, thereby making the position of the interference target that is subsequently delayed and forwarded relatively stable, thereby improving the interference effect.

[0006] The embodiment of the present application provides a radar pulse signal sampling and storage method based on FPGA, comprising the following steps:

[0007] S1: Acquire radar pulse signals and perform sampling, and obtain radar pulse data with a low sampling rate to be stored after processing;

[0008] S2: Obtain a half-power point from the radar pulse data, and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data.

[0009] The beneficial effect of the above embodiment is that compared with conventional practices, this sampling and storage method can effectively avoid the influence of the pulse signal amplitude on the position of the rising edge of the detection signal, which makes the starting position of the data storage more stable, and thus makes the position of the interference target that is delayed and forwarded later also more stable, and has a better interference effect.

[0010] Based on the above embodiments, the present application can be further improved as follows:

[0011] In one embodiment of the present application, step S1 is specifically as follows:

[0012] S1.1: Acquire the radar pulse signal and perform sampling to obtain a sampled signal;

[0013] S1.2: Performing orthogonal down-conversion and first-stage filtering on the sampled signal;

[0014] S1.3: performing a secondary down-conversion process on the sampled signal after the primary filtering;

[0015] S1.4: The sampled signal after the secondary down-conversion is subjected to multiple decimation and secondary filtering to obtain the radar pulse data of the low sampling rate to be stored. This reduces the sampling rate and the amount of data required to be stored.

[0016] In one embodiment of the present application, in step S1.3, the secondary down-conversion processing is performed as follows:

[0017] The sampled signal after primary filtering is copied into two copies. One copy is temporarily stored in RAM, and the other copy undergoes FFT processing. The FFT peak is compared with a set threshold. The frequency of the sampled signal is calculated based on the position of the peak that exceeds the threshold. This frequency is used as the local oscillator to perform a second down-conversion on the cached sampled signal. This shifts the sampled radar pulse signal to near zero frequency.

[0018] In one embodiment of the present application, in step S2, data storage is stopped when the signal amplitude is less than the half power point for the first time.

[0019] In one embodiment of the present application, in step S2, the stored data is triggered by a detection signal. When the signal amplitude in the radar pulse data is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and data storage starts from the time when the detection signal is first set to 1. When the signal amplitude in the radar pulse data is less than the amplitude of the half-power point, the detection signal is set to 0, and data storage stops from the time when the detection signal is first set to 0.

[0020] In one embodiment of the present application, in step S2, the first standard maximum point is obtained as follows:

[0021] The radar pulse data is retrieved from the rising edge of the radar pulse data, and the amplitude average of multiple data points following the maximum point is obtained. This amplitude average is then compared with the amplitude corresponding to the maximum point. If the difference is less than a set value, the maximum point is used as the first standard maximum point. Otherwise, the next maximum point after the maximum point is obtained and verified again until the first standard maximum point is obtained. Any glitches that may exist on the rising edge of the pulse signal are processed to ensure that the detection threshold generated by the pulse signal amplitude is correct.

[0022] In one embodiment of the present application, in step S2, a noise floor threshold is further set, and the maximum point is greater than the noise floor threshold.

[0023] In one embodiment of the present application, in step S2, the set value is set to 6db.

[0024] The present application also provides an FPGA-based radar pulse signal sampling and storage device, including:

[0025] A processing module is used to acquire radar pulse signals and perform sampling, and obtain radar pulse data to be stored after processing;

[0026] A storage module is used to obtain a half-power point from the radar pulse data and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data.

[0027] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0028] 1. This sampling and storage method changes the conventional manually set detection threshold into a detection threshold automatically generated according to the signal amplitude, thus preventing the starting position of data storage from being affected by changes in the signal amplitude.

[0029] 2. This sampling and storage method provides a further improvement solution for the burrs that may exist on the rising edge of the pulse signal. It uses a more accurate method to determine the amplitude of the radar pulse signal to ensure that the detection threshold generated by the pulse signal amplitude is correct.

[0030] 3. This sampling and storage method processes the acquired radar pulse signal in multiple steps, reducing the sampling rate while reducing the amount of data required to be stored, facilitating subsequent data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings required for the specific embodiments or the description of the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. Elements or parts in the drawings are not necessarily drawn to scale.

[0032] Figure 1 This is a flowchart of a radar pulse signal sampling and storage method based on FPGA in an embodiment of the present application;

[0033] Figure 2 A flowchart of the steps for obtaining radar pulse data to be stored in an embodiment of the present application;

[0034] Figure 3 Signal diagram of radar pulse data in the embodiment of this application Figure 1 ;

[0035] Figure 4 Signal diagram of radar pulse data in the embodiment of this application Figure 2 ;

[0036] Figure 5 A block diagram of a radar pulse signal sampling and storage device based on FPGA provided by an embodiment of the present invention;

[0037] Figure 6The present invention provides a schematic structural diagram of an electronic device. DETAILED DESCRIPTION

[0038] The present invention will be further explained below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, modifications of various equivalent forms of the present invention made by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0039] In the description of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art may combine and combine different embodiments or examples described in the present invention, as well as features of different embodiments or examples, without any contradiction.

[0040] Example:

[0041] like Figure 1 As shown, a radar pulse signal sampling and storage method based on FPGA includes the following steps:

[0042] S1: Acquire radar pulse signals and perform sampling, and obtain low-sampling-rate radar pulse data to be stored after processing; specifically:

[0043] S1.1: Acquire and sample a radar pulse signal to obtain a sampled radar pulse signal;

[0044] S1.2: Perform orthogonal down-conversion and first-stage filtering on the sampled radar pulse signal;

[0045] S1.3: Perform secondary down-conversion on the radar pulse signal after the first-stage filtering to adjust the radar pulse signal to near zero frequency;

[0046] Among them, the secondary down-conversion processing method is as follows:

[0047] The radar pulse signal after the first-stage filtering is copied into two copies. One copy is temporarily stored in RAM, and the other copy is processed by FFT. The FFT peak is compared with the threshold. The frequency of the radar pulse signal is calculated based on the position of the peak that exceeds the threshold. This frequency is used as the local oscillator to perform a second down-conversion on the cached radar pulse signal, thereby moving the radar pulse signal to near zero frequency.

[0048] S1.4: Perform multiple decimation and secondary filtering on the near-zero-frequency radar pulse signal to obtain low-sampling-rate radar pulse data to be stored.

[0049] S2: Obtain the half-power point from the radar pulse data. Start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, and stop storing data when the signal amplitude is less than the half-power point. The half-power point is obtained by subtracting the set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data.

[0050] Typically, this setting is set to 6dB. That is, the half-power point is obtained by subtracting 6dB from the amplitude of the pulse signal corresponding to the first standard maximum point. In practice, the half-power point can also be obtained by subtracting 3dB from the power of the pulse signal corresponding to the first standard maximum point.

[0051] Among them, the storage data is triggered by the detection signal. When the signal amplitude in the radar pulse data is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and the pulse data is stored from the time the detection signal is 1. When the signal amplitude is less than the amplitude of the half-power point, the detection signal is set to 0, and the pulse data storage is stopped from the time the detection signal is 0.

[0052] Among them, the first standard maximum point is obtained as follows:

[0053] Obtain the maximum point in the rising edge phase of the radar pulse data, and obtain the amplitude average of multiple data points following the maximum point. Compare the amplitude average with the amplitude corresponding to the maximum point. If the difference is less than the set value, the maximum point is used as the first standard maximum point. Otherwise, obtain the next maximum point after the maximum point and verify again until the first standard maximum point is obtained.

[0054] In practical applications of FPGA, a noise floor threshold must be set. The maximum point must be greater than the noise floor threshold. When the amplitude of the signal data exceeds the threshold, it indicates that a radar pulse signal has arrived, triggering and searching for the first standard maximum point greater than the noise floor threshold.

[0055] The following provides a specific example of a radar pulse signal sampling and storage method based on FPGA.

[0056] like Figure 2 As shown, step S1 is exemplified as follows:

[0057] S1.1: Assume that the microwave module converts the radar pulse signal to an intermediate frequency of 2MHz to 30MHz. The FPGA samples the intermediate frequency radar pulse signal at a sampling rate of 2.4GHz, obtaining 16 channels of AD sampling data with a sampling rate of 150MHz. However, since the radar pulse signal width is relatively large and the sampling rate is also relatively high, in order to store the radar pulse signal data, these 16 channels of AD sampling data need to be extracted, thereby reducing the sampling rate and the amount of data required to be stored.

[0058] S1.2: These 16 channels of data are decimate-filtered to obtain single-channel AD data with a sampling rate of 75 MHz. This single-channel AD data with a sampling rate of 75 MHz is first orthogonally down-converted to a bandwidth of -14 MHz to 14 MHz. The resulting complex signal is then decimate-doubled to obtain single-channel AD data with a sampling rate of 37.5 MHz, which is then filtered.

[0059] S1.3: The filtered data is then copied into two copies. One copy is temporarily stored in RAM, and the other copy undergoes a 2048-point FFT. The FFT peak is then determined to determine whether it exceeds a threshold. The frequency of the radar pulse signal is calculated based on the position of the peak that exceeds the threshold. The buffered data is then down-converted twice using the measured radar pulse signal frequency as the local oscillator, shifting the radar pulse signal to near zero frequency.

[0060] S1.4: Next, the radar pulse signal near the zero frequency is decimated and filtered by a factor of 128, so that the sampling rate of the data becomes 292.96875 kHz. This obtains the radar pulse data with a low sampling rate to be stored, which also facilitates the data storage in the subsequent step S2.

[0061] In this example, since the sample rate of the extracted data in step S1 is 292.96875 kHz, meaning data is collected approximately every 3.41 μs, if the starting position of data storage is not accurately correlated with the pulse start position, the rising edge of the subsequent interference signal will fluctuate significantly. For example, when storing a pulse signal, the data may start and store five data points before the pulse arrives, or storage may begin five data points after the pulse arrives. In any case, if the data fluctuates between the two, the rising edge of the actual pulse will fluctuate by ±17.05 μs compared to the expected rising edge position, which can significantly affect the target position. If the speed of light is calculated as 300 m / μs, the rising edge of the actual pulse will differ from the expected rising edge by 1 μs, resulting in a target position difference of 150 m (radar signals travel in a round trip, so the distance calculation should be divided by 2).

[0062] Therefore, before storing radar data, it is necessary to determine the starting position of data storage to ensure that the positional relationship between the starting position of data storage and the start of the pulse is fixed. Therefore, in step S2, this method uses the half-power point as the starting position and end position of the pulse signal, and shows how to find the half-power point of the pulse signal.

[0063] An example of step S2 is as follows:

[0064] In most cases, radar pulse data looks like this: Figure 3As shown, it is not a standard rectangular pulse signal, because the pulse needs a period of time to rise and fall. To find the half-power point of the pulse, it is necessary to first determine the power or amplitude of the pulse signal, because the power of the pulse signal minus 3db or the pulse signal amplitude minus 6db is the size of its half-power point. Figure 3 It can be seen that the amplitude value of the pulse rising edge stage is constantly increasing, so we only need to find the first maximum value in the rising edge stage, which is the first standard maximum value. This maximum value is the amplitude of the pulse signal, and after subtracting 6db, it is the half-power point. When the signal amplitude is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and the pulse data is stored from the time the detection signal is 1.

[0065] In actual process, the rising and falling edges of radar pulse signals may not be as Figure 3 As shown, not as smooth, but as Figure 4 As shown in the figure, there are many glitches, so the first N maximum values ​​in the rising edge phase are not standard maximum values, and are not the amplitude of the pulse signal. When the accuracy requirement is high, a more accurate method is needed to determine the amplitude of the pulse signal. Figure 4 As can be seen from the figure, the overall trend during the rising edge phase is increasing. Therefore, the data to the right of each maximum point during the rising edge phase is summed, the average of the summed results is then compared with the amplitude of the maximum point. If the difference between the two amplitudes is within 3dB, the maximum point is used as the first standard maximum, and the corresponding amplitude is used as the radar pulse amplitude. Otherwise, the next maximum point is verified. After finding a maximum point that meets the conditions as the first standard maximum, 6dB is subtracted from the amplitude of the first standard maximum to obtain the amplitude of the half-power point. When the signal amplitude is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and pulse data is stored starting from the time the detection signal is 1.

[0066] This invention provides an improved method for determining the storage starting position of pulse data with low sampling rates. Compared to conventional methods, this method replaces the manually set detection threshold with an automatically generated threshold based on the actual pulse signal amplitude, preventing the data storage starting position from being affected by signal amplitude fluctuations. This makes the data storage starting position more stable, and in turn, the position of the interference target that is subsequently delayed and forwarded is also more stable, achieving better interference effectiveness.

[0067] The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages:

[0068] 1. This sampling and storage method changes the conventional manually set detection threshold into a detection threshold automatically generated according to the signal amplitude, thus preventing the starting position of data storage from being affected by changes in the signal amplitude.

[0069] 2. This sampling and storage method provides a further improvement solution for the glitches that may exist on the rising edge of the pulse signal, namely, a more precise method is used to determine the amplitude of the radar pulse signal to ensure that the detection threshold generated by the pulse signal amplitude is correct.

[0070] 3. This sampling and storage method processes the acquired radar pulse signal in multiple steps, reducing the sampling rate while reducing the amount of data required to be stored, facilitating subsequent data storage.

[0071] Figure 5 This is a block diagram of a radar pulse signal sampling and storage device based on an FPGA according to an embodiment of the present invention. Based on the aforementioned radar pulse signal sampling and storage method, the device includes:

[0072] A processing module is used to acquire radar pulse signals and perform sampling, and obtain radar pulse data to be stored after processing;

[0073] The storage module is used to obtain the half-power point from the radar pulse data and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time. The half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data.

[0074] Figure 5 The functions of each module in the embodiment correspond to the contents in the corresponding method embodiment and will not be repeated here.

[0075] Figure 3 The structure diagram of the electronic device 60 provided in an embodiment of the present invention is shown. The electronic device 60 includes at least one processor 601 (such as a CPU), at least one input / output interface 604, a memory 602, and at least one communication bus 603 for realizing connection and communication between these components. The at least one processor 601 is used to execute computer instructions stored in the memory 602 so that the at least one processor 601 can execute any embodiment of the aforementioned radar pulse signal sampling and storage method. The memory 602 is a non-transitory memory, which may include a volatile memory, such as a high-speed random access memory (RAM), or a non-volatile memory, such as at least one disk storage. The communication connection with at least one other device or unit is realized through at least one input / output interface 604 (which may be a wired or wireless communication interface).

[0076] In some implementations, the memory 602 stores a program 6021 , and the processor 601 executes the program 6021 to execute the content of any of the aforementioned table partitioning method embodiments.

[0077] The electronic device may take many forms, including but not limited to:

[0078] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and their primary purpose is to provide voice and data communications. These terminals include smartphones, multimedia phones, feature phones, and low-end phones.

[0079] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access. These terminals include PDAs, MIDs, and UMPCs.

[0080] (3) Portable entertainment devices: These devices can display and play multimedia content. These devices include audio and video players, handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0081] (4) Specific server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0082] (5) Other electronic devices with data interaction functions.

[0083] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0084] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0085] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A radar pulse signal sampling and storage method based on FPGA, characterized in that: The following steps are involved: S1: Acquire radar pulse signals and perform sampling, and obtain radar pulse data to be stored after processing; S2: Obtain a half-power point from the radar pulse data, and start storing data when the signal amplitude is first greater than or equal to the half-power point, wherein the half-power point is obtained by subtracting a set value from the amplitude of the pulse signal corresponding to the first standard maximum point on the rising edge of the radar pulse data, and the first standard maximum point is determined in the following manner: obtain the maximum point in the same pulse rising edge stage in the radar pulse data, and obtain the amplitude average of multiple data points subsequent to the maximum point, and compare the amplitude average with the amplitude corresponding to the maximum point; if the difference is less than the set value, use the maximum point as the first standard maximum point, otherwise obtain the next maximum point after the maximum point and verify again until the first standard maximum point is obtained.

2. The radar pulse signal sampling and storage method according to claim 1, wherein: The step S1 is specifically as follows: S1.1: Acquire the radar pulse signal and perform sampling to obtain a sampled signal; S1.2: Performing orthogonal down-conversion and first-stage filtering on the sampled signal; S1.3: performing a secondary down-conversion process on the sampled signal after the primary filtering; S1.4: Perform multiple decimation and secondary filtering on the sampled signal after the secondary down-conversion processing to obtain the radar pulse data to be stored.

3. The radar pulse signal sampling and storage method according to claim 2, wherein: In step S1.3, the secondary down-conversion processing method is as follows: The sampling signal after the first-stage filtering is copied into two copies, one of which is temporarily stored in RAM, and the other is subjected to FFT processing. The FFT peak is compared with the set threshold, and the frequency of the sampling signal is calculated based on the position of the peak that exceeds the threshold. This frequency is used as the local oscillator to perform a second down-conversion on the sampling signal temporarily stored in RAM.

4. The radar pulse signal sampling and storage method according to claim 1, wherein: In the step S2, data storage is stopped when the signal amplitude is smaller than the half power point for the first time.

5. The radar pulse signal sampling and storage method according to claim 4, characterized in that: In step S2, the stored data is triggered by a detection signal. When the signal amplitude in the radar pulse data is greater than or equal to the amplitude of the half-power point, the detection signal is set to 1, and data storage begins when the detection signal is first set to 1. When the signal amplitude in the radar pulse data is less than the amplitude of the half-power point, the detection signal is set to 0, and data storage stops when the detection signal is first set to 0.

6. The radar pulse signal sampling and storage method according to claim 1, wherein: In step S2, a noise floor threshold is further set, and the maximum value point is greater than the noise floor threshold.

7. The radar pulse signal sampling and storage method according to claim 1, wherein: In step S2, the set value is set to 6db.

8. A radar pulse signal sampling and storage device based on FPGA, characterized in that: The radar pulse signal sampling and storage method according to any one of claims 1 to 7 further includes: a processing module, configured to acquire and sample the radar pulse signal, and obtain the radar pulse data to be stored after processing; A storage module is used to obtain the half-power point from the radar pulse data and start storing data when the signal amplitude is greater than or equal to the half-power point for the first time, wherein the half-power point is obtained by subtracting a set value from the amplitude corresponding to the first standard maximum point of the rising edge of the radar pulse data.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the radar pulse signal sampling and storage method according to any one of claims 1 to 7 are implemented.

Images