Semiconductor device with integrated optical component

Abstract

The invention relates to a semiconductor device with an integrated optical component. Semiconductor devices having optical wiring layers and associated systems and methods are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive pad on a first side of a substrate and electrically coupled to a conductive material extending partially through a via of the substrate. The method further includes removing material from a second side of the substrate such that the conductive material of the via protrudes beyond the second side of the substrate to define a protruding portion of the conductive material. The method also includes forming an optical wiring layer on the second side of the substrate and at least partially around the protruding portion of the conductive material.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of an invention patent application with an application date of October 18, 2019, application number “201910994488.7”, and invention name “Semiconductor device with integrated optical components”. The parent case claims priority to U.S. Patent Application No. 16 / 168,652 filed by Kaeding et al. on October 23, 2018, entitled “SEMICONDUCTOR DEVICES HAVING INTEGRATED OPTICAL COMPONENTS”, which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present technology generally relates to semiconductor devices having integrated optical components, and more particularly to semiconductor dies having optical wiring layers formed thereon. Background Art

[0004] Packaged semiconductor dies including memory chips, microprocessor chips, and imager chips typically include a semiconductor die mounted on a substrate and enclosed in a protective cover. The semiconductor die includes functional features such as memory cells, processor circuits, and imager devices and bonding pads electrically connected to the functional features. The bonding pads can be electrically connected to terminals outside the protective cover to allow the semiconductor die to be connected to higher-order circuits.

[0005] In some examples, the semiconductor die package may be electrically coupled to various optical components (e.g., transmitters, receivers, etc.) for converting electrical signals to / from the semiconductor die in the package into optical signals, which may be routed to external devices, for example, at a higher speed and / or bandwidth than the electrical signals. Such optical components are typically discrete components located outside the semiconductor die package. For example, discrete optical components may be integrated on an interposer in a side-by-side manner with the semiconductor die package and electrically coupled to the semiconductor die package via conductive wires, traces, etc. to form an electro-optical semiconductor die assembly. Such electro-optical semiconductor die assemblies may be relatively large, and at high data bandwidths, the electrical signals in the conductive wires, traces, etc. may only propagate a small distance until an additional repeater chip is needed to boost the signal. Such repeater chips consume additional power—increasing the cost and complexity of operating the electro-optical semiconductor die assembly. Summary of the invention

[0006] In one aspect, a semiconductor device is provided. The semiconductor device includes: a substrate having a front side, a plurality of circuit elements at the front side, and a back side opposite the front side; a through substrate via (TSV) extending at least partially through the substrate; a conductive material in the TSV; and an optical wiring layer on the back side of the substrate, wherein the conductive material in at least a portion of the TSV protrudes beyond the back side of the substrate and into the optical wiring layer.

[0007] In another aspect, a semiconductor die package is provided. The semiconductor die package comprises: a semiconductor die including: a substrate having a first surface and a second surface opposite the first surface; through substrate vias (TSVs) in the substrate, the TSVs including a conductive material extending through the substrate; and an optical wiring layer located on the second surface, wherein the conductive material of the TSVs protrudes from the second surface of the substrate and passes through the optical wiring layer; an active optical component (a) electrically coupled to the conductive material of at least one of the TSVs and (b) optically coupled to the optical wiring layer; and an optical fiber optically coupled to the optical wiring layer.

[0008] In yet another aspect, a method of manufacturing a semiconductor device is provided. The method includes: forming a conductive pad on a first side of a substrate and electrically coupled to a conductive material of a through hole extending at least partially through the substrate; removing material from a second side of the substrate so that the conductive material of the through hole protrudes beyond the second side of the substrate to define a protruding portion of the conductive material; and forming an optical wiring layer on the second side of the substrate and at least partially around the protruding portion of the conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Many aspects of the present invention may be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on clearly illustrating the principles of the present invention.

[0010] Figures 1A to 1D 1F-1H are side cross-sectional views illustrating various stages in a method of fabricating a semiconductor device according to an embodiment of the present technology.

[0011] Figure 1E yes Figure 1D An enlarged view of a portion of a semiconductor device shown in FIG.

[0012] Figure 2A and 2B 2. A side cross-sectional view and a partially schematic top view, respectively, of a semiconductor die package according to an embodiment of the present technology.

[0013] Figure 2C and 2D According to an embodiment of the present invention Figure 2A An enlarged view of the semiconductor die assembly shown in FIG.

[0014] Figure 3 is a partially schematic top view of a semiconductor die package according to an embodiment of the present technology.

[0015] Figure 4 is a side cross-sectional view of a semiconductor die package in accordance with an embodiment of the present technology.

[0016] Figure 5 is a side cross-sectional view of a semiconductor die package in accordance with an embodiment of the present technology.

[0017] Figure 6 is a side cross-sectional view of a semiconductor die package in accordance with an embodiment of the present technology.

[0018] Figure 7 is a side cross-sectional view of a semiconductor die package in accordance with an embodiment of the present technology.

[0019] Figure 8 is a side cross-sectional view of a semiconductor die package in accordance with an embodiment of the present technology.

[0020] Fig. 9 is a schematic diagram of a system including a semiconductor device according to an embodiment of the present technology. DETAILED DESCRIPTION

[0021] Specific details of several embodiments of semiconductor devices and associated systems and methods are described below. Those skilled in the art will recognize that appropriate stages of the methods described herein may be performed at the wafer level or at the die level. Thus, depending on the context in which the term "substrate" is used, it may refer to a wafer-level substrate or to a singulated die-level substrate. In addition, unless the context indicates otherwise, the structures disclosed herein may be formed using conventional semiconductor manufacturing techniques. Materials may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques. Those skilled in the art will also understand that the present technology may have additional embodiments and may be used without the following references. Figures 1A to 9 The present technology is practiced without the use of numerous details of the described embodiments.

[0022] In several of the embodiments described below, a semiconductor die (e.g., a memory die) includes an optical wiring layer formed on its back side. More specifically, the semiconductor die may include a substrate having a front side, a plurality of circuit elements at the front side, and a back side opposite the front side. The substrate may include a through-substrate via (TSV) in the substrate, the TSV including a conductive material extending through the substrate and protruding beyond the back side of the substrate. The optical wiring layer may be formed on the back side of the substrate and around the conductive material of the TSV protruding beyond the back side of the substrate. The optical wiring layer may include two or more passivation materials having different refractive indices, the two or more passivation materials being patterned to form passive optical components such as optical waveguides and / or vertically coupled gratings. In some embodiments, an active optical component may be (i) electrically coupled to the conductive material of at least one of the TSVs and (ii) optically coupled to the optical wiring layer. Optical fibers may be optically coupled to the optical wiring layer for transmitting and / or receiving optical signals to and / or from the active optical components.

[0023] Significantly, the optical routing layer may be formed of a passivation material deposited around the exposed portions of the TSVs during conventional semiconductor die fabrication processes (e.g., TSV disclosure processes). In this manner, the optical routing layer may provide additional functionality—such as optical input / output (I / O) signal routing—without increasing the size of the semiconductor die. The optical routing layer may further enable optical I / O connections to the package incorporating the semiconductor die. That is, optical signals may be sent to / received from the semiconductor die package without additional electrical signal routing to external optical components, such as active optical components disposed on an interposer alongside the semiconductor package. This may reduce the amount of conductive metal (e.g., copper wires, traces, etc.) in the data path, thereby increasing the efficiency of the semiconductor die package by, for example, reducing or eliminating the need for repeater chips or other components for enhancing signal strength and / or integrity during data transmission at high bandwidths.

[0024] Numerous specific details are disclosed herein to provide a thorough and useful description of the embodiments of the present invention. However, those skilled in the art will appreciate that the technology may have additional embodiments and the technology may be used without the following references. Figures 1A to 9 The present invention is practiced without the need for several details of the embodiments described herein. For example, some details of semiconductor devices and / or packages well known in the art have been omitted so as not to obscure the present invention. In general, it should be understood that in addition to the specific embodiments disclosed herein, various other devices and systems may also be within the scope of the present invention.

[0025] As used herein, the terms "vertical," "lateral," "upper," "lower," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "uppermost" may refer to a feature that is located closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / under, up / down, and left / right may be interchanged depending on the orientation.

[0026] Figures 1A to 1D 1F-1H are side cross-sectional views illustrating various stages in a method of fabricating a semiconductor device 100 (eg, a memory device) in accordance with the present technology. Figure 1E yes Figure 1D 1 is an enlarged view of a portion of semiconductor device 100 shown in FIG. In general, semiconductor devices can be manufactured as discrete devices or as part of a larger wafer or panel. In wafer-level or panel-level manufacturing, a larger semiconductor device is formed before being singulated to form multiple individual devices. For ease of explanation and understanding, Figures 1A to 1G The diagram illustrates a semiconductor device (eg, semiconductor die) 101 that can be singulated into two individual semiconductor devices (eg, semiconductor dies) 102. Figure 1F However, those skilled in the art will readily appreciate that the fabrication of the semiconductor device 100 can be scaled to the wafer and / or panel level—that is, including more components so as to be singulated into more than two semiconductor dies 101—while including similar features and using similar processes, as described herein.

[0027] like Figure 1A , semiconductor device 100 includes a substrate 102 having a front side 107, a back side 109 opposite the front side 107, and a plurality of circuit elements 104 (e.g., wires, traces, interconnects, transistors, etc.; shown schematically) in and / or on the front side 107. For example, metal traces may be formed on the front side 107 of the substrate 102, and integrated circuit elements may be located in the substrate 102 below the metal traces. For example, the circuit elements 104 may include memory circuits (e.g., dynamic random access memory (DRAM) or other types of memory circuits), controller circuits (e.g., DRAM controllers), logic circuits, and / or other circuits. In other embodiments, substrate 102 may be a "green sheet" substrate that does not include integrated circuit components and is formed of, for example, crystalline, semi-crystalline, and / or ceramic substrate materials (e.g., silicon, polysilicon, aluminum oxide (Al2O3), sapphire, and / or other suitable materials).

[0028] Figure 1AThe semiconductor device 100 is further shown after one or more through substrate vias (TSVs) 106 have been formed in the substrate 102. In the case where the substrate 102 is a silicon substrate, the TSVs 106 may be through silicon vias. In the illustrated embodiment, the TSVs 106 extend from the front side 107 into the substrate 102, but are not yet accessible at the back side 109 (e.g., the TSVs 106 are not exposed or revealed from the substrate 102 at the back side 109). The TSVs 106 may include a conductive material 105 electrically coupled to the circuit element 104, and may be formed using processes well known in the art. For example, the TSVs 106 may be fabricated by forming (e.g., etching) a hole through the front side 107 of the substrate 102 and filling the hole with the conductive material 105. The process for forming the hole may include a photolithography process followed by one or more wet and / or dry chemical etching processes. Conductive material 105 may include copper, nickel, solder (eg, SnAg-based solder), conductor-filled epoxy, and / or other conductive materials. In some embodiments, TSV 106 may include barrier materials and / or other materials disposed between conductive material 105 and surrounding substrate 102 .

[0029] Figure 1A The semiconductor device 100 is further shown after a conductive pillar 108 has been formed on the front side 107 of the substrate 102 to electrically couple to the conductive material 105 of the corresponding one in the TSV 106. In some embodiments, the conductive pillar 108 is a relatively tall structure having a height between about 10 to 100 μm (e.g., between about 35 to 60 μm) above the front side 107 of the substrate 102. The conductive pillar 108 can be made by a suitable electroplating or electroless plating process, as known in the art. In other embodiments, other deposition techniques (e.g., sputtering deposition) can be used instead of electroplating or electroless plating. Therefore, the conductive pillar 108 may include copper, nickel, aluminum, solder (e.g., SnAg-based solder), epoxy resin filled with conductors, and / or other conductive materials, and may include one or more layers of the same or different conductive materials. In some embodiments, the conductive pillar 108 includes one or more seed layers suitable for facilitating the plating process.

[0030] Figure 1BThe semiconductor device 100 is shown after the substrate 102 has been attached to the carrier 110 by the adhesive layer 112. The carrier 110 can provide additional stability and mechanical support in subsequent processing steps to the back side 109 of the substrate 102, and can be later decoupled from the substrate 102 (e.g., released from the substrate, removed, etc.). The carrier 110 can be a temporary carrier formed of, for example, silicon, silicon-on-insulator, a compound semiconductor (e.g., gallium nitride), glass, or other suitable materials. The adhesive layer 112 can be a disposable film (e.g., a laminate film of an epoxy-based material) or other suitable material that secures the carrier 110 to the front side 107 of the substrate 102 and / or to the conductive pillars 108.

[0031] Figure 1C The semiconductor device 100 is shown after the back side 109 of the substrate 102 has been thinned to expose the conductive material 105 of the TSVs 106 through the back side 109 of the substrate. The substrate 102 may be thinned using a suitable back grinding process, such as known in the art. In the illustrated embodiment, after thinning the substrate 102, the protruding portions 111 of the conductive material 105 in individual ones of the TSVs 106 protrude beyond the back side 109 of the substrate 102. In other embodiments, the substrate 102 may be thinned such that the conductive material 105 in some of the TSVs 106 does not protrude beyond the back side 109 and / or is not revealed or exposed at the back side 109. For example, the back side 109 of the substrate 102 may be coplanar with the upper surface of the conductive material 105 in one or more of the TSVs 106.

[0032] Figure 1D The semiconductor device 100 is shown after forming an optical wiring layer 120 over the back side 109 of the substrate 102 and over the protruding portion 111 of the conductive material 105 of the TSV 106. In general, the optical wiring layer 120 includes a plurality of passivation, dielectric, or other suitable insulating material layers (such as, for example, silicon oxide, silicon nitride, tetraethyl orthosilicate (TEOS), etc.). The plurality of passivation material layers include at least two different materials with different refractive indices, so that the optical wiring layer 120 includes one or more passive optical components (e.g., waveguides, vertically coupled gratings, etc.). More specifically, in some embodiments, reference is made to Figure 1E, the optical wiring layer 120 may include (i) a first layer 121 of a first material formed on the back side 109 of the substrate 102, (ii) a second layer 122 of a second material formed over the first layer 121, and (iii) a third layer 123 of a third material formed over the second layer 122. The second material of the second layer 122 may have a higher refractive index than the first material of the first layer 121 and the third material of the third layer 123. In some embodiments, for example, both the first material and the third material may include a silicon oxide material, while the second material includes a silicon nitride material. Therefore, the first layer 121 and the third layer 123 may be used as a cladding layer to confine optical signals emitted into the second layer 122 through the optical wiring layer 120.

[0033] The second layer 122 may be patterned to form one or more passive optical components. In the illustrated embodiment, for example, the second layer is patterned to form (i) a vertical grating coupling portion 125 (e.g., a distributed Bragg grating) and (ii) a waveguide portion 126 that is optically coupled to the vertical grating coupling portion 125. The waveguide portion 126 is configured to route the optical signal generally laterally along the back side 109 of the substrate 102, while the vertical grating coupling portion 125 is configured to redirect the optical signal generally vertically into and / or out of the optical wiring layer 120 (e.g., to / from an optical fiber or active optical component, as described in detail below). In general, the optical wiring layer 120 may include any number of vertical grating coupling portions and / or other optical components. In some embodiments, for example, at least a portion of the second layer 122 may be patterned to form a ring oscillator that can filter an incoming optical signal. In some embodiments, one or more heater elements (e.g., metal layers) may be formed in, on, and / or below the optical wiring layer 120 and may be electrically connected to the conductive material 105 in one or more of the TSVs. The heater elements may be configured to selectively heat the optical wiring layer 120 to, for example, function as a thermo-optical switch (e.g., as described below with reference to Figure 3 Describe in detail).

[0034] The optical wiring layer 120 may be fabricated using photolithography, laser direct writing, UV-laser direct imaging, nanoimprinting, mosquito-biting (e.g., needle-type liquid microdispensing), and / or other suitable deposition and patterning methods known in the art. Significantly, the optical wiring layer 120 may be formed as part of a standard TSV disclosure process in place of a standard passivation layer (e.g., a complete passivation material layer without optical components or functionality). Thus, the optical wiring layer 120 may provide an optical I / O interface for the semiconductor device 100 without increasing the overall size of the semiconductor device 100 (compared to conventional devices).

[0035] Although in Figure 1E 102. Although three layers 121-123 are illustrated in FIG, any number of layers, materials, etc. may be used to form the optical wiring layer 120. For example, the optical wiring layer 120 may include multiple patterned layers of high refractive index material to form a more complex optical component. Furthermore, in the illustrated embodiment, the optical wiring layer is formed over substantially the entire back side 109 of the substrate 102. In other embodiments, the optical wiring layer may be formed over only a portion of the back side 109 of the substrate 102. For example, other portions of the back side 109 may be filled patterned for controlling or suppressing stress and / or warping of the substrate 102. Similarly, additional layers may be added or the thickness of the layers 121-123 may be locally modified to optimize adhesion, reduce reflections, etc.

[0036] like Figure 1F As shown in FIG. 1 , the optical wiring layer 120 (eg, Figure 1E 100) and / or the protruding portion 111 of the conductive material 105 of the TSV 106 is then thinned to coplanarize the conductive material 105 and the optical wiring layer 120. Thus, after thinning, the conductive material 105 of the TSV 106 and the optical wiring layer 120 together define a substantially planar back side 115 of the semiconductor device 100. The thinning may be achieved using, for example, a chemical mechanical planarization (CMP) process.

[0037] Figure 1G The semiconductor device 100 is shown after a UBM feature 116 has been formed on the back side 115 of the semiconductor device 100 to electrically couple to the conductive material 105 of the corresponding one in the TSV 106. The UBM feature 116 is a relatively short feature compared to the conductive pillar 108, and in some embodiments, may have a height between about 1 to 10 μm (e.g., between about 1 to 5 μm) above the back side 115 of the semiconductor device 100. The UBM feature 116 may be fabricated by a suitable electroplating or electroless plating process, as is known in the art. In other embodiments, other deposition techniques (e.g., sputtering deposition) may be used instead of electroplating or electroless plating. Figure 1G The diagram further illustrates that after the carrier 110 and the adhesive layer 112 have been removed ( Figure 1F ) after the semiconductor device 100. In some embodiments, the adhesive layer 112 allows the carrier 110 to be easily removed from the semiconductor device 100 via vacuum, poker pins, laser or other light sources, or other suitable methods, so that the carrier 110 can be reused again. Removing the carrier 110 and the adhesive layer 112 exposes the front side 107 of the substrate 102 and the conductive pillars 108. Figure 1GSemiconductor device 100 is further illustrated after solder balls or solder bumps 118 are deposited onto conductive pillars 108. In some embodiments, for example, a screen printing machine may deposit discrete pieces of solder paste onto conductive pillars 108 and the solder paste may then be reflowed to form solder bumps 118 on conductive pillars 108.

[0038] like Figure 1G As further shown in FIG. 1 , singulation lanes 119 may be disposed along semiconductor device 100 to, for example, facilitate singulation of semiconductor device 100 into a plurality of smaller semiconductor devices (eg, semiconductor dies). Figure 1H The semiconductor device 100 is shown after being singulated to form two semiconductor dies 101. Specifically, the substrate 102 may be cut at and / or along singulation lanes 119 to separate the semiconductor dies 101 from one another. Once singulated, the individual semiconductor dies 101 may be attached to external circuitry via the conductive pads 116 and / or conductive pillars 108, and thus incorporated into a variety of systems, assemblies, packages, and / or devices.

[0039] For example, Figure 2A and 2B 2 are a side cross-sectional view and a partially schematic top view, respectively, of a semiconductor die assembly or package 230 ("package 230") including a semiconductor die 101 in accordance with an embodiment of the present technology. Figure 2A , the semiconductor die 101 may be carried by a package substrate 232 and electrically coupled to the package substrate 232 via the conductive pillars 108 and the solder ball bumps 118. The package substrate 232 may include a redistribution layer, an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (e.g., a logic die), or another suitable substrate. The package substrate 232 may further include an electrical connector 234 (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements) electrically coupled to the package substrate 232 and configured to electrically couple the package 230 to an external device or circuit (not shown).

[0040] Common Reference Figure 2A and 2B The package 230 further includes a first active optical component 242, a second active optical component 244 (in Figure 2A ), the first optical fiber 246 and the second optical fiber 248 (in Figure 2A101 and 102. The active optical components 242 and 244 are both (i) electrically coupled to the semiconductor die 101 and / or the packaging substrate 232 via one or more of the UBM features 116 (e.g., for receiving power), and (ii) optically coupled to the optical wiring layer 120. The active optical components 242 and 244 may be optical transmitters (e.g., laser light sources), receivers (e.g., photodiodes), transceivers, etc. In the illustrated embodiment, for example, the first active optical component 242 is an optical transmitter (e.g., a vertical cavity surface emitting laser (VCSEL)) configured to receive an electrical signal (e.g., an I / O data signal) from the semiconductor die 101 and convert the electrical signal into an optical signal, and the second active optical component 244 is an optical receiver configured to receive an optical signal (e.g., an I / O data signal) from an external circuit (not shown) and convert the optical signal into an electrical signal. The optical fibers 246 and 248 are both optically coupled to the optical wiring layer 120. In some embodiments, optical fibers 246 , 248 are attached and / or optically coupled to optical routing layer 120 via first and second connectors 247 , 249 , respectively.

[0041] More specifically, Figure 2C and 2D 2 and 3 respectively show the first active optical component 242 and the first optical fiber 246 according to an embodiment of the present invention. Figure 2A 230 is an enlarged view of the package. Figure 2B and 2C , the first active optical component 242 can be electrically coupled to the UBM feature 116 of the semiconductor die 101 via a conductive feature such as a solder ball or bump 243. The first active optical component 242 can have a light source (e.g., a laser source) aligned with (e.g., positioned above) the first vertical grating coupling portion 225a of the optical wiring layer 120. In operation, the semiconductor die 101 can modulate the optical signal 239 generated by the first active optical component 242. The first vertical grating coupling portion 225a is configured to receive the optical signal 239 and route or guide the modulated optical signal 239 into the waveguide portion 126 of the optical wiring layer 120 for emission to the first optical fiber 246.

[0042] refer to Figure 2B and 2D, the first connector 247 and / or the first optical fiber 246 may abut the optical wiring layer 120 such that the first optical fiber 246 is aligned with the second vertical grating coupling portion 225b of the optical wiring layer 120. In other embodiments, an optically clear epoxy, an index matching epoxy, an index matching gel, etc. may be disposed between the first optical fiber 246 and the optical wiring layer 120. In operation, the second vertical grating coupling portion 225b is configured to receive the optical signal 239 from the waveguide portion 126 and route the optical signal 239 into the first optical fiber 246 (e.g., for transmission to an external circuit).

[0043] In some embodiments, the second active optical component 244 and the second optical fiber 248 may be optically coupled via the optical wiring layer 120 in a manner substantially similar to the first active optical component 242 and the first optical fiber 246. Figure 2B , the first active optical component 242 may be optically coupled to the first optical fiber 246 via a first (e.g., transmit) optical path 238a (shown schematically) formed in the optical wiring layer 120 for transmitting optical signals from the package 230. Likewise, the second active optical component 244 may be optically coupled to the second optical fiber 248 via a second (e.g., receive) optical path 238b (shown schematically) formed in the optical wiring layer 120 for receiving optical signals from outside the package 230. In some embodiments, the optical paths 238 are separate isolated paths, while in other embodiments, the optical paths 238 may be the same path or may partially overlap.

[0044] Common Reference Figures 2A to 2D , molding material 236 (not shown for clarity) Figure 2B244, optical fibers 246, 248, and / or connectors 247, 249 to protect these components from external contamination or forces. In addition, in the illustrated embodiment, the molding material 236 surrounds a portion of the connectors 247, 249 to secure or maintain the position of the optical fibers 246, 248 relative to the optical wiring layer 120 (e.g., to maintain the alignment of the optical fibers 246, 248 with the vertical grating coupling portion 225). In other embodiments, the package 230 may include an adhesive located between the connectors 247, 249 and / or the optical fibers 246, 248 and the optical wiring layer 120. In some embodiments, molding material 236 is not located between active optical components 242, 244 and optical wiring layer 120, and / or an optically transparent epoxy, index matching gel, etc., rather than molding material 236, may be disposed between active optical components 242, 244 and optical wiring layer 120 to permit or enable transmission of optical signals therebetween. Furthermore, in the illustrated embodiment, molding material 236 extends upwardly beyond back side 115 of semiconductor die 101, while in other embodiments, molding material 236 may be coplanar with back side 115 or below back side 115, such that optical wiring layer 120 is exposed.

[0045] Despite Figures 2A to 2D Two optical fibers and two active optical components are illustrated in FIG, but in practice, any number of optical fibers and / or active optical components may be optically coupled to an optical wiring layer configured according to the present technology. For example, Figure 3 FIG. 1 is a partially schematic top view of a semiconductor die assembly or package 330 (“package 330”) including semiconductor die 101 according to another embodiment of the present technology. Package 330 may include a semiconductor die assembly or package 330 (“package 330”) that is substantially similar to reference 1. Figures 2A to 2D The features of the package 230 are described in detail. For example, the package 330 includes a semiconductor die 101 having an optical wiring layer 120, a package substrate 232, and active optical components 242,244.

[0046] However, in the illustrated embodiment, only a single optical fiber 346 is optically coupled to the optical wiring layer 120 via a connector 347. In some embodiments, the optical wiring layer 120 includes a switch 337 operable to (i) optically couple the first active optical component 242 to the optical fiber 346 via a first (e.g., transmit) optical pathway 338a formed in the optical wiring layer 120, or (ii) optically couple the second active optical component 244 to the optical fiber 346 via a second (e.g., receive) optical pathway 338b formed in the optical wiring layer 120. In the illustrated embodiment, the switch 337 is shown as optically coupling the second active optical component 244 to the optical fiber 346 (e.g., completing the second optical pathway 338b) to, for example, enable the semiconductor die 101 to receive an optical signal from the optical fiber 346. As described in detail above, the switch 337 may be a thermo-optical switch (e.g., a thermally modulated switch) triggered via selective heating of the optical wiring layer 120. In other embodiments, package 330 may include two or more active optical components optically coupled to optical fiber 346 via switch 337 and / or two or more optical fibers optically coupled to active optical components 242 , 244 via one or more switches formed in optical routing layer 120 .

[0047] In some embodiments, a semiconductor package according to the present technology may include multiple stacked semiconductor dies. For example, Figure 4 4 is a side cross-sectional view of a semiconductor die assembly or package 430 ("package 430") according to another embodiment of the present technology. Package 430 includes a plurality of semiconductor dies 101 arranged in a stack 435 on a package substrate 432. In the illustrated embodiment, package 430 includes four of the semiconductor dies 101 arranged in a "front-to-back" configuration (e.g., the front active side 107 of the semiconductor die 101 faces the back side 115 of an adjacent one of the semiconductor dies 101). In practice, package 430 may include a different number of semiconductor dies 101, such as one die, two dies, three dies, five dies, eight dies, sixteen dies, or more. Likewise, semiconductor dies 101 may have other suitable orientations, such as "face-to-face". In some embodiments, semiconductor dies 101 may be identical (e.g., memory dies manufactured to have the same design and specifications), while in other embodiments, semiconductor dies 101 may be different from each other (e.g., different types of memory dies or a combination of controller, logic, memory, and / or other dies).

[0048] As shown, an uppermost semiconductor die among the semiconductor dies 101 may include an optical wiring layer 120. At least one active optical component 442 and at least one optical fiber 446 may be optically coupled to the optical wiring layer 120 for transmitting optical signals to and / or receiving optical signals from the package 430. In some embodiments, each of the semiconductor dies 101 may include an optical wiring layer 120. In other embodiments, only an uppermost semiconductor die among the semiconductor dies 101 may include an optical wiring layer 120, and other lower semiconductor dies among the semiconductor dies 101 may include, for example, a continuous passivation material layer over their backsides.

[0049] In some embodiments, a semiconductor package according to the present technology may include multiple semiconductor dies having different orientations. For example, Figure 5 5 is a side cross-sectional view of a semiconductor die assembly or package 530 ("package 530") according to another embodiment of the present technology. In the illustrated embodiment, package 530 includes (i) a first semiconductor die 550 having a back side 559 coupled to a package substrate 532 via a die attach material 552 (e.g., an adhesive film, epoxy, tape, paste, and / or other suitable material); and (ii) a second semiconductor die 501 stacked above the first semiconductor die 550. The semiconductor dies 550, 501 are arranged in a "face-to-face" configuration, with a front (e.g., active) side 507 of the second semiconductor die 501 facing a front (e.g., active) side 557 of the first semiconductor die 550. The second semiconductor die 501 may include features generally similar to the semiconductor die 101 described in detail above and may include, for example, an optical routing layer 520 over its back side 509. The first semiconductor die 550 can be a memory die, a logic die (eg, a controller die), or another type of semiconductor die as known in the art.

[0050] In the illustrated embodiment, the second semiconductor die 501 is laterally offset from the first semiconductor die 550 to, for example, expose one or more bonding pads 553 of the first semiconductor die 550. The bonding pads 553 can be electrically coupled to the package substrate 532 via one or more wire bonds 554. Thus, in some embodiments, the first semiconductor die 550 need not include any TSVs extending therethrough. Furthermore, at least one active optical component 542 and at least one optical fiber 546 can be optically coupled to the optical routing layer 520 of the second semiconductor die 501 to transmit optical signals to and / or receive optical signals from the package 530, as described in detail above.

[0051] In some embodiments, a semiconductor package in accordance with the present technology may include an optical routing layer on a lower or base semiconductor die in a stack of semiconductor dies. Figure 6 6 is a side cross-sectional view of a semiconductor die assembly or package 630 ("package 630") according to another embodiment of the present technology. In the illustrated embodiment, package 630 includes (i) a first semiconductor die 601, which is carried by and electrically coupled to a package substrate 632; and (ii) a plurality of second semiconductor dies 650, which are arranged in a stack 655 on the first semiconductor die 601. The first semiconductor die 601 may include features generally similar to the semiconductor dies 101 and 501 described in detail above, and may include, for example, an optical routing layer 620 over its back side. The second semiconductor die 650 may be a memory die, a logic die, and / or other types of semiconductor die known in the art. In some embodiments, the first semiconductor die 601 may be a logic die, such as a memory controller, and the second semiconductor die 650 may be a memory die (e.g., a DRAM memory die). In the illustrated embodiment, the semiconductor dies 601 , 650 are arranged in a front-to-back configuration, in other embodiments, the semiconductor dies 601 , 650 may have a different arrangement (eg, face-to-face).

[0052] like Figure 6 As further shown in FIG. 1 , the first semiconductor die 601 includes a peripheral portion (eg, edge or shelf) 661 that extends laterally outward beyond the stack 655 of the second semiconductor die 650. At least one active optical component (in Figure 6 601) and at least one optical fiber 646 may be (i) electrically coupled to the first semiconductor die 601 (e.g., for receiving power) and / or (ii) optically coupled to the optical routing layer 620 of the first semiconductor die 601 for transmitting optical signals to and / or receiving optical signals from the package 630, as described in detail above. In the illustrated embodiment, the first semiconductor die 601 includes TSVs 606 and UBM features 616 electrically coupled to conductive materials disposed in the TSVs 606. In some embodiments, the TSVs 606 may be exposed at the peripheral portion 661, while in other embodiments, some or all of the TSVs 606 need not be exposed at the peripheral portion 661. Furthermore, in the illustrated embodiment, the uppermost semiconductor die of the second semiconductor die 660 does not include TSVs extending therethrough. In other embodiments, the uppermost semiconductor die in the second semiconductor dies 650 may have TSVs extending therethrough and / or an optical routing layer formed on an upper (eg, backside) surface thereof.

[0053] In some embodiments, semiconductor packages according to the present technology may include in-package optical connections. Figure 77 is a side cross-sectional view of a semiconductor die assembly or package 730 ("package 730") according to another embodiment of the present technology. In the illustrated embodiment, package 730 includes (i) an interposer 770, which is carried by and electrically coupled to a package substrate 732, (ii) a plurality of (first) semiconductor dies 101 ( Figures 1A to 3 ), which are arranged in a stack 735 above a first portion of the interposer 770 and electrically coupled to the interposer 770, and (iii) a second semiconductor die 780, which is positioned above a second portion of the interposer 770 and electrically coupled to the interposer 770. In some embodiments, the first semiconductor die 101 may be a memory die (e.g., a DRAM memory die) and the second semiconductor die 780 may be a logic die such as a memory controller. In the illustrated embodiment, the uppermost semiconductor die of the semiconductor die 101 may include a (first) optical routing layer 120 and the second semiconductor die 780 may include a second optical routing layer 720 formed over its back side. In some embodiments, the optical routing layer may also be formed on one or more of the lower first semiconductor dies 101 in the stack 735 and / or on the interposer 770. The interposer 770 may include a printed circuit board, a semiconductor substrate, or other suitable substrate formed without integrated circuit components. For example, interposer 770 may include a "green sheet" substrate formed of a crystalline, semi-crystalline, and / or ceramic substrate material such as silicon, polysilicon, aluminum oxide (Al2O3), sapphire, and / or other suitable materials.

[0054] like Figure 7101 and 102. It is further shown that at least one first active optical component 772 is (i) electrically coupled to the uppermost semiconductor die in the first semiconductor die 101 and (ii) optically coupled to the first optical wiring layer 120. Similarly, at least one first active optical component 774 is (i) electrically coupled to the second semiconductor die 780 and (ii) optically coupled to the second optical wiring layer 720. The active optical components 772, 774 may be, for example, photodiodes, laser sources, etc. The first optical fiber 776a is optically coupled to the first optical wiring layer 120 and may optically couple the stack 735 of the first semiconductor die 101 and / or other components of the package 730 to an external circuit. The second optical fiber 776b is optically coupled to the second optical wiring layer 720 and may optically couple the second semiconductor die 780 and / or other components of the package 730 to an external circuit. In some embodiments, the third optical fiber 776c extends between the optical wiring layers 120, 720 and optically couples the optical wiring layers 120, 720. Thus, the third optical fiber 776 c may provide an in-package optical coupling between the second semiconductor die 780 and the stack 735 of first semiconductor dies 101 , which may, for example, provide high speed and / or bandwidth data transmission between the semiconductor dies 101 , 780 .

[0055] In some embodiments, the molding material 736 may be formed around and / or over the first semiconductor die 101, the second semiconductor die 780, the interposer 770, and / or the package substrate 732. In the illustrated embodiment, the optical wiring layers 120, 720 are exposed from the molding material 736. In other embodiments, the molding material 736 may be formed over the optical wiring layers 120, 720. For example, the molding material 736 may be formed to encapsulate or at least partially surround the third (in-package) optical fiber 776c to inhibit damage or misalignment of the third optical fiber 776c caused by external forces.

[0056] In some embodiments, a semiconductor package according to the present technology may include an optical routing layer on an interposer configured to carry multiple semiconductor dies. Figure 8 FIG. 8 is a side cross-sectional view of a semiconductor die assembly or package 830 (“package 830”) according to another embodiment of the present technology. Package 830 includes a semiconductor die assembly or package 830 that is substantially similar to the semiconductor die assembly of FIG. Figure 7Several features of the package 730 are described in detail. For example, the package 830 includes (i) an interposer 870 carried by and electrically coupled to a package substrate 832, (ii) a plurality of first semiconductor dies 850 arranged in a stack 855 over a first portion of the interposer 870 and electrically coupled to the interposer 870, and (iii) a second semiconductor die 880 positioned over a second portion of the interposer 870 and electrically coupled to the interposer 870. However, in the illustrated embodiment, the optical routing layer 820 is formed over the interposer 870 (e.g., a back side of the interposer 870).

[0057] like Figure 8 As further shown in FIG. 1 , the interposer 870 includes a disconnect portion 881 that is laterally located between the first portion and the second portion of the interposer 870 and is not located below the stack 855 of the first semiconductor die 850 or the second semiconductor die 880. Figure 8 870 and / or the optical wiring layer 820 of the interposer 870 for transmitting optical signals to the package 830 and / or receiving optical signals from the package 830. In the illustrated embodiment, the uppermost semiconductor die of the first semiconductor die 850 and the second semiconductor die 880 do not include TSVs extending therethrough. In other embodiments, the uppermost semiconductor die of the first semiconductor die 850 and / or the second semiconductor die 880 may have TSVs extending therethrough and / or an optical wiring layer formed on an upper (e.g., backside) surface thereof. Furthermore, in other embodiments, the stack 855 of the first semiconductor die 850 and / or the second semiconductor die 880 may be arranged in a different manner such that the disconnected portion 881 may be a different portion of the interposer 870, such as a peripheral portion of the interposer 870.

[0058] Based on the above, it will be appreciated that specific embodiments of the present technology have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present technology. That is, in some embodiments, the details of the semiconductor device and package may differ from those shown in the foregoing figures. In general, as a TSV disclosure process for the following items (e.g., Figures 1A to 1H) or other suitable process, an optical wiring layer may be formed: (i) a memory die, a logic die, or other semiconductor die and / or (ii) an interposer or other substrate that does not include active (e.g., integrated) circuit components. In addition, different components including the optical wiring layer may be combined in the same package and the components may be located at the top, bottom, or elsewhere in the semiconductor component stack or package, or may be located side by side. Likewise, the semiconductor package may include any number of active optical components, passive optical components, and optical fibers. The optical fibers may be coupled to the optical wiring layer and used to optically couple the semiconductor package to external circuits and / or optically couple different components in the same package (e.g., intra-package optical connections). In addition, in some embodiments, the semiconductor package may include other components such as an external heat sink, an enclosure (e.g., a thermally conductive enclosure), an electromagnetic interference (EMI) shielding component, etc.

[0059] The above reference Figures 1A to 8 Any of the semiconductor devices and / or packages of the described features are incorporated into any of a number of larger and / or more complex systems, a representative example of which is Fig. 9 900 is schematically shown in FIG. The system 900 may include a processor 902, a memory 904 (eg, SRAM, DRAM, flash and / or other memory devices), an input / output device 905, and / or other subsystems or components 908. Figures 1A to 8 The semiconductor die and / or package described may be included in Fig. 9 . The resulting system 900 may be configured to perform any of a variety of suitable computing, processing, storage, sensing, imaging and / or other functions. Therefore, representative examples of system 900 include, without limitation, computers and / or other data processors, such as desktop computers, laptop computers, Internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multiprocessor systems, processor-based or programmable consumer electronic devices, network computers, and minicomputers. Additional representative examples of system 900 include lights, cameras, vehicles, etc. With respect to these and other examples, system 900 may be housed in a single unit or distributed over multiple interconnected units (e.g., through a communication network). Therefore, components of system 900 may include local and / or remote memory storage devices and any of a variety of suitable computer-readable media.

[0060] Based on the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for illustration purposes, but various modifications may be made without departing from the present invention. Therefore, the present invention is not subject to limitations beyond the appended claims. Specific aspects of the new technology described in the context of a specific embodiment may also be combined or eliminated in other embodiments. In addition, although the advantages associated with the embodiments have been described in the context of the specific embodiments of the new technology, other embodiments may also exhibit such advantages and not all embodiments must exhibit such advantages to be within the scope of the present technology. Therefore, the present invention and associated technologies may encompass other embodiments not explicitly shown or described herein.

Claims

1. A semiconductor device comprising: a substrate having a first side and a second side, wherein the first side of the substrate defines a first outer surface of the semiconductor device; an optical wiring layer located on the second side of the substrate, wherein the optical wiring layer defines a second outer surface of the semiconductor device; a conductive through substrate via TSV extending through the substrate and the optical wiring layer; a first conductive feature on the first side of the substrate, the first conductive feature being over and electrically coupled to a respective one of the TSVs, wherein the first conductive feature is electrically contactable at the first outer surface; as well as A second conductive feature is located on the optical routing layer, the second conductive feature is located above and electrically coupled to a corresponding one of the TSVs, wherein the second conductive feature is electrically contactable at the second outer surface. 2 . The semiconductor device of claim 1 , wherein the substrate includes a plurality of circuit elements on the first side. 3 . The semiconductor device of claim 1 , wherein the first conductive feature has a first height, and wherein the second conductive feature has a second height different from the first height. 4 . The semiconductor device of claim 1 , wherein the first conductive feature has a first height, and wherein the second conductive feature has a second height that is less than the first height. 5 . The semiconductor device of claim 1 , wherein the first conductive feature has a first height between about 10-100 μm, and wherein the second conductive feature has a second height less than about 1-10 μm. 6 . The semiconductor device according to claim 1 , wherein the optical wiring layer includes at least two passivation materials having different refractive indices. 7 . The semiconductor device according to claim 1 , wherein the optical wiring layer includes at least a first layer of a silicon nitride material and at least a second layer of a silicon oxide material.

8. The semiconductor device according to claim 1, wherein the optical wiring layer comprises: a first layer of a first material having a first refractive index; a second layer of a second material having a second refractive index; as well as A third layer of a third material having a third refractive index, wherein the second refractive index is higher than the first and third refractive indices, such that optical signals received by the optical wiring layer are substantially confined to the second layer.

9. The semiconductor device of claim 8, wherein the first material and the third material are the same, and wherein the second layer is patterned to form an optical waveguide.

10. The semiconductor device of claim 9, wherein the second layer is further patterned to form at least one vertical coupling grating, the at least one vertical coupling grating being optically connected to the optical waveguide.

11. A semiconductor device comprising: Semiconductor die, including: a substrate having a first side and a second side, wherein the first side of the substrate defines a first outer surface of the semiconductor die; an optical wiring layer located on the second side of the substrate, wherein the optical wiring layer defines a second outer surface of the semiconductor die; a conductive through substrate via TSV extending through the substrate and the optical wiring layer; A first conductive feature located on the first side of the substrate, the first conductive feature located at the TSV over and electrically coupled to a corresponding TSV in the first conductive feature, wherein the first conductive feature is electrically contactable at the first outer surface; and a second conductive feature on the optical routing layer, the second conductive feature being over and electrically coupled to a corresponding one of the TSVs, wherein the second conductive feature is electrically contactable at the second outer surface; and An optical component is (a) electrically coupled to at least one of the TSVs and (b) optically coupled to the optical routing layer. 12 . The semiconductor device according to claim 11 , further comprising an optical fiber optically coupled to the optical wiring layer, wherein the optical wiring layer is configured to transmit an optical signal between the optical component and the optical fiber.

13. The semiconductor device according to claim 11, wherein the optical component is a laser source or a photodiode.

14. The semiconductor device according to claim 11, further comprising: an optical fiber optically coupled to the optical wiring layer, wherein the optical wiring layer is configured to transmit an optical signal between the optical component and the optical fiber; a packaging substrate, wherein the semiconductor die is electrically coupled to the packaging substrate; as well as A molding material at least partially surrounds the semiconductor die, the optical component, and the optical fiber.

15. The semiconductor device of claim 14, further comprising an optical connector coupled to the optical fiber, wherein the optical connector abuts the optical wiring layer, and wherein the molding material at least partially surrounds the optical connector.

16. A method for manufacturing a semiconductor device, the method comprising: forming an optical wiring layer on a second side of a substrate, the second side of the substrate being opposite to the first side of the substrate, wherein the first side of the substrate defines a first outer surface of the semiconductor device, and wherein the optical wiring layer defines a second outer surface of the semiconductor device; forming a conductive through-substrate via (TSV) extending through the substrate and the optical wiring layer; forming a first conductive feature on the first side of the substrate, the first conductive feature being located over and electrically coupled to a conductive material in a corresponding one of the TSVs, wherein the first conductive feature is electrically contactable at a first outer surface; and A second conductive feature is formed on the optical routing layer, the second conductive feature being located over and electrically coupled to the conductive material in a corresponding one of the TSVs, wherein the second conductive feature is electrically contactable at the second outer surface.

17. The method according to claim 16, wherein: Forming the TSV includes, prior to forming the optical routing layer, removing material from the second side of the substrate such that portions of the TSV protrude beyond the second side of the substrate. 18 . The method of claim 17 , wherein forming the optical routing layer comprises forming the optical routing layer surrounding the portion of the TSV on the second side of the substrate.

19. The method of claim 16, wherein forming the optical wiring layer comprises: disposing a first layer of a first material over the second side of the substrate; disposing a second layer of a second material over the first layer; patterning the second layer; as well as A third layer of the first material is disposed over the second layer, wherein the second material has a higher refractive index than the first material such that optical signals are substantially confined within the second layer.

20. The method of claim 16, further comprising: electrically coupling an optical component to at least one of the TSVs; optically coupling the optical component to the optical wiring layer; as well as An optical fiber is optically coupled to the optical wiring layer such that the optical wiring layer optically couples the optical component and the optical fiber.

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