Splicing method for exposure manufacturing process

Abstract

The invention discloses a splicing method for an exposure manufacturing process. The splicing method comprises the following steps. A wafer is provided. The wafer includes a plurality of interposer regions. Each interposer region includes a logic chip region, a first memory chip region, and a second memory chip region. The logic chip region is located between the first memory chip region and the second memory chip region. A photoresist layer is formed on the wafer. A plurality of first exposure processes are performed on the photoresist layer using a first photomask to form a plurality of first exposure regions in the photoresist layer. A plurality of second exposure processes are performed on the photoresist layer using a second photomask to form a plurality of second exposure regions in the photoresist layer. The plurality of first exposure areas and the plurality of second exposure areas are alternately arranged in the first direction. The plurality of first exposure areas and the plurality of second exposure areas are overlapped to form a plurality of splicing areas. Each splice region is not located in the logic chip region.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing process, and in particular to a stitching method for an exposure manufacturing process. Background Art

[0002] Currently, a semiconductor package has been developed in which semiconductor chips are stacked or arranged side by side on an interposer. Since the size of the interposer is larger than the size of the photomask, a circuit pattern on the interposer needs to be formed by lithography stitching. However, if the process window of the stitching process is small, the photoresist pattern at the stitching is easily deformed, and the expected photoresist pattern cannot be obtained. Summary of the invention

[0003] The invention provides a splicing method for an exposure manufacturing process, which can effectively improve the manufacturing process margin of the splicing manufacturing process.

[0004] The present invention proposes a splicing method for an exposure process, comprising the following steps. A wafer is provided. The wafer includes a plurality of interposer regions. Each interposer region includes a logic chip region, a first memory chip region, and a second memory chip region. The logic chip region is located between the first memory chip region and the second memory chip region. A photoresist layer is formed on the wafer. A first photomask is used to perform a plurality of first exposure processes on the photoresist layer, and a plurality of first shot regions are formed in the photoresist layer. A second photomask is used to perform a plurality of second exposure processes on the photoresist layer, and a plurality of second exposure regions are formed in the photoresist layer. The plurality of first exposure regions and the plurality of second exposure regions are alternately arranged in a first direction. The plurality of first exposure regions overlap with the plurality of second exposure regions to form a plurality of splicing regions. Each splicing region is not located in the logic chip region.

[0005] According to an embodiment of the present invention, in the splicing method for the exposure process, the logic chip area in each interposer area may be located only in the corresponding first exposure area.

[0006] According to an embodiment of the present invention, in the splicing method for exposure process, the size of each first exposure area may be equal to or greater than the size of each second exposure area.

[0007] According to an embodiment of the present invention, in the splicing method for the exposure process, the first memory chip area in each interposer area may be located in the corresponding second exposure area.

[0008] According to an embodiment of the present invention, in the splicing method for the exposure process, the first memory chip area in each interposer area may also be located in the corresponding first exposure area.

[0009] According to an embodiment of the present invention, in the splicing method for the exposure process, the second memory chip area in each interposer area may be located in the corresponding second exposure area.

[0010] According to an embodiment of the present invention, in the splicing method for the exposure process, the second memory chip area in each interposer area may also be located in the corresponding first exposure area.

[0011] According to an embodiment of the present invention, in the splicing method for the exposure process, each first exposure area may overlap with a corresponding logic chip area in the interposer area.

[0012] According to an embodiment of the present invention, in the splicing method for the exposure process, each first exposure area may also overlap with the first memory chip area and the second memory chip area in the corresponding interposer area.

[0013] According to an embodiment of the present invention, in the splicing method for exposure process, each second exposure area may overlap the first memory chip area of ​​one of two adjacent interposer areas and the second memory chip area of ​​the other of the two adjacent interposer areas.

[0014] According to an embodiment of the present invention, in the splicing method for the exposure process, each intermediate layer region may have two splicing regions.

[0015] According to an embodiment of the present invention, in the splicing method for the exposure process, one of the two splicing regions may be located between the logic chip region and the first memory chip region in the corresponding interposer region.

[0016] According to an embodiment of the present invention, in the splicing method for the exposure process, the other of the two splicing regions may be located between the logic chip region and the second memory chip region in the corresponding interposer region.

[0017] According to an embodiment of the present invention, in the splicing method for the exposure process, one of the two splicing areas may overlap with the first memory chip area in the corresponding interposer area.

[0018] According to an embodiment of the present invention, in the splicing method for the exposure process, the other of the two splicing areas may overlap with the second memory chip area in the corresponding interposer area.

[0019] According to one embodiment of the present invention, in the above-mentioned splicing method for exposure manufacturing process, the wafer may further include a plurality of first cutting street areas and a plurality of second cutting street areas. The plurality of first cutting street areas may extend in the first direction and may be arranged in the second direction. The plurality of second cutting street areas may extend in the second direction and may be arranged in the first direction. The first direction may intersect with the second direction. The plurality of first cutting street areas may intersect with the plurality of second cutting street areas.

[0020] According to an embodiment of the present invention, in the splicing method for the exposure process, a plurality of first scribe line regions and a plurality of second scribe line regions may define a plurality of intermediate layer regions.

[0021] According to an embodiment of the present invention, in the splicing method for the exposure process, the first direction may be perpendicular to the second direction.

[0022] According to an embodiment of the present invention, in the splicing method for the exposure process, each first exposure area may overlap with a corresponding first scribe line area.

[0023] According to an embodiment of the present invention, in the splicing method for the exposure process, each second exposure area can overlap with the corresponding first scribe line area and the corresponding second scribe line area.

[0024] Based on the above, in the splicing method for exposure manufacturing process proposed by the present invention, since the splicing area is not located in the logic chip area with complex circuit patterns, the manufacturing process margin of the splicing manufacturing process can be effectively improved. In this way, after the photoresist layer is subjected to the development manufacturing process, the expected photoresist pattern can be obtained.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic top view of a wafer according to some embodiments of the present invention;

[0027] Figure 2 Schematic diagram of the exposure process of some embodiments of the present invention;

[0028] Figure 3 Schematic diagrams of exposure manufacturing processes of other embodiments of the present invention;

[0029] Figure 4 Schematic diagrams of exposure processes according to other embodiments of the present invention.

[0030] Explanation of symbols

[0031] 100: Photoresist layer

[0032] D1,D2: Direction

[0033] IR, IR1, IR2: Intermediary layer area

[0034] LR: logic chip area

[0035] M1,M2: Photomask

[0036] MR1, MR2: memory chip area

[0037] P1, P2: Exposure production process

[0038] R: Region

[0039] SLR1, SLR2: cutting path area

[0040] SR1,SR2: Exposure area

[0041] ST, ST1, ST2: Splicing area

[0042] W: Wafer DETAILED DESCRIPTION

[0043] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.

[0044] Figure 1 Schematic diagram of a top view of a wafer according to some embodiments of the present invention. Figure 2 Schematic diagram of an exposure process according to some embodiments of the present invention. Figure 3 Schematic diagram of exposure manufacturing process according to some other embodiments of the present invention. Figure 4 Schematic diagram of exposure manufacturing process according to some other embodiments of the present invention. Figures 2 to 4 The wafer W in Figure 1 An enlarged view of the wafer W in the region R in FIG. Figure 1 in, omit Figures 2 to 4 To clearly describe some of the components in Figure 1 The relationship between components in the setting.

[0045] Please refer to Figure 1 and Figure 2, providing a wafer W. In some embodiments, the wafer W may be a semiconductor wafer, such as a silicon wafer. The wafer W includes a plurality of interposer regions IR. In some embodiments, the interposer region IR may be a region of the wafer W that is predetermined to be cut into an interposer (e.g., a silicon interposer (Si-interposer)).

[0046] Each interposer region IR includes a logic chip region LR, a memory chip region MR1, and a memory chip region MR2. The logic chip region LR is located between the memory chip region MR1 and the memory chip region MR2. In some embodiments, the logic chip region LR may be a region of the interposer for carrying a logic chip and for electrically connecting to the logic chip. In some embodiments, the logic chip is, for example, a system-on-chip (SoC). In some embodiments, the memory chip region MR1 and the memory chip region MR2 may be a region of the interposer for carrying a memory chip and for electrically connecting to the memory chip. In some embodiments, the memory chip is, for example, a high bandwidth memory (HBM).

[0047] The wafer W may further include a plurality of scribe line regions SLR1 and a plurality of scribe line regions SLR2. The plurality of scribe line regions SLR1 may extend in a direction D1 and may be arranged in a direction D2. The plurality of scribe line regions SLR2 may extend in a direction D2 and may be arranged in a direction D1. The direction D1 may intersect with the direction D2. In some embodiments, the direction D1 may be perpendicular to the direction D2. The plurality of first scribe line regions SLR1 may intersect with the plurality of second scribe line regions SLR2. The plurality of scribe line regions SLR1 and the plurality of scribe line regions SLR2 may define a plurality of interposer regions IR.

[0048] Please refer to Figure 2 , a photoresist layer 100 is formed on the wafer W. In some embodiments, the photoresist layer 100 is formed by, for example, a spin coating method.

[0049] The photoresist layer 100 is subjected to a plurality of exposure processes P1 using a photomask M1, and a plurality of exposure regions SR1 are formed in the photoresist layer 100. In addition, the photoresist layer 100 is subjected to a plurality of exposure processes P2 using a photomask M2, and a plurality of exposure regions SR2 are formed in the photoresist layer 100. In some embodiments, the photoresist layer 100 may be subjected to a plurality of exposure processes P1 using a photomask M1 first, and then the photoresist layer 100 may be subjected to a plurality of exposure processes P2 using a photomask M2, but the present invention is not limited thereto. In other embodiments, the photoresist layer 100 may be subjected to a plurality of exposure processes P2 using a photomask M2 first, and then the photoresist layer 100 may be subjected to a plurality of exposure processes P1 using a photomask M1. In some embodiments, the pattern on the photomask M1 may be different from the pattern on the photomask M2.

[0050] The plurality of exposure regions SR1 and the plurality of exposure regions SR2 are alternately arranged in the direction D1. The plurality of exposure regions SR1 and the plurality of exposure regions SR2 overlap to form a plurality of stitching regions ST. Each stitching region ST is not located in the logic chip region LR. Since the stitching region ST is not located in the logic chip region LR having a complex circuit pattern, the manufacturing process margin of the stitching manufacturing process can be effectively improved.

[0051] In some embodiments, the logic chip region LR in each interposer region IR may be located only in the corresponding exposure region SR1. That is, the logic chip region LR in the interposer region IR may not be located in the exposure region SR2. In some embodiments, the memory chip region MR1 in each interposer region IR may be located in the corresponding exposure region SR2. In some embodiments, the memory chip region MR2 in each interposer region IR may be located in the corresponding exposure region SR2.

[0052] In some embodiments, each exposure region SR1 may overlap the logic chip region LR in the corresponding interposer region IR. In some embodiments, each exposure region SR2 may overlap the memory chip region MR1 of one of the two adjacent interposer regions IR (e.g., interposer region IR1) and the memory chip region MR2 of the other of the two adjacent interposer regions IR (e.g., interposer region IR2). In some embodiments, each exposure region SR1 may overlap the corresponding cutting road region SLR1. In some embodiments, each exposure region SR2 may overlap the corresponding cutting road region SLR1 and the corresponding cutting road region SLR2.

[0053] In some embodiments, two stitching areas ST may be provided in each interposer region IR. In some embodiments, one of the two stitching areas ST (e.g., stitching area ST1) may be located between the logic chip area LR and the memory chip area MR1 in the corresponding interposer region IR. In some embodiments, the other of the two stitching areas ST (e.g., stitching area ST2) may be located between the logic chip area LR and the memory chip area MR2 in the corresponding interposer region IR.

[0054] In other embodiments, Figure 3 and Figure 4 As shown, the memory chip region MR1 in each interposer region IR may also be located in the corresponding exposure region SR1, and the memory chip region MR2 in each interposer region IR may also be located in the corresponding exposure region SR1. Figure 3 and Figure 4 As shown, each exposure region SR1 may also overlap with the corresponding memory chip region MR1 and the memory chip region MR2 in the interposer region IR.

[0055] In other embodiments, Figure 3 and Figure 4 As shown, one of the two stitching areas ST (eg, stitching area ST1) may overlap with the memory chip area MR1 in the corresponding interposer area IR, and the other of the two stitching areas ST (eg, stitching area ST2) may overlap with the memory chip area MR2 in the corresponding interposer area IR.

[0056] exist Figure 2 In the embodiment of the present invention, the photomask M1 includes a pattern for forming a circuit in the logic chip region LR, and the photomask M2 includes a pattern for forming a circuit in the memory chip region MR1 and a pattern for forming a circuit in the memory chip region MR2. Figure 3 and Figure 4 In an embodiment of the present invention, the photomask M1 includes a pattern for forming a circuit in the logic chip area LR, a pattern for forming a circuit in the memory chip area MR1, and a pattern for forming a circuit in the memory chip area MR2, and the photomask M2 includes a pattern for forming a circuit in the memory chip area MR1 and a pattern for forming a circuit in the memory chip area MR2.

[0057] In some embodiments, Figure 2 and Figure 3 As shown, the size (eg, area) of each exposure region SR1 may be equal to the size (eg, area) of each exposure region SR2, but the present invention is not limited thereto. Figure 2 and Figure 3As shown, the exposure region SR1 may overlap about one-half of the interposer region IR1, and the exposure region SR2 may overlap about one-quarter of the interposer region IR1 and about one-quarter of the interposer region IR2. Figure 4 As shown, the size (eg, area) of each exposure region SR1 may be larger than the size (eg, area) of each exposure region SR2.

[0058] Based on the above embodiment, it can be known that in the above splicing method for exposure process, since the splicing area ST is not located in the logic chip area LR having a complex circuit pattern, the process margin of the splicing process can be effectively improved. In this way, after the photoresist layer 100 is subjected to the development process, the expected photoresist pattern can be obtained.

[0059] In summary, the splicing method of the exposure process of the above embodiment can effectively improve the process margin of the splicing process, thereby obtaining a desired photoresist pattern.

[0060] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any ordinary technician in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A splicing method for an exposure production process, comprising: Providing a wafer, wherein the wafer comprises a plurality of interposer regions, wherein each of the interposer regions comprises a logic chip region, a first memory chip region and a second memory chip region, and the logic chip region is located between the first memory chip region and the second memory chip region; forming a photoresist layer on the wafer; Using a first photomask to perform a plurality of first exposure processes on the photoresist layer to form a plurality of first exposure areas in the photoresist layer; as well as A second photomask is used to perform a plurality of second exposure processes on the photoresist layer to form a plurality of second exposure areas in the photoresist layer. A plurality of the first exposure areas and a plurality of the second exposure areas are alternately arranged in a first direction, A plurality of the first exposure areas overlap with a plurality of the second exposure areas to form a plurality of splicing areas, Each of the stitching areas is not located in the logic chip area.

2. The splicing method for exposure manufacturing process as claimed in claim 1, wherein the logic chip area in each of the interposer areas is only located in the corresponding first exposure area.

3. The splicing method for exposure process as claimed in claim 2, wherein the size of each of the first exposure areas is equal to or larger than the size of each of the second exposure areas. 4 . The splicing method for exposure manufacturing process as claimed in claim 2 , wherein the first memory chip area in each of the interposer areas is located in the corresponding second exposure area. 5 . The splicing method for exposure manufacturing process as claimed in claim 4 , wherein the first memory chip area in each of the interposer areas is also located in the corresponding first exposure area. 6 . The splicing method for exposure manufacturing process as claimed in claim 2 , wherein the second memory chip area in each of the interposer areas is located in the corresponding second exposure area. 7 . The splicing method for exposure manufacturing process as claimed in claim 6 , wherein the second memory chip area in each of the interposer areas is also located in the corresponding first exposure area. 8 . The splicing method for exposure manufacturing process as claimed in claim 1 , wherein each of the first exposure areas overlaps with the corresponding logic chip area in the interposer area. 9 . The splicing method for exposure manufacturing process according to claim 8 , wherein each of the first exposure areas also overlaps with the first memory chip area and the second memory chip area in the corresponding interposer area. 10 . The splicing method for exposure manufacturing process according to claim 8 , wherein each of the second exposure areas overlaps the first memory chip area of ​​one of two adjacent interposer areas and the second memory chip area of ​​the other of two adjacent interposer areas.

11. The splicing method for exposure manufacturing process as claimed in claim 1, wherein there are two splicing areas in each of the intermediate layer areas. 12 . The splicing method for exposure manufacturing process according to claim 11 , wherein one of the two splicing areas is located between the logic chip area and the first memory chip area in the corresponding interposer area. 13 . The splicing method for exposure manufacturing process according to claim 12 , wherein the other of the two splicing areas is located between the logic chip area and the second memory chip area in the corresponding interposer area. 14 . The splicing method for exposure manufacturing process according to claim 11 , wherein one of the two splicing areas overlaps with the first memory chip area in the corresponding interposer area. 15 . The splicing method for exposure manufacturing process as claimed in claim 14 , wherein the other of the two splicing areas overlaps with the second memory chip area in the corresponding interposer area.

16. The splicing method for exposure manufacturing process according to claim 1, wherein The wafer further includes a plurality of first scribe line areas and a plurality of second scribe line areas. A plurality of the first cutting line regions extend in the first direction and are arranged in the second direction, A plurality of the second cutting line regions extend in the second direction and are arranged in the first direction, The first direction intersects the second direction, and A plurality of the first scribe line regions intersect with a plurality of the second scribe line regions. 17 . The splicing method for exposure manufacturing process according to claim 16 , wherein a plurality of the first scribe line areas and a plurality of the second scribe line areas define a plurality of the intermediate layer areas.

18. The splicing method for exposure manufacturing process according to claim 16, wherein the first direction is perpendicular to the second direction.

19. The splicing method for exposure process according to claim 16, wherein each of the first exposure areas overlaps with the corresponding first scribe line area. 20 . The splicing method for exposure process according to claim 19 , wherein each of the second exposure areas overlaps with the corresponding first scribe line area and the corresponding second scribe line area.

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