Miller compensation circuit with pole-zero tracking for LDO (Low Dropout Regulator)

Abstract

The invention provides an LDO (Low Dropout Regulator) miller compensation circuit with a pole-zero tracking function. The LDO miller compensation circuit comprises a miller gain stage connected between an input node and an output node of the miller compensation circuit, and a second switch tube, a fixed resistor and a miller capacitor which are connected between the input node and the output node of the miller compensation circuit and are connected in series; the grid electrode of the second switching tube is connected with a signal related to load current, so that the equivalent resistance is reduced when the load current is increased; when the load current is reduced, the equivalent resistance is increased. According to the Miller compensation circuit with pole-zero point tracking of the LDO, the second switch tube and the Miller capacitor are connected in series to generate a self-adaptive zero point, so that the zero point of the Miller compensation circuit tracks the pole of the output end, and the output performance of the LDO is improved.

Description

Technical Field

[0001] The invention belongs to the field of low voltage dropout regulators, and in particular relates to a Miller compensation circuit with pole-zero tracking of an LDO. Background Art

[0002] Low dropout regulator (LDO) is a commonly used power management device used to provide a stable voltage in a circuit. However, frequency compensation has always been a key issue in the design of LDO.

[0003] In traditional LDO design, frequency compensation is mainly achieved by fixed compensation capacitors and resistors. However, due to factors such as process changes and temperature changes, fixed compensation methods often cannot meet the application requirements of high precision and wide temperature range. Therefore, frequency compensation is usually achieved by using pole-zero tracking technology and Miller compensation technology to improve the performance of LDO.

[0004] The pole-zero tracking technique is often used as a compensation scheme for wide load range LDOs. The basic idea behind it is: "We need to create a load-dependent resistor so that we can make the LHP (left half plane) zeros track the pole load and cancel each other out. Then the system can actually become a single-pole system (ideally)".

[0005] Figure 1 The circuit diagram of an existing LDO using a pole-zero tracking method is shown in FIG. Figure 1 In this case, Type 1 compensation is used, where the poles and zeros are easy to observe and interpret. Figure 1As shown, the LDO using the pole-zero tracking method includes an error amplifier Amp1, the two input terminals of the error amplifier Amp1 are connected to the reference voltage Vref and the feedback voltage fb respectively, the output terminal of the error amplifier Amp1 and the ground are connected in series with a first capacitor Cc1 and a first adjustable resistor Rc1, the output terminal of the error amplifier Amp1 is connected to the input terminal of the buffer B1, the output terminal of the buffer B1 is connected to the gate of the main power tube NM1, the drain of the main power tube NM1 is connected to the input voltage VIN, the source is used as the voltage output terminal VOUT of the LDO, and the voltage output terminal VOUT of the LDO is connected to a grounded feedback resistor network (including a first feedback resistor Rfb1 and a second feedback resistor Rfb2 connected in series), and the feedback resistor network outputs the feedback voltage fb. Therefore, the first main pole is located at the output terminal of the error amplifier Amp1, which is composed of the output impedance Zo1 of the error amplifier Amp1 and the first capacitor Cc1, and the main pole frequency of the output terminal of the error amplifier Amp1 is 1 / (2π × Zo1 × Cc). The load-related zero is formed by the first capacitor Cc1 and the first adjustable resistor Rc1. The other main pole is located at the output of the LDO, which varies with the load resistance RL. Figure 1 In the LDO shown, the value of the first adjustable resistor Rc1 is proportional to the load resistance RL (i.e., changes with the load). Therefore, the zero point formed by the first adjustable resistor Rc1 and the first capacitor Cc1 can follow the pole of the output end, offset the influence of the pole of the output end of the LDO, and make the LDO almost a single-pole system, thereby making the system stable to the load.

[0006] Miller compensation is also commonly used for LDO compensation, especially in multi-stage LDOs where it is often used to obtain high DC gain, good power supply ripple rejection ratio (PSRR), and noise rejection ratio. Figure 2 A circuit diagram of a conventional LDO using a Miller compensation circuit is shown.

[0007] exist Figure 2 In the embodiment, the LDO using Miller compensation includes an error amplifier Amp1, wherein the two input terminals of the error amplifier Amp1 are respectively connected to a reference voltage Vref and a feedback voltage fb, the output terminal of the error amplifier Amp1 is connected to the input terminal of a Miller gain stage G1, the output terminal of the Miller gain stage G1 is connected to the input terminal of a buffer B1, and the input terminal and the output terminal of the Miller gain stage G1 are also connected through a second adjustable resistor Rc and a Miller capacitor Cc connected in series. The output terminal of the buffer B1 is connected to the gate of the main power tube NM1, the drain of the main power tube NM1 is connected to the input voltage VIN, the source is used as the voltage output terminal VOUT of the LDO, and the voltage output terminal VOUT of the LDO is grounded through a feedback resistor network (including a first feedback resistor Rfb1 and a second feedback resistor Rfb2 connected in series), and the feedback resistor network outputs the feedback voltage fb.

[0008] Figure 2 The combination of the Miller gain stage G1, the second adjustable resistor Rc and the Miller capacitor Cc constitutes the basic structure diagram of the Miller compensation circuit of the LDO. In other embodiments, the actual circuit diagram of the Miller compensation circuit will be more complicated.

[0009] Thus, one dominant pole is located at the input node n1 of the Miller compensation circuit of the LDO, and the other pole is located at the output node n2 of the Miller compensation circuit of the LDO. In this embodiment, the gain of the gain stage = Av, and the output signal of the gain stage is asynchronous with the input signal (phase shift is 180°), and Miller compensation is achieved by amplifying the input capacitance of the Miller gain stage G1 by the Miller capacitor. At this time, the dominant pole frequency of the input node n1 of the Miller compensation circuit is 1 / (2π × Zo1 × (1 + Av) × Cc), Zo1 is the output impedance of the error amplifier Amp1, Cc is the Miller capacitor, and Av is the gain of the gain stage. The specific principle of Miller compensation can be found in [R. Jabcob-Baker, CMOS Circuit Design Layout and Simulation 3rd Edition, page 660].

[0010] Although both pole-zero tracking technology and Miller compensation technology can achieve frequency compensation to improve the performance of LDO, there is currently no technology that combines zero-pole tracking technology and Miller compensation to take into account the advantages of both. This combination requires some skills because the two nodes of Miller compensation (i.e. Figure 2 The n1 and n2 in the figure vary with the process, bias conditions and temperature. Summary of the invention

[0011] The invention provides a Miller compensation circuit with pole-zero tracking of an LDO, so as to combine the pole-zero tracking technology with Miller compensation to improve the output performance of the LDO.

[0012] In order to achieve the above-mentioned object, the present invention provides a Miller compensation circuit with pole-zero tracking of an LDO, which is arranged between the output end of the error amplifier of the LDO and the input end of the buffer, and includes a Miller gain stage connected between the input node and the output node of the Miller compensation circuit, and a second switch tube, a fixed resistor and a Miller capacitor connected between the input node and the output node of the Miller compensation circuit and connected in series; the gate of the second switch tube is connected to a signal related to the load current, so that when the load current increases, its equivalent resistance decreases; when the load current decreases, its equivalent resistance increases.

[0013] The second switch tube is connected in series with a fixed resistor and a Miller capacitor via a source and a drain.

[0014] The Miller gain stage between the input node and the output node of the Miller compensation circuit is a common source amplifier, including a first switch tube and a first current source. The source of the first switch tube is grounded, the gate is connected to the input node of the Miller compensation circuit, and the drain is connected to the output node of the Miller compensation circuit and connected to the first current source.

[0015] The Miller compensation circuit with pole-zero tracking of the LDO also includes a third switch tube connected to the gate of the second switch tube to form a current mirror, the source of the third switch tube is grounded through a fourth switch tube connected in a diode manner, and the drain of the third switch tube is connected to the second current source and the sensing current of the load current.

[0016] The fourth switch tube has the same size and orientation as the first switch tube and is arranged with a common center of mass, and the second switch tube has the same size and orientation as the third switch tube and is arranged with a common center of mass.

[0017] The zero point of the Miller compensation circuit is moved by adjusting the values ​​of the first current source, the second current source, and the sense current of the load current.

[0018] The LDO includes an error amplifier, wherein two input terminals of the error amplifier are respectively connected to a reference voltage and a feedback voltage, an output terminal of the error amplifier is connected to an input node of the Miller compensation circuit, and an output node of the Miller compensation circuit is connected to an input terminal of a buffer; an output terminal of the buffer is connected to a gate of a main power tube, a drain of the main power tube is connected to an input voltage, a source serves as a voltage output terminal of the LDO, and a voltage output terminal of the LDO is connected to a feedback resistor network, and the feedback resistor network is used to output a feedback voltage.

[0019] The error amplifier is a single-ended differential circuit.

[0020] The buffer adopts a PMOS type source follower, the gate of the source follower is connected to the output node of the Miller compensation circuit, the source is connected to the third current source, and the drain is grounded.

[0021] The main power tube includes a sensing resistor and a first power tube connected in series and a second power tube connected in parallel with the sensing resistor and the first power tube. Both ends of the sensing resistor are connected to a load current sensing circuit to output a sensing current of the load current through the load current sensing circuit.

[0022] The Miller compensation circuit with pole-zero tracking of the LDO of the present invention generates an adaptive zero point by connecting the second switch tube in series with the Miller capacitor, so that the zero point of the Miller compensation circuit tracks the output terminal pole to improve the output performance of the LDO. Among them, by matching two pairs of MOS tubes, the second switch tube can track the bias condition of the input node of the Miller compensation circuit. In addition, by correcting the values ​​of the sensing current of the first current source, the second current source and the load current, the adaptive zero point is moved, thereby adjusting the distance between the output terminal pole and the zero point of the Miller compensation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The present invention is a circuit diagram of an existing LDO using a pole-zero tracking method.

[0024] Figure 2 The present invention is a circuit diagram of an existing LDO using a Miller compensation circuit.

[0025] Figure 3 is a circuit diagram of a Miller compensation circuit with pole-zero tracking of an LDO according to an embodiment of the present invention.

[0026] Figure 4 Is based on Figure 3 Detailed circuit diagram of the Miller compensation circuit with pole-zero tracking of the LDO.

[0027] Figure 5 1 is the Bode diagram of the pole-zero tracking Miller compensation circuit of the present invention.

[0028] Figure 6 is relative to Figure 5 The Bode plot shown is the Bode plot of the Miller compensation circuit without pole-zero tracking technology when the load changes.

[0029] Figure 7 is relative to Figure 5 The Bode plot shown is the Bode plot of the change of the Miller compensation circuit using pole-zero tracking technology when the load changes. DETAILED DESCRIPTION

[0030] like Figure 3 The figure shows a circuit diagram of a Miller compensation circuit with pole-zero tracking of an LDO according to an embodiment of the present invention, which is further improved on the basis of the existing Miller compensation circuit of the LDO to realize the combination of pole-zero tracking technology and Miller compensation technology, taking into account the advantages of both and improving the output performance of the LDO.

[0031] like Figure 3As shown, the LDO includes an error amplifier Amp1, the two input terminals of the error amplifier Amp1 are respectively connected to a reference voltage Vref and a feedback voltage fb, the output terminal of the error amplifier Amp1 is connected to an input node n1 of a Miller compensation circuit, and the output node n2 of the Miller compensation circuit is connected to an input terminal of a buffer B1. The output terminal of the buffer B1 is connected to the gate of the main power tube NM1, the drain of the main power tube NM1 is connected to the input voltage VIN, and the source is used as a voltage output terminal VOUT of the LDO, and the voltage output terminal VOUT of the LDO is grounded through a feedback resistor network (including a first feedback resistor Rfb1 and a second feedback resistor Rfb2 connected in series), and the feedback resistor network is used to output the feedback voltage fb. That is, the Miller compensation circuit with pole-zero tracking of the LDO of the present invention is arranged between the output terminal of the error amplifier Amp1 of the LDO and the input terminal of the buffer B1.

[0032] The Miller compensation circuit with pole-zero tracking of the LDO includes a Miller gain stage G1 connected between an input node n1 and an output node n2 of the Miller compensation circuit, and a second switch tube M2B, a fixed resistor R2 and a Miller capacitor Cc connected between the input node n1 and the output node n2 of the Miller compensation circuit and connected in series.

[0033] The second switch tube M2B is preferably an NMOS tube, which is connected in series with the fixed resistor R2 and the Miller capacitor Cc through the source and the drain, and its gate is connected to a signal related to the load current Iload, so that the second switch tube M2B acts as a load-related resistor.

[0034] See also Figure 3 For the Miller compensation circuit, the gain of the Miller gain stage G1 between its input node n1 and output node n2 is expressed as -Av. The input node n1 of the Miller compensation circuit is used to receive the input signal of the Miller gain stage G1, and the output node n2 of the Miller compensation circuit is used to output the output signal of the Miller gain stage G1.

[0035] In this embodiment, the Miller gain stage G1 between the input node n1 and the output node n2 of the Miller compensation circuit is a common source amplifier, specifically including a first switch tube M1A of NMOS tube type and a first current source Ib1, the source of the first switch tube M1A is grounded, the gate is connected to the input node n1 of the Miller compensation circuit, and the drain is connected to the output node n2 of the Miller compensation circuit and connected to the first current source Ib1.

[0036] Obviously, the DC bias voltage nodes (i.e., input node n1 and output node n2) will vary with process, bias conditions (i.e., first current source Ib1) or temperature. In addition, as we mentioned, in order to achieve zero-pole tracking, a load-dependent resistor in series with the Miller capacitor Cc needs to be inserted.

[0037] This situation is similar to trying to follow a car and measure the length of its doors. Of course, this task would be much easier if the car was not moving. Figure 1 Or, if people are sitting in a car, it means we are sitting on a chair and moving in the direction of the car. In this regard, we only need to focus on measuring the length of the door, and we don't need to do two difficult things at the same time. The purpose of the present invention is to find the chair that follows the car - a circuit for tracking the DC bias condition of the Miller gain stage of the Miller compensation circuit. And in this circuit, the present invention adds more load-related information. Thereby, the combination of pole-zero tracking technology and Miller compensation technology is realized.

[0038] The Miller compensation circuit with pole-zero tracking of an LDO of the present invention comprises a pole-zero tracking circuit.

[0039] like Figure 3 As shown in the red box in FIG. 1 , the pole-zero tracking circuit is a part of the Miller compensation circuit of the present invention, which includes the second switch tube M2B, the third switch tube M2A connected to the second switch tube M2B with the same gate to form a current mirror, the source of the third switch tube M2A is grounded through the fourth switch tube M1B in a diode connection mode, and the drain of the third switch tube M2A is connected to the second current source Ib2 and the sense current Iload_sense of the load current Iload. Among them, the gate and drain of the fourth switch tube M1B are short-circuited and connected to the third switch tube M2A, and the source is grounded to achieve a function similar to a diode.

[0040] In this embodiment, the first switch tube M1A, the second switch tube M2B, the third switch tube M2A, and the fourth switch tube M1B are all NMOS tubes.

[0041] The working principle of the Miller compensation circuit with pole-zero tracking of the LDO of the present invention is as follows:

[0042] The second switch tube M2B plays the role of the load-related resistor Rc. The third switch tube M2A and the fourth switch tube M1B are used to control the gate of the second switch tube M2B. The second current source Ib2 is a bias current flowing into the third switch tube M2A and the fourth switch tube M1B. Therefore, when the load current is equal to 0, the second current source Ib2 sets a DC bias condition for the third switch tube M2A and the fourth switch tube M1B. Since the second switch tube M2B forms a current mirror with the third switch tube M2A, the second current source Ib2 also sets a DC bias condition for the second switch tube M2B. The fourth switch tube M1B is layout-matched with the first switch tube M1A, and the second switch tube M2B is layout-matched with the third switch tube M2A (that is, the two layout-matched switches have the same size and the same orientation, and adopt the common common centroid layout in the analog layout, so that the internal and external effects of the switch tube are similar), so that the second switch tube M2B can better track the bias condition of the input node n1 of the Miller compensation circuit. That is, when the DC bias condition of the first switch tube M1A changes, the gate of the second switch tube M2B can respond to and follow the change of the DC bias condition of the first switch tube M1A, so that the equivalent resistance of the second switch tube M2B changes.

[0043] In addition, the load-related bias current (i.e., the sense current Iload_sense of the load current Iload) is also fed into the branch where the third switch tube M2A and the fourth switch tube M1B are located. This current will control the voltage of the gate of the second switch tube M2B, so the current passing through the second switch tube M2B also depends on the load current.

[0044] Therefore, in the present invention, by adjusting the sensed current values of the first current source Ib1, the second current source lb2, and the load current Iload, the zero point Zmiller of the Miller compensation circuit is shifted, so that the distance between the output pole Pload and the zero point Zmiller of the Miller compensation circuit can be adjusted to the required range before using the LDO. Ideally, if Zmiller and Pload are always in the same position, but this is not easy. Theoretically, the distance between the output pole Pload and the zero point Zmiller of the Miller compensation circuit should be within one decade (i.e., F_Zmiller / 10 < F_Pload < F_Zmiller×10) to have an effect, where F_Zmiller is the frequency of the zero point Zmiller of the Miller compensation circuit, and F_Pload is the frequency of the output pole Pload. Nowadays, it is very difficult to accurately calculate the position of the zero point Zmiller of the Miller compensation circuit by manual calculation alone. We completed this work with the help of simulation tools. We usually choose that when there is no load (Iload = 0), F_Zmiller = 1.5×F_Pload ~ 2×F_Pload. When the load increases, usually we make Zmiller move faster than Pload, so actually the zero point Zmiller of the Miller compensation circuit does not work under a load of about 100 mA. At this load (100 mA), usually the output pole Pload is already far from the Miller pole Pmiller, so the phase margin is also acceptable.

[0045] Specifically, since the Miller gain stage G1 of the Miller compensation circuit uses a common-source amplifier (i.e., the first switching transistor M1A), the gate-source voltage VGS_M1A of the first switching transistor M1A (i.e., the voltage of the input node n1 of the Miller compensation circuit) is decomposed into Vtn + VOV1. Among them, Vtn is the threshold voltage of the switching transistor, and VOV1 is the overdrive voltage of the switching transistor. The drain-source voltage of the MOSFET needs to be higher than this number to make the MOSFET operate in the saturation region.

[0046] The following combines Figure 3 , and uses Kirchhoff's voltage law to calculate the gate-source voltage (VGS_M2B) of the second switching transistor M2B and the equivalent resistance of the second switching transistor M2B.

[0047] According to Figure 3 the loop formed by the first switching transistor M1A, the second switching transistor M2B, the third switching transistor M2A, and the fourth switching transistor M1B in

[0048] Based on Kirchhoff's voltage law, the following formula (1) is obtained: VGS_M1A - VGS_M1B - VGS_M2A + VGS_M2B = 0

[0049] →VGS_M2B=VGS_M1B+VGS_M2A-VGS_M1A (1)

[0050] According to the gate-source voltage decomposition described above, we can get:

[0051] VGS_M2B=VT_M2B+VOV_M2B

[0052] VGS_M1B=VT_M1B+VOV_M1B

[0053] VGS_M1A=VT_M1A+VOV_M1A

[0054] VGS_M2A=VT_M2A+VOV_M2A

[0055] Among them, VT_M2B, VT_M1B, VT_M1A, and VT_M2A are threshold voltages of the switch tubes M2B, M1B, M1A, and M2A respectively, and VOV_M2B, VOV_M1B, VOV_M1A, and VOV_M2A are overdrive voltages of the switch tubes M2B, M1B, M1A, and M2A respectively.

[0056] Therefore, according to formula (1), the transformation results in the following formula (2):

[0057] VT_M2B+VOV_M2B=(VT_M1B+VOV_M1B)+(VT_M2A+VOV_M2A)-(VT_M1A+VOV_M1A)(2)

[0058] Because all these switch tubes M2B, M1B, M1A, and M2A are matched, all threshold voltages of these switch tubes M2B, M1B, M1A, and M2A are equal to each other, that is, they satisfy:

[0059] VT_M2B=VT_M1B=VT_M2A=VT_M1A.

[0060] Then, according to formula (2), we can simplify formula (3):

[0061] VOV_M2B=VOV_M1B+VOV_M2A-VOV_M1A (3)

[0062] Among them, the overdrive voltage of the switch tube is equal to:

[0063]

[0064] in, is the gate-source voltage, is the overdrive voltage, is the threshold voltage, which is the minimum gate-source voltage required for an electronic device to begin conducting. is the drain current, is the transconductance parameter of the switching tube, W and L are the width and length of the conductive channel of the switching tube.

[0065] Under bias conditions, the sense current of the load current Iload_sense=0. Therefore, if Ib1=Ib2 is set, and the sizes of the first switch tube M1A and the fourth switch tube M1B are set so that VOV_M1A=VOV_M1B, then VOV_M2B=VOV_M2A is satisfied. If the size of the second switch tube M2B is further set equal to the third switch tube M2A, the drain current ID_M2B (capacity) of the second switch tube M2B=the drain current ID_M2A of the third switch tube M2A=the current Ib2 of the second current source=the current Ib1 of the first current source=the bias current Ibias.

[0066] Now we need to convert the drain current capability of the second switch tube M2B into an equivalent resistance. To do this, we assume that 1V AC (alternating current) is applied between the input node n1 and the output node n2 of the Miller compensation circuit. Obviously, the second switch tube M2B will help limit the current charged into the Miller capacitor Cc. Please note that the fixed resistor R2 is only to limit the minimum value of the Miller resistance to avoid the RHP (right half plane) zero effect of the Miller compensation. Then in fact, the current charged into the Miller capacitor Cc is mostly limited by the second switch tube M2B, and the current is equal to the drain current ID_M2B of the second switch tube M2B, and then equal to the current Ib2 of the second current source. Therefore, in this case, the equivalent resistance of the second switch tube M2B is equal to 1V / ID_M2B. If the current Ib2 of the second current source = 1uA, then the equivalent resistance is equal to 1V / 1uA = 1Meg.

[0067] According to the prior art, the zero point Zmiller of the Miller compensation circuit satisfies the following formula:

[0068] Zmiller = 1 / (2π × Rc × Cc),

[0069] Where Rc is the load dependent resistor and Cc is the capacitance value of the Miller capacitor.

[0070] In the present invention, the zero point Zmiller of the Miller compensation circuit is an adaptive zero point. The following will start from formula (3) to calculate the change of the zero point Zmiller of the Miller compensation circuit with the load current.

[0071] VOV_M2B=VOV_M1B+VOV_M2A-VOV_M1A (3)

[0072] Now, the current flowing through the fourth switch tube M1B and the third switch tube M2A includes the sense current Iload_sense of the load current, where Iload_sense=k×Iload.

[0073] Similarly, in order to obtain a simple manual calculation result, in one example, if the size of the fourth switch tube M1B is selected to be equal to the third switch tube M2A, then:

[0074] VOV_M1B=VOV_M2A=

[0075] Wherein, Iload_sense is the sensing current of the load current, Ib2 is the current of the second current source, is the transconductance parameter of the switch tube, W_M2A and L_M2A are the width and length of the conductive channel of the third switch tube M2A.

[0076] VOV_M1A=

[0077] VOV_M2B=

[0078] Wherein, Ib1 is the current of the first current source, ID_M2B is the drain current of the second switch tube M2B, is the transconductance parameter of the switch tube, W_M1A and L_M1A are the width and length of the conductive channel of the first switch tube M1A, and W_M2B and L_M2B are the width and length of the conductive channel of the second switch tube M2B.

[0079] Therefore, formula (3) is transformed into formula (4):

[0080] VOV_M2B=VOV_M1B+VOV_M2A-VOV_M1A =2×VOV_M2A-VOV_M1A =2×

[0081] =

[0082] →ID_M2B={ } (W_M2B / L_M2B) / 2 (4)

[0083] If all devices have the same width and length, then squaring the two sides of formula (4) and rearranging them yields formula (5):

[0084] ID_M2B={ } W / 2L =4 (Iload_sense+Ib2)+Ib1- [ ] W / 2L (5)

[0085] From formula (5), we can see that the value of the drain current ID_M2B of the second switch tube M2B is not linearly proportional to the sense current Iload_sense of the load current, but it is obviously dependent on the sense current Iload_sense of the load current. When the sense current Iload_sense of the load current increases, the drain current ID_M2B of the second switch tube M2B will also increase, and vice versa.

[0086] As described above, the equivalent resistance of the second switch tube M2B is inversely proportional to the drain current ID_M2B of the second switch tube M2B. Therefore, it is obvious that when the sense current Iload_sense of the load current increases (meaning that the load current Iload increases), the load-related resistance Rc of the Miller compensation circuit (that is, the equivalent resistance Rc_M2B of the second switch tube M2B) decreases, and when the load decreases, the equivalent resistance Rc_M2B of the second switch tube M2B increases. This means that when the load current is high, the Miller zero is pushed to a higher frequency; when the load current is small, the Miller zero will be pulled to a lower frequency. This allows the Miller zero Zmiller to keep close to the tracking of the output pole Pload (that is, the pole located at the load or the output of the LDO), achieving an adaptive zero, thereby improving the phase margin of the system as a whole.

[0087] The detailed circuit diagram of the LDO with the Miller compensation circuit of the pole-zero tracking of the present invention is as follows: Figure 4 shown.

[0088] In this embodiment, the error amplifier Amp1 is just a common single-ended differential circuit, including a first error amplifier switch tube PM1 and a second error amplifier switch tube PM2 (both PMOS tubes) whose sources are simultaneously connected to the error amplifier current source Ib0, the drains of the first error amplifier switch tube PM1 and the second error amplifier switch tube PM2 are respectively connected to the drains of the third error amplifier switch tube NMD1 and the fourth error amplifier switch tube NMD1 (both NMOS tubes), the sources of the third error amplifier switch tube NMD1 and the fourth error amplifier switch tube NMD1 are both grounded, the gates are connected to each other, and the gate of the third error amplifier switch tube NMD1 is connected to the drain.

[0089] Miller capacitor Cc is arranged between input node n1 and output node n2 of Miller compensation circuit, input node n1 of Miller compensation circuit is gate of Miller gain stage G1, output node n2 of Miller compensation circuit is drain of Miller gain stage G1, Miller gain stage G1 comprises a first switch tube M1A and a first current source Ib1, source of the first switch tube M1A is grounded, gate is connected to input node n1 of Miller compensation circuit, drain is connected to output node n2 of Miller compensation circuit and connected to first current source Ib1. Buffer B1 connected to gate of main power tube NM1 adopts PMOS type source follower PMgt, gate of source follower PMgt is connected to output node n2 of Miller compensation circuit, source is connected to third current source Ib3, and drain is grounded.

[0090] The main power tube NM1 includes a sensing resistor Rsense and a first power tube NPW1 connected in series, and a second power tube NPW2 connected in parallel with the sensing resistor Rsense and the first power tube NPW1. Both ends of the sensing resistor Rsense are connected to a load current sensing circuit to output a sensing current Iload_sense of the load current through the load current sensing circuit. The sensing current Iload_sense is proportional to the load current Iload, that is, Iload_sense=k×Iload. Through this setting, the sensing current Iload_sense is obtained.

[0091] The pole-zero tracking Miller compensation circuit of the present invention has been verified on silicon.

[0092] Combine the following Figure 5-Figure 7 To illustrate the Bode diagram of the pole-zero tracking Miller compensation circuit of the present invention, and the influence of three main poles / zeros on the Bode diagram.

[0093] Pmiller, Pload, and Zmiller correspond to the main poles / zeros generated by the Miller capacitance, where Pload is the output pole (i.e., the pole located at the load or the output of the LDO), Pmiller is the Miller pole (i.e., the pole located at the input node of the Miller compensation circuit), and Zmiller is the zero of the Miller compensation circuit.

[0094] The main poles of each Miller capacitor are:

[0095] Pmiller=1 / (2π × Zo1 ×(1+Av) × Cc),

[0096] Among them, Zo1 is the output impedance of the error amplifier, Cc is the Miller capacitance, and Av is the gain of the gain stage.

[0097] Pload=1 / (2π × (1 / Gm_NPWR / / RL) × Cout),

[0098] Among them, Gm_NPWR is the transconductance of the main power tube, RL is the load resistance, / / represents the parallel operator, and Cout is the output capacitance value.

[0099] Zmiller = 1 / (2π × Rc × Cc),

[0100] Where Rc is the load dependent resistor whose value is proportional to the value of the load resistance RL, and Cc is the capacitance value of the Miller capacitor.

[0101] The Miller pole Pmiller acts as the dominant pole of the system and is located at the input node n1 of the Miller compensation circuit. The output pole Pload acts as another major pole and is located at the output of the LDO. The zero point Zmiller of the Miller compensation circuit acts as the main LHPZ (left half plane zero) and is created by the Miller capacitor Cc and the load-related resistors (i.e., the fixed resistor R2 and the second switch tube M2B in series with each other). There are two more poles at the output node n2 of the Miller compensation circuit and the gate NGATE of the main power tube NM1. They are pushed to high frequencies by the Miller effect or buffer B1, respectively. These poles are at high frequencies and are beyond the scope of our investigation, so we will not talk too much about them.

[0102] In the present embodiment, the LDO is an LDO based on an NMOS type main power tube, so its output impedance is not large compared to an LDO based on a PMOS type main power tube. The output impedance of the LDO based on an NMOS type main power tube is (1 / Gm_NPWR), and is connected in parallel with the load resistor RL. When the output impedance (1 / Gm_NPWR) of the LDO is not large, especially under heavy load, the LDO based on an NMOS type main power tube is particularly unsuitable for using the output pole as the dominant node to compensate the LDO. In fact, due to the capacitor multiplication effect caused by the Miller effect, Miller compensation is a good candidate for loop compensation of an NMOS-based LDO. Due to the Miller effect, the capacitance of the input node n1 of the Miller compensation circuit becomes huge, and the pole of the input node n1 of the Miller compensation circuit is pushed to a low frequency and dominates.

[0103] exist Figure 5 As can be seen in the Bode plot shown, the Miller pole Pmiller is the dominant pole. The other main poles / zeros move with the load but track each other. The pink arrows indicate that the output pole Pload and the zero Zmiller of the Miller compensation circuit can move left or right with changes in load, but they will track each other.

[0104] The loop gain of the Miller compensation circuit with pole-zero tracking of the LDO of the present invention starts to decrease from the Miller pole Pmiller, and the amplitude of the signal is attenuated by 20 dB (ie -20 db / decade) every time the frequency is reduced by 10 times.

[0105] The phase starts to decrease from one decade before the Miller pole Pmiller (that is, when the frequency is reduced to one tenth of the frequency corresponding to the Miller pole Pmiller). At the Miller pole Pmiller, the phase has dropped by 45°, and when the frequency reaches one decade after the Miller pole, the phase will drop another 45°. At this point, if there are no other poles, it can be said that the phase graph stops decreasing, but the loop gain continues to decrease at a slope of -20dB per decade.

[0106] The frequency of the output pole Pload depends on the load current IL and is also related to the zero Zmiller of the Miller compensation circuit. These poles / zeros track each other, but they are not always at the same frequency. On the Bode plot, the output pole Pload may appear before or after the zero Zmiller of the Miller compensation circuit, but they are always close to each other.

[0107] exist Figure 5 In the figure, the output pole Pload appears before the zero Zmiller of the Miller compensation circuit on the Bode plot. Since the output pole Pload appears first, the loop gain decreases at a slope of -40dB per decade from the output pole Pload until the frequency of the Miller zero is reached, and then the slope returns to -20dB per decade.

[0108] Similarly, since the loop gain appears before the zero Zmiller of the Miller compensation circuit, the output pole Pload will also have an impact earlier in the phase margin curve; this causes the phase margin to decrease until the zero Zmiller of the Miller compensation circuit begins to work. At this point, the phase margin stops decreasing and begins to change direction. On the phase diagram, you can see that there is a depression here. Therefore, the distance between the output pole Pload and the zero Zmiller of the Miller compensation circuit determines the depth of this depression. In fact, this phase depression has a great influence on the size of the ringing waveform in the load transient response of the low dropout linear regulator (LDO).

[0109] To better understand the impact of pole-zero tracking, look at the two example Bode plots below, where Example 1 is a Miller compensation circuit without pole-zero tracking and Example 2 is a Miller compensation circuit with pole-zero tracking.

[0110] The Bode plot of the Miller compensation circuit (i.e., Example 1) without pole-zero tracking is shown in Figure 1. Figure 6 As shown in Figure 2, the output pole Pload moves to low frequency (i.e. light load), but the zero Zmiller of the Miller compensation circuit remains at the same Figure 5 The Bode plot shown in the figure is at the same position, far away from the output pole Pload. Since the Miller pole Pmiller and the output pole Pload are close to each other and both are far away from the zero point Zmiller of the Miller compensation circuit, the phase margin drops to 0 before the gain drops to 0, so the system is susceptible to oscillation.

[0111] The Bode plot of the Miller compensation circuit (Example 2) using pole-zero tracking technology is as follows: Figure 7 As shown. Figure 7 In the figure, when the output pole Pload moves to a low frequency (i.e., light load), the output pole Pload moves to the left on the Bode plot. At this time, since the zero point Zmiller of the Miller compensation circuit tracks the output pole Pload, it moves to the left together with the output pole Pload. Therefore, Figure 7 The phase margin is still good.

[0112] In summary, the Miller compensation circuit with pole-zero tracking of the LDO of the present invention generates an adaptive zero point by connecting the second switch tube M2B in series with the Miller capacitor Cc, so that the zero point Zmiller of the Miller compensation circuit tracks the output pole Pload to improve the output performance of the LDO. Among them, by matching two pairs of MOS tubes (M1A, M1B), (M2A, M2B), the second switch tube M2B can track the bias condition of the input node n1 of the Miller compensation circuit. In addition, by correcting the values ​​of the sense current Iload_sense of the first current source Ib1, the second current source lb2 and the load current Iload, the adaptive zero point is moved, thereby adjusting the distance between the output pole Pload and the zero point Zmiller of the Miller compensation circuit.

[0113] The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The above embodiments of the present invention can also be modified in various ways. All simple, equivalent changes and modifications made according to the claims and the description of the present invention fall within the scope of protection of the claims of the present invention. The contents not described in detail in the present invention are all conventional technical contents.

Claims

1. A Miller compensation circuit with pole-zero tracking of an LDO, which is arranged between the output end of an error amplifier (Amp1) of the LDO and the input end of a buffer (B1), characterized in that: The invention comprises a Miller gain stage (G1) connected between an input node (n1) and an output node (n2) of a Miller compensation circuit, and a second switch tube (M2B), a fixed resistor (R2) and a Miller capacitor (Cc) connected between the input node (n1) and the output node (n2) of the Miller compensation circuit and connected in series; the gate of the second switch tube (M2B) is connected to a signal related to the load current, so that when the load current increases, its equivalent resistance decreases; when the load current decreases, its equivalent resistance increases.

2. The Miller compensation circuit with pole-zero tracking of LDO according to claim 1, characterized in that: The second switch tube (M2B) is connected in series with a fixed resistor (R2) and a Miller capacitor (Cc) via a source and a drain.

3. The Miller compensation circuit with pole-zero tracking of LDO according to claim 1, characterized in that: The Miller gain stage (G1) between the input node (n1) and the output node (n2) of the Miller compensation circuit is a common source amplifier, comprising a first switch tube (M1A) and a first current source (Ib1), wherein the source of the first switch tube (M1A) is grounded, the gate is connected to the input node (n1) of the Miller compensation circuit, and the drain is connected to the output node (n2) of the Miller compensation circuit and connected to the first current source (Ib1).

4. The Miller compensation circuit with pole-zero tracking of LDO according to claim 3, characterized in that: It also includes a third switch tube (M2A) connected to the second switch tube (M2B) with a common gate to form a current mirror, the source of the third switch tube (M2A) is grounded through a fourth switch tube (M1B) connected in a diode manner, and the drain of the third switch tube (M2A) is connected to the second current source (Ib2) and the sensing current of the load current.

5. The Miller compensation circuit with pole-zero tracking of LDO according to claim 4, characterized in that: The fourth switch tube (M1B) and the first switch tube (M1A) have the same size, the same orientation and adopt a common centroid layout, and the second switch tube (M2B) and the third switch tube (M2A) have the same size, the same orientation and adopt a common centroid layout.

6. The Miller compensation circuit with pole-zero tracking of LDO according to claim 4, characterized in that: The zero point of the Miller compensation circuit is moved by adjusting the values ​​of the first current source (Ib1), the second current source (lb2), and the sense current (Iload_sense) of the load current.

7. The Miller compensation circuit with pole-zero tracking of LDO according to claim 1, characterized in that: The LDO comprises an error amplifier (Amp1), wherein two input ends of the error amplifier (Amp1) are respectively connected to a reference voltage (Vref) and a feedback voltage (fb), an output end of the error amplifier (Amp1) is connected to an input node (n1) of the Miller compensation circuit, and an output node (n2) of the Miller compensation circuit is connected to an input end of a buffer (B1); an output end of the buffer (B1) is connected to a gate of a main power tube (NM1), a drain of the main power tube (NM1) is connected to an input voltage, a source serves as a voltage output end (VOUT) of the LDO, and the voltage output end (VOUT) of the LDO is connected to a feedback resistor network, and the feedback resistor network is used to output a feedback voltage (fb).

8. The Miller compensation circuit with pole-zero tracking of LDO according to claim 7, characterized in that: The error amplifier (Amp1) is a single-ended differential circuit.

9. The Miller compensation circuit with pole-zero tracking of LDO according to claim 7, characterized in that: The buffer (B1) adopts a PMOS type source follower (PMgt), the gate of the source follower (PMgt) is connected to the output node (n2) of the Miller compensation circuit, the source is connected to the third current source (Ib3), and the drain is grounded.

10. The Miller compensation circuit with pole-zero tracking of LDO according to claim 7, characterized in that: The main power tube (NM1) includes a sensing resistor (Rsense) and a first power tube (NPW1) connected in series, and a second power tube (NPW2) connected in parallel with the sensing resistor (Rsense) and the first power tube (NPW1), and both ends of the sensing resistor (Rsense) are connected to a load current sensing circuit to output a sensed current (Iload_sense) of the load current through the load current sensing circuit.

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