Miller Compensation Circuit with Pole-Zero Tracking for LDO

Abstract

The present invention provides a Miller compensation circuit with pole-zero tracking for an LDO, which includes a Miller gain stage connected between the input node and the output node of the Miller compensation circuit, and a second switching transistor, a fixed resistor, and a Miller capacitor that are connected between the input node and the output node of the Miller compensation circuit and are connected in series; the gate of the second switching transistor is connected to a signal related to the load current, so that when the load current increases, its equivalent resistance decreases; when the load current decreases, its equivalent resistance increases. The Miller compensation circuit with pole-zero tracking for the LDO of the present invention generates an adaptive zero point by connecting the second switching transistor in series with the Miller capacitor, and further enables the zero point of the Miller compensation circuit to track the output terminal pole, so as to improve the output performance of the LDO.

Description

Technical Field

[0001] The present invention belongs to the field of low-dropout regulators, and particularly relates to a Miller compensation circuit with pole-zero tracking for an LDO. Background Art

[0002] A low-dropout regulator (LDO) is a commonly used power management device for providing a stable voltage in a circuit. However, in the design of an LDO, frequency compensation has always been a key issue.

[0003] In traditional LDO designs, frequency compensation is mainly achieved through fixed compensation capacitors and resistors. However, due to factors such as process variations and temperature changes, the fixed compensation method often fails to meet the application requirements of high precision and wide temperature range. Therefore, frequency compensation is usually achieved by using pole-zero tracking technology and Miller compensation technology to improve the performance of the LDO.

[0004] The pole-zero tracking technology is usually used in the compensation scheme for LDOs with a wide load range. The basic idea behind it is: "We need to create a load-dependent resistor so that we can make the left half-plane (LHP) zero track the pole load and cancel each other out. Then the system can actually become a single-pole system (ideally)".

[0005] Figure 1 is a circuit diagram of an existing LDO using the pole-zero tracking method. In Figure 1 it, Class 1 compensation is adopted, where both the pole and the zero are easy to observe and interpret. As Figure 1As shown, the LDO using the pole-zero tracking method includes an error amplifier Amp1. Two input terminals of the error amplifier Amp1 are respectively connected to a reference voltage Vref and a feedback voltage fb. A first capacitor Cc1 and a first adjustable resistor Rc1 are connected in series between the output terminal of the error amplifier Amp1 and the ground. The output terminal of the error amplifier Amp1 is connected to the input terminal of a buffer B1. The output terminal of the buffer B1 is connected to the gate of a main power transistor NM1. The drain of the main power transistor NM1 is connected to an input voltage VIN, and the source is used as the voltage output terminal VOUT of the LDO. And the voltage output terminal VOUT of the LDO is connected to a feedback resistor network grounded (including a series-connected first feedback resistor Rfb1 and a second feedback resistor Rfb2), and the feedback resistor network outputs the feedback voltage fb. Thus, the first main pole is located at the output terminal of the error amplifier Amp1 and is composed of the output impedance Zo1 of the error amplifier Amp1 and the first capacitor Cc1. The main pole frequency at the output terminal of the error amplifier Amp1 is 1 / (2π × Zo1 × Cc). The load-related zero is composed of the first capacitor Cc1 and the first adjustable resistor Rc1. Another main pole is located at the output terminal of the LDO and varies with the load resistor RL. In Figure 1 In the LDO shown, the value of the first adjustable resistor Rc1 is proportional to the load resistor RL (i.e., changes with the load). Therefore, the zero composed of the first adjustable resistor Rc1 and the first capacitor Cc1 can follow the pole at the output terminal, cancel the influence of the pole at the output terminal of the LDO, and make the LDO almost a single-pole system, thereby making the system stable with respect to the load.

[0006] Miller compensation is also commonly used for LDO compensation, especially in multi-stage LDOs that are usually used to obtain high DC gain, good power supply ripple rejection ratio (PSRR), and noise rejection ratio. Figure 2 The circuit diagram of an existing LDO using a Miller compensation circuit is shown.

[0007] In Figure 2 the LDO using Miller compensation includes an error amplifier Amp1. Two input terminals of the error amplifier Amp1 are respectively connected to a reference voltage Vref and a feedback voltage fb. The output terminal of the error amplifier Amp1 is connected to the input terminal of a Miller gain stage G1. The output terminal of the Miller gain stage G1 is connected to the input terminal of a buffer B1. And a second adjustable resistor Rc and a Miller capacitor Cc are also connected in series between the input terminal and the output terminal of the Miller gain stage G1. The output terminal of the buffer B1 is connected to the gate of a main power transistor NM1. The drain of the main power transistor NM1 is connected to an input voltage VIN, and the source is used as the voltage output terminal VOUT of the LDO. And the voltage output terminal VOUT of the LDO is grounded through a feedback resistor network (including a series-connected first feedback resistor Rfb1 and a second feedback resistor Rfb2), and the feedback resistor network outputs the feedback voltage fb.

[0008] Figure 2 The combination of the Miller gain stage G1, the second adjustable resistor Rc, and the Miller capacitor Cc in [description] constitutes the basic structural diagram of the Miller compensation circuit of the LDO. In other embodiments, the actual circuit diagram of the Miller compensation circuit will be more complex.

[0009] Thus, one dominant pole is located at the input node n1 of the Miller compensation circuit of the LDO, and the other pole is located at the output node n2 of the Miller compensation circuit of the LDO. In this embodiment, the gain of the gain stage = Av, and the output signal of this gain stage is asynchronous with the input signal (phase shift is 180°). Miller compensation is achieved by amplifying the input capacitance of the Miller gain stage G1 through the Miller capacitor. At this time, the main pole frequency of the input node n1 of the Miller compensation circuit is 1 / (2π × Zo1 × (1 + Av) × Cc), where Zo1 is the output impedance of the error amplifier Amp1, Cc is the Miller capacitor, and Av is the gain of the gain stage. For the specific principle of Miller compensation, please refer to [R.Jabcob - Baker, CMOS Circuit Design Layout and Simulation 3rd Edition, page 660].

[0010] Although both the pole - zero tracking technique and the Miller compensation technique can achieve frequency compensation to improve the performance of the LDO, however, there is currently no technique that combines the pole - zero tracking technique and the Miller compensation to take into account the advantages of both. This combination requires some skills because the two nodes of the Miller compensation (i.e., Figure 2 n1 and n2 in [description]) both change with the process, bias conditions, and temperature. Summary of the Invention

[0011] The present invention provides a Miller compensation circuit with pole - zero tracking for an LDO to combine the pole - zero tracking technique with the Miller compensation to improve the output performance of the LDO.

[0012] To achieve the above object, the present invention provides a Miller compensation circuit with pole - zero tracking for an LDO, which is arranged between the output end of the error amplifier of the LDO and the input end of the buffer, and includes a Miller gain stage connected between the input node and the output node of the Miller compensation circuit, and a second switching transistor, a fixed resistor, and a Miller capacitor connected in series between the input node and the output node of the Miller compensation circuit; the gate of the second switching transistor is connected to a signal related to the load current, so that when the load current increases, its equivalent resistance decreases; when the load current decreases, its equivalent resistance increases.

[0013] The second switching transistor is connected in series with the fixed resistor and the Miller capacitor through the source and the drain.

[0014] The Miller gain stage between the input node and the output node of the Miller compensation circuit is a common-source amplifier, which includes a first switching transistor and a first current source. The source of the first switching transistor is grounded, the gate is connected to the input node of the Miller compensation circuit, and the drain is connected to the output node of the Miller compensation circuit and the first current source.

[0015] The Miller compensation circuit of the LDO with pole-zero tracking further includes a third switching transistor connected in common-gate with the second switching transistor to form a current mirror. The source of the third switching transistor is grounded through a fourth switching transistor in a diode-connected manner, and the drain of the third switching transistor is connected to the second current source and the sensed current of the load current.

[0016] The fourth switching transistor has the same size, the same orientation as the first switching transistor and adopts a centroid-sharing layout, and the second switching transistor has the same size, the same orientation as the third switching transistor and adopts a centroid-sharing layout.

[0017] The zero point of the Miller compensation circuit is shifted by adjusting the values of the first current source, the second current source and the sensed current of the load current.

[0018] The LDO includes an error amplifier. Two input terminals of the error amplifier are respectively connected to a reference voltage and a feedback voltage. The output terminal of the error amplifier is connected to the input node of the Miller compensation circuit. The output node of the Miller compensation circuit is connected to the input terminal of a buffer; the output terminal of the buffer is connected to the gate of a main power transistor. The drain of the main power transistor is connected to an input voltage, and the source is used as the voltage output terminal of the LDO. The voltage output terminal of the LDO is connected to a feedback resistor network, and the feedback resistor network is used to output a feedback voltage.

[0019] The error amplifier is a single-ended differential circuit.

[0020] The buffer adopts a PMOS type source follower. The gate of the source follower is connected to the output node of the Miller compensation circuit, the source is connected to a third current source, and the drain is grounded.

[0021] The main power transistor includes a sensing resistor and a first power transistor connected in series, and a second power transistor connected in parallel with the sensing resistor and the first power transistor. Both ends of the sensing resistor are connected to a load current sensing circuit to output the sensed current of the load current through the load current sensing circuit.

[0022] The Miller compensation circuit with pole-zero tracking of the LDO of the present invention generates an adaptive zero by connecting a second switching transistor in series with the Miller capacitor, thereby enabling the zero of the Miller compensation circuit to track the output pole, so as to improve the output performance of the LDO. Among them, by matching 2 pairs of MOS transistors, the second switching transistor can track the bias condition of the input node of the Miller compensation circuit. In addition, by correcting the sensed current values of the first current source, the second current source, and the load current, the adaptive zero is shifted, thereby adjusting the distance between the output pole and the zero of the Miller compensation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a circuit diagram of an existing LDO using the pole-zero tracking method.

[0024] Figure 2 is a circuit diagram of an existing LDO using a Miller compensation circuit.

[0025] Figure 3 is a circuit diagram of the Miller compensation circuit with pole-zero tracking of the LDO according to an embodiment of the present invention.

[0026] Figure 4 is according to Figure 3 the detailed circuit diagram of the Miller compensation circuit with pole-zero tracking of the LDO.

[0027] Figure 5 is the Bode plot of the pole-zero tracking Miller compensation circuit of the present invention.

[0028] Figure 6 is relative to Figure 5 the Bode plot shown, when the load changes, the changed Bode plot of the Miller compensation circuit without using the pole-zero tracking technique.

[0029] Figure 7 is relative to Figure 5 the Bode plot shown, when the load changes, the changed Bode plot of the Miller compensation circuit using the pole-zero tracking technique. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] As Figure 3 shown is the circuit diagram of the Miller compensation circuit with pole-zero tracking of the LDO according to an embodiment of the present invention, which is further improved on the basis of the existing Miller compensation circuit of the LDO to realize the combination of the pole-zero tracking technique and the Miller compensation technique, taking into account the advantages of both and improving the output performance of the LDO.

[0031] As Figure 3As shown, the LDO includes an error amplifier Amp1. Two input terminals of the error amplifier Amp1 are respectively connected to a reference voltage Vref and a feedback voltage fb. An output terminal of the error amplifier Amp1 is connected to an input node n1 of a Miller compensation circuit. An output node n2 of the Miller compensation circuit is connected to an input terminal of a buffer B1. An output terminal of the buffer B1 is connected to a gate of a main power transistor NM1. A drain of the main power transistor NM1 is connected to an input voltage VIN, and a source thereof serves as a voltage output terminal VOUT of the LDO. Moreover, the voltage output terminal VOUT of the LDO is grounded through a feedback resistor network (including a series-connected first feedback resistor Rfb1 and second feedback resistor Rfb2), and the feedback resistor network is used to output the feedback voltage fb. That is to say, the Miller compensation circuit with pole-zero tracking of the LDO of the present invention is arranged between the output terminal of the error amplifier Amp1 of the LDO and the input terminal of the buffer B1.

[0032] The Miller compensation circuit with pole-zero tracking of the LDO includes a Miller gain stage G1 connected between the input node n1 and the output node n2 of the Miller compensation circuit, and a second switching transistor M2B, a fixed resistor R2, and a Miller capacitor Cc that are connected between the input node n1 and the output node n2 of the Miller compensation circuit and are in series with each other.

[0033] The second switching transistor M2B is preferably an NMOS transistor, which is connected in series with the fixed resistor R2 and the Miller capacitor Cc through its source and drain, and its gate is connected to a signal related to the load current Iload, so that the second switching transistor M2B functions as a load-related resistor.

[0034] Please refer to Figure 3 again. For the Miller compensation circuit, the gain of the Miller gain stage G1 between its input node n1 and output node n2 is expressed as -Av. The input node n1 of the Miller compensation circuit is used to receive the input signal of the Miller gain stage G1, and the output node n2 of the Miller compensation circuit is used to output the output signal of the Miller gain stage G1.

[0035] In this embodiment, the Miller gain stage G1 between the input node n1 and the output node n2 of the Miller compensation circuit is a common-source amplifier, which specifically includes a first switching transistor M1A of NMOS transistor type and a first current source Ib1. The source of the first switching transistor M1A is grounded, the gate is connected to the input node n1 of the Miller compensation circuit, and the drain is connected to the output node n2 of the Miller compensation circuit and is connected to the first current source Ib1.

[0036] Obviously, both the DC bias voltage nodes (i.e., the input node n1 and the output node n2) vary with the process, the bias condition (i.e., the first current source Ib1), or the temperature. In addition, as we mentioned, in order to achieve zero-pole tracking, a load-related resistor in series with the Miller capacitor Cc needs to be inserted.

[0037] This situation is similar to trying to follow a car and measure the length of the car door. Of course, this task would be much easier if the car were not moving, which is the Figure 1 type 1 compensation in. Or, if people are sitting in the car, which means we are sitting on a chair and moving along the direction of the car. In this regard, we only need to focus on measuring the length of the door, and we don't need to do two difficult things simultaneously. The purpose of the present invention is to find this chair for following the car - a circuit for tracking the DC bias condition of the Miller gain stage of the Miller compensation circuit. And in this circuit, the present invention adds more load-related information. Thus, the combination of the pole-zero tracking technology and the Miller compensation technology is achieved.

[0038] The Miller compensation circuit with pole-zero tracking of the LDO of the present invention includes a pole-zero tracking circuit.

[0039] As Figure 3 shown by the red box in, the pole-zero tracking circuit is a part of the Miller compensation circuit of the present invention, which includes the second switching transistor M2B, the third switching transistor M2A connected in common-gate with the second switching transistor M2B to form a current mirror, the source of the third switching transistor M2A is grounded through the fourth switching transistor M1B in diode connection mode, and the drain of the third switching transistor M2A is connected to the second current source Ib2 and the sensed current Iload_sense of the load current Iload. Among them, the gate and the drain of the fourth switching transistor M1B are short-circuited and connected to the third switching transistor M2A, and the source is grounded to achieve a function similar to that of a diode.

[0040] In this embodiment, the first switching transistor M1A, the second switching transistor M2B, the third switching transistor M2A, and the fourth switching transistor M1B are all NMOS transistors.

[0041] The working principle of the Miller compensation circuit with pole-zero tracking of the LDO of the present invention is as follows:

[0042] The second switching transistor M2B functions as the load-related resistor Rc. The third switching transistor M2A and the fourth switching transistor M1B are used to control the gate of the second switching transistor M2B. The second current source Ib2 is the bias current flowing into the third switching transistor M2A and the fourth switching transistor M1B. Therefore, when the load current is equal to 0, the second current source Ib2 sets the DC bias condition for the third switching transistor M2A and the fourth switching transistor M1B. Since the second switching transistor M2B and the third switching transistor M2A form a current mirror, the second current source Ib2 also sets the DC bias condition for the second switching transistor M2B. The fourth switching transistor M1B and the first switching transistor M1A are layout-matched, and the second switching transistor M2B and the third switching transistor M2A are layout-matched (i.e., the two layout-matched switching transistors have the same size, the same orientation, and adopt the common centroid layout in the analog layout, so that the internal and external effects of the switching transistors are similar), so that the second switching transistor M2B can better track the bias condition of the input node n1 of the Miller compensation circuit. That is, when the DC bias condition of the first switching transistor M1A changes, the gate of the second switching transistor M2B can respond and follow the change of the DC bias condition of the first switching transistor M1A, causing the equivalent resistance of the second switching transistor M2B to change.

[0043] In addition, the load-related bias current (i.e., the sensed current Iload_sense of the load current Iload) is also fed into the branch where the third switching transistor M2A and the fourth switching transistor M1B are located. This current will control the voltage of the gate of the second switching transistor M2B. Therefore, the current passing through the second switching transistor M2B also depends on the load current.

[0044] Therefore, the present invention adjusts the value of the sense current Iload_sense of the first current source Ib1, the second current source lb2, and the load current Iload to move the zero point Zmiller of the Miller compensation circuit, so that the distance between the output pole Pload and the zero point Zmiller of the Miller compensation circuit can be adjusted to the required range before using the LDO. Ideally, if Zmiller and Pload are always in the same position, but this is not easy. Theoretically, the distance between the output pole Pload and the zero point Zmiller of the Miller compensation circuit should be within one decade (i.e., F_Zmiller / 10 < F_Pload < F_Zmiller×10) to have an effect, where F_Zmiller is the frequency of the zero point Zmiller of the Miller compensation circuit, and F_Pload is the frequency of the output pole Pload. Nowadays, it is very difficult to accurately calculate the position of the zero point Zmiller of the Miller compensation circuit only by manual calculation. We completed this work with the help of simulation tools. We usually choose that when there is no load (Iload = 0), F_Zmiller = 1.5×F_Pload~2×F_Pload. When the load increases, usually we make Zmiller move faster than Pload, so actually the zero point Zmiller of the Miller compensation circuit will not work under a load of about 100 mA. At this load (100 mA), usually the output pole Pload is already far from the Miller pole Pmiller, so the phase margin is also acceptable.

[0045] Specifically, since the Miller gain stage G1 of the Miller compensation circuit uses a common-source amplifier (i.e., the first switching transistor M1A), therefore, the gate-source voltage VGS_M1A of the first switching transistor M1A (i.e., the voltage of the input node n1 of the Miller compensation circuit) is decomposed into Vtn + VOV1. Where Vtn is the threshold voltage of the switching transistor, and VOV1 is the overdrive voltage of the switching transistor. The drain-source voltage of the MOSFET needs to be higher than this number to make the MOSFET operate in the saturation region.

[0046] The following combines Figure 3 , and uses Kirchhoff's voltage law to calculate the gate-source voltage (VGS_M2B) of the second switching transistor M2B and the equivalent resistance of the second switching transistor M2B.

[0047] According to Figure 3 the loop formed by the first switching transistor M1A, the second switching transistor M2B, the third switching transistor M2A, and the fourth switching transistor M1B in

[0048] VGS_M1A - VGS_M1B - VGS_M2A + VGS_M2B = 0

[0049] →VGS_M2B = VGS_M1B + VGS_M2A - VGS_M1A (1)

[0050] According to the gate-source voltage decomposition described above, we can obtain:

[0051] VGS_M2B = VT_M2B + VOV_M2B

[0052] VGS_M1B = VT_M1B + VOV_M1B

[0053] VGS_M1A = VT_M1A + VOV_M1A

[0054] VGS_M2A = VT_M2A + VOV_M2A

[0055] Among them, VT_M2B, VT_M1B, VT_M1A, and VT_M2A are the threshold voltages of switching transistors M2B, M1B, M1A, and M2A respectively, and VOV_M2B, VOV_M1B, VOV_M1A, and VOV_M2A are the overdrive voltages of switching transistors M2B, M1B, M1A, and M2A respectively.

[0056] Therefore, according to formula (1), the following formula (2) is obtained through transformation:

[0057] VT_M2B + VOV_M2B = (VT_M1B + VOV_M1B) + (VT_M2A + VOV_M2A) - (VT_M1A + VOV_M1A) (2)

[0058] Because all these switching transistors M2B, M1B, M1A, and M2A are matched, therefore, all the threshold voltages of these switching transistors M2B, M1B, M1A, and M2A are equal to each other, that is, it satisfies:

[0059] VT_M2B = VT_M1B = VT_M2A = VT_M1A.

[0060] Then, according to formula (2), formula (3) can be simplified as follows:

[0061] VOV_M2B = VOV_M1B + VOV_M2A - VOV_M1A (3)

[0062] Among them, the overdrive voltage of the switching transistor is equal to:

[0063]

[0064] Among them, is the gate-source voltage, is the overdrive voltage, is the threshold voltage, which is the lowest gate-source voltage required for the electronic device to start conducting. is the drain current. is the transconductance parameter of the switching transistor, and W and L are the width and length of the conductive channel of the switching transistor.

[0065] Under the bias condition, the sensed current of the load current Iload_sense = 0. Therefore, if Ib1 = Ib2 is set, and the sizes of the first switching transistor M1A and the fourth switching transistor M1B are set such that VOV_M1A = VOV_M1B, then VOV_M2B = VOV_M2A is satisfied. If the size of the second switching transistor M2B is further set to be equal to that of the third switching transistor M2A, then the drain current ID_M2B (capability) of the second switching transistor M2B = the drain current ID_M2A of the third switching transistor M2A = the current Ib2 of the second current source = the current Ib1 of the first current source = the bias current Ibias.

[0066] Now we need to convert the drain current capability of the second switching transistor M2B into an equivalent resistance. For this purpose, we assume that 1V of AC (alternating current) is applied between the input node n1 and the output node n2 of the Miller compensation circuit. Obviously, the second switching transistor M2B will help limit the current charging into the Miller capacitor Cc. Note that the fixed resistor R2 is only to limit the minimum value of the Miller resistance to avoid the RHP (right half plane) zero effect of Miller compensation. Then in fact, the current charging into the Miller capacitor Cc is mostly limited by the second switching transistor M2B, and the current is equal to the drain current ID_M2B of the second switching transistor M2B, and thus equal to the current Ib2 of the second current source. Therefore, in this case, the equivalent resistance of the second switching transistor M2B is equal to 1V / ID_M2B. If the current Ib2 of the second current source = 1uA, then this equivalent resistance is equal to 1V / 1uA = 1Meg.

[0067] According to the prior art, the zero point Zmiller of the Miller compensation circuit satisfies the following formula:

[0068] Zmiller = 1 / (2π × Rc × Cc),

[0069] where Rc is the load-related resistor and Cc is the capacitance value of the Miller capacitor.

[0070] In the present invention, the zero point Zmiller of the Miller compensation circuit is an adaptive zero point. Below, the change of the zero point Zmiller of the Miller compensation circuit with the load current will be calculated starting from formula (3).

[0071] VOV_M2B = VOV_M1B + VOV_M2A - VOV_M1A (3)

[0072] Now, the current flowing through the fourth switching transistor M1B and the third switching transistor M2A includes the sensed current Iload_sense of the load current, and Iload_sense = k × Iload.

[0073] Similarly, for the sake of obtaining a simple hand-calculation result, in one example, if the size of the fourth switching transistor M1B is selected to be equal to that of the third switching transistor M2A, then:

[0074] VOV_M1B = VOV_M2A =

[0075] where Iload_sense is the sensed current of the load current, Ib2 is the current of the second current source, is the transconductance parameter of the switching transistor, and W_M2A and L_M2A are the width and length of the conducting channel of the third switching transistor M2A.

[0076] VOV_M1A =

[0077] VOV_M2B =

[0078] where Ib1 is the current of the first current source, ID_M2B is the drain current of the second switching transistor M2B, is the transconductance parameter of the switching transistor, W_M1A and L_M1A are the width and length of the conducting channel of the first switching transistor M1A, and W_M2B and L_M2B are the width and length of the conducting channel of the second switching transistor M2B.

[0079] Therefore, Equation (3) is transformed into Equation (4):

[0080] VOV_M2B = VOV_M1B + VOV_M2A - VOV_M1A

[0081] = 2 × VOV_M2A - VOV_M1A

[0082] = 2 ×

[0083] =

[0084] → ID_M2B = { } (W_M2B / L_M2B) / 2 (4)

[0085] If the widths and lengths of all devices are the same, then by squaring both sides of Equation (4) and rearranging, Equation (5) can be obtained:

[0086] ID_M2B = { } W / 2L

[0087] =4 (Iload_sense + Ib2) + Ib1 - W / 2L (5)

[0088] From Equation (5), we can see that the value of the drain current ID_M2B of the second switching transistor M2B is not linearly proportional to the load current sense current Iload_sense, but it significantly depends on the load current sense current Iload_sense. When the load current sense current Iload_sense increases, the drain current ID_M2B of the second switching transistor M2B also increases, and vice versa.

[0089] As described above, the equivalent resistance of the second switching transistor M2B is inversely proportional to the drain current ID_M2B of the second switching transistor M2B. Therefore, it is obvious that when the load current sense current Iload_sense increases (which means the load current Iload increases), the load-related resistance Rc of the Miller compensation circuit (i.e., the equivalent resistance Rc_M2B of the second switching transistor M2B) decreases, and when the load decreases, the equivalent resistance Rc_M2B of the second switching transistor M2B increases. This means that when the load current is high, the Miller zero is pushed to a higher frequency; when the load current is small, the Miller zero will be pulled to a lower frequency. This enables the Miller zero Zmiller to maintain close tracking of the output pole Pload (i.e., the pole located at the load or the output of the LDO), achieving an adaptive zero, thereby overall improving the phase margin of the system.

[0090] The detailed circuit of the LDO with the Miller compensation circuit having the pole-zero tracking of the present invention is as Figure 4 shown.

[0091] In this embodiment, the error amplifier Amp1 is just a common single-ended differential circuit, including a first error amplifier switching transistor PM1 and a second error amplifier switching transistor PM2 (both are PMOS transistors) whose sources are simultaneously connected to the error amplifier current source Ib0. The drains of the first error amplifier switching transistor PM1 and the second error amplifier switching transistor PM2 are respectively connected to the drains of a third error amplifier switching transistor NMD1 and a fourth error amplifier switching transistor NMD1 (both are NMOS transistors). The sources of the third error amplifier switching transistor NMD1 and the fourth error amplifier switching transistor NMD1 are both grounded, the gates are connected to each other, and the gate of the third error amplifier switching transistor NMD1 is connected to its drain.

[0092] ​​The Miller capacitor Cc is disposed between the input node n1 and the output node n2 of the Miller compensation circuit. The input node n1 of the Miller compensation circuit is the gate of the Miller gain stage G1, and the output node n2 of the Miller compensation circuit is the drain of the Miller gain stage G1. The Miller gain stage G1 includes a first switching transistor M1A and a first current source Ib1. The source of the first switching transistor M1A is grounded, the gate is connected to the input node n1 of the Miller compensation circuit, and the drain is connected to the output node n2 of the Miller compensation circuit and is connected to the first current source Ib1. The buffer B1 connected to the gate of the main power transistor NM1 employs a PMOS type source follower PMgt. The gate of the source follower PMgt is connected to the output node n2 of the Miller compensation circuit, the source is connected to the third current source Ib3, and the drain is grounded.

[0093] The main power transistor NM1 includes a series-connected sense resistor Rsense, a first power transistor NPW1, and a second power transistor NPW2 connected in parallel with the sense resistor Rsense and the first power transistor NPW1. Both ends of the sense resistor Rsense are connected to the load current sensing circuit to output a sense current Iload_sense of the load current through the load current sensing circuit. The sense current Iload_sense is proportional to the load current Iload, that is: Iload_sense = k × Iload. Through this setting, the sense current Iload_sense is obtained.

[0094] The pole-zero tracking Miller compensation circuit of the present invention has been verified on silicon.

[0095] The following combines Figures 5 - 7 to illustrate the Bode plot of the pole-zero tracking Miller compensation circuit of the present invention, and the influence of 3 main poles / zeros on the Bode plot.

[0096] Pmiller, Pload, and Zmiller correspond to the main poles / zeros generated by the Miller capacitor. Among them, Pload is the output pole (i.e., the pole located at the load or the output of the LDO), Pmiller is the Miller pole (i.e., the pole located at the input node of the Miller compensation circuit), and Zmiller is the zero of the Miller compensation circuit.

[0097] The main poles of each Miller capacitor are:

[0098] Pmiller = 1 / (2π × Zo1 × (1 + Av) × Cc),

[0099] where Zo1 is the output impedance of the error amplifier, Cc is the Miller capacitor, and Av is the gain of the gain stage.

[0100] Pload = 1 / (2π × (1 / Gm_NPWR / / RL) × Cout),

[0101] where Gm_NPWR is the transconductance of the main power transistor, RL is the load resistance, / / represents the parallel operator, and Cout is the output capacitance value.

[0102] Zmiller = 1 / (2π × Rc × Cc),

[0103] where Rc is the load-related resistor whose value is proportional to the value of the load resistance RL, and Cc is the capacitance value of the Miller capacitor.

[0104] The Miller pole Pmiller serves as the dominant pole of the system and is located at the input node n1 of the Miller compensation circuit. The output pole Pload serves as another main pole and is at the output of the LDO. The zero Zmiller of the Miller compensation circuit serves as the main LHPZ (left half-plane zero) and is created by the Miller capacitor Cc and the load-related resistor (i.e., the fixed resistor R2 and the second switching transistor M2B in series with each other). There are also two poles at the output node n2 of the Miller compensation circuit and the gate NGATE of the main power transistor NM1. They are pushed to high frequencies by the Miller effect or the buffer B1 respectively. These pole frequencies are very high and beyond the scope of our investigation, so we will not talk about them too much.

[0105] In this embodiment, the LDO is an LDO based on an NMOS-type main power transistor. Therefore, compared with an LDO based on a PMOS-type main power transistor, its output impedance is not large. The output impedance of the LDO based on an NMOS-type main power transistor is (1 / Gm_NPWR) and is in parallel with the load resistance RL. When the output impedance (1 / Gm_NPWR) of the LDO is not large, especially under heavy load, the LDO based on an NMOS-type main power transistor is particularly not suitable for using the output pole as the dominant node for LDO compensation. In fact, due to the capacitor multiplication effect caused by the Miller effect, Miller compensation is a good candidate for the loop compensation of an NMOS-based LDO. Due to the Miller effect, the capacitance of the input node n1 of the Miller compensation circuit becomes huge, and the pole of the input node n1 of the Miller compensation circuit is pushed to low frequency and dominates.

[0106] In Figure 5 the shown Bode plot, it can be seen that the Miller pole Pmiller is the dominant pole. The other main poles / zeros move with the load but track each other. Among them, the pink arrow indicates that the output pole Pload and the zero Zmiller of the Miller compensation circuit can move left or right with the change of the load but will track each other.

[0107] The loop gain of the Miller compensation circuit with pole-zero tracking in the LDO of the present invention starts to decline from the Miller pole Pmiller. For every 10-fold decrease in frequency, the amplitude of the signal attenuates by 20 dB (i.e., -20 dB / decade).

[0108] The phase starts to decline at one decade before the Miller pole Pmiller (i.e., when the frequency is reduced to one-tenth of the frequency corresponding to the Miller pole Pmiller). At the Miller pole Pmiller, the phase has already declined by 45°, and when the frequency reaches one decade after the Miller pole, the phase will decline by another 45°. At this time, if there are no other poles, it can be said that the phase diagram stops declining, but the loop gain still continues to decline at a slope of -20 dB per decade.

[0109] The frequency of the output pole Pload depends on the magnitude of the load current IL and is also related to the zero Zmiller of the Miller compensation circuit. These poles / zeros will track each other, but they are not necessarily always at the same frequency. On the Bode plot, the output pole Pload may appear before or after the zero Zmiller of the Miller compensation circuit, but they are always close to each other.

[0110] In Figure 5 is shown the case where the output pole Pload appears before the zero Zmiller of the Miller compensation circuit on the Bode plot. Since the output pole Pload appears first, the loop gain starts to decline at a slope of -40 dB per decade from the output pole Pload until it reaches the frequency of the Miller zero, and then the slope resumes to -20 dB per decade.

[0111] Similarly, since the loop gain appears before the zero Zmiller of the Miller compensation circuit, in the phase margin curve, the output pole Pload will also have an earlier impact; this causes the phase margin to decline until the zero Zmiller of the Miller compensation circuit starts to take effect. At this time, the phase margin stops decreasing and starts to change direction. On the phase diagram, a depression can be seen here. Therefore, the distance between the output pole Pload and the zero Zmiller of the Miller compensation circuit determines the depth of this depression. In fact, this phase depression has a great impact on the magnitude of the ringing waveform in the load transient response of the low dropout regulator (LDO).

[0112] To understand the impact of the pole-zero tracking technique more deeply, please view the following two exemplary Bode plots, where Example 1 is the Miller compensation circuit without the pole-zero tracking technique and Example 2 is the Miller compensation circuit with the pole-zero tracking technique.

[0113] The Bode plot of the Miller compensation circuit without pole-zero tracking technology (i.e., Example 1) is as follows Figure 6 shown. When the output pole Pload moves to low frequency (i.e., light load), the zero point Zmiller of the Miller compensation circuit remains at the same position as the Bode plot shown in Figure 5 and is far from the output pole Pload. Since the Miller pole Pmiller and the output pole Pload are adjacent to each other and both are far from the zero point Zmiller of the Miller compensation circuit, the phase margin drops to 0 before the gain drops to 0, so the system is vulnerable to oscillation.

[0114] The Bode plot of the Miller compensation circuit with pole-zero tracking technology (i.e., Example 2) is as follows Figure 7 shown. In Figure 7 , when the output pole Pload moves to low frequency (i.e., light load), the output pole Pload moves to the left on the Bode plot. At this time, since the zero point Zmiller of the Miller compensation circuit tracks the output pole Pload, it moves to the left together with the output pole Pload. Therefore, Figure 7 the phase margin in is still good.

[0115] In summary, the Miller compensation circuit with pole-zero tracking of the LDO of the present invention generates an adaptive zero point by connecting the second switching transistor M2B in series with the Miller capacitor Cc, so that the zero point Zmiller of the Miller compensation circuit tracks the output pole Pload to improve the output performance of the LDO. Among them, by matching two pairs of MOS transistors (M1A, M1B), (M2A, M2B), the second switching transistor M2B can track the bias condition of the input node n1 of the Miller compensation circuit. In addition, by correcting the sensed currents Iload_sense of the first current source Ib1, the second current source lb2, and the load current Iload, the adaptive zero point is moved, and then the distance between the output pole Pload and the zero point Zmiller of the Miller compensation circuit is adjusted.

[0116] The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various changes can be made to the above embodiments of the present invention. All simple, equivalent changes and modifications made according to the claims and the content of the specification of the present invention application fall within the scope of the claims of the present invention patent. Those not described in detail in the present invention are all conventional technical contents.

Claims

1. A Miller compensation circuit with pole-zero tracking for an LDO, which is arranged between the output terminal of an error amplifier (Amp1) of the LDO and the input terminal of a buffer (B1), and is characterized in that, It includes a Miller gain stage (G1) connected between the input node (n1) and the output node (n2) of the Miller compensation circuit, and a second switching transistor (M2B), a fixed resistor (R2), and a Miller capacitor (Cc) connected in series between the input node (n1) and the output node (n2) of the Miller compensation circuit; the gate of the second switching transistor (M2B) is connected to a signal related to the load current, such that when the load current increases, its equivalent resistance decreases; when the load current decreases, its equivalent resistance increases. The Miller gain stage (G1) between the input node (n1) and the output node (n2) of the Miller compensation circuit is a common-source amplifier, including a first switching transistor (M1A) and a first current source (Ib1). The source of the first switching transistor (M1A) is grounded, the gate is connected to the input node (n1) of the Miller compensation circuit, and the drain is connected to the output node (n2) of the Miller compensation circuit and to the first current source (Ib1). The second switching transistor (M2B) and the third switching transistor (M2A) are connected in a common-gate configuration to form a current mirror. The source of the third switching transistor (M2A) is grounded through a fourth switching transistor (M1B) in a diode-connected manner, and the drain of the third switching transistor (M2A) is connected to a second current source (Ib2) and the sensed current of the load current. The zero point of the Miller compensation circuit is shifted by adjusting the values of the first current source (Ib1), the second current source (Ib2), and the sensed current of the load current (Iload_sense). The buffer (B1) uses a PMOS type source follower (PMgt). The gate of the source follower (PMgt) is connected to the output node (n2) of the Miller compensation circuit, the source is connected to a third current source (Ib3), and the drain is grounded; the LDO is an LDO based on an NMOS type main power transistor.

2. The Miller compensation circuit with pole-zero tracking of the LDO according to claim 1, characterized in that, The second switching transistor (M2B) is connected in series with the fixed resistor (R2) and the Miller capacitor (Cc) through its source and drain.

3. The Miller compensation circuit with pole-zero tracking of the LDO according to claim 1, characterized in that, The fourth switching transistor (M1B) has the same size, the same orientation as the first switching transistor (M1A) and adopts a common-centroid layout, and the second switching transistor (M2B) has the same size, the same orientation as the third switching transistor (M2A) and adopts a common-centroid layout.

4. The Miller compensation circuit with pole-zero tracking for the LDO according to claim 1, wherein The LDO includes an error amplifier (Amp1). The two input terminals of the error amplifier (Amp1) are respectively connected to a reference voltage (Vref) and a feedback voltage (fb). The output terminal of the error amplifier (Amp1) is connected to the input node (n1) of the Miller compensation circuit. The output node (n2) of the Miller compensation circuit is connected to the input terminal of the buffer (B1); the output terminal of the buffer (B1) is connected to the gate of the main power transistor (NM1). The drain of the main power transistor (NM1) is connected to the input voltage, and the source is the voltage output terminal (VOUT) of the LDO. The voltage output terminal (VOUT) of the LDO is connected to a feedback resistor network, and the feedback resistor network is used to output the feedback voltage (fb).

5. The Miller compensation circuit with pole-zero tracking of the LDO according to claim 4, characterized in that, The error amplifier (Amp1) is a single-ended differential circuit.

6. The Miller compensation circuit with pole-zero tracking of the LDO according to claim 4, characterized in that, The main power transistor (NM1) includes a sense resistor (Rsense) and a first power transistor (NPW1) connected in series, and a second power transistor (NPW2) connected in parallel with the sense resistor (Rsense) and the first power transistor (NPW1). Both ends of the sense resistor (Rsense) are connected to a load current sensing circuit to output a sense current (Iload_sense) of the load current through the load current sensing circuit.

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