BGR circuit compatible with low-voltage domain and over-voltage domain

Abstract

The invention discloses a low-voltage domain and over-voltage domain compatible BGR circuit, and belongs to the technical field of microelectronics. The circuit comprises divider resistors R1, R2 and R3 and voltage stabilizing capacitors C1-C4, the divider resistors R1, R2 and R3 are used for providing bias voltage for N1, N5, N6, P5, P6, P7 and P11, the N1, N5 and N6 are deep N-well MOS tubes, and P1, N1, N2, N3, N4 and R4 form a starting circuit; when the power supply voltage is 2.3 V-5. 5V, the 3.3 V device is used for realizing the design of the low-power-consumption BGR, and the functions that the low-voltage device is not punctured and the service life of the low-voltage device is not attenuated when the low-voltage device is applied to an over-voltage working condition, and the performance of the device is not reduced in a low-voltage environment are realized.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, and more particularly to a BGR circuit compatible with a low voltage domain and an overvoltage domain. Background Art

[0002] At present, when designing BGR circuits, devices are generally selected based on the maximum value of the power supply voltage domain; for example, if the power supply voltage is 5 volts, a 5 volt device will be selected; if the power supply voltage is 1.8 volts, a 1.8 volt device will be selected; this is not only to prevent device breakdown and shortened device life, but also for better performance. However, under certain processes, the maximum value of the power supply voltage domain is 5 volts, but the process can only support 3.3 volt devices; in addition, it is also necessary to consider that the battery performance can still be maintained under low voltage conditions after the performance is reduced. For example, when the battery voltage drops to 2.3 volts, the performance of the device should not be affected. This requires a special design that can use low-voltage devices to cope with overvoltage working conditions, while ensuring that the performance of the device does not decrease in a low-voltage environment. Summary of the invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a BGR circuit that is compatible with the low-voltage domain and the overvoltage domain, and to solve the following technical problems: it is necessary to be able to use low-voltage devices to cope with overvoltage working conditions, while ensuring that the performance of the equipment does not degrade in a low-voltage environment.

[0004] The purpose of the present invention can be achieved by the following technical solutions:

[0005] A BGR circuit compatible with a low voltage domain and an overvoltage domain, comprising voltage divider resistors R1, R2 and R3, for providing bias voltages to N1, N5, N6, P5, P6, P7 and P11, wherein N1, N5 and N6 are deep N-well MOS tubes, and P1, N1, N2, N3, N4 and R4 form a startup circuit;

[0006] The gate of N2 is connected to the drain of N3, the gate of N4, and the negative electrode of R4, and the source is connected to the positive electrode of R4, so that when the BGR does not work normally, the gate voltage of N4 is quickly pulled up;

[0007] The source of N4 and the source of N10 are connected to the ground GND, and the drain of N4 is connected to the drain of N10, the source of N6 and the substrate, which are used to pull BGR out of the dead zone.

[0008] As a further solution of the present invention, the positive electrode of R1 is connected to the power supply voltage AVDD, the negative electrode of R1 is connected to the positive electrode of R2, the gates of N1, N5 and N6 and the positive electrode of C1, and the negative electrode of R2 is connected to the positive electrode of R3, the positive electrode of C2, the gates of P5, P6, P7 and P11.

[0009] As a further solution of the present invention, at a high voltage of 5.5V, N1, N5, N6, P5, P6, P7, and P11 operate in a saturation region, and their functions are equivalent to voltage-dividing resistors. At a low voltage of 2.3V, N1, N5, N6, P5, P6, P7, and P11 operate in a linear region, and their functions are equivalent to switching tubes, so that N1-N10 and P1-P13 will not be over-voltage at a high voltage of 5.5V, and at a low voltage of 2.3V, P2, P3, P4, P8, P9, P10, P12, P13, and N7-N10 will all operate in a saturation region and will not enter a linear region, thereby reducing performance.

[0010] As a further solution of the present invention, N2 is an intrinsic tube for providing high resistance.

[0011] As a further solution of the present invention, the substrates of all NMOS devices except the self-well device are grounded, and the substrates of all PMOS devices are connected to the power supply voltage.

[0012] Compared with the existing solutions, the present invention has the following beneficial effects:

[0013] When the power supply voltage is 2.3V-5.5V, the present invention realizes the design of low-power BGR with 3.3V devices, realizes the function that low-voltage devices will not be broken down and life will not be reduced under overvoltage working conditions, and the performance of equipment will not be reduced in low-voltage environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The present invention provides a BGR circuit diagram that is compatible with a low-voltage domain and an overvoltage domain. DETAILED DESCRIPTION

[0015] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present invention are provided for the purpose of illustration and description, and are not intended to be exhaustive or to limit the present invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention, and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

[0016] Example 1

[0017] Reference Figure 1As shown, the present invention is a BGR circuit compatible with a low-voltage domain and an overvoltage domain, including voltage-dividing resistors R1, R2 and R3 and voltage-stabilizing capacitors C1-C4, wherein the voltage-dividing resistors R1, R2 and R3 are used to provide bias voltages to N1, N5, N6, P5, P6, P7 and P11, wherein N1, N5 and N6 are deep N-well MOS tubes, P1, N1, N2, N3, N4 and R4 constitute a startup circuit, and the voltage-stabilizing capacitors C1-C4 are used to improve the stability of the voltages at VRES1, VRES2, VBAIS and AIO_VBG_1P2 when the power supply is powered on, so that the risk of oscillation of the BGR circuit is smaller;

[0018] The BGR is in voltage mode and has only one degenerate point. Only when the current flowing through Q1, Q2, and Q3 is zero, the BGR circuit is in the "dead zone". At this time, the feedback voltage VFB is low, N3 is closed, and the gate voltage of N4 is pulled up. When the gate voltage of N4 is greater than its threshold voltage V TH When N4 is turned on, the VBACK voltage is pulled down, so the gate voltage VBAIS of P2, P3, P4, and P10 is also pulled down, which increases the current flowing through P2, P3, P4, and P10, and the feedback voltage VFB increases. When the feedback voltage VFB is greater than the threshold voltage V TH When N3 is turned on, the gate voltage of N4 drops to ground GND, and N4 is turned off. At this time, the BGR circuit has left the "dead zone".

[0019] N2 is an intrinsic transistor used to provide high resistance, the threshold voltage of the intrinsic transistor is V TH The gate of N2 is not connected to GND like the traditional intrinsic tube, but is connected to the drain of N3, the gate of N4, and the negative electrode of R4. If the gate of N2 is connected to GND, the V GS The limitation makes the gate voltage of N4 unable to reach a high potential even if BGR is in the dead zone, and even less than the threshold voltage V of N4. TH This is not conducive to the establishment of soft start. The gate of N2 is connected to the drain of N3, the gate of N4, and the negative electrode of R4, and the source is connected to the positive electrode of R4, so that when BGR does not work normally, the gate voltage of N4 is quickly pulled up.

[0020] P1-P13 are PMOS transistors, N1-N10 are NMOS transistors, R1-R7 are resistors, C1-C4 are voltage stabilizing capacitors, N1, N5 and N6 are deep N-well MOS transistors, and are 6-terminal devices;

[0021] The positive electrode of R1 is connected to the power supply voltage AVDD, the negative electrode of R1 is connected to the positive electrode of R2, the gates of N1, N5, N6 and the positive electrode of C1; the negative electrode of R2 is connected to the positive electrode of R3, the positive electrode of C2, the gates of P5, P6, P7 and P11; the negative electrode of R3 is grounded GND.

[0022] The gate and drain of P1 are connected to the drain and deep N-well of N1, and the source is connected to the power supply voltage AVDD; the source and substrate of N1 are connected to the drain of N2; the gate of N2 is connected to the drain of N3, the gate of N4, and the negative electrode of R4, and the source is connected to the positive electrode of R4; the gate of N3 is connected to the negative electrode of R6 and the positive electrode of R7, and the source is connected to the ground GND; the source of N4 is connected to the ground GND, and the drain is connected to the drain of N10, the source of N6, and the substrate; the gate of P2 is connected to the gate of P3, the gate of P4, the gate of P9, the drain of P10, the negative electrode of C3, the drain of N6, and the deep N-well, the source is connected to the power supply voltage AVDD, and the drain is connected to the source of P5;

[0023] The source of P3 is connected to the power supply voltage AVDD, and the drain is connected to the source of P6; the source of P4 is connected to the power supply voltage AVDD, and the drain is connected to the source of P7; the drain of P5 is connected to the emitter of the bipolar junction pnp transistor Q1 and the gate of P12; the drain of P6 is connected to the positive electrode of R5 and the gate of P13; the drain of P7 is connected to the positive electrode of capacitor C4 and the positive electrode of R6; the negative electrode of R5 is connected to the emitter of the bipolar junction pnp transistor Q2; the negative electrode of R7 is connected to the emitter of the bipolar junction pnp transistor Q3. The collector and base of Q1, the collector and base of Q2, and the collector and base of Q3 are all connected to the ground GND; the positive electrode of C3 is connected to the power supply AVDD; the negative electrodes of C1, C2, and C4 are all connected to the ground GND.

[0024] The gate and drain of P8 are connected to the gate of P10, the drain of N5, and the deep N-well, and the source is connected to the power supply AVDD; the source of P9 is connected to the power supply AVDD, and the drain is connected to the source of P11; the source of P10 is connected to the power supply AVDD; the drain of P11 is connected to the source and substrate of P12, and the source and substrate of P13; the drain of P12 is connected to the drain and gate of N8, and the gate of N7; the drain of P13 is connected to the drain and gate of N9, and the gate of N10; the source and substrate of N5 are connected to the drain of N7; the source and substrate of N6 are connected to the drain of N10; the sources of N7, N8, N9, and N10 are all connected to the ground GND.

[0025] The drain of N4 is connected to the drain of N10, the source of N6 and the substrate to pull BGR out of the dead zone. Because N4 is a 3.3V device, it cannot be connected to the gates of P2 and P3 as in the traditional connection method. Otherwise, the V of N4 will be DBThat is, the voltage difference between the drain and the substrate will be over-voltage, which greatly reduces the life of the MOS tube. At 5.5V high voltage, N1, N5, N6, P5, P6, P7 and P11 work in the saturation region, which is equivalent to the function of the voltage divider resistor. At 2.3V low voltage, N1, N5, N6, P5, P6, P7 and P11 work in the linear region, which is equivalent to the function of the switch tube, so that N1-N10 and P1-P13 will not be over-voltage at 5.5V high voltage, and P2, P3, P4, P8, P9, P10, P12, P13 and N7-N10 will work in the saturation region and will not enter the linear region at 2.3V low voltage, thereby reducing performance.

[0026] The substrates of all NMOS devices except the self-well device are grounded, and the substrates of all PMOS devices are connected to the power supply voltage.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A BGR circuit compatible with a low voltage domain and an overvoltage domain, characterized in that: It includes voltage-dividing resistors R1, R2 and R3 and voltage-stabilizing capacitors C1-C4. The voltage-dividing resistors R1, R2 and R3 are used to provide bias voltages to N1, N5, N6, P5, P6, P7 and P11, wherein N1, N5 and N6 are deep N-well MOS tubes, and P1, N1, N2, N3, N4 and R4 constitute a startup circuit; The gate of N2 is connected to the drain of N3, the gate of N4, and the negative electrode of R4, and the source of N2 is connected to the positive electrode of R4, so that when the BGR does not work normally, the gate voltage of N4 is quickly pulled up; The source of N4 and the source of N10 are connected to the ground GND, and the drain of N4 is connected to the drain of N10, the source of N6 and the substrate, which are used to pull BGR out of the dead zone.

2. A BGR circuit compatible with low voltage domain and super voltage domain according to claim 1, characterized in that: The positive electrode of R1 is connected to the power supply voltage AVDD, the negative electrode of R1 is connected to the positive electrode of R2, the gates of N1, N5, N6 and the positive electrode of C1, and the negative electrode of R2 is connected to the positive electrode of R3, the positive electrode of C2, the gates of P5, P6, P7 and P11.

3. A BGR circuit compatible with low voltage domain and super voltage domain according to claim 1, characterized in that: At a high voltage of 5.5V, N1, N5, N6, P5, P6, P7 and P11 work in the saturation region and function as voltage-dividing resistors. At a low voltage of 2.3V, N1, N5, N6, P5, P6, P7 and P11 work in the linear region and function as switching tubes, so that N1-N10 and P1-P13 will not be over-voltage at a high voltage of 5.5V. At a low voltage of 2.3V, P2, P3, P4, P8, P9, P10, P12, P13 and N7-N10 all work in the saturation region and will not enter the linear region, thereby reducing performance.

4. A BGR circuit compatible with low voltage domain and super voltage domain according to claim 1, characterized in that: N2 is an intrinsic tube used to provide high resistance.

5. The BGR circuit compatible with the low voltage domain and the super voltage domain according to claim 1, characterized in that: The substrates of all NMOS devices except the self-well device are grounded, and the substrates of all PMOS devices are connected to the power supply voltage.

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