Sleep chip power-on system in integrated chip and sleep chip startup method

Abstract

The present invention discloses a dormant chip power-on system and a dormant chip startup method in an integrated chip, comprising: an uninterruptible power chip and a dormant chip; the uninterruptible power chip comprises: a control chip and a power-on detection circuit, the control chip is provided with at least two data transmission terminals, each of which is connected to the first input terminal of the power-on detection circuit; the dormant chip comprises: a second NAND gate adder, an integrated clock gating and a dormant judgment circuit, each of which is connected to the input terminal of the second NAND gate adder, the output terminal of the second NAND gate adder is connected to the first input terminal of the dormant judgment circuit, the integrated clock gating input terminal is connected to the clock signal of the dormant chip itself, and the integrated clock gating output terminal is connected to the second input terminal of the dormant judgment circuit. The dormant chip power-on system and the dormant chip startup method in the integrated chip solve the problem of high integrated chip cost caused by power-on based on analog sub-chips in the prior art.

Description

Technical Field

[0001] The invention relates to an integrated chip, and in particular to a dormant chip power-on system and a dormant chip starting method in the integrated chip. Background Art

[0002] The integrated chip includes several sub-chips, and after all the sub-chips are connected, an integrated chip is obtained. Since the power-on time of each sub-chip is not certain, how to reduce the power-on time of the entire integrated chip is the main topic discussed in this application.

[0003] In the prior art, there are two methods for reducing the power-on time of the entire integrated chip, namely: software program-based power-on and analog chip-based power-on.

[0004] Software program power-on: Set the power-on waiting program in the sub-chip. Each sub-chip has a power-on waiting program. There are many power-on waiting programs in the integrated chip. Generally, a power-on waiting program waits for 50ms. Although the power-on waiting can be completed, the stabilization time of the sub-chip is different in different situations. If the sub-chip is powered on and stabilized quickly, other sub-chips need to continue to wait because they have not yet been powered on and stabilized, resulting in performance waste; if the power-on software system of the sub-chip has been completed, it is also possible that the waiting time is insufficient, resulting in the release preparation before the power-on is stable, causing the system to freeze.

[0005] Analog chip power-on: Power-on is achieved based on analog sub-chips. This solution can also achieve stable power-on of each sub-chip, but the disadvantages are obvious: analog sub-chips have large area and high cost. If there are multiple sub-chips in the chip that need power-on detection, the sub-chip area overhead will be the largest production cost, resulting in a high cost for the entire integrated chip. Summary of the invention

[0006] The present invention provides a dormant chip power-on system and a dormant chip startup method in an integrated chip, so as to solve the problem in the prior art that power-on is achieved based on analog sub-chips, resulting in high integrated chip costs.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] The invention firstly discloses a power-on system for a dormant chip in an integrated chip, comprising: an uninterruptible power chip and a dormant chip; the uninterruptible power chip comprises: a control chip and a power-on detection circuit, the control chip is provided with at least two data transmission ends, each of which is connected to a first input end of the power-on detection circuit; the dormant chip comprises: a second NAND gate adder, an integrated clock gating and a dormancy judgment circuit, each of which is connected to an input end of the second NAND gate adder, an output end of the second NAND gate adder is connected to a first input end of the dormancy judgment circuit, an integrated clock gating input end is connected to a clock signal of the dormant chip itself, an integrated clock gating output end is connected to a second input end of the dormancy judgment circuit, the dormancy judgment circuit is used for outputting a high level only when both the second NAND gate adder output end and the integrated clock gating output end output a high level; the output end of the dormancy judgment circuit is connected to the second input end of the power-on detection circuit, the power-on detection circuit is used for judging that the power-on is stable when both the data transmission end and the output end of the dormancy judgment circuit output a high level; the power-on detection circuit and the dormancy judgment circuit both adopt digital chips.

[0009] Preferably, the power-on detection circuit includes: a first NAND gate adder, an equality judgement device, and a state judgment circuit; the input end of the first NAND gate adder is the first input end of the power-on detection circuit, the output end of the first NAND gate adder is connected to the first input end of the equality judgement device, the second input end of the equality judgement device is the second input end of the power-on detection circuit, the output end of the equality judgement device is connected to the first input end of the state judgment circuit, and the output end of the state judgment circuit is connected to the input end of the control chip. The control output end of the control chip is connected to the second input end of the state judgment circuit.

[0010] Preferably, the sleep determination circuit is a data-triggered trigger.

[0011] Preferably, the second NAND gate adder is arranged in the middle of the sleep chip.

[0012] The present invention also discloses a dormant chip startup method, which is implemented based on the dormant chip power-on system in the integrated chip as described above.

[0013] The dormant chip startup method comprises the following steps:

[0014] S1, the integrated chip software power-on system starts, the dormant chip starts to power on, and the uninterrupted power chip enters the awake state;

[0015] S2, the non-stop power chip uses the characteristics of the dormant chip generating a clock signal and being able to receive data after being powered on to detect whether the dormant chip is powered on for the first time. If it is detected that the dormant chip has been powered on, step S3 is performed; if it is determined that the dormant chip has not been powered on, step S4 is performed and the output result is that the power-on is not completed;

[0016] S3, the non-power-off chip uses the characteristics of the dormant chip generating a clock signal and being able to receive data after being powered on to perform a second power-on detection on the dormant chip; if it is detected that the dormant chip has been powered on, step S4 is performed and the output result is that the power-on is completed; if it is determined that the dormant chip has not been powered on, step S4 is performed and the output result is that the power-on is not completed;

[0017] S4. End and output the result.

[0018] Preferably, both step S2 and step S3 include the following steps:

[0019] S21, the data transmission end of the control chip outputs the specified data group to the first input end of the power-on detection circuit and the second NAND gate adder input end, and at the same time, the sleep chip automatically generates a clock signal after powering on and adds it to the integrated clock gating input end;

[0020] S22, the second NAND gate adder outputs the added voltage value only after satisfying two conditions, and the added voltage value is associated with the specified data group, the two conditions being: 1. All NAND gates in the second NAND gate adder are powered on; 2. The second NAND gate adder receives all data in the specified data group; when the integrated clock gating receives the automatic generation of the clock signal after the dormant chip is powered on, it outputs a high level; when the integrated clock gating does not receive the automatic generation of the clock signal after the dormant chip is powered on, it outputs a low level;

[0021] S23, the sleep determination circuit receives the added voltage value and the output of the integrated clock gating, and the sleep determination circuit is used to output the added voltage value only when the integrated clock gating outputs a high level;

[0022] S24, the power-on detection circuit is used to process the directly received designated data group to obtain a processed voltage value, and compare the added voltage value with the processed voltage value to determine whether the added voltage value from the sleep chip is consistent with the processed voltage value; if they are consistent, it is determined that the sleep chip has been powered on; otherwise, it is determined that the sleep chip has not been powered on; and the determination result is returned to the control chip;

[0023] S25. The control chip determines whether the dormant chip has been powered on according to the return result of the power-on detection circuit.

[0024] Preferably, step S24 includes the following steps:

[0025] S241, the first NAND gate adder adds the received designated data group to obtain a processed voltage value;

[0026] S242, the equality judgement device judges whether the processed voltage value is equal to the added voltage value from the sleep chip; if they are equal, it outputs True, and if they are not equal, it outputs False;

[0027] S243, the state judgment circuit receives the judgment result;

[0028] S244, the status judgment circuit returns the judgment result to the control chip.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1) In the present application, the control chip, power-on detection circuit, second NAND gate adder, integrated clock gating and sleep judgment circuit (the control chip, power-on detection circuit, second NAND gate adder, integrated clock gating and sleep judgment circuit are sub-chips in the prior art) are all digital chips, which avoids the use of analog sub-chips in the prior art, resulting in a larger volume of the entire integrated chip, and also reduces the cost of the entire integrated chip; it avoids relying on the power-on program to wait for power-on and causing the system to freeze;

[0031] 2) This application divides each sub-chip in the integrated chip into an uninterruptible power chip and a dormant chip, that is, the uninterruptible power chip is always powered on, and the dormant chip is powered off when not working, thereby reducing energy consumption. When working, the overall power-on system of the integrated chip is started, that is, the power-on begins. The difference from the power-on procedure in the prior art is that there is no power-on wait. After the power-on system is started, the uninterruptible power chip changes from the original waiting state to the awake state, and the specified data group is sent to the dormant chip through the control chip in the uninterruptible power chip. After power-on, the second NAND gate adder in the dormant chip adds the specified data group to obtain the added voltage value. At the same time, the integrated clock gating in the dormant chip also receives the clock signal automatically generated after the dormant chip is powered on. The dormant judgment circuit performs logical judgment to realize that the added voltage value can be sent out if and only if the clock signal is generated after the dormant chip is powered on. At the same time, there are many NAND gates, many NAND gates are distributed in different positions in the sleep chip. Due to the long circuit, the power-on time is different, so the power-on time of each NAND gate is different, but all NAND gates need to be powered on successfully to output the correct added voltage value. Therefore, it can ensure that the sleep chip is powered on stably before the correct added voltage value can be output from the sleep judgment circuit, ensuring the accuracy of detecting the power-on stability of the sleep chip. When the sleep judgment circuit outputs the added voltage value, it is compared with the directly received processed voltage value in the uninterruptible power chip to judge the accuracy of the added voltage value. When it is correct, it can be judged that the power-on is stable, and then returned to the uninterruptible power chip. The uninterruptible power chip can perform the Release reset operation, so that subsequent operations can proceed smoothly. It can be seen from the above that the sleep chip needs to automatically generate a clock signal and all the NAND gates in the second NAND gate adder are powered on before the accurate added voltage value can be output, thereby detecting whether all parts of the sleep chip have been powered on;

[0032] 3) Due to the one-time detection, when the power-on is unstable and all the NAND gates are working, it is possible to output the accurate added voltage value. Therefore, two detections are required, and the specified data groups with different values ​​are output. Although step S2 and step S3 are the same in terms of steps, the specified data groups with different values ​​are transmitted, thereby avoiding receiving the accurate added voltage value due to a coincidence. The two detections improve the accuracy of the detection and reduce the probability of error.

[0033] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The schematic diagram of the circuit of the power-on system of the sleep chip in the integrated chip.

[0035] Figure numerals: uninterruptible power chip 1, control chip 11, first NAND gate adder 12, equality judgement circuit 13, state judgment circuit 14, sleep chip 2, second NAND gate adder 21, integrated clock gating 22, sleep judgment circuit 23. DETAILED DESCRIPTION

[0036] In order to make the technical means, creative features, objectives and functions achieved by the present invention clearer and easier to understand, the present invention is further explained below in conjunction with the accompanying drawings and specific implementation methods.

[0037] like Figure 1 As shown, this embodiment discloses a power-on system for a sleep chip in an integrated chip, including: an uninterruptible power chip 1 and a sleep chip 2; the uninterruptible power chip 1 includes: a control chip 11 and a power-on detection circuit, the control chip 11 is provided with at least two data transmission terminals, each of which is connected to a first input terminal of the power-on detection circuit; the sleep chip 2 includes: a second NAND gate adder 21, an integrated clock gating 22 and a sleep judgment circuit 23, each of which is connected to an input terminal of the second NAND gate adder 21, and an output terminal of the second NAND gate adder 21 is connected to a first input terminal of the sleep judgment circuit 23. An input end, the input end of the integrated clock gating 22 is connected to the clock signal of the sleep chip 2 itself, and the output end of the integrated clock gating 22 is connected to the second input end of the sleep judgment circuit 23. The sleep judgment circuit 23 is used to output a high level only when the output end of the second NAND gate adder 21 and the output end of the integrated clock gating 22 both output a high level; the output end of the sleep judgment circuit 23 is connected to the second input end of the power-on detection circuit, and the power-on detection circuit is used to judge that the power-on is stable when the data transmission end and the output end of the sleep judgment circuit 23 both output a high level; the power-on detection circuit and the sleep judgment circuit 23 both use digital chips.

[0038] The power-on detection circuit includes: a first NAND gate adder 12, an equality judgement 13 and a state judgment circuit 14; the input end of the first NAND gate adder 12 is the first input end of the power-on detection circuit, the output end of the first NAND gate adder 12 is connected to the first input end of the equality judgement 13, the second input end of the equality judgement 13 is the second input end of the power-on detection circuit, the output end of the equality judgement 13 is connected to the first input end of the state judgment circuit 14, and the output end of the state judgment circuit 14 is connected to the input end of the control chip 11. The first NAND gate adder 12 directly receives the specified data group sent by the control chip 11 in the uninterruptible power chip 1 where it is located, and performs addition operation processing. Then, the first NAND gate adder 12 composed of multiple NAND gates arranged in the uninterruptible power chip 1 can also detect whether the power supply is normal at all places of the uninterruptible power chip, and also realizes the self-detection of the uninterruptible power chip 1. The control output end of the control chip 11 is connected to the second input end of the state judgment circuit 14.

[0039] The sleep determination circuit 23 is a data-triggered trigger and implements logic processing behavior.

[0040] The second NAND gate adder 21 is arranged in the middle of the sleep chip 2. In the integrated chip, the closer to the middle, the longer the power-on time is, so the second NAND gate adder 21 is arranged in the middle of the sleep chip 2, thereby improving the accuracy of power-on detection.

[0041] When making a design drawing, it is necessary to constrain the positions of the first NAND gate adder 12 and the second NAND gate adder 21 in the present application to avoid being optimized. Because in the design concept, the first NAND gate adder 12 and the second NAND gate adder 21 are redundant and cannot be displayed normally after being optimized, while the first NAND gate adder 12 and the second NAND gate adder 21 in the present application are necessary and are the focus of the design.

[0042] This embodiment discloses a method for starting a dormant chip. The method for starting a dormant chip is implemented based on the dormant chip power-on system in the integrated chip as described in the embodiment.

[0043] The dormant chip startup method comprises the following steps:

[0044] S1, the integrated chip software power-on system starts, the dormant chip starts to power on, and the uninterrupted power chip enters the awake state;

[0045] S2, the non-stop power chip uses the characteristics of the dormant chip generating a clock signal and being able to receive data after being powered on to detect whether the dormant chip is powered on for the first time. If it is detected that the dormant chip has been powered on, step S3 is performed; if it is determined that the dormant chip has not been powered on, step S4 is performed and the output result is that the power-on is not completed;

[0046] S3, the non-power-off chip uses the characteristics of the dormant chip generating a clock signal and being able to receive data after being powered on to perform a second power-on detection on the dormant chip; if it is detected that the dormant chip has been powered on, step S4 is performed and the output result is that the power-on is completed; if it is determined that the dormant chip has not been powered on, step S4 is performed and the output result is that the power-on is not completed;

[0047] S4. End and output the result.

[0048] Preferably, both step S2 and step S3 include the following steps:

[0049] S21, the data transmission end of the control chip outputs the specified data group to the first input end of the power-on detection circuit and the second NAND gate adder input end, and at the same time, the sleep chip automatically generates a clock signal after powering on and adds it to the integrated clock gating input end;

[0050] S22, the second NAND gate adder outputs the added voltage value only after satisfying two conditions, and the added voltage value is associated with the specified data group, the two conditions being: 1. All NAND gates in the second NAND gate adder are powered on; 2. The second NAND gate adder receives all data in the specified data group; when the integrated clock gating receives the automatic generation of the clock signal after the dormant chip is powered on, it outputs a high level; when the integrated clock gating does not receive the automatic generation of the clock signal after the dormant chip is powered on, it outputs a low level;

[0051] S23, the sleep determination circuit receives the added voltage value and the output of the integrated clock gating, and the sleep determination circuit is used to output the added voltage value only when the integrated clock gating outputs a high level;

[0052] S24, the power-on detection circuit is used to process the directly received designated data group to obtain a processed voltage value, and compare the added voltage value with the processed voltage value to determine whether the added voltage value from the sleep chip is consistent with the processed voltage value; if they are consistent, it is determined that the sleep chip has been powered on; otherwise, it is determined that the sleep chip has not been powered on; and the determination result is returned to the control chip;

[0053] S25. The control chip determines whether the dormant chip has been powered on according to the return result of the power-on detection circuit.

[0054] Preferably, step S24 includes the following steps:

[0055] S241, the first NAND gate adder adds the received designated data group to obtain a processed voltage value;

[0056] S242, the equality judgement device judges whether the processed voltage value is equal to the added voltage value from the sleep chip; if they are equal, it outputs True, and if they are not equal, it outputs False;

[0057] S243, the state judgment circuit receives the judgment result;

[0058] S244, the status judgment circuit returns the judgment result to the control chip.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A dormant chip power-on system in an integrated chip, characterized in that: include: Uninterruptible power chip and sleep chip; The uninterruptible power chip comprises: a control chip and a power-on detection circuit, wherein the control chip is provided with at least two data transmission terminals, each of which is connected to a first input terminal of the power-on detection circuit; The sleep chip comprises: a second NAND gate adder, an integrated clock gating and a sleep judgment circuit, each data transmission end is connected to the input end of the second NAND gate adder, the output end of the second NAND gate adder is connected to the first input end of the sleep judgment circuit, the integrated clock gating input end is connected to the clock signal of the sleep chip itself, the integrated clock gating output end is connected to the second input end of the sleep judgment circuit, and the sleep judgment circuit is used to output a high level only when the output end of the second NAND gate adder and the integrated clock gating output end both output a high level; The output end of the sleep judgment circuit is connected to the second input end of the power-on detection circuit. The power-on detection circuit is used to judge whether the power-on is stable when the data transmission end and the output end of the sleep judgment circuit both output high levels. Both the power-on detection circuit and the sleep judgment circuit use digital chips.

2. The power-on system for a dormant chip in an integrated chip according to claim 1, characterized in that: The power-on detection circuit includes: a first NAND gate adder, an equality judgement device and a state judgment circuit; The input end of the first NAND gate adder is the first input end of the power-on detection circuit, the output end of the first NAND gate adder is connected to the first input end of the equality judgement, the second input end of the equality judgement is the second input end of the power-on detection circuit, the output end of the equality judgement is connected to the first input end of the state judgment circuit, the output end of the state judgment circuit is connected to the input end of the control chip, and the control output end of the control chip is connected to the second input end of the state judgment circuit.

3. The power-on system for a dormant chip in an integrated chip according to claim 2, characterized in that: The sleep determination circuit is a data-triggered trigger.

4. The power-on system for a dormant chip in an integrated chip according to claim 2 or 3, characterized in that: The second NAND gate adder is arranged in the middle of the sleep chip.

5. A method for starting a dormant chip, characterized in that: The dormant chip startup method is implemented based on the dormant chip power-on system in the integrated chip according to any one of claims 1 to 4, The dormant chip startup method comprises the following steps: S1, the integrated chip software power-on system starts, the dormant chip starts to power on, and the uninterrupted power chip enters the awake state; S2, the non-stop power chip uses the characteristics of the dormant chip generating a clock signal and being able to receive data after being powered on to detect whether the dormant chip is powered on for the first time. If it is detected that the dormant chip has been powered on, step S3 is performed; if it is determined that the dormant chip has not been powered on, step S4 is performed and the output result is that the power-on is not completed; S3, the non-power-off chip uses the characteristics of the dormant chip generating a clock signal and being able to receive data after being powered on to perform a second power-on detection on the dormant chip; if it is detected that the dormant chip has been powered on, step S4 is performed and the output result is that the power-on is completed; if it is determined that the dormant chip has not been powered on, step S4 is performed and the output result is that the power-on is not completed; S4. End and output the result.

6. The method for starting a dormant chip according to claim 5, characterized in that: Step S2 and step S3 both include the following steps: S21, the data transmission end of the control chip outputs the specified data group to the first input end of the power-on detection circuit and the second NAND gate adder input end, and at the same time, the sleep chip automatically generates a clock signal after powering on and adds it to the integrated clock gating input end; S22, the second NAND gate adder outputs the added voltage value only after satisfying two conditions, and the added voltage value is associated with the specified data group, the two conditions being:

1. All NAND gates in the second NAND gate adder are powered on; 2. The second NAND gate adder receives all data in the specified data group; when the integrated clock gating receives the automatic generation of the clock signal after the dormant chip is powered on, it outputs a high level; when the integrated clock gating does not receive the automatic generation of the clock signal after the dormant chip is powered on, it outputs a low level; S23, the sleep determination circuit receives the added voltage value and the output of the integrated clock gating, and the sleep determination circuit is used to output the added voltage value only when the integrated clock gating outputs a high level; S24, the power-on detection circuit is used to process the directly received designated data group to obtain a processed voltage value, and compare the added voltage value with the processed voltage value to determine whether the added voltage value from the sleep chip is consistent with the processed voltage value; If they are consistent, it is determined that the dormant chip has been powered on; Otherwise, it is determined that the dormant chip has not been powered on; and the determination result is returned to the control chip; S25. The control chip determines whether the dormant chip has been powered on according to the return result of the power-on detection circuit.

7. The method for starting a dormant chip according to claim 6, characterized in that: Step S24 includes the following steps: S241, the first NAND gate adder adds the received designated data group to obtain a processed voltage value; S242, the equality judgement device judges whether the processed voltage value is equal to the added voltage value from the sleep chip; If they are equal, output True; if they are not equal, output False; S243, the state judgment circuit receives the judgment result; S244, the status judgment circuit returns the judgment result to the control chip.

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