Self-optimization of data placement in memory or storage system

Abstract

The invention relates to self-optimization of data placement in a memory or storage system. Systems and methods including a memory and a processing device operably coupled to the memory are disclosed. The processing device may perform operations including: identifying a set of logical addresses associated with data in one or more blocks of a first type stored on the memory device; determining a class of time metrics associated with the set of logical addresses, wherein the class of time metrics is associated with a corresponding range of predicted update characteristics of the data; identifying a set of blocks of a second type based on the time metric class, where a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell exceeding the first number of bits per cell; and moving the data to the set of identified chunks.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to self-optimization of data placement in a memory or storage system. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, nonvolatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a system comprising: a memory device; and a processing device operably coupled to the memory device to perform operations comprising: identifying a set of logical addresses associated with data in one or more blocks of a first type stored on the memory device; determining a time metric class associated with the set of logical addresses, wherein the time metric class is associated with a corresponding range of predicted update characteristics of the data; identifying a set of blocks of a second type based on the time metric class, wherein a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell exceeding the first number of bits per cell; and moving the data to the identified set of blocks.

[0004] On the other hand, the present disclosure further provides a method, comprising: identifying, by a processing device, a set of logical addresses associated with data in one or more blocks of a first type stored on the memory device; determining a time metric class associated with the set of logical addresses, wherein the time metric class is associated with a corresponding range of predicted update characteristics of the data; identifying a set of blocks of a second type based on the time metric class, wherein a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell exceeding the first number of bits per cell; and moving the data to the identified set of blocks.

[0005] On the other hand, the present disclosure further provides a non-transitory computer-readable storage medium, which includes instructions that, when executed by a processing device operably coupled to a memory, perform operations including the following: identifying a set of logical addresses associated with data in one or more blocks of a first type stored on the memory device; determining a time metric class associated with the set of logical addresses, wherein the time metric class is associated with a corresponding range of predicted update characteristics of the data; identifying a set of blocks of a second type based on the time metric class, wherein a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell exceeding the first number of bits per cell; and moving the data to the identified set of blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figures 2 to 3 An example system architecture including a memory device using a data placement component according to some embodiments of the present disclosure is described.

[0009] Figure 4 Example data placement according to aspects of the present disclosure is described.

[0010] Figure 5 is a flowchart of an example method for training a machine learning model for use in data placement according to some embodiments of the present disclosure.

[0011] Figure 6 is a flowchart of an example method of using a trained machine learning model for data placement according to some embodiments of the present disclosure.

[0012] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to self-optimization of data placement in a memory or storage system. A memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device, that stores data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. Each of the memory devices may include one or more memory cell arrays. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states related to the number of bits stored. The logical state may be represented by a binary value such as "0" and "1" or a combination of such values.

[0015] Various data operations may be performed by the memory subsystem. The data operation may be an operation initiated by the host. For example, the host system may initiate a data operation (e.g., write, read, erase, etc.) on the memory subsystem. The host system may send an access request (e.g., a write command, a read command) to the memory subsystem, for example, to store data on a memory device at the memory subsystem and to read data from a memory device on the memory subsystem. The data to be read or written as specified by the host request is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated with the host data by the host system. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword parity data), data version (e.g., for distinguishing the age of the written data), valid bitmap (which LBA or logical transfer unit contains valid data), etc.

[0016] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. For some types of non-volatile memory devices (such as NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells storing data bits. For some memory devices (such as NAND devices), a block is the smallest area that can be erased. A block may contain valid data, invalid data, or no data. Invalid data is data that is marked as obsolete as a new version of data is stored on the memory device. Invalid data includes data that was previously written but is no longer associated with a valid logical address (such as a logical address referenced by a host system in a physical to logical (P2L) mapping table). Valid data is the latest version of such data stored on the memory device. The memory subsystem may mark data as invalid based on information received, for example, from an operating system.

[0017] The memory subsystem controller may perform operations for media management operations such as wear leveling, refresh, trash collection, scrubbing, etc. A block may have some pages containing valid data and some pages containing invalid data. To avoid waiting for all pages in a block to have invalid data in order to erase and reuse the block, an algorithm referred to hereinafter as "trash collection" may be invoked to allow the block to be erased and released as a free block for subsequent write operations. Trash collection is a set of media management operations that include, for example: selecting a block containing valid and invalid data; selecting a page in a block containing valid data; copying the valid data to a new location (e.g., a free page in another block); marking the data in a previously selected page as invalid; and erasing the selected block. Trash collection hereinafter involves selecting a block, rewriting valid data from the selected block to another block, and erasing all invalid data and valid data stored at the selected block. Valid data from multiple selected blocks may be copied to a smaller number of other blocks, and then the selected block may be erased. Thus, the number of erased blocks may be increased, making more blocks available for storing subsequent data from the host system. The memory subsystem may implement garbage collection operations to maintain or generate a contiguous supply of free data blocks for the host application to use for storing data.

[0018] As described above, obsolete collection is an operation that copies valid data from one data block to another data block, and the source data block (e.g., the data block from which the valid data was copied) can then be erased and released as a free block for subsequent host writes. This additional rewriting of valid data in the data block during the obsolete collection operation results in write amplification. Write amplification can reduce the operating life of the memory subsystem and affect its performance.

[0019] The write amplification factor (WAF) is the ratio of the number of write operations occurring within the memory subsystem compared to the number of write operations received from the host system. For example, a WAF of 5 indicates that for each write operation received from the host system, the memory subsystem performs four additional back-end write operations related to media management. In addition, data that exhibits a lower value of a selected time metric (e.g., referred to as low time metric data) may be stored on the same memory block as data that exhibits a higher value of a selected time metric value (e.g., high time metric or medium time metric data). The time metric may reflect, for example, the time that has passed since the data was last accessed, the frequency of update of the data, etc. Due to changes to the high time metric data located on the same block, the unchanged low time metric data located on the same block as the high time metric data may be copied to new blocks multiple times through the discarded item collection operation. Since the low time metric data is less likely to change, repeatedly writing and rewriting the low time metric data during the discarded item collection operation increases the WAF of the memory subsystem.

[0020] A memory device may include one or more memory cell arrays, such as a single-level cell (SLC) memory, a multi-level cell (MLC) memory, a three-level cell (TLC) memory, or a four-level cell (QLC) memory. Each type may have a different data density, which corresponds to the amount of data (e.g., data bits) that can be stored per memory cell of the memory device. Using an example of a flash-based memory, a four-level cell (QLC) can store four data bits, while a single-level cell (SLC) can store one data bit. Therefore, a memory device including a QLC memory cell will have a higher data density than a memory device including an SLC memory cell. In addition, each type of memory cell may have a different endurance for storing data. The endurance of a memory device is the number of write operations or the number of program / erase operations performed on the memory cell before the data can no longer be reliably stored at the memory cell of the memory device. For example, an SLC memory cell having a lower data density may have a higher endurance threshold than a QLC memory cell having a higher data density.

[0021] Some memory devices use certain types of high-density memory cells, such as quad-level cell (QLC) memory cells that store four bits of data in each memory cell. QLC memory is particularly well suited for read-intensive workloads common in data center applications, where data is typically generated once and then read periodically to perform calculations and analysis. The memory subsystem can allocate a set of SLC blocks as a cache to initially program the SLC blocks with data to be written to the QLC blocks. Thereafter, the data can be moved from the SLC cache to the QLC memory for long-term storage.

[0022] Aspects of the present disclosure improve the efficiency of memory access operations by implementing a system capable of determining a time metric class associated with data cached in an SLC block of a memory device and moving the data to a group of non-SLC (e.g., QLC) blocks of the memory device according to the time metric class of the data. The time metric class reflects the update characteristics of the data (e.g., update frequency) and may be associated with a corresponding range of predicted update characteristics of the data (e.g., update frequency). In one example, address information (e.g., LBA) may be used to represent the data, and the time metric class of the data may be marked as a time metric class according to the update frequency of the data stored at the address (e.g., a frequency above a threshold or a frequency below a threshold). In some embodiments, the time metric class may reflect the time elapsed since the most recent update to the data. In one example, the time metric classification is binary, including a short time metric class and a long time metric class. The short time metric class may be associated with an update frequency of data exceeding a threshold (e.g., high frequency), while the long time metric class may be associated with an update frequency of data not exceeding a threshold (e.g., low frequency). Alternatively or additionally, the short time metric class may be associated with elapsed times below a threshold, while the long time metric class may be associated with elapsed times above a threshold.

[0023] As another example, the time metric class is one of a plurality of classes, including a short time metric class, one or more medium time metric classes, and a long time metric class. The short time metric class may be associated with a data update frequency exceeding a first threshold, the long time metric class may be associated with a data update frequency not exceeding a second threshold, and the one or more medium time metric classes may be associated with a data update frequency falling between the first threshold and the second threshold. Alternatively or in addition, the short time metric class may be associated with an elapsed time below a first threshold, the long time metric class may be associated with an elapsed time above a second threshold, and the one or more medium time metric classes may be associated with an elapsed time falling between the first threshold and the second threshold.

[0024] A group of non-SLC blocks of a memory device refers to a set of contiguous non-SLC blocks used to store data in the same time metric class, and in some embodiments, may be referred to as a super block. Although data movement is described as from an SLC block to a non-SLC block, data movement may occur from a first type of block to a second type of block, wherein the first type of block includes memory cells having a first number of bits per cell, and the second type of block includes memory cells having a second number of bits per cell that exceeds the first number of bits per cell. For example, data movement may occur from an SLC block to at least one of an MLC, TLC, QLC, etc. block. As another example, data movement may occur from an MLC block to at least one of a TLC, QLC, etc. block.

[0025] The data stored in the SLC blocks may be specific to the type of workload, such as the workload experienced by a hard disk drive (HDD), the workload experienced by a solid state drive (SSD), the workload experienced by a dynamic random access memory (DRAM), etc. The type of workload refers to a workload that follows a write / read pattern suitable for a specific type of memory device. The type of memory device may depend on the service purpose of the memory device to the host system. The same type of workload includes workloads that follow a write / read pattern suitable for the same type of memory device. The workload experienced by the HDD may include, for example, read-intensive workloads in data center applications, where data is typically generated once and then read regularly to perform calculations and analysis. The workload experienced by the SSD may include a write-intensive workload, where data is typically updated (e.g., overwritten) regularly. The workload experienced by the DRAM may include write-intensive and read-intensive workloads, such as workloads in the main memory of the host system. The workload may also include workloads transmitted between different types of memory devices through a compute express link (CXL) bus.

[0026] Determining the time metric class may be performed by a trained machine learning model (MLM). The MLM may be trained using historical data of a workload type that matches the workload type of the data to be used for inference. For example, to determine an update frequency classification of data in a workload experienced by a HDD, the MLM is trained using historical data of the workload experienced by the HDD. As another example, to determine an update frequency classification of data in a workload experienced by an SSD, the MLM is trained using historical data of the workload experienced by the SSD.

[0027] Specifically, a data placement component coupled to a memory device may obtain a set of logical addresses (e.g., LBA ranges) of data cached in an SLC block of the memory device. The data placement component may feed the address information to a trained MLM, which may generate a corresponding time metric class associated with the address. The memory device may then store the data from the SLC block in a group (e.g., a super block) of non-SLC blocks according to the corresponding time metric class. For example, assuming that a first LBA range is determined to be associated with a short time metric class, a second LBA range is determined to be associated with a long time metric class, and a third LBA range is determined to be associated with a short time metric class, the memory device may store data of the first LBA range and data of the third LBA range in the same group of non-SLC blocks while storing data of the second LBA in a different group of non-SLC blocks. As another example, assuming that a first group of LBAs are determined to be associated with a short time measurement class, a second group of LBAs are determined to be associated with a medium time measurement class, and a third group of LBAs are determined to be associated with a long time measurement class, then the memory device may store data from the first group of LBAs, data from the second group of LBAs, and data from the third group of LBAs in different groups of non-SLC blocks.

[0028] In order to train the MLM, historical data may be collected. In some embodiments, a tiered storage stack is used to collect training data. For example, the tiered storage stack may include a first tier memory device such as a DRAM, a second tier memory device such as an SSD, and a third tier memory device such as an HDD. Specifically, data of a specific workload type (e.g., a workload experienced by the HDD) is supplied to the tiered storage stack, and the tiered storage stack performs storage tiering by moving data across tiers to relocate low time metric data to a lower cost, higher capacity storage device, such as from a first tier memory device to a second tier memory device and / or from a second tier memory device to a third tier memory device. For example, a data placement component may track data movement from a second tier memory device to a third tier memory device, such as by recording metadata (e.g., address information) of data retained in the second tier memory device and data moved to the third tier memory device. In this case, data that has been moved from the second tier memory device to the third tier memory device may represent low time metric data and may be annotated as such, while data retained in the second tier memory device may represent high time metric data and may be annotated as such. The data placement component can use the tracked data described above to generate training data that includes training inputs and expected training outputs. The training inputs include LBAs of the tracked data, and the training outputs include annotation metadata indicating the classes of the LBAs of the tracked data. The data placement component can provide the training data to the MLM, and the MLM can classify the LBAs and compare the classifications to the annotation metadata to determine parameters for the MLM.

[0029] Advantages of the present disclosure include improving data placement of a memory subsystem by grouping data stored in SLC blocks according to access frequency so that data placed in non-SLC (e.g., QLC) blocks is optimized. Data placement optimization can be specific to a workload or customer. This can result in improved performance of the memory subsystem and reduced write amplification. In addition, this can increase the life of the memory subsystem. Moreover, data placement optimization can be applicable to systems using a tiered storage stack. Although embodiments are described using certain memory cells of NAND flash memory, aspects of the present disclosure can be applied to other types of memory subsystems and other types of memory cells (e.g., MLC, TLC, etc.).

[0030] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or a combination thereof.

[0031] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0032] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0033] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0034] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0035] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0036] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices such as memory device 140 may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory devices, such as memory device 130, include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0039] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) have been described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0040] The memory subsystem controller 115 (or, for simplicity, the controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0041] The memory subsystem controller 115 may be a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0042] In some embodiments, local memory 119 may include memory registers that store memory pointers, extracted data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0043] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0044] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0045] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device that includes a raw memory device 130 with control logic on the die (e.g., the local controller) and a controller for media management within the same memory device package (e.g., the memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0046] The memory subsystem 110 includes a data placement component 113 that can place data associated with a workload to a storage device that represents an optimized storage device for the workload. In some embodiments, the memory subsystem 110 includes at least a portion of the data placement component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the data placement component 113 is part of a host system 120, an application, or an operating system. The data placement component 113 is described in more detail below.

[0047] Figure 2 An example system architecture 200 including a host server 220 using a memory subsystem 210 is illustrated according to some embodiments of the present disclosure. The system architecture 200 includes the memory subsystem 210, one or more host servers 220, a memory device 255, and a data placement component 113. In some implementations, the memory subsystem 210 is the same as the memory subsystem 110. In some implementations, the host server 220 is the same as the host system 120. In some implementations, the memory device 255 is of a type that can be used to replace a third tier memory device (e.g., third tier memory device 250) for certain workloads.

[0048] The host server 220 may be a desktop computer, a laptop computer, a smart phone, a tablet computer, or any suitable computing device capable of providing a host service through different user interfaces (including applications, websites). In some embodiments, the host server 220 provides a workload 225 suitable for a type of memory device (e.g., HDD, SSD, or DRAM).

[0049] The memory subsystem 210 may perform storage tiering and generate tracked data 245 by tracking the movement of data through the storage tiers using the workload 225. Storage tiering refers to the process of moving each data object (or file) to the most appropriate storage tier based on its access frequency. For example, the memory subsystem 210 may include a first tier memory device 230, a second tier memory device 240, and a third tier memory device 250. When deciding the tier to store data, the memory subsystem 210 may consider access patterns including access frequencies. In one example, high time metric data includes data accessed at a frequency exceeding a first threshold frequency (i.e., frequently), low time metric data includes data accessed at a frequency below a second threshold frequency (e.g., infrequently), and medium time metric data includes data accessed at a frequency falling between the first threshold frequency and the second threshold frequency. In one example, high time metric data needs to be stored on faster storage devices, such as solid state drives (SSDs), medium time metric data can be stored on slower storage devices, such as hard drives, and low time metric data can be stored on the slowest storage devices, such as cheap object storage services. Figure 2 In the example of , high time metric data may be stored on a first tier memory device 230 such as a DRAM, medium time metric data may be stored on a second tier memory device 240 such as an SSD, and low time metric data may be stored on a third tier memory device 250 such as an HDD. Figure 2 Specific types of memory devices are illustrated in the memory subsystem 210 in FIG. 1 , but the memory subsystem 210 may include one or more CXL memory systems. CXL memory devices refer to memory devices attached via a CXL bus and may provide additional bandwidth and capacity to the host processor. For example, the first-tier memory device 230 may be a DRAM attached via a CXL bus.

[0050] The memory subsystem 210 allows data to be placed according to the storage tier by moving data across tiers (e.g., by relocating low-time metric data to lower-cost, higher-capacity storage devices). For example, a new file may be created in a hot storage tier (e.g., first-tier storage device 230), and if the memory subsystem 210 determines that the file has not been accessed for a period of time, the file is moved to a warm storage tier (e.g., second-tier storage device 240), and if the file remains unaccessed for a long time, the file is eventually moved to a cold storage tier (e.g., third-tier storage device 250).

[0051] In some embodiments, the data involved in data placement may be specific to a customer's workload, and the workload may be associated with an object store, a cloud store, an all-flash array, a software defined storage (SDS) capacity tier, or various rates of data ingestion and data analysis (e.g., an ingest rate that is faster than the analysis rate). Figure 2 In an example of , workload 225 may be an HDD-type workload, and memory subsystem 210 may move some data associated with workload 225 from first tier memory device 230 to second tier memory device 240 and from second tier memory device 240 to third tier memory device 250. Specifically, a first set of data associated with workload 225 may be accessed at a frequency lower than a first threshold frequency, and memory subsystem 210 may move the first set of data from first tier memory device 230 to second tier memory device 240. After a period of time, the first set of data may be accessed at a frequency lower than a second threshold frequency, the second threshold frequency being lower than the first threshold frequency, and memory subsystem 210 may move the first set of data from second tier memory device 240 to third tier memory device 250. In this example, the first set of data is tracked as data 245 and may be used to train a machine learning model (MLM).

[0052] The data placement component 113 can perform storage optimization using machine learning (e.g., trained MLM) to effectively optimize storage for a specific customer environment containing a workload. Figure 2 In an example of , the data placement component 113 can track the data 245, use the tracked data 245 to train the MLM, such as by the method 500, and implement the trained MLM, such as by the method 600. In some embodiments, the data 245 can include an LBA (or LBA range) and information indicating whether the LBA has been overwritten and moved to the third-level memory device 250. In some embodiments, the data 245 can include an LBA (or LBA range) and information indicating whether the LBA corresponds to a short-time metric class or a long-time metric class. In some embodiments, the data 245 can be processed with domain knowledge (e.g., by Figure 3A feature making component 316 in the MLM makes features to be fed into the MLM. In some embodiments, the made features may include the size of the data written to the LBA. For example, assuming that the LBA is LBA 1, where the block size addressed by one LBA is in units of unit block size, and the size of the data written to LBA 1 may be 6 block sizes, then LBA 1 to LBA 7 may be annotated as corresponding to the same time measurement class. In some embodiments, the made features may include time information about writes and / or overwrites associated with the LBA. For example, assuming that the LBA is LBA 1, at time T1, LBA 1 has been written, and at time T2, LBA 1 has been overwritten, then the time difference between T1 and T2 can be used to determine whether LBA 1 corresponds to a short time measurement class or a long time measurement class.

[0053] The data placement component 113 may include a training engine (e.g., Figure 3 362 in the training engine 362) to train one or more MLMs and save the trained MLMs (e.g., Figure 3 MLM 314 in). The term engine herein refers to a hardware machine or software component used to perform operations associated with a specific (e.g., training, annotation, interface, etc.) function. An MLM group may refer to a model artifact created using training data that includes training inputs and corresponding target outputs (correct answers to the corresponding training inputs). The trained MLMs may be stored by inserting them into a flash translation layer (FTL) as migration logic. When the FTL provides a mapping of LBAs to physical addresses of a memory device, the migration logic may modify the mapping of LBAs to physical addresses of a memory device when data is moved from an SLC block to a QLC block, as described below. In one embodiment, the data placement component 113 may be included in the memory subsystem 210. In one embodiment, the data placement component 113 may be included in the memory device 255. Figure 3 Describe the details of the machine learning model.

[0054] Although some specifications are described above, it should be understood that according to aspects of the present disclosure, the number and type of models used and the arrangement of such models can be modified to achieve the same or similar end results. In some embodiments, one or more models are used to perform one or more optimization tasks, for example, optimization for different workloads and / or different memory devices. Each task can be performed by a separate model. Alternatively, a single model can perform each task or a subset of tasks. Additionally or alternatively, different models can be used to perform different combinations of tasks.

[0055] The data placement component 113 may communicate with the memory device 255 regarding the trained MLM. The data placement component 113 may communicate with the memory device 255 for implementing the trained MLM. Specifically, the input data 253 may correspond to a specific workload, such as similar to the workload 255, and the memory device 255 may store the input data 253 in one or more SLC blocks 254. The memory device 255 may obtain the LBAs of the input data 253 stored in the one or more SLC blocks 254. The memory device 255 may apply the LBAs of the input data 253 to the trained MLM provided by the data placement component 113. The memory device 255 may receive a respective class associated with each of the LBAs of the input data 253, and group the input data 253 in view of the respective class. The memory device 255 may move the data from the one or more SLC blocks 254 to the one or more QLC blocks 246 by storing the input data 253 in a group of the one or more QLC blocks 246 according to the respective class of the LBA. A logical-to-physical (L2P) mapping data structure (e.g., an L2P mapping table) maintains a one-to-one mapping for a plurality of logical addresses to corresponding physical addresses (e.g., physical locations of SLC and / or QLC blocks). Thus, prior to programming a QLC block, the L2P mapping table will contain the physical addresses of the SLC blocks storing data to be written to the QLC blocks. Once the QLC blocks are programmed, the L2P mapping table is updated to replace the physical addresses of the SLC blocks with the physical addresses of the QLC blocks. In some implementations, the memory device 255 may be used to replace the initially used third level memory device 250. Figure 4 Details regarding placement of data from one or more SLC blocks 254 to one or more QLC blocks 246 are described.

[0056] Figure 3 An example system architecture 300 is illustrated that includes a memory device 255 that uses a data placement component 113 to train an MLM and implements the trained MLM, according to some embodiments of the present disclosure. The system architecture 300 includes the memory device 255, the data placement component 113 connected to a network 340, a data storage device 350, and a training server 360. The network 340 can be a public network (e.g., the Internet), a private network (e.g., a local area network (LAN) or a wide area network (WAN)), a wireless network, a personal area network (PAN), or a combination thereof.

[0057] The memory device 255 may send the data 301 (e.g., LBAs) to the data placement component 113 for sorting the data 301 so that the data 301 may be optimally placed from the SLC blocks 254 to the QLC blocks 256. In response, the memory device 255 may receive sorting information 303 from the data placement component 113. In some implementations, the memory device 255 may use the sorting information 303 to place the data in groups so that data associated with the short time metric class and data associated with the long time metric class are placed in different groups in the QLC blocks 256.

[0058] The data storage device 350 may store training data 351 for training one or more machine learning models for data placement optimization, and may store test data 353 for testing one or more machine learning models for data placement optimization. The data storage device 350 may be accessed directly by the data placement component 113 or (as shown) via the network 340. The data storage device 350 may be a persistent storage device capable of storing data and metadata of the stored data. The data storage device 350 may be hosted by one or more storage devices, such as main memory, magnetic or optical storage-based disks, tapes or hard drives, network attached storage devices (NAS), storage area networks (SAN), etc. Although depicted as separate from the data placement component 113, in at least one embodiment, the data storage device 350 may be part of the data placement component 113. In at least some embodiments, the data storage device 350 may be a network-attached file server, while in other embodiments, the data storage device 350 may be some other type of persistent storage device, such as an object-oriented database, a relational database, etc., which may be hosted by a server machine or one or more different machines coupled to the data placement component 113 via the network 340.

[0059] The data placement component 113 may include a feature creation component 316 to create features of the data 301. The features of the data 301 may be used as additional information for training and using the MLM. For example, the features of the data 301 may include the time difference between data overwriting and data writing in the LBA. As another example, the features of the data 301 may include the size of the data associated with the LBA.

[0060] The data placement component 113 may include a memory communicatively coupled to one or more processing devices, such as one or more graphics processing units (GPUs) and one or more central processing units (CPUs). The memory may store one or more machine learning models (MLMs) 314.

[0061] The MLM 314 may be trained by a training server 360. In at least one embodiment, the training server 360 may be part of the data placement component 113. In other embodiments, the training server 360 may be communicatively coupled to the data placement component 113 directly or via a network 340. The training server 360 may be (and / or include) a rack server, a router computer, a personal computer, a laptop computer, a tablet computer, a desktop computer, a media center, or any combination thereof. The training server 360 may include a training engine 362. In at least one embodiment, the training engine 362 may generate one or more machine learning models (e.g., MLM 314). The generated machine learning models may be trained by the training engine 362 using training data (e.g., training data 351), which may include training inputs 365 and corresponding target outputs 367. In at least one embodiment, different machine learning models may be trained separately for different types of workloads (e.g., workloads experienced by HDDs or workloads experienced by SSDs).

[0062] For training of the MLM 314, the training input 365 may include training data and associated metadata. The training data may be the tracked data 245. The annotation engine 363 may annotate features in the tracked data 245 with classifications of LBAs (e.g., according to the metadata of the tracked data 245), and generate a target output 367, which may be a target annotation for the training input 365. Additionally, the training engine 362 may generate mapping data 366 (e.g., metadata) that associates the training input 365 with the correct target output 367. During training of the MLM 314, the training engine 362 may identify patterns in the training input 365 based on the desired target output 367, and train the MLM 314 to perform classification of LBAs using the identified patterns.

[0063] In some embodiments, MLM 314 includes a neural network, and the neural network can be trained using training data. In at least one embodiment, each or some of MLM 314 may include multiple neurons, and each neuron may receive its input from other neurons or from an external source, and may generate an output by applying an activation function to the sum of (trainable) weighted inputs and bias values. In at least one embodiment, each or some of MLM 314 may include multiple neurons arranged in several layers, the layers including an input layer, one or more hidden layers, and an output layer. Neurons from adjacent layers may be connected by weighted edges. In at least one embodiment, weights may be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, an untrained neural network is trained using supervised learning, and inputs from a training data set are processed, and the resulting output is compared with a set of expected or desired outputs. In at least one embodiment, the error is then back-propagated through the untrained neural network. In at least one embodiment, the training server 360 adjusts the weights of the untrained neural network. In at least one embodiment, the training server 360 includes tools for monitoring the degree of convergence of the untrained neural network toward the MLM 314 suitable for producing the correct answer based on the input data. In at least one embodiment, the training server 360 repeatedly trains the untrained neural network while adjusting the weights using a loss function and an adjustment algorithm (e.g., stochastic gradient descent) to refine the output of the untrained neural network. In at least one embodiment, the training server 360 trains the untrained neural network until the untrained neural network reaches a desired accuracy. In at least one embodiment, the trained neural network can then be deployed to implement any number of machine learning operations.

[0064] For example, initially, the edge weights may be assigned some starting (e.g., random) values. For each training input 365, the training engine 362 may cause each or some of the MLMs 314 to produce an output. The training engine 362 may then compare the observed output to the desired target output 367. The resulting error or mismatch (e.g., the difference between the desired target output 367 and the actual output of the neural network) may be back-propagated through the corresponding neural network, and the weights in the neural network may be adjusted to bring the actual output closer to the target output. This adjustment may be repeated until the output error for a given training input 365 satisfies a predetermined condition (e.g., is below a predetermined value). Subsequently, a different training input 365 may be selected, a new output generated, and a series of new adjustments implemented until the corresponding neural network is trained to an acceptable accuracy.

[0065] In some embodiments, MLM 314 may use logistic regression, support vector machine (SVM) algorithm, or random forest for binary classification (e.g., long time metric class, short time metric class), or use naive Bayes, K nearest neighbor, gradient boosting, SVM, or logistic regression for multi-class classification (e.g., long time metric class, medium time metric class, short time metric class). Figure 5 Details of training the MLM 314 for data placement optimization are described.

[0066] The data placement component 113 can host the inference engine 312 to run the already trained one or more MLMs 314. The inference engine 312 can use data (e.g., data 301) as input and apply the input to the already trained MLMs 314 to determine the class of the LBA of the data. Figure 6 Details of using MLM 314 for data placement optimization are described.

[0067] It should be noted that although Figures 2 to 3 A specific system architecture is shown in the present invention, but any one or part of the components or devices in the system may be incorporated into other parts of the system, separated into smaller components or combined together, and the arrangement and number of components and devices in the system and the communication between components and devices may be modified as long as the end result according to the present disclosure is achieved.

[0068] Figure 4Schematically illustrates example data placement according to aspects of the present disclosure. Memory device 255 includes SLC blocks 254 and QLC blocks 256. Initially, data stored in SLC blocks 254 may have LBA ranges (e.g., LBA range 0, LBA range 1, LBA range 2, LBA range 3, ..., LBA range N, LBA range N+1, LBA range N+2, LBA range N+3, ...). For each LBA, memory device 255 (e.g., through data placement component 113) may use a trained MLM to classify the LBA into classes (e.g., binary classes or multiple classes). For example, as shown in table 403, when memory device 255 requests to move data cached in SLC block 254 to QLC block 256, trained MLM 314 may classify LBA range 0 as class C1, LBA range 1 as class C3, LBA range 2 as class C1, LBA range 3 as class C3, LBA range N as class C2, and LBA range N+1 as class C1. In some embodiments, class C1 may represent a short time metric class, class C2 may represent a medium time metric class, and class 3 may represent a long time metric class. In some embodiments, class C1 may represent a long time metric class, class C2 may represent a short time metric class, and class C3 may represent a parity data class used to check for program failures (e.g., redundant array of independent NAND (RAIN)).

[0069] like Figure 4 , according to the class of data, memory device 255 may place data having LBA 0, LBA 2, and LBA N+1 into group 1 of QLC blocks 256 (e.g., superblock); memory device 255 may place data having LBA N into group 2 of QLC blocks 256 (e.g., superblock); and memory device 255 may place data having LBA 1 and LBA 3 into group 3 of QLC blocks 256 (e.g., superblock). Figure 4 The data represented by the LBAs shown in FIG. 5 is uniform in size, and the groups of QLC blocks are also uniform in size, but the data size associated with the LBA and the group size of the QLC array may vary.

[0070] Figure 5 and 6 Flowcharts of example methods 500 and 600 of workload-specific data placement optimization according to some embodiments of the present disclosure. Methods 500 and 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, methods 500 and 600 are performed by Figures 1 to 3 113. Although shown in a particular sequence or order, the order of operations may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated operations may be performed in a different order, while some operations may be performed in parallel. In addition, one or more operations may be omitted in some embodiments. Therefore, not all of the illustrated operations are required in every embodiment, and other process flows are possible.

[0071] Figure 5 is a flow chart of an example method 500 for training a machine learning model for data placement optimization in accordance with at least one embodiment. The method 500 can be performed to train a MLM for data placement optimization.

[0072] At operation 510, processing logic may generate first training data that may include a first training input and a first target output. The first training input may include a plurality of LBAs in the first training data. The first target output may include first annotation metadata indicating a class (e.g., a binary class - a long time metric class or a short time metric class, a multi-class - a long time metric class, a medium time metric class, or a short time metric class) of each of the plurality of LBAs. The first training input may be one of the first set of training inputs. Similarly, the first target output may be one of the first set of target outputs.

[0073] At operation 520, processing logic may provide first training data to train a classification MLM. The classification MLM may identify a plurality of LBAs within the first training input and predict classes of the first training input associated with the LBAs and compare the predictions with annotation metadata to determine or correct one or more parameters of the MLM.

[0074] In at least one embodiment, during training, the MLM may select a plurality of features associated with the LBA. The selection may be made using human input. In at least one embodiment, the selection may be made without any human input. The selected features may be features that are likely to be present in the data associated with the LBA. The features may be selected by operator knowledge, rigorous testing, statistical analysis, or algorithmic methods. Algorithmic methods for selecting features include sequential forward selection, sequential floating forward selection, sequential backward selection, and sequential floating backward selection.

[0075] In at least one embodiment, processing logic may use the selected features to predict the class of the LBA associated with the feature. In some implementations, the processing unit may use the selected features to predict the class. The prediction may be in the form of a probability, where the class with the greatest probability among all classes is the class to which the LBA is predicted to belong.

[0076] In at least one embodiment, processing logic may determine a mismatch between the prediction and the annotation metadata by comparing the prediction to the annotation metadata. For example, the predicted class may not be completely accurate compared to the information specified in the annotation metadata for the training signal, for example, may have an error (mismatch) that exceeds the maximum tolerable error. In response to determining that the maximum tolerable error is exceeded, the processing logic may update one or more parameters of the MLM based on the identified mismatch. In at least one embodiment, the prediction may be updated in any (multiple) directions, and the updated prediction may be back-propagated through the MLM for the same training signal. Based on the results of the (one or more such (classes)) back-propagation, the derivative (or gradient) of the loss function may be calculated, and the direction of the most favorable update may be selected. This process may be repeated until the mismatch with the prediction is minimized.

[0077] In some embodiments, the processing logic may generate second (third, etc.) training data including second (third, etc.) training inputs and second (third, etc.) target outputs. The second (third, etc.) training inputs may include second (third, etc.) training signals representing first (second, etc.) multiple features. The second (third, etc.) training data may further include second (third, etc.) target outputs including second (third, etc.) annotation metadata identifying first (second, etc.) multiple features. The second (third, etc.) training input may be one of the second (third, etc.) sets of training inputs. Similarly, the second (third, etc.) target output may be one of the second (third, etc.) sets of target outputs. In some embodiments, the processing logic may provide second (third, etc.) training data to train the MLM. After training based on the second (third, etc.) sets of training inputs and the second (third, etc.) sets of target outputs, the MLM may be able to classify the LBAs of the data.

[0078] Figure 6 is a flow diagram of an example method 600 of using a trained machine learning model for data placement optimization according to at least one embodiment.

[0079] At operation 610, processing logic may identify a range of logical block addresses (LBAs) associated with data stored in one or more blocks of a first type on a memory device. In some embodiments, processing logic may obtain a set of logical block addresses (LBAs) associated with data stored in one or more single level cell (SLC) blocks of memory. In some embodiments, the data is associated with a workload experienced by a hard drive.

[0080] At operation 620, processing logic may determine a time metric class associated with the LBA range, wherein the time metric class is associated with a corresponding range of predicted update frequencies of the data. In some embodiments, processing logic may input the LBA range to a machine learning model, and may output corresponding time metric classes associated with the LBA range from the machine learning model. In some embodiments, the machine learning model is trained using data collected from a tiered storage stack including a solid state drive (SSD) and a hard disk drive (HDD). In some embodiments, the machine learning model is trained using historical data of a workload type, wherein the workload type is the same as the workload type of the data. In some embodiments, the historical data includes the LBA range, the time difference between updates associated with the update frequency, and the size of the data associated with the LBA range.

[0081] In some embodiments, determining a corresponding time measurement class associated with an LBA range is performed in view of a size of data associated with the LBA range. For example, the size of the data identified by the LBA range may exceed a threshold size, which may correspond to a long time measurement class. In some embodiments, determining a corresponding time measurement class associated with an LBA range is performed in view of a time difference between a write and an overwrite of the data associated with the LBA range. For example, the time difference between a write and an overwrite of the data identified by the LBA range may exceed a threshold time period, which may correspond to a long time measurement class.

[0082] In some embodiments, the time measurement class includes at least one of the following: a first class corresponding to a first time that has passed since the data was last accessed, the first time being below a threshold; or a second class corresponding to a second time that has passed since the data was last accessed, the second time not being below the threshold. In some embodiments, the time measurement class includes at least one of the following: a first class corresponding to a first time that has passed since the data was last accessed, the first time being above a threshold; or a second class corresponding to a second time that has passed since the data was last accessed, the second time not being above the threshold.

[0083] In some embodiments, the time metric class includes at least one of the following: a first class corresponding to a first update frequency of the data, the first frequency being lower than a threshold value (e.g., a first frequency range); or a second class corresponding to a second update frequency of the data, the second frequency not being lower than the threshold value (e.g., a second frequency range). In some embodiments, the time metric class includes at least one of the following: a first class corresponding to a first update frequency of the data, the first frequency being higher than a threshold value (e.g., a third frequency range); or a second class corresponding to a second update frequency of the data, the second frequency not being higher than the threshold value (e.g., a fourth frequency range).

[0084] At operation 630, processing logic may identify a group of blocks of a second type based on the time metric class, wherein a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell that exceeds the first number of bits per cell, and move data to the identified group of blocks. In some embodiments, the first number of bits per cell includes a single bit per cell, and the second number of bits per cell includes four bits per cell.

[0085] In some embodiments, the processing logic may store data in one or more groups of one or more non-single-level cell blocks of the memory device according to the corresponding time metric class. In some embodiments, data associated with the same time metric class is stored in the same group of one or more groups of one or more non-single-level cell blocks. In some embodiments, the one or more non-single-level cell blocks include one or more quad-level cell (QLC) blocks. In some embodiments, the one or more non-single-level cell blocks include one or more multi-level cell (MLC) blocks. In some embodiments, the one or more non-single-level cell blocks include one or more tri-level cell (TLC) blocks.

[0086] Figure 7 An example machine illustrating a computer system 700 may be executed within the computer system 700 to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1 ) that includes or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to execute operations of the controller (eg, execute an operating system to execute operations corresponding to Figures 1 to 3 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0087] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0088] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM), such as a synchronous DRAM (SDRAM) or a Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., a flash memory, a static random access memory (SRAM), etc.), and a data storage device 718, which communicate with each other via a bus 730. The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or one processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 to communicate over a network 720.

[0089] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0090] In one embodiment, instruction 726 includes implementing Figures 1 to 3The functional instructions of the data placement component 113 are provided. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0091] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. Here, and in general, an algorithm is considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes for reasons of customary usage, to refer to these signals, in principle, as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0092] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0093] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0094] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures for various of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0095] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0096] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory device; and A processing device operably coupled to the memory device to perform operations comprising: identifying a set of logical addresses associated with data stored in one or more blocks of a first type on the memory device; determining a time metric class associated with the set of logical addresses, wherein the time metric class is associated with a corresponding range of predicted update characteristics of the data; identifying a group of blocks of a second type based on the time metric class, wherein a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell exceeding the first number of bits per cell; and The data is moved to the identified set of blocks.

2. The system of claim 1 , wherein identifying the set of logical addresses and determining the time metric class are performed by a machine learning model trained to group host data according to expected update frequency.

3. The system of claim 2, wherein the machine learning model is trained using data collected from a tiered storage stack comprising at least one of: a volatile memory device and a non-volatile memory device.

4. The system of claim 2, wherein the machine learning model is trained using historical data of the same workload type as the workload type of the data.

5. The system of claim 4, wherein the historical data includes input / output commands having a set of logical addresses, time differences between updates associated with the update characteristics, and sizes of data associated with the set of logical addresses.

6. The system of claim 1, wherein the time metric class associated with the set of logical addresses is determined in view of a size of the data associated with the set of logical addresses.

7. The system of claim 1, wherein the time metric class associated with the set of logical addresses is determined in view of a time difference between updates associated with the update characteristics associated with the set of logical addresses.

8. The system of claim 1, wherein the first number of bits per cell comprises a single bit per cell, and wherein the second number of bits per cell comprises four bits per cell.

9. A method comprising: identifying, by a processing device, a set of logical addresses associated with data stored in one or more blocks of a first type on a memory device; determining a time metric class associated with the set of logical addresses, wherein the time metric class is associated with a corresponding range of predicted update characteristics of the data; identifying a group of blocks of a second type based on the time metric class, wherein a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell exceeding the first number of bits per cell; and The data is moved to the identified set of blocks.

10. The method of claim 9, wherein identifying the set of logical addresses and determining the time metric class are performed by a machine learning model trained to group host data according to expected update frequency.

11. The method of claim 10, wherein the machine learning model is trained using data collected from a tiered storage stack comprising at least one of: a volatile memory device and a non-volatile memory device.

12. The method of claim 10, wherein the machine learning model is trained using historical data of the same workload type as the workload type of the data.

13. The method of claim 12, wherein the historical data comprises a set of logical addresses, a time difference between updates associated with the update characteristic, and a size of data associated with the set of logical addresses.

14. The method of claim 9, wherein the first number of bits per cell comprises a single bit per cell, and wherein the second number of bits per cell comprises four bits per cell.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operably coupled to a memory, perform operations comprising: identifying a set of logical addresses associated with data stored in one or more blocks of a first type on the memory device; determining a time metric class associated with the set of logical addresses, wherein the time metric class is associated with a corresponding range of predicted update characteristics of the data; Identifying a group of blocks of a second type based on the time metric class, wherein a first block of the first type includes a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type includes a second plurality of memory cells having a second number of bits per cell exceeding the first number of bits per cell; and moving the data to the identified group of blocks.

16. The non-transitory computer-readable storage medium of claim 15, wherein identifying the set of logical addresses and determining the time metric class are performed by a machine learning model trained to group host data by expected update frequency.

17. The non-transitory computer-readable storage medium of claim 16, wherein the machine learning model is trained using data collected from a tiered storage stack comprising at least one of: a volatile memory device and a non-volatile memory device.

18. The non-transitory computer-readable storage medium of claim 16, wherein the machine learning model is trained using historical data of the same workload type as the workload type of the data.

19. The non-transitory computer-readable storage medium of claim 18, wherein the historical data comprises a set of logical addresses, a time difference between updates associated with the update characteristic, and a size of data associated with the set of logical addresses.

20. The non-transitory computer-readable storage medium of claim 15, wherein the first number of bits per cell comprises a single bit per cell, and wherein the second number of bits per cell comprises four bits per cell.

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