Automatic reading system for main control chip of solid state disk, use method, device and medium

Abstract

The invention provides an automatic reading system for a main control chip of a solid state disk, a using method, a device and a medium, and belongs to the technical field of main control chips of solid state disks. And the host sends a read command to the main control chip, and the command acquisition module receives and analyzes the read command, acquires the transmission data volume and the memory address of the host, and stores reply information at the same time. And the system judges whether the memory address has offset and whether the data volume exceeds the limit, and if conditions are met, memory address list information is acquired. The memory address analysis module splits addresses according to logic, and each logic block address corresponds to one list unit. And the read-write cache management module searches whether the cache is hit or not, if yes, a cache serial number and a mark are returned, otherwise, cache reading is applied, and a logic address is converted into a physical address. And the direct memory access module starts transmission after configuring related information, and replies to the host according to the stored information after completion. According to the invention, the data can be directly read from the flash memory to the host memory, the reading performance is obviously improved, and the reading delay is reduced.

Description

Technical Field

[0001] The invention relates to a solid state hard disk main control chip automatic reading system and a use method, a device and a medium, belonging to the technical field of solid state hard disk main control chips. Background Art

[0002] With the continuous growth of global solid-state drive shipments and the continuous improvement of consumer demand for storage performance, the reading speed of solid-state drives is also continuously improving. Traditional solid-state drives have a series of cumbersome steps and performance bottlenecks in the process of reading data. Specifically, when a traditional solid-state drive receives a read command sent by the host, the firmware is first responsible for parsing the host memory address and calculating the mapping relationship from the logical address to the physical address. In this process, the firmware needs to apply for the corresponding DRAM memory space, and then move the data of the corresponding physical address on the flash memory medium to the DRAM memory. After completing this internal data move, the firmware intervenes again to move the memory data in the DRAM to the corresponding memory address of the host.

[0003] This traditional data reading method has multiple problems. First, the firmware needs to participate in a lot of processing during the entire reading process, which makes the reading performance overly dependent on the processor computing power of the main control chip. If the processor computing power of the main control chip is insufficient, it will seriously affect the reading speed of the SSD. Secondly, the data is moved multiple times inside the SSD, which not only increases the reading delay, but also consumes additional system resources. In response to the above problems, the industry has been seeking more efficient data reading methods. Summary of the invention The purpose of the present invention is to provide a solid state hard disk main control chip automatic reading system and use method, device, and medium. Through innovative hardware design, the function of directly reading data from the flash memory medium to the host memory is realized, thereby greatly improving the reading performance and reducing the reading delay.

[0004] In order to achieve the above object, the present invention is implemented through the following technical solutions: A solid state hard disk main control chip automatic reading system, comprising: The command acquisition module is used to receive the read command sent by the host, parse the command to obtain the amount of data to be transmitted and the host memory address, and save the information required for the host command reply; pass the logical address, transmission data amount, and memory address list to the memory address parsing module; The memory address parsing module determines whether the host memory address is offset and whether the amount of data transmitted exceeds a specified threshold according to the amount of data to be transmitted and the host memory address. If so, a read request is initiated to the memory address list address corresponding to the host to obtain the host memory address list information; the host memory address is split according to the logical address; The read-write cache management module is used to receive the logical LBA address list unit, and find out whether the corresponding read-write cache is hit according to the logical address. If it is hit, the corresponding read-write cache sequence number and hit mark are returned; if it is not hit, a read cache is applied, and the read cache sequence number and logical block address are passed to the address conversion module to convert the logical LBA address into a physical block address; it is also used to receive a sequence number application request, determine whether there is an idle read cache sequence number at present, and return the sequence number if there is, and if there is no idle read cache sequence number, the longest used read cache sequence number is returned, and the logical block address associated with the cache sequence number is eliminated; An address conversion module, used for converting a logical block address into a physical block address; The direct memory access module is used to configure the module and start data transmission, check the hit mark, and if it hits, calculate the corresponding write cache address according to the read-write cache sequence number and the base address information of the read-write cache, and transmit the data to the host; if it does not hit, read the data directly from the flash memory medium and transmit it to the host according to the configured physical block address, and write the data to the cache address corresponding to the read cache sequence number at the same time. After the writing is completed, it triggers the read-write cache module to activate the corresponding cache number; after completing the data transmission of all logical addresses, reply to the host with a completion message according to the information required for the saved host command reply.

[0005] A method for using a solid state hard disk main control chip automatic reading system comprises the following steps: The host sends a read command to the SSD main control chip, and the command acquisition module in the SSD main control chip receives and parses the read command, obtains the amount of data to be transmitted and the host memory address, and saves the information required for the host command reply; According to the amount of data to be transmitted and the host memory address, determine whether the host memory address is offset and whether the amount of data transmitted exceeds a specified threshold. If so, initiate a read request to the memory address list address corresponding to the host to obtain the host memory address list information; The logical address, the amount of data to be transferred, and the memory address list are passed to the memory address parsing module, and the host memory address is split according to the logical address, so that each logical block address corresponds to a host memory address list, that is, a logical LBA address list unit; Each logical LBA address list unit is passed to the read-write cache management module, and the corresponding read-write cache is checked according to the logical address. If it is hit, the corresponding read-write cache sequence number and hit mark are returned; if it is not hit, a read cache is applied, and the read cache sequence number and logical block address are passed to the address conversion module to convert the logical LBA address into a physical block address; Configure the information required for the host command reply, the logical LBA address list unit, the hit information, the cache sequence number, and the physical block address information to the direct memory access module, and start the data transmission; After the DMA module completes the data transfer of all logical addresses, it replies a completion message to the host according to the information required for the saved host command reply.

[0006] Preferably, the data transmission is specifically carried out in the following manner: The direct memory access module checks the hit mark during transmission. If a hit occurs, the corresponding write cache address is calculated based on the read-write cache sequence number and the base address information of the read-write cache, and the data is transmitted to the host. If a hit occurs, the data is directly read from the flash memory medium according to the configured physical block address and transmitted to the host, and the data is simultaneously written to the cache address corresponding to the read cache sequence number. After the write is completed, the read-write cache module is triggered to activate the corresponding cache number.

[0007] Preferably, when receiving a read cache sequence number application request, the read-write cache management module determines whether there is currently an idle read cache sequence number. If so, it returns the sequence number; if not, it returns the longest-used read cache sequence number and eliminates the logical address associated with the cache sequence number.

[0008] Preferably, the specified threshold is 4K.

[0009] Preferably, a completion message is replied to the host according to the information required for the saved host command reply, and the release command acquisition module is triggered to release the corresponding host read command.

[0010] A device for an automatic reading system of a solid state hard disk main control chip comprises a processor and a memory storing program instructions, wherein the processor is configured to execute the method for the automatic reading system of the solid state hard disk main control chip when running the program instructions.

[0011] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the method of automatically reading a system for a main control chip of a solid-state hard disk.

[0012] The advantages of the present invention are: through innovative hardware parsing of host memory addresses, hardware conversion of logical addresses to physical addresses, and direct reading of data from flash memory media to host memory, the read performance of the solid-state hard disk is greatly improved. The involvement of the firmware in processing read commands is reduced, and the number of data moves within the solid-state hard disk is reduced, thereby significantly reducing the read delay.

[0013] While transferring data from the flash media to the host memory, the data is also written to the cache inside the SSD, establishing an effective hit mechanism. When a subsequent read command hits the cache, the data can be read directly from the cache, further improving read performance.

[0014] Through the interconnected configuration of various hardware modules, automatic parsing of commands and memory addresses, automatic address mapping conversion, and automatic completion of host command replies greatly reduce the involvement of firmware in the reading process. This not only improves the overall performance, but also releases a large amount of main control processor computing power, allowing the use of fewer processor cores during chip main control integration, thereby reducing the power consumption of the main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0016] Figure 1 It is a schematic diagram of the system architecture of the present invention; Figure 2 The figure is a flow chart of the method for using the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] Example 1 like Figure 1 As shown, a solid state hard disk main control chip automatic reading system includes: The command acquisition module is used to receive the read command sent by the host, parse the command to obtain the amount of data to be transmitted and the host memory address, and save the information required for the host command reply; pass the logical address, transmission data amount, and memory address list to the memory address parsing module; The memory address parsing module determines whether the host memory address is offset and whether the amount of data transmitted exceeds a specified threshold according to the amount of data to be transmitted and the host memory address. If so, a read request is initiated to the memory address list address corresponding to the host to obtain the host memory address list information; the host memory address is split according to the logical address; The read-write cache management module is used to receive the logical LBA address list unit, and find out whether the corresponding read-write cache is hit according to the logical address. If it is hit, the corresponding read-write cache sequence number and hit mark are returned; if it is not hit, a read cache is applied, and the read cache sequence number and logical block address are passed to the address conversion module to convert the logical LBA address into a physical block address; it is also used to receive a sequence number application request, determine whether there is an idle read cache sequence number at present, and return the sequence number if there is, and if there is no idle read cache sequence number, the longest used read cache sequence number is returned, and the logical block address associated with the cache sequence number is eliminated; An address conversion module, used for converting a logical block address into a physical block address; The direct memory access module is used to configure the module and start data transmission, check the hit mark, and if it hits, calculate the corresponding write cache address according to the read-write cache sequence number and the base address information of the read-write cache, and transmit the data to the host; if it does not hit, read the data directly from the flash memory medium and transmit it to the host according to the configured physical block address, and write the data to the cache address corresponding to the read cache sequence number at the same time. After the writing is completed, it triggers the read-write cache module to activate the corresponding cache number; after completing the data transmission of all logical addresses, reply to the host with a completion message according to the information required for the saved host command reply.

[0019] Example 2 like Figure 2 As shown, a method for using the automatic reading system of the solid state drive main control chip includes the following steps: S1: The host sends a read command to the SSD main control chip. The command acquisition module in the SSD main control chip receives and parses the read command, obtains the amount of data to be transmitted and the host memory address, and saves the information required for the host command reply.

[0020] S2: According to the amount of data to be transmitted and the host memory address, determine whether the host memory address is offset and whether the amount of data transmitted exceeds a specified threshold. If so, initiate a read request to the memory address list address corresponding to the host to obtain the host memory address list information.

[0021] As a refinement of the above embodiment, the specified threshold is 4K.

[0022] S3: The logical address, the amount of data to be transferred, and the memory address list are passed to the memory address resolution module, and the host memory address is split according to the logical address, so that each logical block address corresponds to a host memory address list, that is, a logical LBA address list unit.

[0023] S4: Pass each logical LBA address list unit to the read-write cache management module, and check whether the corresponding read-write cache is hit according to the logical address. If it is hit, the corresponding read-write cache sequence number and hit mark are returned; if it is not hit, apply for a read cache, pass the read cache sequence number and logical block address to the address conversion module, and convert the logical LBA address into a physical block address.

[0024] S5: The information required for the host command reply, the logical LBA address list unit, the hit information, the cache sequence number, and the physical block address information are configured to the direct memory access module, and data transmission is started.

[0025] As a refinement of the above embodiment, the specific method of data transmission is as follows: The direct memory access module checks the hit mark during transmission. If a hit occurs, the corresponding write cache address is calculated based on the read-write cache sequence number and the base address information of the read-write cache, and the data is transmitted to the host. If a hit occurs, the data is directly read from the flash memory medium according to the configured physical block address and transmitted to the host, and the data is simultaneously written to the cache address corresponding to the read cache sequence number. After the write is completed, the read-write cache module is triggered to activate the corresponding cache number.

[0026] S6: After the DMA module completes the data transmission of all logical addresses, it replies a completion message to the host according to the information required by the saved host command reply.

[0027] As a refinement of the above embodiment, when the read-write cache management module receives a read cache sequence number application request, it determines whether there is currently an idle read cache sequence number. If so, it returns the sequence number; if not, it returns the longest-used read cache sequence number and eliminates the logical address associated with the cache sequence number.

[0028] As a refinement of the above embodiment, a completion message is replied to the host according to the information required for the saved host command reply, and the release command acquisition module is triggered to release the corresponding host read command.

[0029] It should be noted that: through the hardware module design, data can be read directly from the flash memory medium to the host memory, which reduces the degree of firmware involvement, improves read performance, and reduces read latency.

[0030] While transferring data from the flash media to the host memory, the data is also written to the cache inside the SSD, establishing a hit mechanism, further improving the read performance when a read hit occurs.

[0031] Through the mutual linkage configuration of various hardware modules, automatic parsing of commands and memory addresses, automatic address mapping conversion, and automatic reply to host command completion messages, the involvement of firmware in the reading process is greatly reduced. While improving performance, a large amount of main control processor computing power is released. During the chip main control integration process, fewer processor cores can be used, reducing the power consumption of the main control chip.

[0032] The disclosed embodiment also provides a device for an automatic reading system of a solid-state hard disk main control chip, including a processor and a memory. Optionally, the device may also include a communication interface and a bus. The processor, the communication interface, and the memory may communicate with each other through the bus. The communication interface may be used for information transmission. The processor may call the logic instructions in the memory to execute the method of the automatic reading system of the solid-state hard disk main control chip of the above embodiment.

[0033] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0034] The memory, as a computer-readable storage medium, can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor executes the functional application and data processing by running the program instructions / modules stored in the memory, that is, the method of the automatic reading system of the solid-state hard disk main control chip in the above embodiment is realized.

[0035] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory may include a high-speed random access memory and may also include a non-volatile memory.

[0036] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A solid state hard disk main control chip automatic reading system, characterized in that: include: The command acquisition module is used to receive the read command sent by the host, parse the command to obtain the amount of data to be transmitted and the host memory address, and save the information required for the host command reply; The logical address, the amount of data transferred, and the memory address list are passed to the memory address resolution module; The memory address parsing module determines whether the host memory address is offset and whether the amount of data transmitted exceeds a specified threshold according to the amount of data to be transmitted and the host memory address. If so, a read request is initiated to the memory address list address corresponding to the host to obtain the host memory address list information; Split the host memory address according to the logical address; The read-write cache management module is used to receive the logical LBA address list unit, and find out whether the corresponding read-write cache is hit according to the logical address. If it is hit, the corresponding read-write cache sequence number and hit mark are returned; if it is not hit, a read cache is applied, and the read cache sequence number and logical block address are passed to the address conversion module to convert the logical LBA address into a physical block address; it is also used to receive a sequence number application request, determine whether there is an idle read cache sequence number at present, and return the sequence number if there is, and if there is no idle read cache sequence number, the longest used read cache sequence number is returned, and the logical block address associated with the cache sequence number is eliminated; An address conversion module, used for converting a logical block address into a physical block address; The direct memory access module is used to configure the module and start data transmission, check the hit mark, and if it hits, calculate the corresponding write cache address according to the read-write cache sequence number and the base address information of the read-write cache, and transmit the data to the host; if it does not hit, read the data directly from the flash memory medium and transmit it to the host according to the configured physical block address, and write the data to the cache address corresponding to the read cache sequence number at the same time. After the writing is completed, it triggers the read-write cache module to activate the corresponding cache number; after completing the data transmission of all logical addresses, reply to the host with a completion message according to the information required for the saved host command reply.

2. A method for using a solid state hard disk master chip automatic reading system, characterized in that: The following steps are involved: The host sends a read command to the SSD main control chip, and the command acquisition module in the SSD main control chip receives and parses the read command, obtains the amount of data to be transmitted and the host memory address, and saves the information required for the host command reply; According to the amount of data to be transmitted and the host memory address, determine whether the host memory address is offset and whether the amount of data transmitted exceeds the specified threshold. If so, initiate a read request to the memory address list address corresponding to the host to obtain the host memory address list information. If not, use the memory address list in the read command; The logical address, the amount of data to be transferred, and the memory address list are passed to the memory address parsing module, and the host memory address is split according to the logical address, so that each logical block address corresponds to a host memory address list, that is, a logical LBA address list unit; Each logical LBA address list unit is passed to the read-write cache management module, and the corresponding read-write cache is checked according to the logical address. If it is hit, the corresponding read-write cache sequence number and hit mark are returned; if it is not hit, a read cache is applied, and the read cache sequence number and logical block address are passed to the address conversion module to convert the logical LBA address into a physical block address; Configure the information required for the host command reply, the logical LBA address list unit, the hit information, the cache sequence number, and the physical block address information to the direct memory access module, and start the data transmission; After the DMA module completes the data transfer of all logical addresses, it replies a completion message to the host according to the information required for the saved host command reply.

3. The method of use according to claim 2, characterized in that: The specific method of data transmission is as follows: The direct memory access module checks the hit mark during transmission. If a hit occurs, the corresponding write cache address is calculated based on the read-write cache sequence number and the base address information of the read-write cache, and the data is transmitted to the host. If a hit occurs, the data is directly read from the flash memory medium according to the configured physical block address and transmitted to the host, and the data is simultaneously written to the cache address corresponding to the read cache sequence number. After the write is completed, the read-write cache module is triggered to activate the corresponding cache number.

4. The method of use according to claim 2, characterized in that: When receiving a read cache sequence number application request, the read / write cache management module determines whether there is an idle read cache sequence number. If so, it returns the sequence number. If not, it returns the longest-used read cache sequence number and eliminates the logical address associated with the cache sequence number.

5. The method of use according to claim 2, characterized in that: The specified threshold is 4K.

6. The method of use according to claim 2, characterized in that: A completion message is replied to the host according to the information required for the saved host command reply, and the release command acquisition module is triggered to release the corresponding host read command.

7. A device for an automatic reading system of a solid state hard disk main control chip, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the method of the automatic reading system of the solid state drive main control chip as described in any one of claims 2-6 when running the program instructions.

8. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the method of the automatic reading system of the solid state hard disk master control chip as described in any one of claims 2-6 above is implemented.

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