Approximate floating point multiply-accumulate circuit and method

Abstract

The invention discloses an approximate floating point multiply-accumulate circuit and method, and belongs to the field of computer system structures and the technical field of digital circuit design, and the circuit comprises an approximate floating point multiplier precision arbitration module which receives a preprocessed floating point number and outputs a first precision control signal; the approximate floating point multiplication module is used for outputting an approximate floating point multiplication result by adopting an approximate addition scheme of different mantissa multiplication according to the first precision control signal; the approximate floating point adder precision arbitration module is used for receiving an approximate floating point multiplication result and a last partial sum result and outputting a second precision control signal; and the approximate floating point addition module is used for outputting a partial sum result by adopting an approximate addition scheme of different mantissa addition according to the second precision control signal. The calculation process is dynamically adjusted according to the characteristics of the input data, and when the difference of the input data is large, the circuit adopts accurate calculation to ensure the accuracy of the calculation result; when the input data difference is small, the circuit is switched to an approximate calculation mode to simplify the operation process.

Description

Technical Field

[0001] The present application relates to the field of digital circuit design, and in particular to an approximate floating-point multiplication-accumulation circuit and method. Background Art

[0002] Floating-point numbers are a numerical format used to represent real numbers in computers. They can represent extremely large or small values ​​within a limited bit width, so they are widely used in scientific computing, image processing, artificial intelligence, big data analysis and other fields. Compared with fixed-point numbers, the main advantage of floating-point numbers is that they can dynamically adjust the decimal point position to represent a larger dynamic range, and they still have an irreplaceable position in application scenarios that require dynamic range and high precision. However, due to the complexity of floating-point operations, their hardware design often consumes more resources. Floating-point calculations require complex mantissa alignment, exponent adjustment, and normalization processing. These processes not only increase the complexity of the hardware circuit, but also lead to higher power consumption and longer operation delays.

[0003] Approximate computing is a technique that actively introduces controllable errors in hardware design in order to improve computing efficiency. In recent years, with the rise of applications with high fault tolerance such as deep learning, neural networks, and image processing, approximate computing has received widespread attention as an optimization method. Especially in floating-point computing, approximate computing can significantly reduce hardware complexity, power consumption, and latency by simplifying the calculation process or reducing accuracy requirements.

[0004] Although approximate computing can improve the energy efficiency of floating-point operations, in actual applications, different scenarios have significantly different requirements for computing accuracy. For example, in scenarios such as image processing or deep learning reasoning, lower computing accuracy can usually meet the needs, while in precision-sensitive scenarios such as scientific computing and financial simulation, strict computing accuracy must be guaranteed. Summary of the invention

[0005] The present application aims to provide an approximate floating-point multiplication-accumulation circuit to introduce a precision adaptation mechanism in floating-point operations, and to design a floating-point multiplication-accumulation unit that can dynamically adjust the calculation accuracy according to the characteristics of the input data, thereby meeting the needs of different application scenarios.

[0006] In order to achieve the above-mentioned purpose, the technical solution of this application is: An approximate floating-point multiplication-accumulation circuit, comprising: Preprocessing module; An approximate floating-point multiplier precision arbitration module connected to the preprocessing module; An approximate floating-point multiplication module, connected to the preprocessing module and the approximate floating-point multiplier precision arbitration module respectively; An approximate floating-point adder precision arbitration module connected to the approximate floating-point multiplication module; an approximate floating-point addition module, connected to the approximate floating-point multiplication module and the approximate floating-point adder precision arbitration module respectively; A partial sum storage module is connected to the approximate floating-point addition module.

[0007] Optionally, the approximate floating-point multiplier precision arbitration module includes: a floating-point multiplication exponent input analysis unit and a first approximate resolution configuration unit, and the floating-point multiplication exponent input analysis unit is connected to the first approximate resolution configuration unit.

[0008] Optionally, the floating-point multiplication exponent input analysis unit includes: a first exponent receiver, a first leading one detector, a first subtractor and a first multiplexer selector, and the first exponent receiver, the first leading one detector, the first subtractor and the first multiplexer selector are connected in sequence.

[0009] Optionally, the first approximate analysis configuration unit includes: a first shift controller and a first 4-bit shift register, and the first shift controller and the first 4-bit shift register are connected in sequence.

[0010] Optionally, the approximate floating-point multiplication module includes: an adder array, the adder array includes n adders, each adder includes two sub-adders, the sub-adders include: a first two-to-one selector, a first precise adder, and a first approximate adder, the first two-to-one selector is connected to the first precise adder and the first approximate adder respectively, the first precise adder is connected to the first approximate adder, the first two-to-one selector of each sub-adder is connected, the first precise adder of each sub-adder is connected, and the first approximate adder of each sub-adder is connected.

[0011] Optionally, the approximate floating-point adder precision arbitration module includes: a floating-point addition exponent input analysis unit and a second approximate resolution configuration unit, and the floating-point addition exponent input analysis unit is connected to the second approximate resolution configuration unit.

[0012] Optionally, the floating-point addition exponent input analysis unit includes: a second exponent receiver, a second leading one detector, a second subtractor and a second multiplexer selector, and the second exponent receiver, the second leading one detector, the second subtractor and the second multiplexer selector are connected in sequence.

[0013] Optionally, the second approximate analysis configuration unit includes: a second shift controller and a second 4-bit shift register, and the second shift controller and the second 4-bit shift register are connected in sequence.

[0014] Optionally, the approximate floating-point addition module includes: four sub-adders, each sub-adder includes: a second two-to-one selector, a second precise adder, and a second approximate adder, the second two-to-one selector is connected to the second precise adder and the second approximate adder respectively, the second precise adder is connected to the second approximate adder, the second two-to-one selector of each sub-adder is connected, the second precise adder of each sub-adder is connected, and the second approximate adder of each sub-adder is connected.

[0015] An approximate floating-point multiplication-accumulation method, applied to the approximate floating-point multiplication-accumulation circuit as described in any one of the above items, comprising: Step S1: input a floating point number; Step S2: Input floating point number exponential analysis; Step S3: Generate configuration code; Step S4: Determine whether to use approximate calculation, if yes, proceed to step S5; if no, proceed to step S6; Step S5: approximate configuration; Step S6: adopt mantissa multiplication; Step S7: Input floating point number exponential analysis; Step S8: Generate configuration code; Step S9: Determine whether to use approximate calculation, if yes, go to step S12; if no, go to step S11; Step S10: approximate configuration; Step S11: adding the mantissas; Step S12: Determine whether the accumulation is completed, if so, proceed to step S13; if not, return to step S8; Step S13: Output the result.

[0016] This application designs a precision arbitration module for floating-point multipliers and adders, dynamically adjusts the calculation process according to the characteristics of the input data, and flexibly chooses to use approximate calculation or precise calculation mode. When the input data differs greatly, the circuit gives priority to precise calculation to ensure the accuracy of the calculation result; when the input data differs less, the circuit switches to approximate calculation mode to simplify the calculation process, speed up the calculation speed and reduce power consumption. This dynamic adjustment mechanism can achieve the best balance between calculation accuracy and hardware resource utilization in different application scenarios, meet the calculation accuracy of different requirements, improve the calculation speed and reduce power consumption while maintaining a certain accuracy.

[0017] In order to make the above features and advantages of the application more obvious and easy to understand, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1This is a module diagram of the approximate floating-point multiplication and accumulation circuit provided in this application.

[0019] Figure 2 This is a diagram of the precision arbitration module of the approximate floating-point multiplier of the present application.

[0020] Figure 3 This is a module diagram of an approximate resolution configuration unit of an approximate floating-point multiplier precision arbitration module of the present application.

[0021] Figure 4 This is a block diagram of the adder array of the approximate floating-point multiplication module of the present application.

[0022] Figure 5 It is a block diagram of an adder in the adder array of the present application.

[0023] Figure 6 This is a diagram of the precision arbitration module of the approximate floating-point adder of the present application.

[0024] Figure 7 This is a block diagram of an approximate mantissa adder of an approximate floating-point addition module of the present application.

[0025] Figure 8 This is a flow chart of the approximate floating-point multiplication-accumulation method proposed in this application. DETAILED DESCRIPTION

[0026] In order to make the purpose and technical solution of the embodiment of the present application clearer, the technical solution of the embodiment of the present application will be clearly and completely described in conjunction with the drawings of the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, not all of the embodiments. Based on the described embodiment of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] In one embodiment of the present application, please refer to Figure 1 , Figure 1 The module diagram of the approximate floating-point multiplication and accumulation circuit provided in the present application includes: an approximate floating-point multiplier precision arbitration module 1, an approximate floating-point multiplication module 2, an approximate floating-point adder precision arbitration module 3, an approximate floating-point addition module 4, a preprocessing module 5 and a partial sum storage module 6.

[0028] The approximate floating-point multiplier precision arbitration module 1 is connected to the approximate floating-point multiplication module 2, the approximate floating-point multiplication module 2 is connected to the approximate floating-point adder precision arbitration module 3 and the approximate floating-point addition module 4, the approximate floating-point adder precision arbitration module 3 is connected to the approximate floating-point addition module 4 and the partial sum storage module 6, the preprocessing module 5 is connected to the approximate floating-point multiplier precision arbitration module 1 and the approximate floating-point multiplication module 2 respectively, and the partial sum storage module 6 is connected to the approximate floating-point addition module 4.

[0029] As an example, the approximate floating-point multiplier precision arbitration module 1 is used to receive preprocessed floating-point numbers, input the exponent parts of the multiplier and the multiplicand, and the bit width is 8 bits; output the precision control signal for controlling the precision of the approximate floating-point multiplication module 2, and the bit width is 4 bits.

[0030] The approximate floating-point multiplication module 2 is used to receive the preprocessed floating-point number and the precision control signal output by the approximate floating-point multiplier precision arbitration module 1, adopt the approximate addition scheme of different mantissa multiplication to achieve controllable precision, and output the approximate floating-point multiplication result.

[0031] The approximate floating-point adder precision arbitration module 3 is used to receive the approximate floating-point multiplication result and the partial sum result obtained after the previous approximate floating-point addition calculation, and input the exponent part of the addend and the augend, with a bit width of 8 bits; output the precision control signal for controlling the approximate floating-point addition module 4, with a bit width of 4 bits.

[0032] The approximate floating-point addition module 4 is used to receive the approximate floating-point multiplication result, the partial sum result obtained after the previous approximate floating-point addition calculation and the precision control signal output by the approximate floating-point adder precision arbitration module 3, adopt the approximate addition scheme of different mantissa addition to achieve controllable precision, and output the partial sum result.

[0033] The preprocessing module 5 is used to receive a floating point number and preprocess the floating point number, including: dividing the floating point number by the number of bits according to the data format of the received floating point number to obtain a sign bit, an exponent part, and a mantissa part. For example, a single-precision floating point number is a 32-bit binary number, the 32nd bit is the sign bit, the 31st to 24th bits are the exponent part, and the 23rd to 1st bits are the mantissa part. According to the data format of the floating point number, these three bits are extracted and input into the approximate floating point multiplier precision arbitration module 1 and the approximate floating point multiplication module 2.

[0034] The partial sum storage module 6 is used to store the partial sum result obtained by the approximate floating point addition module 4.

[0035] Specifically, the partial sum result is the augend input into the approximate floating-point addition module 4 for the next approximate floating-point addition calculation, and the approximate floating-point multiplication result is the addend input into the approximate floating-point addition module 4 .

[0036] This application designs an accuracy arbitration module for approximate floating-point multipliers and approximate floating-point adders, dynamically adjusts the calculation process according to the characteristics of the input data, and flexibly chooses to use approximate calculation or precise calculation mode. When the input data differs greatly, the circuit gives priority to precise calculation to ensure the accuracy of the calculation result; when the input data differs less, the circuit switches to approximate calculation mode to simplify the calculation process, speed up the calculation speed and reduce power consumption. This dynamic adjustment mechanism can achieve the best balance between calculation accuracy and hardware resource utilization in different application scenarios, meet different requirements of calculation accuracy, improve calculation speed and reduce power consumption while maintaining a certain accuracy.

[0037] As an example, see Figure 2 , Figure 2 This is a structural diagram of an approximate floating-point multiplier precision arbitration module 1 of the present application. The approximate floating-point multiplier precision arbitration module 1 includes: a floating-point multiplication exponent input analysis unit 11 and an approximate resolution configuration unit 12, and the floating-point multiplication exponent input analysis unit 11 is connected to the approximate resolution configuration unit 12; the floating-point multiplication exponent input analysis unit 11 includes: an exponent receiver 111, a leading one detector (LOD) 112, a subtractor 113 and a multiplexing selector 114, and the exponent receiver 111, the leading one detector 112, the subtractor 113 and the multiplexing selector 114 are connected in sequence, and the multiplexing selector 114 is connected to the approximate resolution configuration unit 12.

[0038] The floating-point multiplication exponent input analysis unit 11 is used to perform exponential analysis on the input preprocessed floating-point number, and the exponential analysis includes: according to the difference in the exponential magnitude of the input floating-point number, outputting different signals to process the subsequent calculation in different ways.

[0039] The exponent receiver 111 is used to receive the exponent of an input preprocessed floating point number.

[0040] The leading one detector 112 is used to detect the highest bit of the exponent of the received floating point number, that is, the number of bits where the first 1 is located from high to low, and input the result into the subtractor.

[0041] The subtractor 113 is used to receive the result of the number of bits of the highest bit of the exponent of the input preprocessed floating point number, and obtain the magnitude difference of the exponent of the input floating point number for subsequent magnitude division processing.

[0042] The multiplexer selector 114 is used to output different signals according to the magnitude difference of the exponents of the input floating-point numbers, and to switch between different subsequent calculation schemes; when the magnitude difference of the exponents is 0, 1, or 2, the output signal is 10; when the magnitude difference of the exponents is 3, 4, or 5, the output signal is 01; when the magnitude difference of the exponents is 6 or 7, the output signal is 00.

[0043] The approximate analysis configuration unit 12 is used to analyze the signal output by the floating-point multiplication exponent input analysis unit 11, generate a configuration code, interpret the parsed configuration code, generate a precision control signal for configuring the approximate floating-point multiplication module 2, and switch between precise and different approximate schemes.

[0044] Specifically, see Figure 3 , Figure 3 1 is a module diagram of the approximate analysis configuration unit of the present application. The approximate analysis configuration unit 12 includes: a shift controller 121 and a 4-bit shift register 122. The shift controller 121 and the 4-bit shift register 122 are connected in sequence.

[0045] The shift controller 121 is used to receive the signal output by the floating-point multiplication exponent input analysis unit 11, parse it into a corresponding decimal value, and generate a corresponding number of "1" signals according to the value, and output them to the shift register through a shift operation; The 4-bit shift register 122 adopts a parallel loading structure, receives a sequence of "1" signals from the shift controller 121, and performs a bit-by-bit right shift operation under the drive of the shift pulse. When the number of shifts reaches the preset bit width, the binary digits stored in the 4-bit shift register 122 are directly mapped to the first precision control signal output. That is, the corresponding decimal value is the number of 1s in the output precision control signal.

[0046] When the signal output by the floating-point multiplication exponent input analysis unit 11 is 00, the shift controller 121 parses the corresponding decimal value as 0, generates 0 "1" signals, and the 4-bit shift register 122 outputs the precision control signal 00 after shifting; when the signal is 01, the shift controller 121 parses the corresponding decimal value as 1, generates 1 "1" signal, and the 4-bit shift register 122 outputs the precision control signal 01 after shifting; when the signal is 10, the shift controller 121 parses the corresponding decimal value as 2, generates 2 "1" signals, and the 4-bit shift register 122 outputs the precision control signal 11 after shifting.

[0047] As an example, see Figure 4 The approximate floating-point multiplication module 2 includes: an adder array 21, and the adder array 21 includes n adders 211 to 21n. Figure 4This is a schematic diagram of the structure of the adder array of the approximate floating-point multiplication module of the present application. Since addition is also required in the mantissa multiplication calculation process, and the mantissa multiplication bit width is relatively large, a lot of results will be obtained after each bit is multiplied, and the final result can only be obtained after addition, so an adder array is used. The adder array 21 of the approximate floating-point multiplication module 2 uses a block adder to perform approximate calculations to obtain results. Each adder is divided into two sub-adders, and each sub-adder has an accurate adder and an approximate adder. Each adder in the adder array 21 is controlled by a precision control signal to use an accurate adder or an approximate adder. For example, 100 × 111, in the calculation process, each bit in the multiplier and the multiplicand are multiplied to obtain 100 + 1000 + 10000, and here it is necessary to use the adder array 21 for addition to obtain the mantissa multiplication result.

[0048] Please continue reading Figure 5 Taking adder 211 as an example, adder 211 includes sub-adder 2111 and sub-adder 2112, and sub-adder 2111 and sub-adder 2112 are connected. The sub-adder 2111 includes: a selector 21111, an accurate adder 21112 and an approximate adder 21113, the selector 21111 is connected to the accurate adder 21112 and the approximate adder 21113, and the accurate adder 21112 is connected to the approximate adder 21113; the sub-adder 2112 includes: a selector 21121, an accurate adder 21122 and an approximate adder 21123, the selector 21121 is connected to the accurate adder 21122, the approximate adder 21123 and the selector 21111, and the accurate adder 21122 is connected to the approximate adder 21123 and the accurate adder 21112. The bit widths of the sub-adder 2111 and the sub-adder 2112 are both 12 bits.

[0049] As an example, both the two-to-one selector 21111 and the two-to-one selector 21121 are MUXs.

[0050] As an example, the approximate floating-point multiplication module 2 receives a precision control signal from the approximate resolution configuration unit 12, and selects whether each adder uses an approximate adder or an exact adder. When the received precision control signal is 11, the two sub-adders representing each adder in the adder array 21 both choose to use an approximate adder; when the received precision control signal is 01, the first sub-adder representing each adder in the adder array 21 uses an exact adder, and the second sub-adder uses an approximate adder; when the received precision control signal is 00, the two sub-adders of each adder in the adder array 21 both choose to use an exact adder. The number of approximate adders is flexibly used according to the precision control signal, achieving the goal of controllable precision.

[0051] Furthermore, the exponential part of the input floating point number is added by a precise adder and shifted to obtain the exponential addition result, the sign bit is XORed, and finally the approximate floating point multiplication module 2 outputs the approximate floating point multiplication result. The approximate floating point multiplication result is a floating point number.

[0052] As an example, see Figure 6 , Figure 6 This is a structural diagram of the approximate floating-point adder precision arbitration module 3 of the present application. The approximate floating-point adder precision arbitration module 3 includes: a floating-point addition exponent input analysis unit 31 and an approximate parsing configuration unit 32, and the floating-point addition exponent input analysis unit 31 is connected to the approximate parsing configuration unit 32; the floating-point addition exponent input analysis unit 31 includes: an exponent receiver 311, a leading one detector 312, a subtractor 313 and a multiplexer selector 314, and the exponent receiver 311, the leading one detector 312, the subtractor 313 and the multiplexer selector 314 are connected in sequence, and the multiplexer selector 314 is connected to the approximate parsing configuration unit 32.

[0053] The floating-point addition exponent input analysis unit 31 is used to perform exponential analysis on the input approximate floating-point multiplication result and the part obtained by the approximate floating-point addition module 4 after the last approximate floating-point addition calculation and the exponential part of the result, and output different signals according to the difference in the exponential magnitude of the input floating-point number to process the subsequent calculation in different ways.

[0054] The exponent receiver 311 is used to receive the exponent part of the approximate floating-point multiplication result and the exponent part of the sum result obtained by the approximate floating-point addition module 4 after the last approximate floating-point addition calculation, and store the two exponent parts for subsequent processing.

[0055] The leading one detector 312 is used to detect the number of bits of the highest bits of the two received exponential parts and input the result into the subtractor 313.

[0056] The subtractor 313 is used to obtain the magnitude difference of the two exponents, which is used for subsequent magnitude division processing to achieve the purpose of quickly obtaining the exponent difference.

[0057] The multiplexer selector 314 is used to output different signals according to the difference in the exponential magnitudes, and to switch between different subsequent calculation schemes; when the difference in the exponential magnitudes is 0, the output signal is 100; when the difference in the exponential magnitudes is 1 and 2, the output signal is 011; when the difference in the exponential magnitudes is 3 and 4, the output signal is 010; when the difference in the exponential magnitudes is 5 and 6, the output signal is 001; and when the difference in the exponential magnitudes is 7 and 8, the output signal is 000.

[0058] The approximate analysis configuration unit 32 is used to analyze the signal output by the floating-point addition exponent input analysis unit 31, generate a configuration code, interpret the parsed configuration code, generate a precision control signal for configuring the approximate floating-point addition module 4, and switch between precise and different approximate schemes.

[0059] Specifically, the approximate analysis configuration unit 32 and Figure 3 The structure and function of the approximate analysis configuration unit 12 are the same, including: a shift controller and a 4-bit shift register, and the shift controller and the 4-bit shift register are connected in sequence. When the signal output by the floating-point addition exponent input analysis unit 31 is 000, the shift controller generates 0 '1' signals, and the 4-bit shift register outputs a precision control signal of 0000 after shifting; when the signal is 001, the shift controller generates 1 '1' signal, and the 4-bit shift register outputs a precision control signal of 0001 after shifting; when the signal is 010, the shift controller generates 2 '1' signals, and the 4-bit shift register outputs a precision control signal of 0011 after shifting; when the signal is 011, the shift controller generates 3 '1' signals, and the 4-bit shift register outputs a precision control signal of 0111 after shifting; when the signal is 100, the shift controller generates 4 '1' signals, and the 4-bit shift register outputs a precision control signal of 1111 after shifting.

[0060] Furthermore, the maximum exponent in the partial sum result obtained by the approximate floating-point addition module 4 after the approximate floating-point multiplication result and the last approximate floating-point addition calculation is aligned to obtain the result of the exponent part, and the mantissa is shifted before the mantissa addition calculation is performed.

[0061] As an example, see Figure 7 The approximate floating-point addition module 4 includes: an approximate mantissa adder 41. Figure 7The block diagram of the approximate mantissa adder of the approximate floating-point addition module of the present application, the approximate mantissa adder 41 of the approximate floating-point addition module 4 includes a sub-adder 411, a sub-adder 412, a sub-adder 413 and a sub-adder 414, and the sub-adder 411, the sub-adder 412, the sub-adder 413 and the sub-adder 414 are connected in sequence; the sub-adder 411 includes: a two-choice selector 4111, an accurate adder 411 2. Approximate adder 4113, the two-choice selector 4111 is connected to the precise adder 4112 and the approximate adder 4113 respectively, and the precise adder 4112 is connected to the approximate adder 4113; the sub-adder 412 includes: a two-choice selector 4121, a precise adder 4122, an approximate adder 4123, the two-choice selector 4121 is connected to the precise adder 4122, the approximate adder 4123 and the two-choice The selector 4111 is connected respectively, the precise adder 4122 is connected respectively with the approximate adder 4123 and the precise adder 4112; the sub-adder 413 includes: a two-choice selector 4131, a precise adder 4132, an approximate adder 4133, the two-choice selector 4131 is connected respectively with the precise adder 4132, the approximate adder 4133 and the two-choice selector 4121, the precise adder 4122 is connected with the approximate adder 4133 The quasi-adder 4123 and the precise adder 4122 are connected respectively; the sub-adder 414 includes: a two-to-one selector 4141, a precise adder 4142, and an approximate adder 4143. The two-to-one selector 4141 is connected to the precise adder 4142, the approximate adder 4143 and the two-to-one selector 4131 respectively, and the precise adder 4142 is connected to the approximate adder 4143 and the precise adder 4132 respectively.

[0062] As an example, the two-to-one selector 4111, the two-to-one selector 4121, the two-to-one selector 4131 and the two-to-one selector 4141 are all MUXs.

[0063] Specifically, the two-choice selector 4111, the two-choice selector 4121, the two-choice selector 4131 and the two-choice selector 4141 receive the precision control signal from the approximate analysis configuration unit 32, and each precision control signal controls the two-choice selector to select the block adder to be used in a one-to-one correspondence manner. The approximate adders do not propagate carry, and only when the precision control signal is 0000, the precise adder is used to output the precise result, and the other precision control signals output the addition results of different approximate degrees; when the precision control signal is 0001, the approximate adder is selected from the first sub-adder from the low position to the high position; when the precision control signal is 0011, the approximate adder is selected from the first and second sub-adders from the low position to the high position; when the precision control signal is 0111, the approximate adder is selected from the first, second and third sub-adders from the low position to the high position; when the precision control signal is 1111, the approximate adder is used to output the approximate result. As the number of 1s in the precision control signal increases, it also indicates that the difference between the exponents of the two input floating-point numbers is too large, and more approximate adders can be used to achieve the purpose of controllable precision.

[0064] Furthermore, the sign bit adopts an XOR operation, and finally the approximate floating point addition module 4 outputs the partial sum result. The approximate floating point multiplication result is a floating point number.

[0065] In this embodiment, two single-precision floating-point numbers are taken as an example, and the approximate floating-point multiplication and accumulation circuit of this embodiment is used to complete an approximate floating-point multiplication and accumulation calculation. Assume that there are multiple groups of data for multiplication and accumulation calculation, and this time the calculation is performed for the next group of data. First, the preprocessing module 5 inputs the single-precision floating point number A (decimal 1.3867, binary 0011 1111 10110001 0111 1111 0110 0011) and the single-precision floating point number B (decimal 0.895, binary 0011 1111 01100101 0001 1110 1011 1000), after data preprocessing, the sign bit sign_A (0), exponent part exp_A (01111111) and mantissa part mant_A (10110001011111101100011) of the single-precision floating-point number A, as well as the sign bit sign_B (0), exponent part exp_B (01111110) and mantissa part mant_B (111001010001111010111000) of the single-precision floating-point number B are obtained. The preprocessing results are all output to the approximate floating-point multiplication module 2.

[0066] Next, the exponent part exp_A of the single-precision floating-point number A and the exponent part exp_B of the single-precision floating-point number B enter the approximate floating-point multiplier precision arbitration module 1. The exponent receiver 111 receives the exponent parts of the two single-precision floating-point numbers and sends them to the leading one detector 112 to obtain the highest bit LOD_A (0111) and LOD_B (0111) where 1 is located in the exponent bits of the two single-precision floating-point numbers. The difference obtained by subtracting the difference through the subtractor 113 is 0, and the multiplexer selector 114 outputs a signal 10 according to the difference being 0, and then the signal 10 is parsed into a precision control signal 11 through the approximate parsing configuration unit 12.

[0067] Secondly, the precision control signal 11 is input into the approximate floating-point multiplication module 2, and the approximate floating-point multiplication module 2 performs mantissa multiplication calculation, exponent addition calculation and sign bit determination of the single-precision floating-point number A and the single-precision floating-point number B. According to the precision control signal 11, the composition scheme of all 25-bit adders 211-21n of the adder array 21 in the approximate floating-point multiplication module 2 is a low-12-bit approximate adder and a high-13-bit approximate adder. After the adder array 21, the mantissa multiplication result is output: 100111101111111100100000. The exponent part is added using a precise adder and shifted to obtain 011111111, and the sign bit is XORed to obtain 0. Finally, the approximate floating-point multiplication module 2 outputs the approximate floating-point multiplication result C (0011 1111 1001 1110 1111 1111 0010 0000).

[0068] Assuming that the partial sum D obtained by the previous approximate floating-point addition module 4 is stored in the partial sum storage module 6, the approximate floating-point multiplication result C and the partial sum D (decimal 27.384, binary 0100 00011101 1011 0001 0010 0110 1111) obtained by the approximate floating-point multiplication module 2 enter the approximate floating-point addition module 4 for this floating-point addition calculation. Among them, the approximate floating-point multiplication result C includes: the exponent part exp_C (01111111), the sign bit sign_C (0) and the mantissa part mant_C (100111101111111100100000), and the partial sum D includes: the exponent part exp_D (10000011), the sign bit sign_D (0) and the mantissa part mant_D (110110110001001001101111).

[0069] Next, in the approximate floating-point adder precision arbitration module 3, the exponent receiver 311 receives the exponent part of the approximate floating-point multiplication result C and the partial sum D, and sends it to the leading one detector 312, and obtains the highest bit LOD_C (0111) and LOD_D (1000) where 1 is located in the exponent bit of the approximate floating-point multiplication result C and the partial sum D. The difference obtained by subtracting the difference is 1, and the multiplexer selector 314 outputs a signal 011 according to the difference being 1, and then the signal 011 is parsed into a precision control signal 0111 by the approximate parsing configuration unit 32.

[0070] Finally, the precision control signal 0111 is input to the approximate floating-point addition module 4, the sign bit is judged to be 00 according to the size of the exponent and the mantissa, and the exponent result 10000011 is obtained by aligning the approximate floating-point multiplication result C and the maximum exponent sign_D of the partial sum D, and then the mantissa mant_C is shifted to obtain (100000011110111111110010) and then the mantissa addition operation is performed. According to the precision control signal 0111, the composition scheme of the 24-bit mantissa adder is to use an accurate adder for the highest 6 bits and three 8-bit approximate adders for the lower 18 bits. After approximate calculation, the output is 1010111001111000111011111. The exponent part is also adjusted again according to the range of the mantissa to obtain the final approximate adder output part and result of 10000010 (0 1000 0010 1010 1110 0111 1000 1110 11111).

[0071] This process is a multiplication and addition calculation. The partial sum result obtained by each multiplication and addition calculation is stored in the register for the next multiplication and addition calculation. After multiple cycles, it is a multiplication and accumulation calculation until the termination signal arrives, the calculation stops, and the final multiplication and accumulation calculation result is output.

[0072] In another embodiment of the present application, the present application provides an approximate floating-point multiplication-accumulation method, which is applied to the above-mentioned approximate floating-point multiplication-accumulation circuit. Figure 8 , Figure 8 This is a flow chart of the approximate floating-point multiplication and accumulation method proposed in this application, including: steps S1 to S13.

[0073] Step S1: input a floating point number; Step S2: Input floating point number exponential analysis; Step S3: Generate configuration code; Step S4: Determine whether to use approximate calculation, if yes, proceed to step S5; if no, proceed to step S6; Step S5: approximate configuration; Step S6: adopt mantissa multiplication; Step S7: Input floating point number exponential analysis; Step S8: Generate configuration code; Step S9: Determine whether to use approximate calculation, if yes, go to step S12; if no, go to step S11; Step S10: approximate configuration; Step S11: adding the mantissas; Step S12: Determine whether the accumulation is completed, if so, proceed to step S13; if not, return to step S8; Step S13: Output the result.

[0074] The input numbers of step S7 include: the approximate floating-point multiplication result and the partial sum result obtained after the last approximate floating-point addition calculation.

[0075] The approximate floating-point multiplication and accumulation circuit and method proposed in this application can dynamically adjust the calculation process according to the characteristics of the input data, and flexibly choose to use approximate calculation or precise calculation mode. When the input data differs greatly, the circuit gives priority to precise calculation to ensure the accuracy of the calculation result; when the input data differs little, the circuit switches to approximate calculation mode to simplify the calculation process, speed up the calculation speed and reduce power consumption. This dynamic adjustment mechanism can achieve the best balance between calculation accuracy and hardware resource utilization in different application scenarios, meet the calculation accuracy of different requirements, improve the calculation speed and reduce power consumption while maintaining a certain accuracy.

[0076] Although the present application has been disclosed as above with the embodiments, it is not intended to limit the present application. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope of the attached patent application.

Claims

1. An approximate floating-point multiplication-accumulation circuit, characterized in that: include, Preprocessing module; An approximate floating-point multiplier precision arbitration module connected to the preprocessing module; An approximate floating-point multiplication module, connected to the preprocessing module and the approximate floating-point multiplier precision arbitration module respectively; An approximate floating-point adder precision arbitration module connected to the approximate floating-point multiplication module; an approximate floating-point addition module, connected to the approximate floating-point multiplication module and the approximate floating-point adder precision arbitration module respectively; A partial sum storage module is connected to the approximate floating-point addition module.

2. The approximate floating-point multiplication-accumulation circuit according to claim 1, wherein: The approximate floating-point multiplier precision arbitration module comprises: a floating-point multiplication exponent input analysis unit and a first approximate resolution configuration unit, wherein the floating-point multiplication exponent input analysis unit is connected to the first approximate resolution configuration unit.

3. The approximate floating-point multiplication-accumulation circuit according to claim 2, wherein: The floating-point multiplication exponent input analysis unit comprises: a first exponent receiver, a first leading one detector, a first subtractor and a first multiplex selector, wherein the first exponent receiver, the first leading one detector, the first subtractor and the first multiplex selector are connected in sequence.

4. The approximate floating-point multiplication-accumulation circuit according to claim 2, wherein: The first approximate analysis configuration unit includes: a first shift controller and a first 4-bit shift register, and the first shift controller and the first 4-bit shift register are connected in sequence.

5. The approximate floating-point multiplication-accumulation circuit according to claim 1, wherein: The approximate floating-point multiplication module comprises: an adder array, the adder array comprises n adders, each adder comprises two sub-adders, the sub-adders comprise: a first two-to-one selector, a first precise adder, and a first approximate adder, the first two-to-one selector is connected to the first precise adder and the first approximate adder respectively, the first precise adder is connected to the first approximate adder, the first two-to-one selector of each sub-adder is connected, the first precise adder of each sub-adder is connected, and the first approximate adder of each sub-adder is connected.

6. The approximate floating-point multiplication-accumulation circuit according to claim 1, characterized in that: The approximate floating-point adder precision arbitration module comprises: a floating-point addition exponent input analysis unit and a second approximate analysis configuration unit, wherein the floating-point addition exponent input analysis unit is connected to the second approximate analysis configuration unit.

7. The approximate floating-point multiplication-accumulation circuit according to claim 6, characterized in that: The floating-point addition exponent input analysis unit comprises: a second exponent receiver, a second leading one detector, a second subtractor and a second multiplexer selector, wherein the second exponent receiver, the second leading one detector, the second subtractor and the second multiplexer selector are connected in sequence.

8. The approximate floating-point multiplication-accumulation circuit according to claim 6, characterized in that: The second approximate analysis configuration unit includes: a second shift controller and a second 4-bit shift register, and the second shift controller and the second 4-bit shift register are connected in sequence.

9. The approximate floating-point multiplication-accumulation circuit according to claim 1, characterized in that: The approximate floating-point addition module includes: four sub-adders, each sub-adder includes: a second two-to-one selector, a second precise adder, and a second approximate adder, the second two-to-one selector is connected to the second precise adder and the second approximate adder respectively, the second precise adder is connected to the second approximate adder, the second two-to-one selector of each sub-adder is connected, the second precise adder of each sub-adder is connected, and the second approximate adder of each sub-adder is connected.

10. An approximate floating-point multiplication and accumulation method, characterized in that: The approximate floating-point multiplication-accumulation circuit according to any one of claims 1 to 9 comprises: Step S1: input a floating point number; Step S2: Input floating point number exponential analysis; Step S3: Generate configuration code; Step S4: Determine whether to use approximate calculation, if yes, proceed to step S5; if no, proceed to step S6; Step S5: approximate configuration; Step S6: adopt mantissa multiplication; Step S7: Input floating point number exponential analysis; Step S8: Generate configuration code; Step S9: Determine whether to use approximate calculation, if yes, go to step S12; if no, go to step S11; Step S10: approximate configuration; Step S11: adding the mantissas; Step S12: Determine whether the accumulation is completed, if so, proceed to step S13; if not, return to step S8; Step S13: Output the result.

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