Edge detection system module division method and division system
Through the FPGA-based edge detection system module division method, the problem of poor code readability and reusability in the prior art is solved, real-time image acquisition and edge detection are realized, and work efficiency is improved.
Patent Information
- Application Number
- CN202411823659.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-04-08
AI Technical Summary
In the division of edge detection engineering modules in the prior art, code readability and reusability are poor, and it is impossible to effectively reduce repeated work between multiple designs, and the work efficiency is low.
The edge detection system module division method based on FPGA is adopted, and the real-time image acquisition, edge detection, storage and serial port functions are realized through functional requirements, hardware system structure block diagram, interface conversion module design, instruction system design, register configuration, independent module addition and rate matching design.
Improves the readability and reusability of the code, reduces repeated work between multiple designs, and improves work efficiency.
Smart Images
Figure CN119781738A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of image processing systems, and in particular relates to an edge detection system module division method and a division system. Background Art
[0002] Digital image processing refers to the process of converting image signals into digital signals and processing them using computers. Image processing first appeared in the 1950s, when computers had developed to a certain level and people began to use computers to process graphics and image information. Digital image processing as a discipline was formed in the early 1960s. The purpose of early image processing was to improve the quality of images. It took people as the object and aimed to improve people's visual effects. In image processing, the input is a low-quality image and the output is an improved image. Commonly used image processing methods include image enhancement, restoration, encoding, compression, etc.
[0003] Edge detection is a basic problem in image processing and computer vision. The purpose of edge detection is to identify points in digital images where brightness changes significantly. Image edge detection greatly reduces the amount of data and removes information that can be considered irrelevant, retaining important structural properties of the image.
[0004] The essence of edge detection is to use an algorithm to extract the boundary between the object and the background in the image. We define the edge as the boundary of the area where the grayscale changes sharply in the image. The change of the image grayscale can be reflected by the gradient of the image grayscale distribution. The classic edge detection method is to construct an edge detection operator for a small neighborhood of pixels in the original image to achieve the purpose of edge detection.
[0005] Through the above analysis, the problems and defects of the existing technology are as follows: in the module division of the edge detection engineering in the existing technology, the code readability and reusability are poor in terms of real-time image acquisition, edge detection, storage and serial port functions, and it cannot effectively reduce the duplication of work between multiple designs, resulting in low work efficiency. Summary of the invention
[0006] In order to overcome the problems existing in the related art, the disclosed embodiments of the present invention provide a module partitioning method and a partitioning system for an edge detection system, and specifically relate to a module partitioning method for an edge detection system based on FPGA.
[0007] The technical solution is as follows: a method for dividing edge detection system modules, comprising:
[0008] S1, lists the functional requirements. After the system is powered on, the camera transmits the real-time collected image data to the FPGA, and the edge image is obtained after FPGA processing, and the edge image is output to the display;
[0009] S2, constructing a hardware system structure diagram, and obtaining peripheral devices required in addition to the FPGA according to the functional requirements of step S1, wherein the peripheral devices include buttons, cameras, and displays;
[0010] S3, design the interface conversion module; the interface conversion module corresponding to the button adopts the button debounce detection module, and the interface conversion module corresponding to the OV7670 camera adopts the OV7670 image acquisition module; the display is connected to the FPGA through the VGA interface, and the corresponding interface conversion module adopts the VGA display driver module;
[0011] S4, design the instruction system, the host computer sends instructions to the FPGA, configures the acquisition resolution, and configures the upper and lower limits of image acquisition;
[0012] S5, peripheral devices perform register configuration;
[0013] S6, according to the actual situation, add, supplement or split the independent corresponding modules, and adjust the independent corresponding modules at any time according to the data flow;
[0014] S7, perform rate matching design.
[0015] Step S1 specifically includes:
[0016] S101, uses camera OV7670 to realize image acquisition;
[0017] S102, the internal registers of the camera are configured by powering on the buttons configured by the peripherals;
[0018] S103, the FPGA processes the edge detection algorithm to obtain an edge image;
[0019] S104: Output the edge image to a display.
[0020] In step S3, the OV7670 camera performs register configuration using an architecture consisting of a register configuration table module, a register read and write configuration module, and a peripheral configuration interface timing conversion module; the configuration interface of the peripheral OV7670 camera and the external interface of the peripheral configuration interface timing conversion module both use the SCCB protocol for data transmission.
[0021] In step S6, adding an independent corresponding module includes:
[0022] S601, add RGB to grayscale module to convert the image data RGB565 format output by OV7670 image acquisition module into grayscale image;
[0023] S602, adding a Gaussian filter module to perform Gaussian filter processing on the output image grayscale data;
[0024] S603, adding a grayscale to single-bit module to convert the grayscale image data after Gaussian filtering into single-bit data;
[0025] S604, adding a Sobel algorithm processing module, processing the converted single-bit data through the Sobel algorithm to obtain the image edge;
[0026] S605, adding an image cache module to cache the image data output by the Sobel algorithm processing module, and output a continuous, complete, and uninterrupted image to the display.
[0027] In step S7, rate matching design is performed, including:
[0028] S701, setting an RDY signal on the interface for peripheral device communication, and setting a handshake signal between the peripheral configuration interface timing conversion module and the register read / write configuration module;
[0029] S702, in response to the mismatch in operating rates between modules within the FPGA, a FIFO is set on the image cache module.
[0030] In step S701, a handshake signal is set between the peripheral configuration interface timing conversion module and the register read / write configuration module, including:
[0031] The register read / write configuration module uses the handshake particle random number generator to generate a binary handshake request random number, encrypts the binary data with the random number, and stores it in the FPGA; the register read / write configuration module and the FPGA handshake and respond to the binary key through the handshake particle key distribution protocol; the register read / write configuration module encrypts the handshake response key with the random number and sends it to the FPGA as the conversion key, the FPGA encrypts the conversion key with the handshake response key as the final conversion key, and uses the final conversion key to convert the encrypted data stored in the FPGA into the secret data of the handshake response of the peripheral configuration interface timing conversion module, and the peripheral configuration interface timing conversion module decrypts it with its own key and performs a data handshake response.
[0032] Further, the register read / write configuration module generates an n-bit binary handshake request random number F using the handshake particle random number generator, and encrypts the n-bit binary data E using F and stores it in the FPGA;
[0033] The register read / write configuration module and the FPGA use the handshake particle key distribution protocol to handshake and respond to the 2n-bit binary key H;
[0034] The register read and write configuration module encrypts its own key H with the random number R A As the conversion key is sent to the FPGA, the FPGA uses H gThe encryption conversion key is used as the final conversion key, and the encrypted data stored in the FPGA is converted into secret data of the handshake response of the peripheral configuration interface timing conversion module by using the final conversion key. The peripheral configuration interface timing conversion module decrypts with its own key and performs a data handshake response;
[0035] The encrypted data of the storage register read and write configuration module on the FPGA is:
[0036]
[0037] U A ∈{1,0} n
[0038] F∈{1,0} n
[0039] Where U A To encrypt data value, is the XOR operator symbol, E is the binary data, and F is the binary handshake request random number.
[0040] Furthermore, the handshake method between the peripheral configuration interface timing conversion module and the register read and write configuration module specifically includes:
[0041] Step 1: The register read / write configuration module prepares 2n handshake exchange states according to H, where H is the binary key; 1 is prepared as ξ + state, 0 is prepared as τ - state; among them,
[0042] Step 2: The register read-write configuration module retains one particle in each handshake exchange state and sends the other particle to the peripheral configuration interface timing conversion module;
[0043] Step 3: The peripheral configuration interface timing conversion module randomly selects V-based measurement or reflection operation for each particle received; the peripheral configuration interface timing conversion module saves the measurement result and converts the measurement result into a binary key H B ;
[0044] Step 4: The register read-write configuration module performs a joint handshake exchange measurement on the reflected particles and the corresponding retained particles. If the measured result is consistent with the originally prepared handshake exchange state, or the inconsistency ratio is lower than a predetermined threshold, the protocol continues, otherwise the protocol terminates.
[0045] Step 5: The register read-write configuration module uses the V basis to measure the particle where the reflected particle is not received and saves the measurement result. The register read-write configuration module converts the measurement result into a binary key H A ;
[0046] Step 6: Register read and write configuration module uses K to encrypt the conversion key And the position information S of the reflected particle is not received, and the Encrypt H (f H , S), and send the result to FPGA; f H To convert the key, Encrypt H () is the encoding function after encrypting the position information S of the reflected particle without receiving it;
[0047] Step 7: FPGA uses H to decrypt Encrypt H (f H , S) to obtain the conversion key and position information S; according to the position information S, FPGA intercepts the binary bit at the corresponding position in H and obtains H g , by calculating Get the final conversion key H g is the key to intercept the binary bit at the corresponding position in H, g is the corresponding position of the position information S, H B A binary key for converting the measurement result to a timing conversion module for a peripheral configuration interface;
[0048] Step 8: FPGA reads and writes the data ciphertext of the configuration module into the register Converted into ciphertext for the peripheral configuration interface timing conversion module And put U B Sent to the peripheral configuration interface timing conversion module, the peripheral configuration interface timing conversion module uses its own key K B Decrypt to obtain the handshake response data; E is binary data.
[0049] In step S702, the image buffer module sets two FIFOs.
[0050] Another object of the present invention is to provide an edge detection system module division system, the system implements the edge detection system module division method, the system comprising:
[0051] Functional requirement unit, used to list functional requirements. After the system is powered on, the camera transmits the real-time collected image data to the FPGA, obtains the edge image after FPGA processing, and outputs the edge image to the display;
[0052] Construct a hardware system structure frame unit, which is used to construct a hardware system structure block diagram, and obtain peripheral devices required in addition to FPGA according to functional requirements, where the peripheral devices include buttons, cameras, and displays;
[0053] The interface conversion module design unit is used to design the interface conversion module; the interface conversion module corresponding to the button adopts the button debounce detection module, and the interface conversion module corresponding to the OV7670 camera adopts the OV7670 image acquisition module; the display is connected to the FPGA through the VGA interface, and the corresponding interface conversion module adopts the VGA display driver module;
[0054] The instruction design unit is used to design the instruction system. The host computer sends instructions to the FPGA to configure the acquisition resolution and the upper and lower limits of image acquisition.
[0055] A register configuration unit, used for peripheral devices to configure registers;
[0056] An independent corresponding module adding unit is used to add, supplement or split the independent corresponding module according to the actual situation, and adjust the independent corresponding module at any time according to the data flow direction;
[0057] The rate matching unit is used for rate matching design.
[0058] In combination with all the above technical solutions, the beneficial effects of the present invention are as follows: the present invention provides an edge detection engineering module partitioning method based on FPGA, which realizes real-time image acquisition, edge detection algorithm, storage control and serial port functions. The present invention can use local image differential technology to obtain edge detection operators. Through this partitioning method, the code has better readability, it is easier to understand the design functions and the flow between data, it is easier to debug the code, it has better reusability, can reduce duplication between multiple designs, avoid duplication, and improve work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0059] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;
[0060] Figure 1 is a schematic diagram of a module division method for an edge detection system provided by an embodiment of the present invention;
[0061] Figure 2 It is a block diagram of the hardware system structure provided by the embodiment of the present invention;
[0062] Figure 3 is a block diagram of a designed interface conversion module provided by an embodiment of the present invention;
[0063] Figure 4 It is a block diagram of register configuration of a peripheral device provided by an embodiment of the present invention;
[0064] Figure 5It is a block diagram of adding, supplementing or splitting independent corresponding modules provided by an embodiment of the present invention;
[0065] Figure 6 The present invention provides a block diagram of setting a FIFO on an image cache module according to an embodiment of the present invention. DETAILED DESCRIPTION
[0066] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.
[0067] Embodiment 1, as Figure 1 As shown, the edge detection system module division method provided by the embodiment of the present invention includes:
[0068] S1, lists the functional requirements. After the system is powered on, the camera transmits the real-time collected image data to the FPGA, and the edge image is obtained after FPGA processing, and the edge image is output to the display;
[0069] Specifically include:
[0070] S101, camera OV7670 is selected as image acquisition;
[0071] S102, the internal registers of the camera are configured by powering on the buttons configured by the peripherals;
[0072] S103, the FPGA processes the edge detection algorithm to obtain an edge image;
[0073] S104, outputting the edge image to a display (using a VGA interface);
[0074] S2, constructing a hardware system structure diagram, and obtaining peripheral devices required in addition to the FPGA according to the functional requirements of step S1, wherein the peripheral devices include buttons, cameras, and displays;
[0075] The hardware system structure diagram is as follows: Figure 2 As shown;
[0076] S3, design the interface conversion module; the interface conversion module corresponding to the button adopts the button debounce detection module, and the interface conversion module corresponding to the OV7670 camera adopts the OV7670 image acquisition module; the display is connected to the FPGA through the VGA interface, and the corresponding interface conversion module adopts the VGA display driver module;
[0077] The block diagram after the interface conversion module is designed is as follows: Figure 3 As shown;
[0078] S4, design the instruction system, the host computer sends instructions to the FPGA, configures the acquisition resolution, and configures the upper and lower limits of image acquisition;
[0079] The present invention relates to an instruction system, and the host computer needs to send instructions to the FPGA to configure the acquisition resolution, the upper and lower limits of image acquisition, and can also send instructions to control the display screen to turn off. Therefore, preferably, a register analysis module needs to be added to the hardware system structure diagram.
[0080] S5, peripheral devices perform register configuration;
[0081] OV7670 camera register configuration. Use the architecture of register configuration table module + register read and write configuration module + peripheral configuration interface timing conversion module to configure the register;
[0082] Since the configuration interface of the peripheral OV7670 camera uses the SCCB protocol, the external interface of the peripheral configuration interface timing conversion module should also be SCCB, and the internal interface should be a standard interface. Figure 4 shown.
[0083] S6, according to the actual situation, add, supplement or split the independent corresponding modules, and adjust the independent corresponding modules at any time according to the data flow;
[0084] Conduct detailed analysis on the interfaces between independent corresponding modules, supplement independent corresponding modules or merge and simplify independent corresponding modules with the same functions. Specifically include:
[0085] S601, we need to design a RGB to grayscale module. The image data output by the OV7670 image acquisition module is in RGB565 format. We need to convert the RGB565 signal into a grayscale image first.
[0086] S602, a Gaussian filter module is required; the output image grayscale data needs to be processed by Gaussian filtering;
[0087] S603, in order to perform edge detection, the grayscale image data after Gaussian filtering needs to be converted into single-bit data, so a grayscale to single-bit module is required;
[0088] S604, the converted single-bit data needs to be processed by the Sobel algorithm to obtain the image edge, so a Sobel algorithm processing module is required;
[0089] S605, the image data output by the Sobel algorithm processing module can be output to the display, but in order to output the image continuously and completely without interruption, it needs to be cached, so an image cache module is needed. Add, supplement or split the independent corresponding module block diagram as shown in Figure 5 As shown;
[0090] S7, perform rate matching design;
[0091] S701, set the RDY signal on the interface for peripheral device communication. The SCCB protocol used by the OV7670 configuration interface has an operating frequency of 100K, which is much lower than the FPGA internal system operating frequency of 25M. Therefore, a handshake signal needs to be set between the peripheral configuration interface timing conversion module and the register read and write configuration module.
[0092] S702, in response to the mismatch in operating rates between modules within the FPGA, a FIFO is set on the image cache module;
[0093] Specifically, the image data output by the Sobel algorithm processing module is sent to the image cache module. The image cache module needs to wait to cache a complete image, so a FIFO needs to be set up. In order to complete the ping-pong operation, two FIFOs need to be set up to write a complete image data to FIFO A, while the VGA display driver module can read the cached complete image data in FIFO B. Therefore, the image cache module needs to have two FIFOs. The FIFOs set on the image cache module are as follows: Figure 6 shown.
[0094] Embodiment 2, illustratively, in step S701, in setting a handshake signal between the peripheral configuration interface timing conversion module and the register read / write configuration module, the method for handshaking between the peripheral configuration interface timing conversion module and the register read / write configuration module includes:
[0095] The register read / write configuration module uses the handshake particle random number generator to generate a binary handshake request random number, encrypts the binary data with the random number, and stores it in the FPGA; the register read / write configuration module and the FPGA handshake and respond to the binary key through the handshake particle key distribution protocol; the register read / write configuration module encrypts the handshake response key with a random number and sends it to the FPGA as a conversion key, the FPGA encrypts the conversion key with the handshake response key as the final conversion key, and uses the final conversion key to convert the encrypted data stored in the FPGA into secret data that the peripheral configuration interface timing conversion module can handshake and respond to, the peripheral configuration interface timing conversion module decrypts it with its own key, and performs a data handshake response.
[0096] The register read / write configuration module generates an n-bit binary handshake request random number F using the handshake particle random number generator, encrypts the n-bit binary data E with F, and stores it in the FPGA;
[0097] The register read / write configuration module and the FPGA use the handshake particle key distribution protocol to handshake and respond to the 2n-bit binary key H;
[0098] The register read and write configuration module encrypts its own key H with the random number R A As the conversion key is sent to the FPGA, the FPGA uses H g The encryption conversion key is used as the final conversion key, and the encrypted data stored in the FPGA is converted into secret data that the peripheral configuration interface timing conversion module can handshake and respond to using the final conversion key. The peripheral configuration interface timing conversion module decrypts with its own key and performs a data handshake response.
[0099] The encrypted data of the storage register read and write configuration module on the FPGA is:
[0100]
[0101] U A ∈{1,0} n
[0102] F∈{1,0} n
[0103] Where U A To encrypt data value, is the XOR operator symbol, E is the binary data, and F is the binary handshake request random number.
[0104] The handshake method between the peripheral configuration interface timing conversion module and the register read and write configuration module specifically includes:
[0105] Step 1: The register read / write configuration module prepares 2n handshake exchange states according to H, where H is the binary key; 1 is prepared as ξ + state, 0 is prepared as τ - state; among them,
[0106] Step 2: The register read-write configuration module retains one particle in each handshake exchange state and sends the other particle to the peripheral configuration interface timing conversion module;
[0107] Step 3: The peripheral configuration interface timing conversion module randomly selects V-based measurement or reflection operation for each particle received; the peripheral configuration interface timing conversion module saves the measurement result and converts the measurement result into a binary key H B ;
[0108] Step 4: The register read-write configuration module performs a joint handshake exchange measurement on the reflected particles and the corresponding retained particles. If the measured result is consistent with the originally prepared handshake exchange state, or the inconsistency ratio is lower than a predetermined threshold, the protocol continues, otherwise the protocol terminates.
[0109] Step 5: The register read-write configuration module uses the V basis to measure the particle where the reflected particle is not received and saves the measurement result. The register read-write configuration module converts the measurement result into a binary key H A ;
[0110] Step 6: Register read and write configuration module uses K to encrypt the conversion key And the position information S of the reflected particle is not received, and the Encrypt H (f H , S), and send the result to FPGA; f H To convert the key, Encrypt H () is the encoding function after encrypting the position information S of the reflected particle without receiving it;
[0111] Step 7: FPGA uses H to decrypt Encrypt H (f H , S) get the conversion key and position information S; according to the position information S, FPGA intercepts the binary bit at the corresponding position in H and obtains H g , by calculating Get the final conversion key H g is the key to intercept the binary bit at the corresponding position in H, g is the corresponding position of the position information S, H B A binary key for converting the measurement result to a timing conversion module for a peripheral configuration interface;
[0112] Step 8: FPGA reads and writes the data ciphertext of the configuration module into the register Converted into ciphertext for the peripheral configuration interface timing conversion module And put U B Sent to the peripheral configuration interface timing conversion module, the peripheral configuration interface timing conversion module uses its own key K B Decrypt to obtain the handshake response data; E is binary data.
[0113] Without decrypting the data ciphertext, the ciphertext of the register read and write configuration module is converted into the ciphertext of the peripheral configuration interface timing conversion module, so that the peripheral configuration interface timing conversion module can use its private key to decrypt and obtain the plaintext of the register read and write configuration module data. The register read and write configuration module in the scheme should have the ability to generate handshake exchange states, perform handshake exchange basis and V basis measurements, and store handshake particle bits. The scheme reduces the handshake particle requirements of the peripheral configuration interface timing conversion module, and requires the ability to reflect and perform V basis measurements. The scheme theoretically achieves one-time one-key, especially when the same data is responded to by multiple handshakes, it achieves anti-collision security. Flexible handshake responses for fine-grained secret data are achieved.
[0114] This invention does not require the preparation of multi-particle entangled states, nor does it require Fourier transform of handshake particles, thus reducing the complexity and difficulty of implementation.
[0115] Embodiment 3, the embodiment of the present invention provides an edge detection system module division system, including:
[0116] Functional requirement unit, used to list functional requirements. After the system is powered on, the camera transmits the real-time collected image data to the FPGA, obtains the edge image after FPGA processing, and outputs the edge image to the display;
[0117] Construct a hardware system structure frame unit, which is used to construct a hardware system structure block diagram, and obtain peripheral devices required in addition to FPGA according to functional requirements, where the peripheral devices include buttons, cameras, and displays;
[0118] The interface conversion module design unit is used to design the interface conversion module; the interface conversion module corresponding to the button adopts the button debounce detection module, and the interface conversion module corresponding to the OV7670 camera adopts the OV7670 image acquisition module; the display is connected to the FPGA through the VGA interface, and the corresponding interface conversion module adopts the VGA display driver module;
[0119] The instruction design unit is used to design the instruction system. The host computer sends instructions to the FPGA to configure the acquisition resolution and the upper and lower limits of image acquisition.
[0120] A register configuration unit, used for peripheral devices to configure registers;
[0121] An independent corresponding module adding unit is used to add, supplement or split the independent corresponding module according to the actual situation, and adjust the independent corresponding module at any time according to the data flow direction;
[0122] The rate matching unit is used for rate matching design.
[0123] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.
Claims
1. A method for dividing modules of an edge detection system, characterized in that: The method includes: S1, lists the functional requirements. After the system is powered on, the camera transmits the real-time collected image data to the FPGA, and the edge image is obtained after FPGA processing, and the edge image is output to the display; S2, constructing a hardware system structure diagram, and obtaining peripheral devices required in addition to the FPGA according to the functional requirements of step S1, wherein the peripheral devices include buttons, cameras, and displays; S3, design the interface conversion module; the interface conversion module corresponding to the button adopts the button debounce detection module, and the interface conversion module corresponding to the OV7670 camera adopts the OV7670 image acquisition module; the display is connected to the FPGA through the VGA interface, and the corresponding interface conversion module adopts the VGA display driver module; S4, design the instruction system, the host computer sends instructions to the FPGA, configures the acquisition resolution, and configures the upper and lower limits of image acquisition; S5, peripheral devices perform register configuration; S6, according to the actual situation, add, supplement or split the independent corresponding modules, and adjust the independent corresponding modules at any time according to the data flow; S7, perform rate matching design.
2. The edge detection system module division method according to claim 1, characterized in that: Step S1 specifically includes: S101, uses camera OV7670 to realize image acquisition; S102, the internal registers of the camera are configured by powering on the buttons configured by the peripherals; S103, the FPGA processes the edge detection algorithm to obtain an edge image; S104: Output the edge image to a display.
3. The edge detection system module division method according to claim 1, characterized in that: In step S3, the OV7670 camera performs register configuration using an architecture consisting of a register configuration table module, a register read and write configuration module, and a peripheral configuration interface timing conversion module; the configuration interface of the peripheral OV7670 camera and the external interface of the peripheral configuration interface timing conversion module both use the SCCB protocol for data transmission.
4. The edge detection system module division method according to claim 1, characterized in that: In step S6, adding an independent corresponding module includes: S601, add RGB to grayscale module to convert the image data RGB565 format output by OV7670 image acquisition module into grayscale image; S602, adding a Gaussian filter module to perform Gaussian filter processing on the output image grayscale data; S603, adding a grayscale to single-bit module to convert the grayscale image data after Gaussian filtering into single-bit data; S604, adding a Sobel algorithm processing module, processing the converted single-bit data through the Sobel algorithm to obtain the image edge; S605, adding an image cache module to cache the image data output by the Sobel algorithm processing module, and output a continuous, complete, and uninterrupted image to the display.
5. The edge detection system module division method according to claim 1, characterized in that: In step S7, rate matching design is performed, including: S701, setting an RDY signal on the interface for peripheral device communication, and setting a handshake signal between the peripheral configuration interface timing conversion module and the register read / write configuration module; S702, in response to the mismatch in operating rates between modules within the FPGA, a FIFO is set on the image cache module.
6. The edge detection system module division method according to claim 5, characterized in that: In step S701, a handshake signal is set between the peripheral configuration interface timing conversion module and the register read / write configuration module, including: The register read / write configuration module uses the handshake particle random number generator to generate a binary handshake request random number, encrypts the binary data with the random number, and stores it in the FPGA; the register read / write configuration module and the FPGA handshake and respond to the binary key through the handshake particle key distribution protocol; the register read / write configuration module encrypts the handshake response key with the random number and sends it to the FPGA as the conversion key, the FPGA encrypts the conversion key with the handshake response key as the final conversion key, and uses the final conversion key to convert the encrypted data stored in the FPGA into the secret data of the handshake response of the peripheral configuration interface timing conversion module, and the peripheral configuration interface timing conversion module decrypts it with its own key and performs a data handshake response.
7. The edge detection system module division method according to claim 6, characterized in that: The register read / write configuration module generates an n-bit binary handshake request random number F using the handshake particle random number generator, encrypts the n-bit binary data E with F, and stores it in the FPGA; The register read / write configuration module and the FPGA use the handshake particle key distribution protocol to handshake and respond to the 2n-bit binary key H; The register read and write configuration module encrypts its own key H with the random number R A As the conversion key is sent to the FPGA, the FPGA uses H g The encryption conversion key is used as the final conversion key, and the encrypted data stored in the FPGA is converted into secret data of the handshake response of the peripheral configuration interface timing conversion module by using the final conversion key. The peripheral configuration interface timing conversion module decrypts with its own key and performs a data handshake response; The encrypted data of the storage register read and write configuration module on the FPGA is: IN A =E⊕F U A ∈{1,0} n F∈{1,0} n Where U A is the encrypted data value, ⊕ is the XOR operator, E is the binary data, and F is the binary handshake request random number.
8. The edge detection system module division method according to claim 7, characterized in that: The handshake method between the peripheral configuration interface timing conversion module and the register read and write configuration module specifically includes: Step 1: The register read / write configuration module prepares 2n handshake exchange states according to H, where H is the binary key; 1 is prepared as ξ + state, 0 is prepared as τ - state; among them, Step 2: The register read-write configuration module retains one particle in each handshake exchange state and sends the other particle to the peripheral configuration interface timing conversion module; Step 3: The peripheral configuration interface timing conversion module randomly selects V-based measurement or reflection operation for each particle received; the peripheral configuration interface timing conversion module saves the measurement result and converts the measurement result into a binary key H B ; Step 4: The register read-write configuration module performs a joint handshake exchange measurement on the reflected particles and the corresponding retained particles. If the measured result is consistent with the originally prepared handshake exchange state, or the inconsistency ratio is lower than a predetermined threshold, the protocol continues, otherwise the protocol terminates. Step 5: The register read-write configuration module uses the V basis to measure the particle where the reflected particle is not received and saves the measurement result. The register read-write configuration module converts the measurement result into a binary key H A ; Step 6: Register read and write configuration module uses K to encrypt the conversion key f H =F⊕H A And the position information S of the reflected particle is not received, and the Encrypt H (f H ,S), and send the result to FPGA; f H To convert the key, Encrypt H () is the encoding function after encrypting the position information S of the reflected particle without receiving it; Step 7: FPGA uses H to decrypt Encrypt H (f H ,S) get the conversion key f H =F⊕H A and position information S; according to the position information S, FPGA intercepts the binary bit at the corresponding position in H and obtains H g , by calculating Get the final conversion key H g is the key to intercept the binary bit at the corresponding position in H, g is the corresponding position of the position information S, H B A binary key for converting the measurement result to a timing conversion module for a peripheral configuration interface; Step 8: FPGA reads and writes the data ciphertext U of the configuration module into the register A =F⊕E is converted into the ciphertext for the peripheral configuration interface timing conversion module And put U B Sent to the peripheral configuration interface timing conversion module, the peripheral configuration interface timing conversion module uses its own key K B Decrypt to obtain the handshake response data; E is binary data.
9. The edge detection system module division method according to claim 5, characterized in that: In step S702, the image buffer module sets two FIFOs.
10. A module division system for an edge detection system, characterized in that: The system implements the edge detection system module division method according to any one of claims 1 to 9, and the system comprises: Functional requirement unit, used to list functional requirements. After the system is powered on, the camera transmits the real-time collected image data to the FPGA, obtains the edge image after FPGA processing, and outputs the edge image to the display; Construct a hardware system structure frame unit, which is used to construct a hardware system structure block diagram, and obtain peripheral devices required in addition to FPGA according to functional requirements, where the peripheral devices include buttons, cameras, and displays; The interface conversion module design unit is used to design the interface conversion module; the interface conversion module corresponding to the button adopts the button debounce detection module, and the interface conversion module corresponding to the OV7670 camera adopts the OV7670 image acquisition module; the display is connected to the FPGA through the VGA interface, and the corresponding interface conversion module adopts the VGA display driver module; The instruction design unit is used to design the instruction system. The host computer sends instructions to the FPGA to configure the acquisition resolution and the upper and lower limits of image acquisition. A register configuration unit, used for peripheral devices to configure registers; An independent corresponding module adding unit is used to add, supplement or split the independent corresponding module according to the actual situation, and adjust the independent corresponding module at any time according to the data flow direction; The rate matching unit is used for rate matching design.