Cache management unit verification method, electronic device and device

Abstract

This application provides a cache management unit verification method, electronic device, and apparatus, relating to the field of testing technology. The method is applied to a verification platform, which predefines logical units, actions to be executed for each logical unit, and a first signal that each logical unit needs to transmit to the cache management unit to implement the action. Each logical unit performs the following steps: executing the target action corresponding to the logical unit; sending the first signal corresponding to the target action to the cache management unit, so that the cache management unit responds to the first signal to allocate or reclaim cache resources requested by the target action, and feeds back a second signal indicating the result of the cache resource allocation or reclamation; receiving the second signal; and verifying the correctness of the cache management unit's processing result for the target action based on the second signal. The solution provided by this application can efficiently and comprehensively verify the cache management unit.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a cache management unit verification method, electronic equipment and device. Background Art

[0002] The cache management unit is responsible for managing the scheduling of cache resources in the chip by other logic units, and is used to maintain key tasks such as data storage, access and management of the chip. As the amount of data that the chip needs to process increases, the cache resources occupied by the data increase, and the amount of cache resources that the cache management unit needs to schedule also increases. The correctness of the cache management unit's scheduling of cache resources seriously affects the overall performance and stability of the chip. Therefore, in order to ensure that the cache management unit can correctly schedule cache resources and ensure the normal operation of the chip, the cache management unit needs to be verified.

[0003] In order to verify the cache management unit, a cache management unit verification method needs to be provided. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a cache management unit verification method, electronic device and device to verify the cache management unit. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a cache management unit verification method, which is applied to a verification platform, wherein the verification platform predefines a logic unit, a behavior to be executed corresponding to each logic unit, and a first signal that each logic unit needs to transmit to the cache management unit to implement the behavior, wherein the behavior is: the corresponding logic unit requests the cache management unit to allocate cache resources or requests the cache management unit to recycle cache resources;

[0006] Each logical unit performs the following steps:

[0007] Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recycling requested by the target behavior, and feeds back a second signal indicating the cache resource allocation or recycling result;

[0008] receiving the second signal;

[0009] According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

[0010] In one embodiment of the present application, a behavior pool is further defined in the verification platform, and a data transmission interface connected to the cache management unit exists in the behavior pool, and sending a first signal corresponding to the target behavior to the cache management unit includes:

[0011] Sending a first signal corresponding to the target behavior to the behavior pool;

[0012] The behavior pool performs the following steps:

[0013] receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface;

[0014] A second signal fed back by the cache management unit is received, and the second signal is forwarded to a logic unit indicated by a destination address of the second signal.

[0015] In one embodiment of the present application, forwarding the first signal to the cache management unit through the data transmission interface includes:

[0016] The received first signal is converted into a target format, and the first signal in the target format is forwarded to the cache management unit through the data transmission interface, wherein the target format is a format predefined by the data transmission interface.

[0017] In one embodiment of the present application, forwarding the first signal to the cache management unit through the data transmission interface includes:

[0018] The first signal is forwarded to the cache management unit through the data transmission interface according to a predefined signal transmission sequence and / or signal transmission rule, wherein the signal transmission rule is: sending each signal in parallel or sending each signal in series.

[0019] In one embodiment of the present application, the information used to define behavior in the verification platform includes at least one of the following information: a first signal that needs to be transmitted to the cache management unit to implement the behavior, an identifier of whether the first signal is valid, an identifier of the logical unit corresponding to the behavior, and the address of the cache resource that the behavior requests the cache management unit to allocate or reclaim.

[0020] In one embodiment of the present application, the information used to define the first signal in the verification platform includes at least one of the following information: an identifier of a logic unit that sends the first signal, an identifier of a sub-management unit in the cache management unit that receives the first signal, an internal and external identifier of the cache, and a signal identifier of the first signal;

[0021] The cache internal and external identifier indicates that the cache resource that the first signal requests the cache management unit to allocate or reclaim is located inside the chip where the cache management unit is located or outside the chip.

[0022] In a second aspect, an embodiment of the present application provides an electronic device, the electronic device comprising:

[0023] processor;

[0024] Transceiver;

[0025] A machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor and a program of a verification platform, wherein the verification platform predefines logic units, behaviors to be executed corresponding to each logic unit, and a first signal that each logic unit needs to transmit to a cache management unit to implement the behavior, wherein the behavior is: the corresponding logic unit requests the cache management unit to allocate cache resources or requests the cache management unit to reclaim cache resources; and the machine-executable instructions cause the processor to drive each logic unit to perform the following steps:

[0026] Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recovery requested by the target behavior, and feeds back a second signal indicating the cache resource scheduling allocation or recovery result;

[0027] receiving the second signal;

[0028] According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

[0029] In one embodiment of the present application, a behavior pool is further defined in the verification platform, and a data transmission interface connected to the cache management unit exists in the behavior pool, and sending a first signal corresponding to the target behavior to the cache management unit includes:

[0030] Sending a first signal corresponding to the target behavior to the behavior pool;

[0031] The behavior pool performs the following steps:

[0032] receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface;

[0033] A second signal fed back by the cache management unit is received, and the second signal is forwarded to a logic unit indicated by a destination address of the second signal.

[0034] In one embodiment of the present application, forwarding the first signal to the cache management unit through the data transmission interface specifically includes:

[0035] The received first signal is converted into a target format, and the first signal in the target format is forwarded to the cache management unit through the data transmission interface, wherein the target format is a format predefined by the data transmission interface.

[0036] In one embodiment of the present application, forwarding the first signal to the cache management unit through the data transmission interface specifically includes:

[0037] The first signal is forwarded to the cache management unit through the data transmission interface according to a predefined signal transmission sequence and / or signal transmission rule, wherein the signal transmission rule is: sending each signal in parallel or sending each signal in series.

[0038] In one embodiment of the present application, the information used to define behavior in the verification platform includes at least one of the following information: a first signal that needs to be transmitted to the cache management unit to implement the behavior, an identifier of whether the first signal is valid, an identifier of the logical unit corresponding to the behavior, and the address of the cache resource that the behavior requests the cache management unit to allocate or reclaim.

[0039] In one embodiment of the present application, the information used to define the first signal in the verification platform includes at least one of the following information: an identifier of a logic unit that sends the first signal, an identifier of a sub-management unit in the cache management unit that receives the first signal, an internal and external identifier of the cache, and a signal identifier of the first signal;

[0040] The cache internal and external identifier indicates that the cache resource that the first signal requests the cache management unit to allocate or reclaim is located inside the chip where the cache management unit is located or outside the chip.

[0041] In a third aspect, an embodiment of the present application provides a cache management unit verification device, wherein the device includes a verification platform, wherein the verification platform predefines a logical unit, a behavior to be executed corresponding to each logical unit, and a first signal that each logical unit needs to transmit to the cache management unit to implement the behavior, wherein the behavior is: the corresponding logical unit requests the cache management unit to allocate cache resources or requests the cache management unit to recycle cache resources; each logical unit is used to:

[0042] Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recycling requested by the target behavior, and feeds back a second signal indicating the cache resource allocation or recycling result;

[0043] receiving the second signal;

[0044] According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

[0045] In one embodiment of the present application, a behavior pool is further defined in the verification platform, and a data transmission interface connected to the cache management unit exists in the behavior pool, and the logic unit is specifically used for:

[0046] Sending a first signal corresponding to the target behavior to the behavior pool;

[0047] The behavior pool is used to:

[0048] receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface;

[0049] A second signal fed back by the cache management unit is received, and the second signal is forwarded to a logic unit indicated by a destination address of the second signal.

[0050] In one embodiment of the present application, the behavior pool is specifically used for:

[0051] The received first signal is converted into a target format, and the first signal in the target format is forwarded to the cache management unit through the data transmission interface, wherein the target format is a format predefined by the data transmission interface.

[0052] In one embodiment of the present application, the behavior pool is specifically used for:

[0053] The first signal is forwarded to the cache management unit through the data transmission interface according to a predefined signal transmission sequence and / or signal transmission rule, wherein the signal transmission rule is: sending each signal in parallel or sending each signal in series.

[0054] In one embodiment of the present application, the information used to define behavior in the verification platform includes at least one of the following information: a first signal that needs to be transmitted to the cache management unit to implement the behavior, an identifier of whether the first signal is valid, an identifier of the logical unit corresponding to the behavior, and the address of the cache resource that the behavior requests the cache management unit to allocate or reclaim.

[0055] In one embodiment of the present application, the information used to define the first signal in the verification platform includes at least one of the following information: an identifier of a logic unit that sends the first signal, an identifier of a sub-management unit in the cache management unit that receives the first signal, an internal and external identifier of the cache, and a signal identifier of the first signal;

[0056] The cache internal and external identifier indicates that the cache resource that the first signal requests the cache management unit to allocate or reclaim is located inside the chip where the cache management unit is located or outside the chip.

[0057] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any method step described in the first aspect is implemented.

[0058] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the methods described in the first aspect above.

[0059] Beneficial effects of the embodiments of the present application:

[0060] The cache management unit verification method provided in the embodiment of the present application provides a verification platform, in which the verification platform uses logic units, behaviors and signals as units to abstractly define the logic units with cache resource allocation and / or cache resource recovery requirements, the behaviors of the logic units requesting cache resource allocation or cache resource recovery, and the first signals that need to be transmitted to implement the behaviors. The above abstract method is used to define the large number of logic units that the cache management unit needs to interact with, and the large number of behaviors and signals that the cache management unit needs to process, in three levels of independent, detailed and logically clear definitions, which is convenient for the staff to manage the defined logic units, behaviors and signals. The process of generating the above verification platform is made simpler, thereby shortening the preparation time for the verification of the cache management unit, and making it easier for the logic units defined by the staff to cover the complete scene of the verification. In addition, after completing the definition of the above logic units, behaviors and first signals, the logic unit can execute the defined behaviors and send the defined first signals to the cache management unit, thereby verifying the cache management unit's ability to process the first signal, and then verifying the cache management unit's ability to allocate cache resources and recycle cache resources, thereby completing the efficient and complete verification of the cache management unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0062] Figure 1 A schematic diagram of a verification platform and a cache management unit provided in the related art;

[0063] Figure 2A schematic diagram of a data interaction relationship between a logic unit and a cache management unit provided in an embodiment of the present application;

[0064] Figure 3 A schematic diagram of a flow chart of a cache management unit verification method provided in an embodiment of the present application;

[0065] Figure 4 A schematic diagram of a connection relationship between a verification platform and a cache management unit provided in an embodiment of the present application;

[0066] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0068] First, an application scenario of an embodiment of the present application is described. In an application scenario, the chip where the cache management unit is located can be a digital communication chip. Digital communication chips are essential basic devices in current communication systems, referred to as data communication chips. There is a cache management unit in the data communication chip, which is mainly responsible for the cache resource allocation and / or cache resource recovery of the data communication chip. Maintain the key tasks of data storage, access and management. The interaction between the cache management unit and other logical units in the communication system mainly includes other logical units requesting to allocate cache space and other logical units requesting to recycle cache space. With the advent of the AIGC (Artificial Intelligence Generated Content) era, the amount of data that needs to be transmitted in the network has greatly increased, and the requirements of real-time business on network switching capabilities are also getting higher and higher. The data communication chip not only needs to forward ordinary traffic such as videos and images, but also needs to forward traffic such as conferences and video calls that have relatively high real-time requirements. This part of the traffic is more sensitive to packet loss. If the outbound interface of the data communication chip is congested, its traffic will be cached and sent out from the outbound port in sequence. Therefore, whether the data communication chip can cache data normally will greatly affect the overall performance and stability of the communication system. The cache data is controlled by the cache management unit. Therefore, in order to ensure the normal operation of the communication system, the cache management unit needs to be verified to determine whether it can normally allocate cache resources and / or recycle cache resources.

[0069] In order to reflect the difference between the embodiments of the present application and the related art, the method of verifying the cache management unit in the related art is first described.

[0070] At present, the verification methods in related technologies are mainly divided into the following three types:

[0071] 1. Use simulation tools in the hardware language Verilog to verify different functional scenarios.

[0072] (ii) Use formal technical means to perform mathematical reasoning on the design specifications of the cache management unit to verify that it meets the design requirements.

[0073] (III) Based on the hardware verification language, use SystemVerilog and write a verification platform based on UVM (Universal Verification Methodology) methodology to perform verification through dynamic simulation.

[0074] Among them, the above method (three) is the most common verification method in the relevant technology. The general practice in the industry is to verify the cache management unit based on a dynamic verification method based on random constraints. The random constraint method can generate random incentive data, thereby realizing random verification of the cache management unit and expanding the coverage of verification. The following problems still exist:

[0075] First, since there are a large number of logical units that need to allocate cache resources and reclaim cache resources, in order to fully verify the cache management unit, sufficient preparation is required before verification. Therefore, the preparation work before verification consumes a lot of time and resources, resulting in a long verification cycle. That is, the verification method in the related art is insufficient in terms of rapid deployment.

[0076] See also Figure 1 , which is a schematic diagram of a verification platform and a cache management unit provided in the related art.

[0077] The upper part of the figure is the verification platform, and the lower part is the cache management unit.

[0078] The verification platform contains 9 verification components, namely agent 1 to agent 9. Each agent contains an exciter, a detector and a driver. The driver is used to obtain transactions from the exciter and send them to the cache management unit through the interface after conversion. The detector is used to monitor the interface data generated by the cache management unit after receiving the transaction, so as to obtain the verification result.

[0079] The square on the cache management unit in the figure is the interface on the cache management unit that interacts with the verification component. There is a data interaction relationship between the interface connected by the arrow in the figure and the verification component. The sub-management units included in the cache management unit have different functions, respectively, and are used to process the first signal received by the cache management unit. The inclusion of 4 sub-management units in the figure is only an example, and this application does not limit the specific number of sub-management units.

[0080] That is, the verification component defined in the verification platform in the related technology adopts transaction-level data transmission. The data structure adopted by the transaction-level data transmission is a class, which essentially transmits a collection of a group of signals.

[0081] For example, in Example 1, there are two logical units a that need to request the cache management unit to allocate cache resources and / or recycle cache resources. Logical unit a has two behaviors 1 and 2 that need to request the cache management unit to schedule cache resources. Then, two verification components need to be defined in the relevant technology to verify whether the cache management unit can handle the above two behaviors. However, the two defined verification components are both for verifying the behavior of logical unit a, so there will be a lot of duplicated information in the two verification components, and the staff needs to do a lot of duplicate work to generate the above two verification components.

[0082] Secondly, the specific verification method is not only related to the chip architecture, but also depends on the staff's experience and verification style. The verification quality will be greatly affected by changes in the staff.

[0083] In addition, the verification method has poor reusability. Verification of the same cache management unit often requires multiple stages such as BT-level verification, IT-level verification, ST-level verification, and post-silicon verification. In related technologies, staff need to manually deploy the verification environment and write verification code for each stage, which consumes a lot of labor costs. In other words, the vertical reusability of the verification method in related technologies is poor. In addition, the verification environment deployed for the cache management unit in one chip cannot be reused in the verification of cache management units in other chips, which means that the horizontal reusability of the verification method in related technologies is poor.

[0084] Taking Example 1 above as an example, the two verification components defined in Example 1 are used to verify Behavior 1 and Behavior 2 of logic unit a. However, if Behavior 3 and Behavior 4 of logic unit a need to be verified during verification of the cache management unit of another chip, the two verification components defined in Example 1 are not available during verification of the other chip, and the horizontal reusability is poor. Similarly, in order to verify the same cache management unit at different stages, the staff also needs to define verification components separately at each stage, and the vertical reusability is also poor.

[0085] In order to solve the above problems, the embodiments of the present application provide a cache management unit verification method, electronic device and apparatus.

[0086] An embodiment of the present application provides a cache management unit verification method, which is applied to a verification platform. The verification platform pre-defines logical units, behaviors to be executed corresponding to each logical unit, and a first signal that each logical unit needs to transmit to the cache management unit to implement the behavior. The behavior is: the corresponding logical unit requests the cache management unit to allocate cache resources or requests the cache management unit to recycle cache resources.

[0087] Specifically, in a real environment, there are virtual or physical modules with cache resource allocation requirements and / or cache resource recovery requirements, and the above-mentioned logic unit is an abstraction of the above modules in the verification platform. The logic unit has the ability to send signals to the cache management unit and receive signals sent by the cache management unit. It should be noted that since the above-mentioned logic unit is only used to test the cache management unit, in order to increase the speed of setting up the verification platform and prevent functional redundancy, the logic unit in the verification platform in this application may not have the actual data processing capabilities of its corresponding module. For example, if the module corresponding to the logic unit is used to forward messages, the logic unit may not have the real ability to forward messages. Of course, specific functions can also be defined for the above-mentioned logic unit.

[0088] In one embodiment of the present application, a chip design SPEC (Specification) can be analyzed by an analysis tool to analyze the modules with cache resource allocation and / or cache resource recycling requirements recorded therein, thereby defining the corresponding logical units. Alternatively, the chip design SPEC can be manually analyzed to determine the logical units.

[0089] See also Figure 2 , which is a schematic diagram of the data interaction relationship between a logic unit and a cache management unit provided in an embodiment of the present application.

[0090] As an example, the figure includes 8 logical units, namely logical unit 0 to logical unit 7, and the logical units can be called slaves. There are bidirectional arrows between each logical unit and the cache management unit in the figure, indicating that there is data interaction between the two.

[0091] In addition, the verification platform in the embodiment of the present application defines a behavior to be executed corresponding to each logical unit, and the above behavior is: the corresponding logical unit requests the above cache management unit to allocate cache resources or requests the above cache management unit to recycle cache resources, so as to simulate the process of the logical unit requesting the cache management unit to allocate and / or requesting cache resource recycle. Often the logical unit needs to request to allocate cache resources first, and then request to recycle the allocated cache resources.

[0092] The information used to define behavior in the above-mentioned verification platform includes at least one of the following information: a first signal that needs to be transmitted to the cache management unit to implement the behavior, an identifier of whether the first signal is valid, an identifier of the logical unit corresponding to the behavior, and the address of the cache resource that the behavior requests the above-mentioned cache management unit to allocate or reclaim.

[0093] Specifically, if the behavior is to request the cache management unit to allocate cache resources, then the first signal is a signal instructing the cache management unit to allocate cache resources; if the behavior is to instruct the cache management unit to recycle cache resources, then the first signal is a signal instructing the cache management unit to recycle cache resources.

[0094] There are two values ​​for the identifier of whether the first signal is valid, namely the first value and the second value. The first value is different from the second value, for example, the first value is 1 and the second value is 0; or, the first value is 0 and the second value is 1. The first value indicates that the first signal is valid, and the second value indicates that the first signal is invalid. If the identifier indicates that the first signal is valid, it means that the logic unit needs to send the first signal. If the identifier indicates that the first signal is invalid, it means that the first signal does not need to be sent at present. Therefore, the verification platform can control the logic unit to send the first signal by modifying the value of the identifier.

[0095] In addition, the identifier of the logic unit corresponding to the behavior can be the name, number, etc. of the logic unit, as long as different logic units can be distinguished. Different logic units have different identifiers.

[0096] Furthermore, if the behavior is a behavior of requesting the cache management unit to allocate cache resources, since the cache resources have not been allocated yet, the address of the cache resources targeted by the behavior in the information of the behavior is empty in the initial case. After the first signal is sent to the cache management unit and the cache management unit actually allocates the cache resources, the address of the allocated cache resources is written into the field. Moreover, the address of the cache resource corresponding to the behavior of requesting to allocate cache resources and the behavior of requesting to reclaim cache resources for the same cache resource is the same. For example, there are two behaviors in logic unit a, namely, a behavior of requesting to allocate cache resources and a behavior of requesting to reclaim cache resources. In this case, the addresses of the cache resources targeted by the behaviors contained in the information of the two behaviors are the same.

[0097] See Table 1, which is an information table of a behavior provided in an embodiment of the present application.

[0098] Table 1

[0099] Table 1 shows the behavior information that needs to be defined when defining a behavior in an embodiment of the present application, wherein the signal represents the first signal that needs to be transmitted to the cache management unit to implement the behavior. The valid indication represents an identifier of whether the first signal is valid. The tag represents the identifier of the logical unit corresponding to the behavior. The address of the cache resource represents the address of the cache resource targeted by the behavior.

[0100] In another embodiment of the present application, the information used to define the first signal in the above-mentioned verification platform includes at least one of the following information: an identifier of the logic unit that sends the first signal, an identifier of the sub-management unit in the above-mentioned cache management unit that receives the first signal, an identifier of the cache internal and external identifiers, and a signal identifier of the first signal.

[0101] The cache internal and external identifier indicates that the cache resource allocated or reclaimed by the cache management unit requested by the first signal is located inside the chip where the cache management unit is located or outside the chip.

[0102] Specifically, the identifier of the logic unit that sends the first signal may be the name, address or number of the logic unit.

[0103] The identifier of the sub-management unit in the cache management unit that receives the first signal may be the name, address or number of the sub-management unit.

[0104] The signal identifiers of different first signals sent between the sub-management units in the same logic unit and cache management unit are different, and the signal identifiers of first signals sent between different logic units and sub-management units in the cache management unit may be the same.

[0105] See Table 2, which is an information table of a signal provided in an embodiment of the present application.

[0106] Table 2

[0107] Wherein, source represents the identifier of the logic unit that sends the first signal, and target represents the identifier of the sub-management unit in the cache management unit that receives the first signal. I / O is the identifier of the cache inside and outside. If the value is I, it means that the cache resources allocated or recovered by the first signal are located inside the chip. If the value is O, it means that the cache resources allocated or recovered by the first signal are located outside the chip. Tag represents the signal identifier of the first signal.

[0108] In this application, the data format specifications of behaviors and signals are defined, so no matter at which stage of verification, or in which chip's cache management unit is verified, the data format of the definition of behaviors and signals is the same. Therefore, the staff only needs to make a small modification to the definition according to the actual situation to be able to transplant the verification platform to the verification task of different chips, so the horizontal reusability of this application is relatively high. Moreover, in this application, the logic unit and the behavior and signal are defined separately, so if the same logic unit exists in two verification tasks, but the same logic unit performs different behaviors and sends different signals. Then the staff can directly transplant the logic unit to the new verification task, and only needs to redefine the behavior and signal, thereby reducing the preparation time of the new verification task, further improving the horizontal reusability of this application.

[0109] Moreover, in the actual verification process, when different stages of verification are performed on the same cache management unit, the logic units, behaviors, and signals used in different stages will basically not change. The difference between the different stages is only that the format of the signal sent by the verification platform to the cache management unit is different. Therefore, when performing BT-level verification, IT-level verification, ST-level verification, and post-silicon verification on the same cache management unit, it is only necessary to implement different signal format conversions in the verification platform without redefining the logic units, behaviors, and signals. The vertical reusability of this application is relatively high.

[0110] See also Figure 3 , which is a flow chart of a cache management unit verification method provided in an embodiment of the present application, and is applied to the aforementioned verification platform, wherein each logic unit executes the following steps S301-S303.

[0111] S301: Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recovery requested by the target behavior, and feeds back a second signal indicating the cache resource allocation or recovery result.

[0112] In the case of multiple logic units, the timing and order of each logic unit executing its corresponding behavior can be pre-set in the verification platform, and each logic unit can execute the behavior according to the pre-set timing and order. Alternatively, it can be controlled by the verification platform. The verification platform can be connected to the upper-level verification control platform, and control the timing and order of each logic unit executing the behavior by receiving instructions sent by the verification control platform. The process of the verification control platform sending instructions can be manually controlled or sent according to pre-set settings.

[0113] In theory, each logic unit needs to execute its corresponding behaviors in order to fully and comprehensively verify the cache management unit.

[0114] In addition, if a logic unit corresponds to multiple behaviors, the order in which each logic unit executes each behavior can also be pre-set, or similar to the above, controlled by the verification control platform.

[0115] It should be noted that the present application does not require that a logic unit execute all its corresponding behaviors before starting to execute the behavior of the next logic unit. For example, after logic unit a executes behavior 1, logic unit b executes behavior 3, then logic unit a executes behavior 2, and logic unit b executes behavior 4. Moreover, the process of each logic unit executing a behavior can be serial or parallel.

[0116] S302: Receive the second signal.

[0117] When the target behavior is to request the cache management unit to allocate cache resources, the second signal may indicate whether the cache resource allocation is successful. If the allocation is successful, the second signal may further include the address of the allocated cache resource.

[0118] When the target behavior is to instruct the cache management unit to reclaim cache resources, the second signal may indicate whether the cache resources are successfully reclaimed.

[0119] S303: Verify the correctness of the processing result of the cache management unit for the target behavior according to the received second signal.

[0120] When the target behavior is to request the cache management unit to allocate cache resources, if the second signal indicates that the cache resources are allocated successfully, the generated verification result is that the cache management unit can correctly complete the cache allocation for the logical unit.

[0121] When the target behavior is to request the cache management unit to allocate cache resources, if the second signal indicates a failure in allocating cache resources, the generated verification result is that the cache management unit cannot correctly complete the cache allocation for the logical unit, and there may be a fault here.

[0122] When the target behavior is to request the cache management unit to reclaim cache resources, if the second signal indicates successful reclaiming of cache resources, the generated verification result is that the cache management unit can correctly complete the cache release for the logical unit.

[0123] When the target behavior is to request the cache management unit to reclaim cache resources, if the second signal indicates that the cache resource reclaiming fails, the generated verification result is that the cache management unit cannot correctly complete the cache release for the logical unit, and there may be a fault here.

[0124] In one embodiment of the present application, the same logic unit can execute the same target behavior multiple times, and then determine the correctness of the processing result for the target behavior. For example, if the number of execution failures during the multiple executions of the target behavior reaches a preset number, a verification result indicating that the cache management unit cannot correctly complete the target behavior for the logic unit can be generated. This can avoid the randomness of the verification result obtained by a single verification.

[0125] As can be seen from the above, a verification platform is provided in the cache management unit verification method provided in the embodiment of the present application. In the verification platform, logical units, behaviors and signals are used as units to abstractly define the logical units with cache resource allocation and / or cache resource recovery requirements, the behaviors of the logical units requesting cache resource allocation or cache resource recovery, and the first signals that need to be transmitted to implement the behaviors. The above abstract method is used to define the large number of logical units that the cache management unit needs to interact with, and the large number of behaviors and signals that the cache management unit needs to process, in three levels of independent, detailed and logically clear definitions, which is convenient for the staff to manage the defined logical units, behaviors and signals. The process of generating the above verification platform is made simpler, thereby shortening the preparation time for the verification of the cache management unit, and making it easier for the logical units defined by the staff to cover the complete verification scenario. In addition, after completing the definition of the above logical units, behaviors and first signals, the logical unit can execute the defined behaviors and send the defined first signals to the cache management unit, thereby verifying the cache management unit's processing ability for the first signal, and then verifying the cache management unit's ability to allocate cache resources and recycle cache resources, thereby completing the efficient and complete verification of the cache management unit.

[0126] In one embodiment of the present application, a behavior pool is also defined in the verification platform, and a data transmission interface connected to the cache management unit exists in the behavior pool. The data transmission interface is a unified data transmission interface, and data interaction between the verification platform and the cache management unit is carried out through the unified data transmission interface. Therefore, the present application only needs to maintain the data transmission interface, which is the same as the above-mentioned Figure 1 Compared with the related art in which multiple interfaces exist between the cache management unit and the verification platform, the present application only maintains one interface, which can greatly reduce the complexity of the interface configuration.

[0127] See also Figure 4 , which is a schematic diagram of the connection relationship between a verification platform and a cache management unit provided in an embodiment of the present application.

[0128] The left side of the figure is the cache management unit, and the right side is the verification platform. The arrow between the two is connected by a data link. The right side of the data link is connected to the data transmission interface on the behavior pool in the verification platform. There are 9 logic units in the verification platform, from logic unit 0 to logic unit 8. There is an arrow between each logic unit and the behavior pool, indicating that each logic unit sends a first signal to the behavior pool and receives a second signal fed back by the behavior pool.

[0129] The above step S301 is implemented by the following step A.

[0130] Step A: Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the behavior pool.

[0131] The first signal req (request) may be a signal requesting the cache management unit to allocate cache resources, or a signal requesting the cache management unit to reclaim cache resources, both of which are sent to the behavior pool.

[0132] The above behavior pool is used to perform the following steps B-C.

[0133] Step B: receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface.

[0134] Step C: receiving the second signal rsm fed back by the cache management unit, and forwarding the second signal to the logic unit indicated by the destination address of the second signal.

[0135] As can be seen from the above, a behavior pool is provided in the verification platform provided in the embodiment of the present application, and the behavior pool is used to receive the first signal sent by all logical units and send it to the cache management unit in a unified manner. And the second signal sent by the cache management unit is uniformly received and distributed in a unified manner. Therefore, in the embodiment of the present application, the management of all signals between the verification platform and the cache management unit can be completed by maintaining the behavior pool and the unified data transmission interface. Compared with each logical unit performing signal interaction with the cache management unit separately through different interfaces, the solution provided in the embodiment of the present application can reduce the complexity of signal interaction management.

[0136] In another embodiment of the present application, since the formats of the first signals sent by different logic units may be different, in order to make the first signal meet the format requirements of the data transmission interface and thus be transmitted through a unified data transmission interface, the above step B can be implemented by the following step B1.

[0137] Step B1: receiving the first signal, converting the received first signal into a target format, and forwarding the first signal in the target format to the cache management unit through the data transmission interface.

[0138] The target format is a format predefined by the data transmission interface.

[0139] In one embodiment of the present application, the behavior pool can convert the received signal into a unified target format so that the first signal after format conversion meets the transmission requirements of the data transmission interface. And converting the received first signal into the same target format also facilitates signal maintenance and management.

[0140] In another embodiment of the present application, the above step B can be implemented by the following step B2.

[0141] Step B2: receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface according to a predefined signal transmission sequence and / or signal transmission rule.

[0142] The above signal sending rule is: sending each signal in parallel or sending each signal in series.

[0143] Specifically, the above-defined signal sending order and / or signal sending rule can be determined according to the signal sending order and / or signal sending rule of the cache management unit in the real application scenario, so that the real application scenario can be simulated. Since there are often multiple modules in the real application scenario that concurrently request the cache management unit to allocate cache resources and / or recycle cache resources, the embodiment of the present application can simulate this situation according to the predefined signal sending rule, so as to verify the processing capability of the cache management unit for concurrent scenarios.

[0144] In one embodiment of the present application, the behavior pool can send the first signal in the order and / or parallel serial situation of receiving the first signal, that is, forward the first signal immediately after receiving it, and the order and / or parallel serial situation of forwarding are consistent with the order and / or parallel serial situation of the first signal arriving at the behavior pool.

[0145] In another embodiment of the present application, the behavior pool may temporarily store the received first signal, and then send the temporarily stored first signal according to a predefined signal sending sequence and / or signal sending rule.

[0146] From the above, it can be seen that the behavior pool in the embodiment of the present application can control the signal sending order and / or signal sending rules for sending the first signal to the cache management unit, so as to simulate the different signal sending orders and / or signal sending rules for the logic unit to send the first signal to the cache management unit in the real scenario according to actual needs, and then perform corresponding verification on the cache management unit.

[0147] Corresponding to the aforementioned cache management unit verification method, an embodiment of the present application also provides an electronic device.

[0148] See also Figure 5 , is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the electronic device comprising:

[0149] Processor 501;

[0150] transceiver 504;

[0151] A machine-readable storage medium 502, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor and a program of a verification platform, wherein the verification platform predefines logic units, behaviors to be executed corresponding to each logic unit, and a first signal that each logic unit needs to transmit to a cache management unit to implement the behaviors, wherein the behaviors are: the corresponding logic unit requests the cache management unit to allocate cache resources or requests the cache management unit to reclaim cache resources; and the machine-executable instructions cause the processor to drive each logic unit to perform the following steps:

[0152] Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recovery requested by the target behavior, and feeds back a second signal indicating the cache resource scheduling allocation or recovery result;

[0153] receiving the second signal;

[0154] According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

[0155] like Figure 5 As shown, the electronic device may further include a communication bus 503. The processor 501, the machine-readable storage medium 502, and the transceiver 504 communicate with each other through the communication bus 503. The communication bus 503 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 503 may be divided into an address bus, a data bus, a control bus, and the like.

[0156] The transceiver 504 may be a wireless communication module. Under the control of the processor 501 , the transceiver 504 exchanges data with other devices.

[0157] The machine-readable storage medium 502 may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk storage. In addition, the machine-readable storage medium 502 may also be at least one storage device located away from the aforementioned processor.

[0158] The processor 501 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0159] As can be seen from the above, the verification platform abstractly defines the logic units with cache resource allocation and / or cache resource recovery requirements, the behavior of the logic unit requesting cache resource allocation or cache resource recovery, and the first signal that needs to be transmitted to implement the behavior, using the logic unit, behavior and signal as units. The above abstract method is used to define the large number of logic units that the cache management unit needs to interact with, and the large number of behaviors and signals that the cache management unit needs to process, in three levels of independent, detailed and logically clear definitions, which is convenient for the staff to manage the defined logic units, behaviors and signals. The process of generating the above verification platform is simpler, thereby shortening the preparation time for the verification of the cache management unit, and making it easier for the logic units defined by the staff to cover the complete verification scenario. In addition, after completing the definition of the above logic units, behaviors and first signals, the logic unit can execute the defined behavior and send the defined first signal to the cache management unit, thereby verifying the cache management unit's processing ability for the first signal, and then verifying the cache management unit's ability to allocate cache resources and recycle cache resources, thereby completing the efficient and complete verification of the cache management unit.

[0160] In one embodiment of the present application, a behavior pool is further defined in the verification platform, and a data transmission interface connected to the cache management unit exists in the behavior pool, and sending a first signal corresponding to the target behavior to the cache management unit includes:

[0161] Sending a first signal corresponding to the target behavior to the behavior pool;

[0162] The behavior pool performs the following steps:

[0163] receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface;

[0164] A second signal fed back by the cache management unit is received, and the second signal is forwarded to a logic unit indicated by a destination address of the second signal.

[0165] As can be seen from the above, a behavior pool is provided in the verification platform provided in the embodiment of the present application, and the behavior pool is used to receive the first signal sent by all logical units and send it to the cache management unit in a unified manner. And the second signal sent by the cache management unit is uniformly received and distributed in a unified manner. Therefore, in the embodiment of the present application, the management of all signals between the verification platform and the cache management unit can be completed by maintaining the behavior pool and the unified data transmission interface. Compared with each logical unit performing signal interaction with the cache management unit separately through different interfaces, the solution provided in the embodiment of the present application can reduce the complexity of signal interaction management.

[0166] In one embodiment of the present application, forwarding the first signal to the cache management unit through the data transmission interface specifically includes:

[0167] The received first signal is converted into a target format, and the first signal in the target format is forwarded to the cache management unit through the data transmission interface, wherein the target format is a format predefined by the data transmission interface.

[0168] As can be seen from the above, the behavior pool can convert the received signal into a unified target format, so that the first signal after format conversion meets the transmission requirements of the data transmission interface. And converting the received first signal into the same target format also facilitates signal maintenance and management.

[0169] In one embodiment of the present application, forwarding the first signal to the cache management unit through the data transmission interface specifically includes:

[0170] The first signal is forwarded to the cache management unit through the data transmission interface according to a predefined signal transmission sequence and / or signal transmission rule, wherein the signal transmission rule is: sending each signal in parallel or sending each signal in series.

[0171] From the above, it can be seen that the behavior pool in the embodiment of the present application can control the signal sending order and / or signal sending rules for sending the first signal to the cache management unit, so as to simulate the different signal sending orders and / or signal sending rules for the logic unit to send the first signal to the cache management unit in the real scenario according to actual needs, and then perform corresponding verification on the cache management unit.

[0172] In one embodiment of the present application, the information used to define behavior in the verification platform includes at least one of the following information: a first signal that needs to be transmitted to the cache management unit to implement the behavior, an identifier of whether the first signal is valid, an identifier of the logical unit corresponding to the behavior, and the address of the cache resource that the behavior requests the cache management unit to allocate or reclaim.

[0173] In one embodiment of the present application, the information used to define the first signal in the verification platform includes at least one of the following information: an identifier of a logic unit that sends the first signal, an identifier of a sub-management unit in the cache management unit that receives the first signal, an internal and external identifier of the cache, and a signal identifier of the first signal;

[0174] The cache internal and external identifier indicates that the cache resource that the first signal requests the cache management unit to allocate or reclaim is located inside the chip where the cache management unit is located or outside the chip.

[0175] Corresponding to the aforementioned cache management unit verification method, an embodiment of the present application also provides a cache management unit verification device.

[0176] The embodiment of the present application provides a cache management unit verification device, the device includes a verification platform, the verification platform pre-defined logic units, behaviors to be executed corresponding to each logic unit, and a first signal that each logic unit needs to transmit to the cache management unit to implement the behavior, wherein the behavior is: the corresponding logic unit requests the cache management unit to allocate cache resources or requests the cache management unit to recycle cache resources; each logic unit is used to:

[0177] Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recycling requested by the target behavior, and feeds back a second signal indicating the cache resource allocation or recycling result;

[0178] receiving the second signal;

[0179] According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

[0180] As can be seen from the above, the verification platform abstractly defines the logic units with cache resource allocation and / or cache resource recovery requirements, the behavior of the logic unit requesting cache resource allocation or cache resource recovery, and the first signal that needs to be transmitted to implement the behavior, using the logic unit, behavior and signal as units. The above abstract method is used to define the large number of logic units that the cache management unit needs to interact with, and the large number of behaviors and signals that the cache management unit needs to process, in three levels of independent, detailed and logically clear definitions, which is convenient for the staff to manage the defined logic units, behaviors and signals. The process of generating the above verification platform is simpler, thereby shortening the preparation time for the verification of the cache management unit, and making it easier for the logic units defined by the staff to cover the complete verification scenario. In addition, after completing the definition of the above logic units, behaviors and first signals, the logic unit can execute the defined behavior and send the defined first signal to the cache management unit, thereby verifying the cache management unit's processing ability for the first signal, and then verifying the cache management unit's ability to allocate cache resources and recycle cache resources, thereby completing the efficient and complete verification of the cache management unit.

[0181] In one embodiment of the present application, a behavior pool is further defined in the verification platform, and a data transmission interface connected to the cache management unit exists in the behavior pool, and the logic unit is specifically used for:

[0182] Sending a first signal corresponding to the target behavior to the behavior pool;

[0183] The behavior pool is used to:

[0184] receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface;

[0185] A second signal fed back by the cache management unit is received, and the second signal is forwarded to a logic unit indicated by a destination address of the second signal.

[0186] As can be seen from the above, a behavior pool is provided in the verification platform provided in the embodiment of the present application, and the behavior pool is used to receive the first signal sent by all logical units and send it to the cache management unit in a unified manner. And the second signal sent by the cache management unit is uniformly received and distributed in a unified manner. Therefore, in the embodiment of the present application, the management of all signals between the verification platform and the cache management unit can be completed by maintaining the behavior pool and the unified data transmission interface. Compared with each logical unit performing signal interaction with the cache management unit separately through different interfaces, the solution provided in the embodiment of the present application can reduce the complexity of signal interaction management.

[0187] In one embodiment of the present application, the behavior pool is specifically used for:

[0188] The received first signal is converted into a target format, and the first signal in the target format is forwarded to the cache management unit through the data transmission interface, wherein the target format is a format predefined by the data transmission interface.

[0189] As can be seen from the above, the behavior pool can convert the received signal into a unified target format, so that the first signal after format conversion meets the transmission requirements of the data transmission interface. And converting the received first signal into the same target format also facilitates signal maintenance and management.

[0190] In one embodiment of the present application, the behavior pool is specifically used for:

[0191] The first signal is forwarded to the cache management unit through the data transmission interface according to a predefined signal transmission sequence and / or signal transmission rule, wherein the signal transmission rule is: sending each signal in parallel or sending each signal in series.

[0192] From the above, it can be seen that the behavior pool in the embodiment of the present application can control the signal sending order and / or signal sending rules for sending the first signal to the cache management unit, so as to simulate the different signal sending orders and / or signal sending rules for the logic unit to send the first signal to the cache management unit in the real scenario according to actual needs, and then perform corresponding verification on the cache management unit.

[0193] In one embodiment of the present application, the information used to define behavior in the verification platform includes at least one of the following information: a first signal that needs to be transmitted to the cache management unit to implement the behavior, an identifier of whether the first signal is valid, an identifier of the logical unit corresponding to the behavior, and the address of the cache resource that the behavior requests the cache management unit to allocate or reclaim.

[0194] In one embodiment of the present application, the information used to define the first signal in the verification platform includes at least one of the following information: an identifier of a logic unit that sends the first signal, an identifier of a sub-management unit in the cache management unit that receives the first signal, an internal and external identifier of the cache, and a signal identifier of the first signal;

[0195] The cache internal and external identifier indicates that the cache resource that the first signal requests the cache management unit to allocate or reclaim is located inside the chip where the cache management unit is located or outside the chip.

[0196] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned cache management unit verification methods are implemented.

[0197] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any cache management unit verification method in the above embodiments.

[0198] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0199] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0200] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the electronic device, device, computer-readable storage medium, and computer program product embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0201] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A cache management unit verification method, characterized in that: Applied to a verification platform, the verification platform pre-defines logic units, behaviors to be executed corresponding to each logic unit, and a first signal that each logic unit needs to transmit to a cache management unit to implement the behaviors, wherein the behaviors are: the corresponding logic unit requests the cache management unit to allocate cache resources or requests the cache management unit to recycle cache resources; Each logical unit performs the following steps: Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recycling requested by the target behavior, and feeds back a second signal indicating the cache resource allocation or recycling result; receiving the second signal; According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

2. The method according to claim 1, characterized in that: The verification platform further defines a behavior pool, wherein the behavior pool has a data transmission interface connected to the cache management unit, and the sending of the first signal corresponding to the target behavior to the cache management unit includes: Sending a first signal corresponding to the target behavior to the behavior pool; The behavior pool performs the following steps: receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface; A second signal fed back by the cache management unit is received, and the second signal is forwarded to a logic unit indicated by a destination address of the second signal.

3. The method according to claim 2, characterized in that The forwarding the first signal to the cache management unit through the data transmission interface includes: The received first signal is converted into a target format, and the first signal in the target format is forwarded to the cache management unit through the data transmission interface, wherein the target format is a format predefined by the data transmission interface.

4. The method according to claim 2, characterized in that: The forwarding the first signal to the cache management unit through the data transmission interface includes: The first signal is forwarded to the cache management unit through the data transmission interface according to a predefined signal transmission sequence and / or signal transmission rule, wherein the signal transmission rule is: sending each signal in parallel or sending each signal in series.

5. The method according to any one of claims 1 to 4, characterized in that The information used to define behavior in the verification platform includes at least one of the following information: a first signal that needs to be transmitted to the cache management unit to implement the behavior, an identifier of whether the first signal is valid, an identifier of the logical unit corresponding to the behavior, and the address of the cache resource that the behavior requests the cache management unit to allocate or reclaim.

6. The method according to any one of claims 1 to 4, characterized in that The information used to define the first signal in the verification platform includes at least one of the following information: an identifier of a logic unit that sends the first signal, an identifier of a sub-management unit in the cache management unit that receives the first signal, an internal and external identifier of the cache, and a signal identifier of the first signal; The cache internal and external identifier indicates that the cache resource that the first signal requests the cache management unit to allocate or reclaim is located inside the chip where the cache management unit is located or outside the chip.

7. An electronic device, characterized in that: The electronic device comprises: processor; Transceiver; A machine-readable storage medium, wherein the machine-readable storage medium stores machine-executable instructions that can be executed by the processor and a program of a verification platform, wherein the verification platform predefines logic units, behaviors to be executed corresponding to each logic unit, and a first signal that each logic unit needs to transmit to a cache management unit to implement the behavior, wherein the behavior is: the corresponding logic unit requests the cache management unit to allocate cache resources or requests the cache management unit to reclaim cache resources; and the machine-executable instructions cause the processor to drive each logic unit to perform the following steps: Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recovery requested by the target behavior, and feeds back a second signal indicating the cache resource scheduling allocation or recovery result; receiving the second signal; According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

8. The electronic device according to claim 7, characterized in that: The verification platform further defines a behavior pool, wherein the behavior pool has a data transmission interface connected to the cache management unit, and the sending of the first signal corresponding to the target behavior to the cache management unit includes: Sending a first signal corresponding to the target behavior to the behavior pool; The behavior pool performs the following steps: receiving the first signal, and forwarding the first signal to the cache management unit through the data transmission interface; A second signal fed back by the cache management unit is received, and the second signal is forwarded to a logic unit indicated by a destination address of the second signal.

9. A cache management unit verification device, characterized in that: The device includes a verification platform, in which logic units, behaviors to be executed corresponding to each logic unit, and a first signal that each logic unit needs to transmit to a cache management unit to implement the behaviors are predefined, wherein the corresponding logic unit requests the cache management unit to allocate cache resources or requests the cache management unit to recycle cache resources; Each logical unit is used to: Execute the target behavior corresponding to the logic unit, and send a first signal corresponding to the target behavior to the cache management unit, so that the cache management unit responds to the first signal to perform cache resource allocation or cache resource recycling requested by the target behavior, and feeds back a second signal indicating the cache resource allocation or recycling result; receiving the second signal; According to the received second signal, the correctness of the processing result of the cache management unit for the target behavior is verified.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1 to 6 are implemented.

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