Parallel processing optimization method, device, equipment, medium and product for systolic array

Abstract

The present application discloses a parallel processing optimization method, device, equipment, medium and product for a systolic array, and relates to the field of computer architecture technology. The method includes: real-time monitoring of the load conditions of each computing unit in the systolic array; calculating the resource requirements of each computing unit according to each load condition; and allocating tasks in the systolic array to each computing unit according to each resource requirement. Based on real-time monitoring data, the present application dynamically reflects the resource requirements of each computing unit, provides a reasonable basis for task allocation, and then allocates tasks according to resource requirements, which can ensure that resources are used most reasonably. Through reasonable task allocation, the present application can achieve load balancing in the systolic array, reduce performance degradation and energy consumption increase caused by uneven resource allocation, thereby maintaining the high efficiency of the systolic array while enhancing its flexibility and adaptability.

Description

Technical Field

[0001] The present application relates to the field of computer architecture technology, and in particular to a method, device, equipment, medium and product for optimizing parallel processing of a systolic array. Background Art

[0002] A systolic array, also known as a pulse array, is a parallel computing structure composed of multiple identical processing elements (PEs) according to specific interconnection rules. These processing elements can be basic computing units in hardware circuits, such as adders, multipliers, etc.

[0003] Although systolic arrays perform well in specific scenarios, their inherent fixed structure has become a key factor limiting their widespread application. In practical applications where computing task requirements change frequently, the fixed systolic array architecture makes it difficult to flexibly adjust resources according to the dynamic requirements of the task. This leads to two major problems: one is insufficient resource utilization, that is, in certain tasks, some computing resources may be idle and fail to be effectively utilized; the other is the degradation of computing performance. When the task requirements do not match the fixed structure of the systolic array, the overall computing efficiency will be affected, thereby reducing the overall performance of the system. Therefore, how to maintain the high efficiency of the systolic array while enhancing its flexibility and adaptability has become a technical problem that needs to be solved urgently.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of this application is to provide a method, device, equipment, medium and product for parallel processing optimization of a systolic array, aiming to solve the technical problem of how to enhance the flexibility and adaptability of the systolic array while maintaining its high efficiency.

[0006] To achieve the above objectives, the present application proposes a parallel processing optimization method for a systolic array, the method comprising:

[0007] Real-time monitoring of the load of each computing unit in the systolic array;

[0008] Calculate the resource requirements of each computing unit according to each load condition;

[0009] The tasks in the systolic array are allocated to the computing units according to the resource requirements.

[0010] In one embodiment, the load condition includes: load and load variation; the step of real-time monitoring the load condition of each computing unit in the systolic array includes:

[0011] Acquire the unit utilization of each computing unit in the systolic array in real time, and acquire the task quantity of the target task in each computing unit and the task weight of each target task;

[0012] Calculating the load of each computing unit according to the utilization rate of each unit, the number of each task and the weight of each task;

[0013] The load variation of each computing unit within a preset monitoring period is calculated in real time.

[0014] In one embodiment, after the step of calculating the resource requirements of each of the computing units according to each of the load conditions, the method further includes:

[0015] Determining a resource allocation priority of each computing unit according to the resource demand of each computing unit, wherein the resource allocation priority is positively correlated with the resource demand;

[0016] The computing resources of the systolic array are allocated to the computing units according to the priorities.

[0017] In one embodiment, after the step of allocating the tasks in the systolic array to each of the computing units according to each of the resource requirements, the method further comprises:

[0018] When the sum of the resource requirements is greater than the preset upper limit of the system resources, for each computing unit, the time slice of each target task is calculated according to the preset priority and the preset weight of each target task in the computing unit, wherein the sum of the time slices is less than the monitoring period;

[0019] The target tasks are executed in turn according to the time slices.

[0020] In one embodiment, after the step of executing each of the target tasks in turn according to each of the time slices, the method further includes:

[0021] Acquire the power consumption of each of the computing units in real time;

[0022] Traversing each of the computing units, if the resource demand of the computing unit is less than a preset threshold, reducing the operating parameters of the computing unit;

[0023] If the resource demand of the computing unit is greater than or equal to the threshold, the operating parameters of the computing unit are restored.

[0024] In one embodiment, the method further comprises:

[0025] The overall performance of the systolic array is calculated according to each of the loads, each of the task weights and the upper limit of the system resources, wherein the overall performance is used to characterize the overall efficiency of the systolic array.

[0026] In addition, to achieve the above-mentioned purpose, the present application also proposes a parallel processing optimization device for a systolic array, and the parallel processing optimization device for a systolic array comprises:

[0027] A load monitoring module is used to monitor the load of each computing unit in the systolic array in real time;

[0028] A hardware control module, used for calculating the resource requirement of each computing unit according to each load condition;

[0029] The task scheduling and allocation module is used to allocate the tasks in the systolic array to each of the computing units according to the resource requirements.

[0030] In addition, to achieve the above objectives, the present application also proposes a parallel processing optimization device for a systolic array, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the parallel processing optimization method for a systolic array as described above.

[0031] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the parallel processing optimization method of the systolic array as described above are implemented.

[0032] In addition, to achieve the above objectives, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the parallel processing optimization method of the systolic array as described above are implemented.

[0033] The present application provides a parallel processing optimization method for a systolic array. The present application monitors the load of each computing unit in the systolic array in real time, then calculates the resource requirement of each computing unit according to the load of each computing unit, and then allocates tasks according to the resource requirement.

[0034] In summary, the present application dynamically reflects the resource requirements of each computing unit based on real-time monitoring data, provides a reasonable basis for task allocation, and then allocates tasks according to resource requirements to ensure that resources are used in the most reasonable way. Through reasonable task allocation, the present application can achieve load balancing in the systolic array, reduce performance degradation and increased energy consumption caused by uneven resource allocation, thereby maintaining the high efficiency of the systolic array while enhancing its flexibility and adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 A flow chart of the first embodiment of the method for optimizing parallel processing of a systolic array of the present application;

[0038] Figure 2 A detailed flow chart of an embodiment of a method for optimizing parallel processing of a systolic array of the present application;

[0039] Figure 3 A flow chart of the second embodiment of the parallel processing optimization method of the systolic array of the present application;

[0040] Figure 4 A schematic diagram of the module structure of a parallel processing optimization device for a systolic array according to an embodiment of the present application;

[0041] Figure 5 Schematic diagram of the device structure of the hardware operating environment involved in the parallel processing optimization method of the systolic array in the embodiment of the present application.

[0042] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0043] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0044] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0045] The main solution of the embodiment of the present application is: to monitor the load of each computing unit in the systolic array in real time; to calculate the resource requirement of each computing unit according to each load condition; and to allocate the tasks in the systolic array to each computing unit according to each resource requirement.

[0046] In this embodiment, for ease of description, the following description is made by taking the parallel processing optimization device of the systolic array as the execution subject.

[0047] A systolic array, also known as a pulse array, is a parallel computing structure composed of multiple identical processing elements (PEs) according to specific interconnection rules. These processing elements can be basic computing units in hardware circuits, such as adders, multipliers, etc.

[0048] Although systolic arrays perform well in specific scenarios, their inherent fixed structure has become a key factor limiting their widespread application. In practical applications where computing task requirements change frequently, the fixed systolic array architecture makes it difficult to flexibly adjust resources according to the dynamic requirements of the task. This leads to two major problems: one is insufficient resource utilization, that is, in certain tasks, some computing resources may be idle and fail to be effectively utilized; the other is the degradation of computing performance. When the task requirements do not match the fixed structure of the systolic array, the overall computing efficiency will be affected, thereby reducing the overall performance of the system. Therefore, how to maintain the high efficiency of the systolic array while enhancing its flexibility and adaptability has become a technical problem that needs to be solved urgently.

[0049] In response to the above problems, the present application provides a parallel processing optimization method for a systolic array. The present application monitors the load of each computing unit in the systolic array in real time, then calculates the resource requirement of each computing unit according to the load of each computing unit, and then allocates tasks according to the resource requirement.

[0050] In summary, the present application dynamically reflects the resource requirements of each computing unit based on real-time monitoring data, provides a reasonable basis for task allocation, and then allocates tasks according to resource requirements to ensure that resources are used in the most reasonable way. Through reasonable task allocation, the present application can achieve load balancing in the systolic array, reduce performance degradation and increased energy consumption caused by uneven resource allocation, thereby maintaining the high efficiency of the systolic array while enhancing its flexibility and adaptability.

[0051] It should be noted that the execution subject of this embodiment may be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a parallel processing optimization device of a systolic array, etc. The following takes the parallel processing optimization device of a systolic array as an example to illustrate this embodiment and the following embodiments.

[0052] Based on this, the embodiment of the present application provides a parallel processing optimization method for a systolic array, referring to Figure 1 , Figure 1 Schematic diagram of the flow chart of the first embodiment of the parallel processing optimization method of the systolic array of the present application.

[0053] In this embodiment, the parallel processing optimization method of the systolic array includes steps S10 to S30:

[0054] Step S10, real-time monitoring of the load of each computing unit in the systolic array;

[0055] In this embodiment, key indicators such as the current computing task volume, processing speed, and waiting queue length of each computing unit in the systolic array are continuously monitored to fully grasp the real-time load status of each computing unit.

[0056] Furthermore, in a feasible implementation manner, the load condition includes: load and load variation; the above step S10 may further include steps S11 to S13:

[0057] Step S11, obtaining the unit utilization of each computing unit in the systolic array in real time, and obtaining the task quantity of the target task in each computing unit and the task weight of each target task;

[0058] In this embodiment, the current utilization rate of each computing unit in the systolic array (i.e., the ratio of the processing capacity to the actual tasks carried) is collected in real time, and the number of target tasks currently carried by each computing unit and the weights of these tasks are obtained. The task weight may be determined based on the complexity, priority or other relevant factors of the task.

[0059] Step S12, respectively calculating the load of each computing unit according to the utilization rate of each unit, the number of each task and the weight of each task;

[0060] In this embodiment, the load value of each computing unit is calculated based on the acquired data. The calculation process of the load value takes into account the utilization rate of the computing unit, the number of tasks and the task weight, so as to more accurately reflect the actual load situation of each computing unit.

[0061] Step S13, calculating in real time the load variation of each calculation unit within a preset monitoring period.

[0062] In this embodiment, after obtaining the load value of each computing unit, the system further calculates the load change of each computing unit within a preset monitoring period (such as one minute, five minutes, etc.).

[0063] Specifically, the current load of each computing unit is set to L_i(t), where i represents the i-th computing unit and t is a time point.

[0064] Then define the load of each unit as L_i(t)=f(N_i,U_i,W_i), where N_i is the number of tasks, U_i is the unit utilization, and W_i is the task weight.

[0065] The load monitoring module provides real-time load data of each computing unit as input for dynamic adjustment by subsequent modules. Initially, the monitoring module sampling period is Δt, and the load trend is determined by detecting the load change ΔL_i(t)=L_i(t)-L_i(t-Δt).

[0066] Step S20, calculating the resource requirements of each of the computing units according to the load conditions;

[0067] In this embodiment, based on the collected load data, the resource demand of each computing unit is further analyzed and calculated. This calculation process may involve comprehensive consideration of multiple dimensions such as the current load of the computing unit, historical load trends, task types and complexity, so as to obtain an evaluation value that can accurately reflect the resource demand of each computing unit at present and in the future.

[0068] Specifically, the control module of the device executes a dynamic allocation algorithm based on the load data. Assume that the system resource demand function is R(L_i)=αL_i+βΔL_i, where α and β are adjustment coefficients, and R(L_i) represents the resource demand.

[0069] Further, in a feasible implementation mode, please refer to Figure 2 , Figure 2 FIG. 1 is a detailed flow chart of an embodiment of a method for optimizing parallel processing of a systolic array of the present application. Figure 2 As shown, after the above step S20, the method may further include steps A10 to A20:

[0070] Step A10, determining the resource allocation priority of each computing unit according to the resource demand of each computing unit, wherein the resource allocation priority is positively correlated with the resource demand;

[0071] In this embodiment, a resource allocation priority is assigned to each computing unit according to the calculated resource demand of each computing unit. This priority is positively correlated with the resource demand of the computing unit, that is, the higher the resource demand of the computing unit, the higher its resource allocation priority. Through such a setting, the system can ensure that when computing resources are limited, the needs of computing units with higher resource demands are met first.

[0072] Step A20: Allocate computing resources of the systolic array to each computing unit according to each priority.

[0073] In this embodiment, after determining the resource allocation priority of each computing unit, the computing resources (such as processor time, memory space, etc.) in the systolic array are allocated to the corresponding computing units according to these priorities. This allocation process follows the principle of "high first, low later", that is, the needs of computing units with higher priorities are met first, and then the needs of computing units with lower priorities are gradually met.

[0074] Specifically, assuming that the total capacity of computing resources in the system is C, the control module allocates computing resources to each unit according to the size of R(L_i), satisfying ∑R(L_i)≤C. Based on the demand R(L_i) of the computing unit and the resource limit C, resources are preferentially allocated to units with high load.

[0075] By allocating computing resources according to priority, the system can ensure that when computing resources are limited, those computing units with higher resource requirements are given priority, thereby maximizing the computing efficiency and resource utilization of the systolic array. At the same time, this allocation method also helps to balance the load of each computing unit in the systolic array, avoiding the situation where some computing units are limited in performance due to insufficient resources, while other computing units have idle resources.

[0076] Step S30, allocating tasks in the systolic array to each of the computing units according to each of the resource requirements.

[0077] In this embodiment, after obtaining the resource requirements of each computing unit, the tasks in the systolic array are dynamically allocated according to these evaluation values. During the allocation process, computing units with higher resource requirements are given priority to ensure that they can obtain sufficient tasks to fully utilize their computing capabilities; at the same time, computing units with lower resource requirements are also taken into account to avoid idleness and waste of resources.

[0078] Specifically, assuming that the task set is T = {T_1, T_2, ..., T_n}, the task scheduling allocation satisfies the constraint ∑w_j x_j≤R(L_i), where x_j represents the task allocation decision variable and w_j is the task weight. The task scheduling module relies on the resource demand data provided by the control module to allocate tasks to PE units and provide a basis for time slice allocation for the time division multiplexing module.

[0079] Through task allocation based on resource demand, dynamic balance and efficient utilization of computing resources in the systolic array are achieved. The above steps not only improve the overall computing efficiency of the systolic array, but also enhance the flexibility and response speed of the system, so that the system can better adapt to complex and changing task requirements.

[0080] Furthermore, in a feasible implementation manner, after the above step S30, the method may further include steps S40 to S50:

[0081] Step S40, when the sum of the resource requirements is greater than the preset system resource upper limit, for each computing unit, the time slice of each target task in the computing unit is calculated according to the preset priority and preset weight of each target task, wherein the sum of the time slices is less than the monitoring period;

[0082] In this embodiment, after the tasks are assigned, if it is detected that the total resource demand of all computing units exceeds the preset system resource upper limit (i.e., the maximum amount of computing resources that the system can provide), it is necessary to further assign time slices to the tasks based on time division multiplexing to ensure that the system can run stably and all tasks can be processed to a certain extent.

[0083] In this embodiment, for the target tasks in each computing unit, the time slice length that each target task should obtain is calculated according to its preset priority and weight. The calculation of the time slice length needs to ensure that the sum of the time slices of all target tasks does not exceed the preset monitoring period (i.e., the time unit used by the system to allocate time slices), while trying to meet the needs of high priority and weight tasks.

[0084] Step S50: executing each of the target tasks in turn according to each of the time slices.

[0085] In this embodiment, after the time slices of each target task are calculated, the target tasks are executed in turn according to the time slices.

[0086] Specifically, when the resource demand exceeds the system resource upper limit C, the time division multiplexing module shares time slices among multiple tasks to minimize resource contention. The time slice τ_j of each task is determined by its weight w_j and priority p_j, satisfying the condition τ_j∝w_j*p_j.

[0087] Define the time slice allocation constraint ∑τ_j≤Δt, where Δt is the monitoring period. The time division multiplexing module increases the time slice allocation of tasks when the load is high and reduces the time slice when the load is low, ensuring the flexibility of resource allocation.

[0088] The time division multiplexing module dynamically allocates the execution time slices of the computing units according to the task allocation results of the task scheduling module, and transmits the output results to the dynamic power management module.

[0089] By executing the target tasks in turn according to time slices, the system can achieve fair scheduling and efficient execution between tasks under limited resources. This helps to improve the overall computing efficiency and resource utilization of the systolic array while ensuring the stability and reliability of the system.

[0090] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 3 , Figure 3 FIG. 1 is a flow chart of a second embodiment of a parallel processing optimization method for a systolic array of the present application. Figure 3 As shown, after the above step S50, the method may further include steps S60 to S80:

[0091] Step S60, obtaining the power consumption of each of the computing units in real time;

[0092] In this embodiment, the power consumption data of each computing unit is obtained in real time. The power consumption data can reflect the energy consumption of the computing unit in the current operating state and is an important indicator for evaluating the energy efficiency of the system.

[0093] Step S70, traversing each of the computing units, if the resource demand of the computing unit is less than a preset threshold, reducing the operating parameters of the computing unit;

[0094] In this embodiment, after obtaining the power consumption data of each computing unit, all computing units are traversed to check whether their resource requirements are less than a preset threshold. If the resource requirement of a computing unit is lower than the threshold, it means that the current task volume or task complexity of the computing unit is small, so its operating parameters (such as operating frequency, voltage, etc.) can be appropriately reduced to reduce power consumption and extend system life.

[0095] Step S80: If the resource demand of the computing unit is greater than or equal to the threshold, the operating parameters of the computing unit are restored.

[0096] In this embodiment, for computing units whose resource demand is greater than or equal to the preset threshold, their original operating parameters are maintained or restored. This is because these computing units currently carry a large amount of tasks or have high task complexity, and require higher operating parameters to ensure timely processing and performance of tasks.

[0097] Specifically, let P_i(t)=V_i^2*f_i, where P_i is the power consumption of the i-th unit, V_i is the voltage, and f_i is the frequency. The dynamic power management module optimizes power consumption by adjusting V_i and f_i.

[0098] When R(L_i) is less than the threshold T_low, V_i and f_i are reduced to save power consumption; when R(L_i) exceeds the threshold T_high, normal voltage and frequency are restored.

[0099] The above steps can effectively reduce the overall power consumption of the system and improve energy efficiency while ensuring the normal execution of tasks and system performance. This helps to extend the service life of the system, reduce operating costs, and comply with the current environmental protection trend of energy conservation and emission reduction.

[0100] Based on the first embodiment and / or the second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those of the first embodiment and / or the second embodiment can be referred to the above introduction, and will not be described in detail later. On this basis, the method further includes step B10:

[0101] Step B10, calculating the overall performance of the systolic array according to each of the loads, each of the task weights and the upper limit of the system resources, wherein the overall performance is used to characterize the overall efficiency of the systolic array.

[0102] In this embodiment, the overall performance of the systolic array can also be calculated based on the load of each computing unit, the weight of each task, and the upper limit of system resources. The overall performance is a comprehensive indicator used to characterize the overall efficiency of the systolic array. It comprehensively considers the load of the computing unit, the priority and weight of the task, and the allocation of system resources.

[0103] Specifically, the performance feedback module monitors the execution time, power consumption and task completion rate of each unit, and defines the system performance function E = ∑(L_i(t)*w_i) / C as the overall efficiency indicator.

[0104] When E is lower than the set value, the feedback module notifies the load monitoring module to adjust the scheduling strategy; when E meets expectations, the current configuration is maintained.

[0105] As the terminal of the closed-loop feedback mechanism, the performance feedback module transmits system performance data back to the load monitoring module, provides historical data of resource adjustments, and helps the system better adapt to load changes in the next round of optimization.

[0106] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the parallel processing optimization method of the systolic array of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0107] The present application also provides a parallel processing optimization device for a systolic array, please refer to Figure 4 , the parallel processing optimization device of the systolic array comprises:

[0108] A load monitoring module 10 is used to monitor the load of each computing unit in the systolic array in real time;

[0109] Specifically, the load monitoring module 10 includes:

[0110] Mathematical model: The current load of each computing unit is set to L_i(t), where i represents the i-th computing unit and t is the time point.

[0111] Load measurement: Define the load of each unit as L_i(t)=f(N_i,U_i,W_i), where N_i is the number of tasks, U_i is the unit utilization, and W_i is the task weight.

[0112] Dependency: The load monitoring module provides the real-time load data of each computing unit as input for dynamic adjustment by subsequent modules. Initially, the sampling period of the monitoring module is Δt, and the load trend is determined by detecting the load change ΔL_i(t)=L_i(t)-L_i(t-Δt).

[0113] The hardware control module 20 is used to calculate the resource demand of each computing unit according to each load condition;

[0114] Specifically, the hardware control module 20 includes:

[0115] Dynamic allocation algorithm: The control module executes the dynamic allocation algorithm based on the load data. Assume that the system resource demand function is R(L_i)=αL_i+βΔL_i, where α and β are adjustment coefficients, and R(L_i) represents the resource demand.

[0116] Resource allocation formula: Assuming that the total capacity of computing resources in the system is C, the control module allocates computing resources to each unit according to the size of R(L_i), satisfying ∑R(L_i)≤C.

[0117] Dependency: The decision results of the control module are passed to the task scheduling module and the time division multiplexing module as the basis for task allocation and resource time slice allocation.

[0118] The task scheduling and allocation module 30 is used to allocate the tasks in the systolic array to each of the computing units according to the resource requirements.

[0119] Specifically, the task scheduling and allocation module 30 also includes:

[0120] Scheduling algorithm: The task scheduling module allocates resources to units with high load first according to the demand R(L_i) of the computing unit and the resource limit C.

[0121] Task allocation model: Assume that the task set is T = {T_1, T_2, ..., T_n}, and the task scheduling allocation satisfies the constraint ∑w_j x_j≤R(L_i), where x_j represents the task allocation decision variable and w_j is the task weight.

[0122] Dependency: The task scheduling module relies on the resource demand data provided by the control module to allocate tasks to PE units and provide a basis for time slice allocation for the time division multiplexing module.

[0123] Optionally, the load condition includes: load and load variation. The load monitoring module 10 can also be used for:

[0124] Acquire the unit utilization of each computing unit in the systolic array in real time, and acquire the task quantity of the target task in each computing unit and the task weight of each target task;

[0125] Calculating the load of each computing unit according to the utilization rate of each unit, the number of each task and the weight of each task;

[0126] The load variation of each computing unit within a preset monitoring period is calculated in real time.

[0127] Optionally, the task scheduling and allocation module 30 is further used for:

[0128] Determining a resource allocation priority of each computing unit according to the resource demand of each computing unit, wherein the resource allocation priority is positively correlated with the resource demand;

[0129] The computing resources of the systolic array are allocated to the computing units according to the priorities.

[0130] Optionally, the parallel processing optimization device of the systolic array further includes:

[0131] A time division multiplexing module is used to calculate the time slices of each target task in each computing unit according to the preset priority and preset weight of each target task in the computing unit when the sum of the resource requirements is greater than the preset system resource upper limit, wherein the sum of the time slices is less than the monitoring period; and execute each target task in turn according to each time slice;

[0132] Specifically, the time division multiplexing module includes:

[0133] Time-division multiplexing strategy: When resource demand exceeds the system resource limit C, the time-division multiplexing module shares time slices among multiple tasks to minimize resource contention. The time slice τ_j of each task is determined by its weight w_j and priority p_j, satisfying the condition τ_j∝w_j*p_j.

[0134] Dynamic adjustment: Define the time slice allocation constraint ∑τ_j≤Δt, where Δt is the monitoring period. The time division multiplexing module increases the time slice allocation of tasks when the load is high and reduces the time slice when the load is low, ensuring the flexibility of resource allocation.

[0135] Dependency: The time-division multiplexing module dynamically allocates the execution time slices of the computing units according to the task allocation results of the task scheduling module, and passes the output results to the dynamic power management module.

[0136] Optionally, the parallel processing optimization device of the systolic array further includes:

[0137] A dynamic power management module is used to obtain the power consumption of each computing unit in real time; traverse each computing unit, and if the resource demand of the computing unit is less than a preset threshold, reduce the operating parameters of the computing unit; if the resource demand of the computing unit is greater than or equal to the threshold, restore the operating parameters of the computing unit.

[0138] Specifically, the dynamic power management module includes:

[0139] Power consumption control model: Let P_i(t) = V_i^2*f_i, where P_i is the power consumption of the i-th unit, V_i is the voltage, and f_i is the frequency. The dynamic power management module optimizes power consumption by adjusting V_i and f_i.

[0140] Dynamic adjustment strategy: When R(L_i) is less than the threshold T_low, V_i and f_i are reduced to save power consumption; when R(L_i) exceeds the threshold T_high, normal voltage and frequency are restored.

[0141] Dependency: The power management module relies on the load output of the time-division multiplexing module, dynamically adjusts the power consumption parameters according to the load conditions, and feeds back the energy consumption data to the performance feedback module.

[0142] Optionally, the parallel processing optimization device of the systolic array further includes:

[0143] A performance feedback module is used to calculate the overall performance of the systolic array according to each of the loads, each of the task weights and the upper limit of the system resources, wherein the overall performance is used to characterize the overall efficiency of the systolic array.

[0144] Specifically, the performance feedback module includes:

[0145] Performance indicators: The performance feedback module monitors the execution time, power consumption and task completion rate of each unit, and defines the system performance function E = ∑(L_i(t)*w_i) / C as the overall efficiency indicator.

[0146] Feedback mechanism: When E is lower than the set value, the feedback module notifies the load monitoring module to adjust the scheduling strategy; when E meets expectations, the current configuration is maintained.

[0147] Dependency: As the terminal of the closed-loop feedback mechanism, the performance feedback module transmits system performance data back to the load monitoring module, provides historical data of resource adjustments, and helps the system better adapt to load changes in the next round of optimization.

[0148] The parallel processing optimization device for a systolic array provided in the present application adopts the parallel processing optimization method for a systolic array in the above embodiment, and can solve the technical problem of how to maintain the high efficiency of the systolic array while enhancing its flexibility and adaptability. Compared with the prior art, the beneficial effects of the parallel processing optimization device for a systolic array provided in the present application are the same as the beneficial effects of the parallel processing optimization method for a systolic array provided in the above embodiment, and other technical features in the parallel processing optimization device for a systolic array are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0149] The present application provides a parallel processing optimization device for a systolic array, the parallel processing optimization device for a systolic array comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the parallel processing optimization method for the systolic array in the first embodiment.

[0150] Reference below Figure 5 , which shows a schematic diagram of the structure of a parallel processing optimization device for a systolic array suitable for implementing an embodiment of the present application. The parallel processing optimization device for a systolic array in the embodiment of the present application may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The parallel processing optimization device of the systolic array shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0151] like Figure 5As shown, the parallel processing optimization device of the systolic array may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. Various programs and data required for the operation of the parallel processing optimization device of the systolic array are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1003 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009. The communication device 1009 may allow the parallel processing optimization device of the systolic array to communicate wirelessly or wired with other devices to exchange data. Although the parallel processing optimization device of the systolic array with various systems is shown in the figure, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have instead.

[0152] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0153] The parallel processing optimization device for a systolic array provided in the present application adopts the parallel processing optimization method for a systolic array in the above embodiment, which can solve the technical problem of how to maintain the high efficiency of the systolic array while enhancing its flexibility and adaptability. Compared with the prior art, the beneficial effects of the parallel processing optimization device for a systolic array provided in the present application are the same as the beneficial effects of the parallel processing optimization method for a systolic array provided in the above embodiment, and other technical features in the parallel processing optimization device for a systolic array are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0154] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0155] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0156] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the parallel processing optimization method of the systolic array in the above-mentioned embodiment.

[0157] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0158] The computer-readable storage medium may be included in the parallel processing optimization device of the systolic array; or may exist independently without being assembled into the parallel processing optimization device of the systolic array.

[0159] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the parallel processing optimization device of the systolic array, the parallel processing optimization device of the systolic array: monitors the load conditions of each computing unit in the systolic array in real time; calculates the resource requirements of each computing unit according to each load condition; and allocates tasks in the systolic array to each computing unit according to each resource requirement.

[0160] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0161] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0162] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0163] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned method for optimizing parallel processing of systolic arrays, and can solve the technical problem of how to enhance the flexibility and adaptability of systolic arrays while maintaining their high efficiency. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the method for optimizing parallel processing of systolic arrays provided in the above-mentioned embodiments, and will not be described in detail here.

[0164] The present application also provides a computer program product, comprising a computer program, which implements the steps of the above-mentioned method for optimizing parallel processing of a systolic array when executed by a processor.

[0165] The computer program product provided in this application can solve the technical problem of how to maintain the high efficiency of the systolic array while enhancing its flexibility and adaptability. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as the beneficial effects of the parallel processing optimization method of the systolic array provided in the above embodiment, which will not be repeated here.

[0166] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for optimizing parallel processing of a systolic array, characterized in that: The method comprises: Real-time monitoring of the load of each computing unit in the systolic array; Calculate the resource requirements of each computing unit according to each load condition; The tasks in the systolic array are allocated to the computing units according to the resource requirements.

2. The method for optimizing parallel processing of a systolic array according to claim 1, wherein: The load condition includes: load and load variation; the step of real-time monitoring the load condition of each computing unit in the systolic array includes: Acquire the unit utilization of each computing unit in the systolic array in real time, and acquire the task quantity of the target task in each computing unit and the task weight of each target task; Calculating the load of each computing unit according to the utilization rate of each unit, the number of each task and the weight of each task; The load variation of each computing unit within a preset monitoring period is calculated in real time.

3. The method for optimizing parallel processing of a systolic array according to claim 1, wherein: After the step of calculating the resource requirements of each of the computing units according to the load conditions, the method further includes: Determining a resource allocation priority of each computing unit according to the resource demand of each computing unit, wherein the resource allocation priority is positively correlated with the resource demand; The computing resources of the systolic array are allocated to the computing units according to the priorities.

4. The method for optimizing parallel processing of a systolic array according to claim 2, wherein: After the step of allocating the tasks in the systolic array to each of the computing units according to each of the resource requirements, the method further includes: When the sum of the resource requirements is greater than the preset upper limit of the system resources, for each computing unit, the time slice of each target task is calculated according to the preset priority and the preset weight of each target task in the computing unit, wherein the sum of the time slices is less than the monitoring period; The target tasks are executed in turn according to the time slices.

5. The method for optimizing parallel processing of a systolic array according to claim 4, wherein: After the step of executing each of the target tasks in turn according to each of the time slices, the method further includes: Acquire the power consumption of each of the computing units in real time; Traversing each of the computing units, if the resource demand of the computing unit is less than a preset threshold, reducing the operating parameters of the computing unit; If the resource demand of the computing unit is greater than or equal to the threshold, the operating parameters of the computing unit are restored.

6. The method for optimizing parallel processing of a systolic array according to claim 4, wherein: The method further comprises: The overall performance of the systolic array is calculated according to each of the loads, each of the task weights and the upper limit of the system resources, wherein the overall performance is used to characterize the overall efficiency of the systolic array.

7. A parallel processing optimization device for a systolic array, characterized in that: The device comprises: A load monitoring module is used to monitor the load of each computing unit in the systolic array in real time; A hardware control module, used for calculating the resource requirement of each computing unit according to each load condition; The task scheduling and allocation module is used to allocate the tasks in the systolic array to each of the computing units according to the resource requirements.

8. A parallel processing optimization device for a systolic array, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the method for optimizing parallel processing of a systolic array according to any one of claims 1 to 6.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the parallel processing optimization method for a systolic array as described in any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the method for optimizing parallel processing of a systolic array according to any one of claims 1 to 6 are implemented.

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