Method and device for preventing bus deadlock on chip system, equipment and storage medium

Abstract

The embodiment of the invention provides a method and device for preventing bus deadlock on a chip system, equipment and a storage medium, and the method comprises the steps that for each address space on a bus, at least one set of configuration registers used for describing address space attributes are provided, and each set of configuration registers comprises a first register and a second register; in the first register, configuring a cacheable attribute bit field, a non-cacheable attribute bit field, a device attribute bit field and an address space initial address bit field; determining the attribute of the current address space according to the values of the cacheable attribute bit field, the non-cacheable attribute bit field and the equipment attribute bit field; according to the attribute of the current address space and the address request of the current address space, whether the current address space is allowed to be accessed or not is determined, and combined description of at least one attribute is performed on the address where the address hole possibly occurs through the configuration register, so that the problem of bus deadlock caused by the address hole is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of chip systems, and in particular, to a method, apparatus, device and storage medium for preventing bus deadlock on a chip system. Background Art

[0002] In modern chip systems, many peripherals are often integrated, and these peripherals have various functional scenarios, such as Figure 1 The following is a typical chip system block diagram, where the peripherals are all connected to the bus, such as Figure 1 The DEVICE below represents all external devices, which generally occupy a part of the bus space. MEM represents the system storage module. The space occupied by DEVICE can be the Device space. In addition, the two-way space coming out of the CORE core can be roughly divided into Cacheable and non-cacheable space.

[0003] Nowadays, the value access unit and memory access unit in the processor will have speculative access or speculative execution to ensure faster and more efficient execution of the processor. Then there is a probability of failure for these speculative address accesses. When the predicted address appears in an empty address space, unknown problems such as system deadlock will occur. For example, if the pre-fetched address space happens to belong to an unknown empty address, then the predicted address will not have any response, which will cause the system deadlock.

[0004] When there is a fixed hole address in the chip system, this hole address may be caused by a space that was not considered during the bus design, resulting in a blank space in the bus space. At this time, if speculative execution or speculative access occurs, accessing the hole address will cause the system to deadlock. This requires a mechanism to adjust the response of the hole address space when it is speculatively executed or accessed to prevent the system from deadlocking.

[0005] In a chip system, some devices may need to sleep or power off in certain application scenarios. In this case, the space where the device is located will be called a hole address at a specific time, and can be accessed normally at a specific time. When a speculative access is performed, the device happens to be in a sleep or power-off state, which will cause a system deadlock. If the space attributes are changed so that the space cannot be speculatively executed or accessed, then when the device is in normal working state, it cannot be accessed normally. This requires dynamic adjustment of the access attributes of the space where the device is located.

[0006] In a chip system, when the system is just started, only a very small part of the device space may be accessible, and the rest of the space is a black hole space. If you need to access these small spaces, you may need to set a lot of space attribute descriptions for these accessible spaces, which will consume a lot of resources. Summary of the invention

[0007] Embodiments of the present application provide a method, apparatus, device, and storage medium for preventing bus deadlock on a chip system.

[0008] A first aspect of an embodiment of the present application provides a method for preventing bus deadlock in a chip system, comprising: For each address space on the bus, at least one group of configuration registers for describing attributes of the address space is provided, wherein each group of configuration registers includes a first register and a second register; In the first register, configure the cacheable attribute bit field, the non-cacheable attribute bit field, the device attribute bit field and the address space start address bit field, and in the second register, configure the bit field used to calculate the size of the address space to be described; Determine the attributes of the current address space according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field and the device attribute bit field; Whether access to the current address space is permitted is determined according to the attributes of the current address space and the address request of the current address space.

[0009] In an optional embodiment of the present application, the attributes of the current address space are determined according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field, including: When the value of the cacheable attribute bit field is 1, and the values ​​of the non-cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the cacheable attribute; When the value of the non-cacheable attribute bit field is 1, and the values ​​of the cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the non-cacheable attribute; When the value of the device attribute bit field is 1, and the values ​​of the non-cacheable attribute bit field and the cacheable attribute bit field are both 0, the attribute of the current address space is the device attribute; When the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field are all 0, the attributes of the current address space are normal attributes.

[0010] In an optional embodiment of the present application, determining whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space includes: In the case where the attribute of the current address space is a device attribute and the address request is a predictive address request, access to the current address space is not allowed; In a case where the attribute of the current address space is any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute and the address request is a predictive address request, access to the current address space is permitted.

[0011] In an optional embodiment of the present application, the method further includes: In the case where multiple groups of configuration registers describe the attributes of the same address space, the attributes of the current address space are determined according to the priority of the address space attributes, where the address space attributes are sorted from high to low priority as follows: cacheable attributes, non-cacheable attributes, device attributes, and common attributes.

[0012] In an optional embodiment of the present application, the method further includes: For each fixed hole address space on the bus, the attributes of the current fixed hole address space are described as device attributes through a group of configuration registers.

[0013] In an optional embodiment of the present application, the method further includes: For each variable hole address space on the bus, during the period when the variable hole address space is a hole address, the attributes of the current variable hole address space are described as device attributes through a group of configuration registers. During the period when the variable hole address space is a non-hole address, the attributes of the current variable hole address space are described as any one of non-cacheable attributes, cacheable attributes and ordinary attributes by modifying the configuration of the current group of configuration registers.

[0014] In an optional embodiment of the present application, the method further includes: For each hybrid address space on the bus, the attributes of the current hybrid address space are described as device attributes through a set of configuration registers, and the attributes of the hole address space in the current hybrid address space are described as any one of uncacheable attributes, cacheable attributes and ordinary attributes through another set of configuration registers, wherein the hybrid address space includes hole address space and non-hole address space and the proportion of non-hole address space in the hybrid address space is less than a preset value.

[0015] A second aspect of an embodiment of the present application provides a device for preventing bus deadlock on a chip system, including: Providing a module for providing, for each address space on the bus, at least one set of configuration registers for describing address space attributes, wherein each set of configuration registers includes a first register and a second register; A configuration module, configured to configure a cacheable attribute bit field, a non-cacheable attribute bit field, a device attribute bit field, and an address space start address bit field in a first register, and to configure a bit field used to calculate a size of an address space to be described in a second register; A first determination module, used to determine the attributes of the current address space according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field and the device attribute bit field; The second determination module is used to determine whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space.

[0016] A third aspect of an embodiment of the present application provides a computer device, comprising: a memory and a processor, the memory storing a computer program, and the processor implementing the steps of any of the above methods for preventing bus deadlock on a chip system when executing the computer program.

[0017] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the method for preventing bus deadlock on a chip system as described in any one of the above items are implemented.

[0018] The above technical solution provided by the embodiment of the present application has at least some or all of the following advantages compared with the prior art: The method for preventing bus deadlock on a chip system described in an embodiment of the present application provides, for each address space on the bus, at least one group of configuration registers for describing address space attributes, wherein each group of configuration registers includes a first register and a second register; in the first register, a cacheable attribute bit field, an uncacheable attribute bit field, a device attribute bit field and an address space starting address bit field are configured, and in the second register, a bit field for calculating the size of the address space to be described is configured; the attributes of the current address space are determined according to the values ​​of the cacheable attribute bit field, the uncacheable attribute bit field and the device attribute bit field; according to the attributes of the current address space and the address request of the current address space, it is determined whether access to the current address space is allowed, and the address where the address hole may occur is described by combining at least one attribute of the configuration register to avoid the problem of bus deadlock caused by the address hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of chip system integration provided by the prior art; Figure 2 A flow chart of a method for preventing bus deadlock on a chip system provided by one embodiment of the present application; Figure 3 A schematic diagram of a first register bit field provided for an embodiment of the present application; Figure 4 A schematic diagram of a fixed hole address deadlock scenario provided for an embodiment of the present application; Figure 5A schematic diagram of a variable hole address deadlock scenario provided for an embodiment of the present application; Figure 6 A schematic diagram of a deadlock scenario in which a small number of addresses can be normally accessed among a large number of empty addresses provided in one embodiment of the present application; Figure 7 A schematic diagram of the structure of a device for preventing bus deadlock on a chip system provided in one embodiment of the present application; Figure 8 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0020] In the process of implementing the present application, the inventor discovered that the current chip system has a bus deadlock problem due to empty addresses.

[0021] In response to the above problems, the embodiments of the present application provide a method, apparatus, device and storage medium for preventing bus deadlock on a chip system, so as to avoid the bus deadlock problem caused by empty addresses on the chip system.

[0022] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0023] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0024] See also Figure 2 The embodiment of the present application provides a method for preventing bus deadlock on a chip system, including the following steps S100 to S400: S100, for each address space on the bus, providing at least one group of configuration registers for describing attributes of the address space, wherein each group of configuration registers includes a first register and a second register; S200, in the first register, configure the cacheable attribute bit field, the non-cacheable attribute bit field, the device attribute bit field and the address space starting address bit field, and in the second register, configure the bit field used to calculate the size of the address space to be described; S300, determining the attributes of the current address space according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field and the device attribute bit field; S400: Determine whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space.

[0025] In an optional embodiment of the present application, the device attribute space is a space provided for device peripherals. It is allowed only when it has been confirmed that the instruction really needs to access the address of the attribute space. When a predictive address request access occurs, an error is reported to the processor. The cacheable attribute space is an attribute provided for the cache memory. In order to explicitly accelerate data access, the space can be accessed by predictive address requests. The non-cacheable attribute space can also be accessed by predictive address requests.

[0026] In an optional embodiment of the present application, in S100, see Figure 3 , taking a 32-bit address as an example, the bit field of the first register includes 0, 1, 2 and 31:3. The following Tables 1 and 2 are description tables of the first register and the second register respectively.

[0027] Table 1

[0028] In Table 1, a first register can only be one of the above three attributes, that is, the above three attributes must be mutually exclusive. If the above three attributes are all 0, it is called a normal attribute, which is a hidden attribute and can be accessed by predictive address requests. The lower 3 bits are occupied, which does not affect the description of the address space, because the minimum described address space is 4k, so it does not affect the setting of BASE_ADDR.

[0029] Table 2

[0030] In an optional embodiment of the present application, when the interval [0x80000000, 0x90000000) needs to be configured as a device attribute, the two register groups of the configuration register entry0 can be configured as follows: The first register entry_base_address_cfg0 = 0x80000004; The second register entry_range_mask_cfg0 = 0xf0000000.

[0031] In an optional embodiment of the present application, in S300, the attributes of the current address space are determined according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field, including: When the value of the cacheable attribute bit field is 1, and the values ​​of the non-cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the cacheable attribute; When the value of the non-cacheable attribute bit field is 1, and the values ​​of the cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the non-cacheable attribute; When the value of the device attribute bit field is 1, and the values ​​of the non-cacheable attribute bit field and the cacheable attribute bit field are both 0, the attribute of the current address space is the device attribute; When the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field are all 0, the attributes of the current address space are normal attributes.

[0032] In an optional embodiment of the present application, in S400, determining whether to allow access to the current address space according to the attribute of the current address space and the address request of the current address space includes: In the case where the attribute of the current address space is a device attribute and the address request is a predictive address request, access to the current address space is not allowed; In a case where the attribute of the current address space is any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute and the address request is a predictive address request, access to the current address space is permitted.

[0033] In an optional embodiment of the present application, the method further includes: In the case where multiple groups of configuration registers describe the attributes of the same address space, the attributes of the current address space are determined according to the priority of the address space attributes, where the address space attributes are sorted from high to low priority as follows: cacheable attributes, non-cacheable attributes, device attributes, and common attributes.

[0034] In an optional embodiment of the present application, there may be many groups of configuration register entries, and the number of groups of configuration register entries required may be selected in hardware according to specific application requirements, and each group of configuration register entries may describe the attributes of the same or different addresses. In other words, multiple configuration register entries may be used to describe the attributes of the same address, and when the same address has multiple attributes, different priorities are assigned to the address attributes, and the attribute with the highest priority is used as the attribute of the address.

[0035] In an optional embodiment of the present application, the method further includes: For each fixed hole address space on the bus, the attributes of the current fixed hole address space are described as device attributes through a group of configuration registers.

[0036] like Figure 4As shown, suppose there is an address space [0x80000000, 0x90000000), which is a hole address space. The address space attribute is uncacheable by default, so when the processor initiates a predictive address request and falls into the area space [0x80000000, 0x90000000), a deadlock will occur. The area space can be described by a set of configuration register entries. Assuming that a set of configuration register entry0 describes the space as uncacheable, the space attribute described by the configuration register entry0 can be changed to a device attribute space. The configuration is as follows: entry_base_address_cfg0 = 0x80000004; entry_range_mask_cfg0 =0xf0000000; Therefore, when the processor initiates a predictive address request, an error will be reported to prevent the deadlock problem caused by the empty address.

[0037] like Figure 5 As shown, suppose there is a bus system now, a part of the address space [0x80000000, 0x800f000) may be a hole address for a period of time, and can be accessed normally by predictable address requests for a period of time, and the rest are all hole address spaces. It can be seen that a small part of the address space can be predictably accessed normally in a specific place, and a specific scene may be a hole address. When the address space [0x80000000, 0x800f000) becomes a hole address at a certain moment, you only need to use the following process to configure it, as follows: entry_base_address_cfg0= 0x80000004; entry_range_mask_cfg0=0xfffff000; At this time, when the processor initiates a predictive address request that falls in this area, an error will be reported to prevent the system from deadlocking. However, if the predictive address request initiated by the processor falls on [0x80000000, 0x800f000), and it happens that in the scenario at that time, the space [0x80000000, 0x800f000) can be accessed normally, if it is still used as a device attribute space, it will lead to the situation that the interval [0x80000000, 0x800f000) cannot be accessed. Therefore, you can continue to configure entry0 to describe the area [0x80000000, 0x800f000) again, and use entry0 to set [0x80000000, 0x800f000) as a cacheable attribute space; entry_base_address_cfg0 = 0x80000001; entry_range_mask_cfg0 =0xfffff000; In this way, the space from 0x80000000 to 0x800f000 changes from device attributes to cacheable attributes, so it can be accessed normally at this time.

[0038] like Figure 6 As shown, suppose there is a bus system now, most of the address space is empty address space, and only a small part of the space [0x80000000, 0x800f000) can be accessed. In this scenario, the entire space can be described as device attribute space. You can use entry0 to configure the entire space as device attributes. The configuration is as follows: entry_base_address_cfg0= 0x00000004; entry_range_mask_cfg0=0x00000000; At this time, when the processor initiates a predictive address request that falls in this area, an error will be reported, thus preventing the system from deadlocking. However, if the processor initiates a predictive address request that falls in [0x80000000, 0x800f000), and the space [0x80000000, 0x800f000) can be accessed normally, if it is still used as a device attribute space, it will result in the situation where the interval [0x80000000, 0x800f000) cannot be accessed. Therefore, another entry1 can be used to describe the area [0x80000000, 0x800f000) again, and entry1 is used to set [0x80000000, 0x800f000) as a cacheable attribute space. The configuration is as follows: entry_base_address_cfg1 = 0x80000001; entry_range_mask_cfg1 =0xfffff000; In this way, the space from 0x80000000 to 0x800f000 has two attributes, cacheable attribute and device attribute. Due to the existence of attribute priority, the device attribute will be overwritten, so it can be accessed normally at this time.

[0039] In an optional embodiment of the present application, the method further includes: For each variable hole address space on the bus, during the period when the variable hole address space is a hole address, the attributes of the current variable hole address space are described as device attributes through a group of configuration registers. During the period when the variable hole address space is a non-hole address, the attributes of the current variable hole address space are described as any one of non-cacheable attributes, cacheable attributes and ordinary attributes by modifying the configuration of the current group of configuration registers.

[0040] In an optional embodiment of the present application, the method further includes: For each hybrid address space on the bus, the attributes of the current hybrid address space are described as device attributes through a set of configuration registers, and the attributes of the hole address space in the current hybrid address space are described as any one of uncacheable attributes, cacheable attributes and ordinary attributes through another set of configuration registers, wherein the hybrid address space includes hole address space and non-hole address space and the proportion of non-hole address space in the hybrid address space is less than a preset value.

[0041] The method for preventing bus deadlock on the chip system of the present application can flexibly change the attributes of the current address space through multiple address attribute descriptions, thereby solving the problem that when the processor in the chip system performs predictive address access, deadlock occurs when accessing a hole address, or the accessed address dynamically changes attributes and becomes inaccessible.

[0042] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0043] See also Figure 7 An embodiment of the present application provides a device 700 for preventing bus deadlock on a chip system, comprising: Providing a module 710, for providing, for each address space on the bus, at least one set of configuration registers for describing address space attributes, wherein each set of configuration registers includes a first register and a second register; A configuration module 720 is used to configure the cacheable attribute bit field, the non-cacheable attribute bit field, the device attribute bit field and the address space start address bit field in the first register, and to configure the bit field used to calculate the address space size to be described in the second register; A first determination module 730, configured to determine the attributes of the current address space according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field; The second determination module 740 is used to determine whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space.

[0044] The device for preventing bus deadlock on the chip system of the present application flexibly changes the attributes of the current address space through multiple address attribute descriptions, thereby solving the problem that when the processor in the chip system encounters predictive address access, deadlock occurs when accessing a hole address, or the accessed address space is sometimes accessible and sometimes becomes a hole address, resulting in the access request being unable to execute normally.

[0045] For the specific definition of the above-mentioned device 700, please refer to the definition of the method for preventing bus deadlock on the chip system above, which will not be repeated here. Each module in the above-mentioned device 700 can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0046] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 8 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for preventing bus deadlock on a chip system as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the method for preventing bus deadlock on a chip system as described above is implemented.

[0047] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the method for preventing bus deadlock on a chip system as described above can be implemented.

[0048] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0049] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0050] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0051] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0052] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0053] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for preventing bus deadlock on a chip system, characterized in that: include: For each address space on the bus, at least one group of configuration registers for describing attributes of the address space is provided, wherein each group of configuration registers includes a first register and a second register; In the first register, configure the cacheable attribute bit field, the non-cacheable attribute bit field, the device attribute bit field and the address space start address bit field, and in the second register, configure the bit field used to calculate the size of the address space to be described; Determine the attributes of the current address space according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field and the device attribute bit field; Whether access to the current address space is permitted is determined according to the attributes of the current address space and the address request of the current address space.

2. The method according to claim 1, characterized in that The attributes of the current address space are determined based on the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field, including: When the value of the cacheable attribute bit field is 1, and the values ​​of the non-cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the cacheable attribute; When the value of the non-cacheable attribute bit field is 1, and the values ​​of the cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the non-cacheable attribute; When the value of the device attribute bit field is 1, and the values ​​of the non-cacheable attribute bit field and the cacheable attribute bit field are both 0, the attribute of the current address space is the device attribute; When the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field are all 0, the attributes of the current address space are normal attributes.

3. The method according to claim 2, characterized in that Determine whether to allow access to the current address space based on the attributes of the current address space and the address request of the current address space, including: In the case where the attribute of the current address space is a device attribute and the address request is a predictive address request, access to the current address space is not allowed; In a case where the attribute of the current address space is any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute and the address request is a predictive address request, access to the current address space is permitted.

4. The method according to claim 2, characterized in that: The method further comprises: In the case where multiple groups of configuration registers describe the attributes of the same address space, the attributes of the current address space are determined according to the priority of the address space attributes, where the address space attributes are sorted from high to low priority as follows: cacheable attributes, non-cacheable attributes, device attributes, and common attributes.

5. The method according to claim 3, characterized in that: The method further comprises: For each fixed hole address space on the bus, the attributes of the current fixed hole address space are described as device attributes through a group of configuration registers.

6. The method according to claim 3, characterized in that The method further comprises: For each variable hole address space on the bus, during the period when the variable hole address space is a hole address, the attributes of the current variable hole address space are described as device attributes through a group of configuration registers. During the period when the variable hole address space is a non-hole address, the attributes of the current variable hole address space are described as any one of non-cacheable attributes, cacheable attributes and ordinary attributes by modifying the configuration of the current group of configuration registers.

7. The method according to claim 3, characterized in that The method further comprises: For each hybrid address space on the bus, the attributes of the current hybrid address space are described as device attributes through a set of configuration registers, and the attributes of the hole address space in the current hybrid address space are described as any one of uncacheable attributes, cacheable attributes and ordinary attributes through another set of configuration registers, wherein the hybrid address space includes hole address space and non-hole address space and the proportion of non-hole address space in the hybrid address space is less than a preset value.

8. A device for preventing bus deadlock on a chip system, characterized in that: include: Providing a module for providing, for each address space on the bus, at least one set of configuration registers for describing address space attributes, wherein each set of configuration registers includes a first register and a second register; A configuration module, configured to configure a cacheable attribute bit field, a non-cacheable attribute bit field, a device attribute bit field, and an address space start address bit field in a first register, and to configure a bit field used to calculate a size of an address space to be described in a second register; A first determination module, used to determine the attributes of the current address space according to the values ​​of the cacheable attribute bit field, the non-cacheable attribute bit field and the device attribute bit field; The second determination module is used to determine whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space.

9. A computer device comprising: It comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the method for preventing bus deadlock on the chip system as described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for preventing bus deadlock on a chip system as described in any one of claims 1 to 7 are implemented.

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