Memory testing method, device, storage medium and electronic device

Abstract

An embodiment of the present invention provides a memory testing method, device, storage medium, electronic device and program product, wherein the method comprises: determining the maximum number of bad blocks allowed to exist when the target memory to be tested operates normally, wherein the bad blocks are memory blocks in abnormal states existing in the target memory; configuring a first number of bad blocks for the target memory, wherein the first number is less than the maximum number of bad blocks; performing a card opening operation on the target memory, and obtaining target bad block information in the target memory when the card opening of the target memory is successful; determining a comparison result between the target bad block information and the first bad block information, wherein the first bad block information includes information of the first number of bad blocks; and determining a test result of the memory based on the comparison result.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computers, and in particular, to a memory testing method, device, storage medium, electronic device, and program product. Background Art

[0002] Memory testing is an important part of computer hardware testing. Testing the memory can ensure the stability of data storage under various operating conditions.

[0003] The memory testing method in the related art can only perform testing based on the actual bad block situation in the memory, so there is a problem of low testing efficiency. Summary of the invention

[0004] Embodiments of the present invention provide a memory testing method, device, storage medium, electronic device and program product to at least solve the problem of low testing efficiency in memory testing methods in related technologies.

[0005] According to one embodiment of the present invention, a method for testing a memory is provided, comprising: determining a maximum number of bad blocks that are allowed to exist when a target memory to be tested is operating normally, wherein the bad blocks are memory blocks in the target memory that are in an abnormal state; configuring a first number of bad blocks for the target memory, wherein the first number is less than the maximum number of bad blocks; performing a card opening operation on the target memory, and obtaining target bad block information in the target memory if the card opening of the target memory is successful; determining a comparison result between the target bad block information and the first bad block information, wherein the first bad block information includes information of the first number of bad blocks; and determining a test result of the memory based on the comparison result.

[0006] In an exemplary embodiment, configuring a first number of bad blocks for the target memory includes: determining a second number of first bad blocks that are actually damaged in the target memory; when the second number is less than the first number, determining a target difference between the second number and the first number, determining the target difference number of normal storage blocks from the target memory to obtain target healthy blocks, and configuring the attribute information of the target healthy blocks as bad block attribute information.

[0007] In an exemplary embodiment, determining the test result of the memory based on the comparison result includes at least one of the following: when the comparison result is used to indicate that the target bad block information is not completely consistent with the first bad block information, determining that the target memory test fails; when the comparison result is used to indicate that the target bad block information is completely consistent with the first bad block information, performing a target read and write test on the target memory to obtain a read and write result, and determining the test result of the target memory based on the read and write result.

[0008] In an exemplary embodiment, determining the test result of the target memory based on the read and write results includes: when the read and write results are used to indicate that the read and write test of the target memory has passed, determining that the target memory test has passed; when the read and write results are used to indicate that the read and write test of the target memory has failed, determining that the target memory test has failed.

[0009] In an exemplary embodiment, configuring the attribute information of the target healthy block as bad block attribute information includes at least one of the following: configuring a flag bit used to record the working status of the target healthy block as a target value, wherein the target value is used to indicate that the working status is an abnormal state; adding the information of the target healthy block in a bad block table used to record bad block information.

[0010] In an exemplary embodiment, the target read / write test includes at least one of the following: a read / write speed test, a read / write accuracy test, a bad block management test, and a read / write stress test.

[0011] According to another embodiment of the present invention, a memory testing device is provided, comprising: a first determination module, used to determine the maximum number of bad blocks allowed to exist when the target memory to be tested operates normally, wherein the bad blocks are memory blocks in the target memory that are in an abnormal state; a configuration module, used to configure a first number of bad blocks for the target memory, wherein the first number is less than the maximum number of bad blocks; a card opening module, used to perform a card opening operation on the target memory, and when the card opening of the target memory is successful, obtain target bad block information in the target memory; a second determination module, used to determine a comparison result between the target bad block information and the first bad block information, wherein the first bad block information includes information of the first number of bad blocks; and a third determination module, used to determine a test result of the memory based on the comparison result.

[0012] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.

[0013] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0014] According to yet another embodiment of the present invention, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0015] Through the present invention, since the number of bad blocks of the memory to be tested is configured according to the maximum number of bad blocks, it is possible to test the capabilities of the memory under different numbers of bad blocks. Therefore, it is possible to solve the problem of low test efficiency existing in the memory testing method in the related art, thereby achieving the effect of improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a hardware structure block diagram of a mobile terminal according to a memory testing method of an embodiment of the present invention;

[0017] Figure 2 The process of the memory testing method according to the embodiment of the present invention is as follows Figure 1 ;

[0018] Figure 3 FIG. 1 is a schematic diagram of a configuration method of a target healthy block according to an embodiment of the present invention. Figure 1 ;

[0019] Figure 4 FIG. 1 is a schematic diagram of a configuration method of a target healthy block according to an embodiment of the present invention. Figure 2 ;

[0020] Figure 5 FIG. 1 is a schematic diagram of a configuration method of a target healthy block according to an embodiment of the present invention. Figure 3 ;

[0021] Figure 6 FIG. 1 is a schematic diagram of a configuration method of a target healthy block according to an embodiment of the present invention. Figure 4 ;

[0022] Figure 7 FIG. 1 is a schematic diagram of a configuration method of a target healthy block according to an embodiment of the present invention. Figure 5 ;

[0023] Figure 8 FIG. 1 is a schematic diagram of a configuration method of a target healthy block according to an embodiment of the present invention. Figure 6 ;

[0024] Fig. 9 The process of the memory testing method according to the embodiment of the present invention is as follows Figure 2;

[0025] Fig.10 4 is a structural block diagram of a memory testing device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0028] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a mobile terminal according to a memory testing method of an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0029] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the memory test method in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0030] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] In this embodiment, a test method for a memory running on the mobile terminal is provided. Figure 2 The process of the memory testing method according to the embodiment of the present invention is as follows Figure 1 ,like Figure 2 As shown, the process includes the following steps:

[0032] Step S202, determining the maximum number of bad blocks that are allowed to exist when the target memory to be tested is operating normally, wherein the bad blocks are storage blocks in the target memory that are in abnormal states;

[0033] Step S204, configuring a first number of bad blocks for the target memory, wherein the first number is less than the maximum number of bad blocks;

[0034] Step S206, performing a card opening operation on the target storage, and obtaining target bad block information in the target storage when the card opening of the target storage is successful;

[0035] Step S208, determining a comparison result between the target bad block information and the first bad block information, wherein the first bad block information includes information of the first number of bad blocks;

[0036] Step S210: determining a test result of the memory based on the comparison result.

[0037] In the above steps, the target memory includes but is not limited to: random access memory (RAM), read-only memory (ROM), flash memory, embedded multimedia memory card (EMMC) memory, etc. The target bad block information includes but is not limited to: the number of bad blocks in the acquired target memory, the physical address, logical address, repair record and access record of each bad block, etc. The first bad block information includes but is not limited to: the first number, the physical address, logical address, repair record and access record of each bad block included in the configured first number of bad blocks, etc. Exemplarily, in the case where the target memory fails to start the card, the test result of the target memory is determined to be failed.

[0038] In the above steps, by configuring the number of bad blocks of the memory to be tested according to the maximum number of bad blocks, it is possible to test the capabilities of the memory under different numbers of bad blocks, thereby avoiding the problem of low testing efficiency caused by the testing method in the related art being able to only test based on the actual bad block situation in the memory, thereby improving the testing efficiency.

[0039] The execution subject of the above steps may be a memory test device, other terminals that can execute memory test programs, etc., but is not limited thereto.

[0040] In an optional embodiment, configuring a first number of bad blocks for the target memory includes: determining a second number of first bad blocks that are actually damaged in the target memory; when the second number is less than the first number, determining a target difference between the second number and the first number; determining the target difference number of normal storage blocks from the target memory to obtain target healthy blocks, and configuring the attribute information of the target healthy blocks as bad block attribute information.

[0041] In the above steps, exemplarily, configuring the attribute information of the target healthy block as bad block attribute information includes but is not limited to: sending an attribute modification instruction of the target healthy block to the memory based on an interface in the memory, and the interface in the memory is but is not limited to: SATA interface, M.2 interface, PCIe interface, SAS interface, NVMe interface, etc.

[0042] Figures 3 to 8 is a schematic diagram of a configuration method of a target health block according to an embodiment of the present invention, such as Figures 3 to 8As shown, the configuration method includes but is not limited to: a random single-row bad block injection algorithm, a random multi-row bad block injection algorithm, a random single-column bad block injection algorithm, a random multi-column bad block injection algorithm, a random multi-row multi-column bad block injection algorithm, and a random bad block injection algorithm. Exemplarily, the random single-row bad block injection algorithm includes but is not limited to: when the target difference is equal to the number of single-row blocks, randomly select a row of blocks to determine as the target healthy block; when the target difference is less than the number of single-row blocks, randomly select a row of blocks, and randomly select the target difference target healthy blocks in the row. The random multi-row bad block injection algorithm includes but is not limited to: when the target difference is an integer multiple of the number of single-row blocks, determine the quotient value M of the target difference and the number of single-row blocks, and randomly select M rows of target healthy blocks; when the quotient value M of the target difference and the number of single-row blocks is greater than 1 and there is a remainder, randomly select M rows of target healthy blocks, randomly select a row from other rows except M rows, and randomly select the remainder target healthy blocks in the row. The random single-column bad block injection algorithm includes but is not limited to: when the target difference is equal to the number of blocks in a single column, randomly select a column of blocks to determine as the target healthy blocks; when the target difference is less than the number of blocks in a single column, randomly select a column of blocks, and randomly select target healthy blocks of the target difference in the column. The random multi-column bad block injection algorithm includes but is not limited to: when the target difference is an integer multiple of the number of blocks in a single column, determine the quotient N of the target difference and the number of blocks in a single column, and randomly select N columns of target healthy blocks; when the quotient N of the target difference and the number of blocks in a single column is greater than 1 and there is a remainder, randomly select N columns of target healthy blocks, randomly select a column from the other columns except the N columns, and randomly select the remainder of target healthy blocks in the column.

[0043] In the above steps, illustratively, determining the target difference number of normal storage blocks from the target memory to obtain the target healthy blocks includes but is not limited to: determining the distribution mode of one or more target blocks by the above algorithm. Exemplarily, when there are multiple distribution modes, the test result of the target memory can be determined according to the card opening results of the target healthy blocks under different distribution modes, the accuracy of the target bad block information, and the results of the target read and write tests.

[0044] In the above steps, by comparing the second number of first bad blocks actually damaged in the target memory with the preset first number, and when the second number is less than the first number, determining a target difference number of target healthy blocks, and configuring the target healthy blocks as bad blocks, a variety of bad block distribution conditions are performed, thereby achieving performance and reliability testing of the memory under different bad block distribution conditions, improving test efficiency, and ensuring the reliability and stability of the memory in actual applications.

[0045] In an optional embodiment, determining the test result of the memory based on the comparison result includes at least one of the following: when the comparison result is used to indicate that the target bad block information is not completely consistent with the first bad block information, determining that the target memory test fails; when the comparison result is used to indicate that the target bad block information is completely consistent with the first bad block information, performing a target read and write test on the target memory to obtain a read and write result, and determining the test result of the target memory based on the read and write result.

[0046] In the above steps, exemplarily, determining the test result of the memory based on the comparison result includes but is not limited to: obtaining the bad block quantity information and location information in the bad block table, determining whether the bad block quantity information and location information in the bad block table are consistent with the first quantity and the bad block location of the first quantity of bad blocks to obtain the test result of the target memory.

[0047] In an optional embodiment, determining the test result of the target memory based on the read and write results includes: when the read and write results are used to indicate that the read and write test of the target memory has passed, determining that the target memory test has passed; when the read and write results are used to indicate that the read and write test of the target memory has failed, determining that the target memory test has failed.

[0048] In an optional embodiment, configuring the attribute information of the target healthy block as bad block attribute information includes at least one of the following: configuring a flag bit used to record the working status of the target healthy block as a target value, wherein the target value is used to indicate that the working status is an abnormal state; adding the information of the target healthy block in a bad block table used to record bad block information.

[0049] In the above steps, exemplarily, configuring the flag used to record the working status of the target healthy block as a target value includes but is not limited to: based on the interface in the memory, customizing the flag modification instruction through software, and sending the flag modification instruction to command the memory to modify the factory bad block flag in the page of the target healthy block in the original particle. The way to configure the attribute information of the target healthy block as bad block attribute information includes but is not limited to: in the case where there are multiple target healthy blocks, marking the target healthy block combination based on the interface of the memory, exemplarily, the interface can calculate the blk position that needs to be marked through DIE, PLANE, RBLK, and the offset offset position of the specific block. In the case where multiple target healthy blocks include a whole row of bad blocks in the same row and column, the interface can support simultaneous batch marking.

[0050] In the above steps, the target healthy block is configured as a bad block by modifying and adding the bad block attribute information of the target healthy block, without the need to erase and mark the bad block through slow real reading and writing, which greatly improves the test efficiency.

[0051] In an optional embodiment, the target read-write test includes at least one of the following: a read-write speed test, a read-write accuracy test, a bad block management test, and a read-write stress test.

[0052] The following is an exemplary description of the embodiments in this application in conjunction with specific embodiments:

[0053] Fig. 9 The process of the memory testing method according to the embodiment of the present invention is as follows Figure 2 ,like Fig. 9 As shown, the process includes the following steps:

[0054] Step S902, modify the manufacturer's bad block flag and construct a bad block interface;

[0055] Step S904, sending multiple bad block injection model combinations using the bad block interface to simulate the bad block distribution that users of batch storage may encounter;

[0056] Step S906, perform a card opening operation and verify whether the bad block information in the bad block table is correct;

[0057] Step S908, use the fio tool to read and write to check whether the disk status is normal;

[0058] Step S910, repeat the above steps in batches to traverse different bad block injection models.

[0059] In the above step S908, the commands executed by the fio tool include but are not limited to:

[0060] fio --name=random-read-write--rw=randread--rw=randwrite--bs=4k--size=100G--numjobs=32--time_based--runtime=20.

[0061] Through the above steps, we can identify and simulate the random bad block situations that batch storage users may encounter, thereby solving the technical difficulties that various random abnormal bad block scenarios cannot be tested and verified in advance, and greatly improving the reliability of products after batch delivery. At the same time, by simulating the bad block mark of the original factory, the test efficiency is doubled compared with the current detection method of real reading, writing and erasing.

[0062] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0063] In this embodiment, a memory test device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0064] Fig.10 is a structural block diagram of a memory test device according to an embodiment of the present invention. Fig.10 As shown, the device includes: a first determination module 1002, used to determine the maximum number of bad blocks allowed to exist when the target memory to be tested is operating normally, wherein the bad blocks are storage blocks in the target memory with abnormal status; a configuration module 1004, used to configure a first number of bad blocks for the target memory, wherein the first number is less than the maximum number of bad blocks; a card opening module 1006, used to perform a card opening operation on the target memory, and when the card opening of the target memory is successful, obtain the target bad block information in the target memory; a second determination module 1008, used to determine the comparison result of the target bad block information and the first bad block information, wherein the first bad block information includes the information of the first number of bad blocks; a third determination module 1010, used to determine the test result of the memory based on the comparison result.

[0065] In an optional embodiment, the configuration module 1004 includes: a first determination unit, used to determine the second number of first bad blocks that are actually damaged in the target memory; a second determination unit, used to determine a target difference between the second number and the first number when the second number is less than the first number; a configuration unit, used to determine the target difference number of normal storage blocks from the target memory to obtain a target healthy block, and configure the attribute information of the target healthy block as bad block attribute information.

[0066] In an optional embodiment, the third determination module 1010 includes at least one of the following: a third determination unit, used to determine that the target memory test fails when the comparison result indicates that the target bad block information is not completely consistent with the first bad block information; a fourth determination unit, used to perform a target read and write test on the target memory to obtain a read and write result when the comparison result indicates that the target bad block information is completely consistent with the first bad block information, and determine the test result of the target memory based on the read and write result.

[0067] In an optional embodiment, the fourth determination unit includes: a first determination subunit, used to determine that the target memory test has passed when the read / write result is used to indicate that the target memory read / write test has passed; and a second determination subunit, used to determine that the target memory test has failed when the read / write result is used to indicate that the target memory read / write test has failed.

[0068] In an optional embodiment, the configuration unit includes at least one of the following: a configuration subunit, used to configure the flag used to record the working status of the target healthy block to a target value, wherein the target value is used to indicate that the working status is an abnormal state; an adding subunit, used to add the information of the target healthy block in the bad block table used to record bad block information.

[0069] In an optional embodiment, the target read-write test includes at least one of the following: a read-write speed test, a read-write accuracy test, a bad block management test, and a read-write stress test.

[0070] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0071] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0072] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0073] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0074] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0075] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0076] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0077] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory testing method, characterized in that: include: Determine the maximum number of bad blocks that are allowed to exist when the target memory to be tested operates normally, wherein the bad blocks are storage blocks in the target memory that are in abnormal states; Allocate a first number of bad blocks for the target memory, wherein the first number is less than the maximum number of bad blocks; Performing a card opening operation on the target memory, and obtaining target bad block information in the target memory when the card opening of the target memory is successful; Determine a comparison result between the target bad block information and first bad block information, wherein the first bad block information includes information of the first number of bad blocks; A test result of the memory is determined based on the comparison result.

2. The method according to claim 1, characterized in that Configuring a first number of bad blocks for the target memory includes: Determine a second number of first bad blocks actually damaged in the target memory; In the case where the second number is less than the first number, determining a target difference between the second number and the first number; The target difference number of normal storage blocks is determined from the target memory to obtain a target healthy block, and the attribute information of the target healthy block is configured as bad block attribute information.

3. The method according to claim 1, characterized in that Determining a test result of the memory based on the comparison result includes at least one of the following: If the comparison result indicates that the target bad block information is not completely consistent with the first bad block information, determining that the target memory test fails; When the comparison result indicates that the target bad block information is completely consistent with the first bad block information, a target read and write test is performed on the target memory to obtain a read and write result, and a test result of the target memory is determined based on the read and write result.

4. The method according to claim 3, characterized in that Determining a test result of the target memory based on the read and write results includes: In a case where the read / write result indicates that the target memory read / write test has passed, determining that the target memory test has passed; In a case where the read / write result indicates that the target memory read / write test fails, it is determined that the target memory test fails.

5. The method according to claim 2, characterized in that: Configuring the attribute information of the target healthy block as bad block attribute information includes at least one of the following: configuring a flag bit used to record the working state of the target healthy block to a target value, wherein the target value is used to indicate that the working state is an abnormal state; The information of the target healthy block is added to a bad block table used to record bad block information.

6. The method according to claim 3, characterized in that: The target read-write test includes at least one of the following: a read-write speed test, a read-write accuracy test, a bad block management test, and a read-write stress test.

7. A memory testing device, characterized in that: include: A first determination module is used to determine the maximum number of bad blocks that are allowed to exist when the target memory to be tested is operating normally, wherein the bad blocks are storage blocks in the target memory that are in abnormal states; a configuration module, configured to configure a first number of bad blocks for the target memory, wherein the first number is less than the maximum number of bad blocks; A card opening module, used to perform a card opening operation on the target memory, and obtain target bad block information in the target memory when the card opening of the target memory is successful; A second determining module, configured to determine a comparison result between the target bad block information and the first bad block information, wherein the first bad block information includes information of the first number of bad blocks; The third determining module is used to determine the test result of the memory based on the comparison result.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 6 when executed by a processor.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 6 are implemented.

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