Chip, chip starting abnormity monitoring method, storage medium and electronic equipment

Abstract

The invention discloses a chip, a chip starting abnormity monitoring method, a storage medium and electronic equipment. The chip comprises a power management circuit, a processor and a monitoring circuit. Wherein the power management circuit is used for triggering the monitoring circuit to execute timing operation in response to the power management circuit entering the running state; in response to the processor entering the running state, the processor is used for triggering the monitoring circuit to stop timing operation; the monitoring circuit is used for determining the numerical relationship between the current timing duration of the timing operation and the preset starting duration, and determining the abnormal starting monitoring result of the chip based on the numerical relationship. According to the embodiment of the invention, the starting abnormity of the chip can be effectively monitored.

Description

Technical Field

[0001] The present disclosure relates to functional safety technology, and in particular to a chip, a chip startup abnormality monitoring method, a storage medium, and an electronic device. Background Art

[0002] At present, the application of chips is very extensive. For example, in the field of intelligent driving, the application of intelligent driving chips is very extensive.

[0003] It should be noted that the normal startup of the chip is a prerequisite for the normal operation of the chip. Conversely, if the chip has a startup abnormality, the chip may not work normally. Therefore, it is necessary to monitor the startup abnormality of the chip. How to implement the startup abnormality monitoring of the chip is a problem worthy of attention for those skilled in the art. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a chip, a chip startup abnormality monitoring method, a storage medium and an electronic device.

[0005] According to one aspect of an embodiment of the present disclosure, a chip is provided, comprising: a power management circuit, a processor, and a monitoring circuit; wherein:

[0006] In response to the power management circuit entering the running state, the power management circuit is used to trigger the monitoring circuit to perform a timing operation;

[0007] In response to the processor entering the running state, the processor is used to trigger the monitoring circuit to stop executing the timing operation;

[0008] The monitoring circuit is used to determine the numerical relationship between the current timing duration of the timing operation and the preset startup duration, and based on the numerical relationship, determine the startup abnormality monitoring result of the chip.

[0009] According to another aspect of an embodiment of the present disclosure, a method for abnormality monitoring of chip startup is provided, comprising:

[0010] In response to a power management circuit in the chip entering an operating state, performing a timing operation;

[0011] In response to the processor in the chip entering a running state, stopping the execution of the timing operation;

[0012] Determine a numerical relationship between a current timing duration of the timing operation and a preset start duration;

[0013] Based on the numerical relationship, a startup abnormality monitoring result of the chip is determined.

[0014] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the above-mentioned chip startup abnormality monitoring method.

[0015] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device comprising:

[0016] processor;

[0017] a memory for storing instructions executable by the processor;

[0018] The processor is used to read the executable instructions from the memory and execute the instructions to implement the above-mentioned chip startup abnormality monitoring method.

[0019] According to another aspect of the embodiments of the present disclosure, a computer program product is provided. When instructions in the computer program product are executed by a processor, the above-mentioned chip startup abnormality monitoring method is executed.

[0020] Based on the chip, chip startup abnormality monitoring method, storage medium, electronic device and program product provided in the above embodiments of the present disclosure,

[0021] In the chip provided by the embodiment of the present disclosure, the power management circuit can trigger the monitoring circuit to perform the timing operation in response to itself entering the running state, and the processor can trigger the monitoring circuit to stop performing the timing operation in response to itself entering the running state. It should be noted that in the normal startup process of the chip, if the chip is powered on, the power management circuit can start working quickly, and after the power management circuit works for a period of time, the processor can start working. Since the processor will trigger the monitoring circuit to stop performing the timing operation, the monitoring circuit will stop timing before the current timing duration of the timing operation reaches the preset startup duration. Accordingly, the current timing duration will not exceed the preset startup duration. On the contrary, if the chip has a startup abnormality, the processor is likely to be unable to start working, and the processor naturally cannot trigger the monitoring circuit to stop performing the timing operation. The monitoring circuit will maintain the timing state for a long time, and accordingly, the current timing duration is likely to exceed the preset startup duration. Therefore, referring to the numerical relationship between the current timing duration and the preset startup duration, it can be effectively inferred whether the processor can normally trigger the monitoring circuit to stop performing the timing operation, thereby determining the startup abnormality monitoring result of the chip. For example, if the processor can normally trigger the monitoring circuit to stop performing the timing operation, the startup abnormality monitoring result of the chip can be used to characterize that the chip does not have a startup abnormality. If the processor cannot normally trigger the monitoring circuit to stop executing the timing operation, the startup abnormality monitoring result of the chip can be used to characterize the existence of startup abnormality in the chip.

[0022] It can be seen that in the embodiments of the present disclosure, the power management circuit, the processor and the monitoring circuit work together to effectively monitor the startup abnormality of the chip. It should be emphasized that the power management circuit, the processor and the monitoring circuit are all components of the chip. Therefore, in the embodiments of the present disclosure, the chip monitors its own startup abnormality without relying on external circuits, which has higher reliability and higher monitoring efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the structure of a chip provided by some exemplary embodiments of the present disclosure.

[0024] Figure 2 It is a schematic diagram of the structure of chips provided by other exemplary embodiments of the present disclosure.

[0025] Figure 3-1 is a schematic diagram of the structure of a monitoring circuit in some exemplary embodiments of the present disclosure.

[0026] Figure 3-2 is a schematic diagram of the structure of the monitoring circuit in some other exemplary embodiments of the present disclosure.

[0027] Figure 4 is a schematic diagram of the structure of a monitoring circuit in some further exemplary embodiments of the present disclosure.

[0028] Figure 5 Schematic diagram of the structure of chips provided by some further exemplary embodiments of the present disclosure.

[0029] Figure 6 is a schematic diagram of the structure of monitoring circuits in some further exemplary embodiments of the present disclosure.

[0030] Figure 7 It is a flowchart of a chip startup abnormality monitoring method provided in some embodiments of the present disclosure.

[0031] Figure 8-1 It is a flowchart of a method for determining a startup abnormality monitoring result of a chip based on a numerical relationship in some embodiments of the present disclosure.

[0032] Figure 8-2 It is a flowchart of a method for determining a startup abnormality monitoring result of a chip based on a numerical relationship and applying the startup abnormality monitoring result in some embodiments of the present disclosure.

[0033] Figure 8-3 It is a flowchart of a method for determining a startup abnormality monitoring result of a chip based on a numerical relationship and applying the startup abnormality monitoring result in other embodiments of the present disclosure.

[0034] Fig. 9 It is a flowchart of a method for stopping execution of a timing operation in some embodiments of the present disclosure.

[0035] Fig.10 It is a flowchart of a chip startup abnormality monitoring method provided in some other embodiments of the present disclosure.

[0036] Fig.11 It is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0038] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0039] Application Overview

[0040] Chip startup can be understood as a series of hardware-level initialization processes from the power-on or reset of the chip to the start of the operating system or application program. It involves very complex processes such as power-on or reset, clock initialization, memory detection and initialization, hardware self-test, and loading system configuration.

[0041] If the chip has a startup abnormality, the chip is likely to not work properly. If the chip is an intelligent driving chip used in the field of intelligent driving, the entire vehicle system is also likely to not work properly, which can easily affect driving safety. Therefore, it is necessary to monitor the chip for startup abnormalities.

[0042] Exemplary Structure

[0043] Figure 1 Schematic diagram of the structure of the chip provided by some exemplary embodiments of the present disclosure. Figure 1 As shown, the chip may include: a power management circuit 10, a processor 20 and a monitoring circuit 30; wherein,

[0044] In response to the power management circuit 10 entering the operating state, the power management circuit 10 is used to trigger the monitoring circuit 30 to perform a timing operation;

[0045] In response to the processor 20 entering the running state, the processor 20 is used to trigger the monitoring circuit 30 to stop executing the timing operation;

[0046] The monitoring circuit 30 is used to determine the numerical relationship between the current timing duration of the timing operation and the preset startup duration, and to determine the startup abnormality monitoring result of the chip based on the numerical relationship.

[0047] Optionally, the power management circuit 10 may be a component of the chip for managing power. The power management circuit 10 may control and monitor the power supply so that a stable and efficient power supply can be maintained under various workloads. The power management circuit 10 may also be referred to as a power management unit (PMU).

[0048] Optionally, the processor 20 may be a component of a chip for executing program instructions and processing data. The processor 20 may include but is not limited to a central processing unit (CPU), a microcontroller (MCU), and the like.

[0049] Optionally, the monitoring circuit 30 may be a core component in the chip for starting abnormality monitoring. The monitoring circuit 30 may be electrically connected to the power management circuit 10 and the processor 20, respectively. The monitoring circuit 30 may have a timing function. The timing function may be either a positive timing function or a countdown function. A preset startup duration may be configured in the monitoring circuit 30. For example, through preliminary experiments, the average duration from the power-on of the chip to the start of the processor 20 when the chip starts normally can be counted, and a certain margin can be added to the average duration to obtain a new duration, which can be used as the preset startup duration and configured in the monitoring circuit 30.

[0050] If the power management circuit 10 enters the running state, the power management circuit 10 can send a trigger signal to the monitoring circuit 30 through the electrical connection between the power management circuit 10 and the monitoring circuit 30 to trigger the monitoring circuit 30 to perform a timing operation. If the processor 20 enters the running state, the processor 20 can send a trigger signal to the monitoring circuit 30 through the electrical connection between the processor 20 and the monitoring circuit 30 to trigger the monitoring circuit 30 to stop performing the timing operation. After the monitoring circuit 30 performs the timing operation due to the triggering of the power management circuit 10, before the monitoring circuit 30 stops performing the timing operation due to the triggering of the processor 20, the monitoring circuit 30 can keep the timing state. In the timing state of the monitoring circuit 30, the monitoring circuit 30 can determine the current timing duration of the timing operation, and determine the numerical relationship between the current timing duration and the preset start-up duration.

[0051] Optionally, the numerical relationship between the current timing duration and the preset startup duration can be the size relationship between the current timing duration and the preset startup duration, or the proportional relationship between the current timing duration and the preset startup duration. If the numerical relationship between the current timing duration and the preset startup duration is the size relationship between the current timing duration and the preset startup duration, and the size relationship is specifically that the current timing duration is greater than or equal to the preset startup duration (equivalent to the current timing duration reaching the preset startup duration), the startup abnormality monitoring result of the chip can be used to characterize the existence of startup abnormality in the chip. If the numerical relationship between the current timing duration and the preset startup duration is the proportional relationship between the current timing duration and the preset startup duration, for example, it is the ratio of the current timing duration to the preset startup duration, and the ratio is greater than or equal to a preset ratio such as 1, 1.1, 1.2 (equivalent to the current timing duration reaching the preset startup duration), the startup abnormality monitoring result of the chip can be used to characterize the existence of startup abnormality in the chip.

[0052] In the chip provided by the embodiment of the present disclosure, the power management circuit 10 can trigger the monitoring circuit 30 to perform the timing operation in response to itself entering the running state, and the processor 20 can trigger the monitoring circuit 30 to stop performing the timing operation in response to itself entering the running state. It should be noted that in the normal startup process of the chip, if the chip is powered on, the power management circuit 10 can start working quickly, and after the power management circuit 10 works for a period of time, the processor 20 can start working. Since the processor 20 will trigger the monitoring circuit 30 to stop performing the timing operation, the monitoring circuit 30 will stop timing before the current timing duration of the timing operation reaches the preset startup duration. Accordingly, the current timing duration will not exceed the preset startup duration. On the contrary, if the chip has a startup abnormality, the processor 20 is likely to be unable to start working, and the processor 20 naturally cannot trigger the monitoring circuit 30 to stop performing the timing operation. The monitoring circuit 30 will maintain the timing state for a long time, and accordingly, the current timing duration is likely to exceed the preset startup duration. Therefore, referring to the numerical relationship between the current timing duration and the preset startup duration, it is possible to effectively infer whether the processor 20 can normally trigger the monitoring circuit 30 to stop executing the timing operation, thereby determining the startup abnormality monitoring result of the chip. For example, if the processor 20 can normally trigger the monitoring circuit 30 to stop executing the timing operation, the startup abnormality monitoring result of the chip can be used to characterize that there is no startup abnormality in the chip. If the processor 20 cannot normally trigger the monitoring circuit 30 to stop executing the timing operation, the startup abnormality monitoring result of the chip can be used to characterize that there is a startup abnormality in the chip.

[0053] It can be seen that in the embodiment of the present disclosure, the startup abnormality monitoring of the chip can be effectively realized through the coordinated work of the power management circuit 10, the processor 20 and the monitoring circuit 30. It should be emphasized that the power management circuit 10, the processor 20 and the monitoring circuit 30 are all components of the chip. Therefore, in the embodiment of the present disclosure, the chip monitors the startup abnormality of itself without relying on external circuits, which has higher reliability and higher monitoring efficiency.

[0054] In some optional examples, such as Figure 2 As shown, the monitoring circuit 30 may include: a timer 302 and a monitoring subcircuit 304;

[0055] In response to the power management circuit 10 entering the running state, the power management circuit 10 is used to trigger the monitoring circuit 30 to perform a timing operation, including:

[0056] In response to the power management circuit 10 entering the running state, the power management circuit 10 is used to trigger the timer 302 to perform a timing operation;

[0057] The monitoring circuit 30 is used to determine the numerical relationship between the current timing duration of the timing operation and the preset startup duration, and based on the numerical relationship, determine the startup abnormality monitoring result of the chip, including:

[0058] The timer 302 is used to determine the numerical relationship between the current timing duration of the timing operation and the preset start duration, and in response to the numerical relationship indicating that the current timing duration has reached the preset start duration, send a timeout signal to the monitoring subcircuit 304;

[0059] The monitoring sub-circuit 304 is used to determine a reception status of the timeout signal, and determine a startup abnormality monitoring result of the chip based on the reception status.

[0060] Optionally, the timer 302 may be a device having a timing function and a timeout prompt function. The timer 302 may be configured with a preset start-up duration. The timer 302 may also be called a Start-up alert timer. The power management circuit 10 may be electrically connected to the timer 302.

[0061] Optionally, the monitoring subcircuit 304 may be a core component of the monitoring circuit 30 for obtaining a startup abnormality monitoring result. The monitoring subcircuit 304 may be electrically connected to the timer 302.

[0062] If the power management circuit 10 enters the running state, through the electrical connection between the power management circuit 10 and the timer 302, the power management circuit 10 can send a trigger signal to the timer 302 to trigger the timer 302 to perform a timing operation. In the timing state of the timer 302, the timer 302 can compare the current timing duration of the timing operation with the preset start-up duration to determine the numerical relationship between the current timing duration and the preset start-up duration. If the numerical relationship indicates that the current timing duration has not reached the preset start-up duration, the timer 302 can continue to maintain the timing state. If the numerical relationship indicates that the current timing duration has reached the preset start-up duration, the timer 302 can send a timeout signal to the monitoring subcircuit 304. In addition, the timer 302 can also exit the timing state (i.e., stop timing).

[0063] In an example, Figure 2 As shown, the timer 302 can be connected to the monitoring subcircuit 304 via the timeout signal transmission line 40 (specifically, it can be electrically connected). If the numerical relationship indicates that the current timing duration has not reached the preset start duration, the level signal transmitted on the timeout signal transmission line 40 can be a low level signal. If the numerical relationship indicates that the current timing duration has reached the preset start duration, the level signal transmitted on the timeout signal transmission line 40 can be a high level signal, and the high level signal can be used as the timeout signal sent by the timer 302 to the monitoring circuit 304.

[0064] The monitoring subcircuit 304 can determine the reception status of the timeout signal. The reception status can be used to indicate whether the monitoring subcircuit 304 obtains the timeout signal. The monitoring subcircuit 304 can also determine the startup abnormality monitoring result of the chip based on the reception status. For example, if the reception status is used to indicate that the monitoring subcircuit 304 obtains the timeout signal, the startup abnormality monitoring result of the chip can be used to indicate that the chip has a startup abnormality. If the reception status is used to indicate that the monitoring subcircuit 304 does not obtain the timeout signal, the startup abnormality monitoring result of the chip can be used to indicate that the chip does not have a startup abnormality.

[0065] In the embodiment of the present disclosure, the power management circuit 10 can trigger the timer 302 to perform the timing operation in response to itself entering the running state, and the timer 302 can send a timeout signal to the monitoring subcircuit 304 in response to the current timing duration of the timing operation reaching the preset startup duration. It should be noted that if the monitoring subcircuit 304 obtains the timeout signal from the timer 302, this indicates that the timing operation of the timer 302 failed to stop within the preset startup duration due to the triggering of the processor 20, that is, the processor 20 failed to enter the running state within the specified time window, the processor 20 is likely to be unable to work normally, and the chip is likely to have a startup abnormality. If the monitoring subcircuit 304 has not obtained the timeout signal from the timer 302, this indicates that the timing operation of the timer 302 can be stopped within the preset startup duration due to the triggering of the processor 20, that is, the processor 20 can enter the running state within the specified time window, the processor 20 can work normally, and then the startup of the chip is normal. Therefore, according to the receiving state of the timeout signal by the monitoring sub-circuit 304, the startup abnormality monitoring result of the chip can be effectively determined, which is conducive to ensuring the accuracy and reliability of the startup abnormality monitoring result.

[0066] In some optional examples, such as Figure 3-1 As shown, the monitoring circuit 30 may include: at least two timers 302, and the preset start durations corresponding to the timers 302 may be the same;

[0067] The monitoring subcircuit 304 is used to determine the startup abnormality monitoring result of the chip based on the receiving state, including:

[0068] In response to the receiving state characterization monitoring subcircuit 304 acquiring timeout signals from more than one timer 302 , the monitoring subcircuit 304 is configured to determine that the startup abnormality monitoring result of the chip is that a startup abnormality exists.

[0069] Optionally, the number of timers 302 included in the monitoring circuit 30 may be N. N may be 2, 3, or an integer greater than 3, which are not listed here one by one. The N timers 302 may be configured with the same preset start-up duration. For example, the preset start-up durations configured in the N timers 302 may all be 1 second, or may all be 2 seconds. The N timers 302 may be electrically connected to the monitoring subcircuit 304 via N timeout signal transmission lines 40. The N timeout signal transmission lines 40 may correspond one to one to the N timers 302.

[0070] Optionally, the monitoring subcircuit 304 may determine the reception status of the timeout signal. If the level signal from more than one of the N timeout signal transmission lines 40 is a high level signal, it indicates that the monitoring subcircuit 304 has obtained the timeout signal from more than one timer 302, and the startup abnormality monitoring result of the chip may be that there is a startup abnormality.

[0071] It should be noted that a high-level signal may be generated on the timeout signal transmission line 40 due to electromagnetic interference and other reasons, and the timer 302 may not send a timeout signal to the monitoring circuit 30 by pulling up the high-level signal. In view of this, in the embodiment of the present disclosure, the monitoring circuit 30 may include at least two timers 302 corresponding to the same preset startup duration. When the monitoring subcircuit 304 obtains the timeout signal from more than one timer 302, the monitoring subcircuit 304 determines that the startup abnormality monitoring result of the chip is that there is a startup abnormality. This is equivalent to introducing a redundant voting strategy to determine the startup abnormality monitoring result of the chip, which is conducive to avoiding the adverse effects of factors such as electromagnetic interference on the determination of the startup abnormality monitoring result, thereby ensuring the accuracy and reliability of the startup abnormality monitoring result.

[0072] In some optional examples, such as Figure 3-2 As shown, the timer 302 can be connected to the monitoring sub-circuit 304 through at least two timeout signal transmission lines 40 respectively;

[0073] The monitoring subcircuit 304 is used to determine the startup abnormality monitoring result of the chip based on the receiving state, including:

[0074] In response to the receiving state characterization monitoring subcircuit 304 acquiring the corresponding timeout signal through one or more timeout signal transmission lines 40 , the monitoring subcircuit 304 is used to determine that the startup abnormality monitoring result of the chip is that there is a startup abnormality.

[0075] Optionally, the number of the timeout signal transmission lines 40 between the timer 302 and the monitoring subcircuit 304 may be M. M may be 2, 3 or an integer greater than 3, which will not be listed here one by one.

[0076] Optionally, the monitoring subcircuit 304 may determine the reception status of the timeout signal. If the level signal from more than one of the M timeout signal transmission lines 40 is a high level signal, this indicates that the monitoring subcircuit 304 has obtained the timeout signal respectively sent by the timer 302 through more than one timeout signal transmission line 40, then the startup abnormality monitoring result of the chip may be that there is a startup abnormality.

[0077] It should be noted that a high-level signal may be generated on the timeout signal transmission line 40 due to electromagnetic interference and other reasons, and the timer 302 may not send a timeout signal to the monitoring circuit 30 by pulling up the high-level signal. In view of this, in the embodiment of the present disclosure, M timeout signal transmission lines 40 may be set between the same timer 302 and the monitoring sub-circuit 304. When the monitoring sub-circuit 304 obtains the corresponding timeout signal through more than one timeout signal transmission line 40, the monitoring sub-circuit 304 determines that the startup abnormality monitoring result of the chip is that there is a startup abnormality. This is equivalent to introducing a redundant voting strategy to determine the startup abnormality monitoring result of the chip, which is conducive to avoiding the adverse effects of factors such as electromagnetic interference on the determination of the startup abnormality monitoring result, thereby facilitating the accuracy and reliability of the startup abnormality monitoring result.

[0078] In some optional examples, such as Figure 3-1 As shown, the monitoring circuit 30 may include: at least two timers 302, and the preset start durations corresponding to the timers 302 may be different;

[0079] The monitoring subcircuit 304 is used to determine the startup abnormality monitoring result of the chip based on the receiving state, including:

[0080] In response to the receiving status characterization monitoring subcircuit 304 obtaining a timeout signal from each timer 302 and the duration of the timeout signal corresponding to each timer 302 reaching a preset duration, the monitoring subcircuit 304 determines that the startup abnormality monitoring result of the chip is that a startup abnormality exists.

[0081] Optionally, the number of timers 302 included in the monitoring circuit 30 may be R. R may be 2, 3, or an integer greater than 3, which are not listed here one by one. The R timers 302 may be respectively configured with preset start-up durations, and the preset start-up durations configured in different timers 302 may be different. For example, the R timers 302 may be three timers 302, wherein the preset start-up duration configured in one timer 302 may be 1 second, the preset start-up duration configured in another timer 302 may be 2 seconds, and the preset start-up duration configured in another timer 302 may be 3 seconds. The R timers 302 may be electrically connected to the monitoring subcircuit 304 via R timeout signal transmission lines 40. The R timeout signal transmission lines 40 may correspond one to one to the R timers 302.

[0082] Optionally, the monitoring subcircuit 304 can determine the receiving state of the timeout signal. If the level signals from the R timeout signal transmission lines 40 are all high-level signals, and the duration of each high-level signal reaches the preset duration, this indicates that the monitoring subcircuit 304 has obtained the timeout signal from each timer 302, and the duration of the timeout signal corresponding to each timer 302 reaches the preset duration, then the startup abnormality monitoring result of the chip can be that there is a startup abnormality. Here, the preset duration can be 5 milliseconds, 8 milliseconds, 10 milliseconds, etc., which are not listed here one by one.

[0083] It should be noted that a high-level signal may be generated on the timeout signal transmission line 40 due to electromagnetic interference and other reasons, and the timer 302 may not send a timeout signal to the monitoring circuit 30 by pulling up the high-level signal. In addition, the high-level signal generated due to electromagnetic interference and other reasons often appears instantaneously and will not last for a period of time. In view of this, in the embodiment of the present disclosure, the monitoring circuit 30 may include at least two timers 302 corresponding to different preset startup durations. When the monitoring subcircuit 304 obtains a timeout signal from each timer 302, and the duration of the timeout signal corresponding to each timer 302 reaches the preset duration, the monitoring subcircuit 304 determines that the startup abnormality monitoring result of the chip is that there is a startup abnormality. This is equivalent to introducing a redundant voting strategy and a duration verification mechanism (i.e., verifying whether the preset duration is reached) to determine the startup abnormality monitoring result of the chip, which can avoid the adverse effects of the instantaneous high-level signal due to electromagnetic interference and other factors on the determination of the startup abnormality monitoring result, thereby facilitating the accuracy and reliability of the startup abnormality monitoring result.

[0084] In some optional examples, such as Figure 4 As shown, the monitoring circuit 30 may include, in addition to the timer 302 and the monitoring subcircuit 304, a configuration subcircuit 306;

[0085] The configuration subcircuit 306 is used to configure the abnormality reporting configuration information in the monitoring subcircuit 304;

[0086] The monitoring subcircuit 304 is used to generate a startup abnormality prompt in response to the startup abnormality monitoring result of the chip being a startup abnormality and the abnormality reporting configuration information indicating to report the abnormality; or, the monitoring subcircuit 304 is used to record the startup abnormality information of the chip in response to the startup abnormality monitoring result of the chip being a startup abnormality and the abnormality reporting configuration information indicating to avoid reporting the abnormality.

[0087] Optionally, the abnormality reporting configuration information may be used to indicate whether to perform abnormality reporting. For example, the abnormality reporting configuration information may be 1, which is used to indicate to perform abnormality reporting. Alternatively, the abnormality reporting configuration information may be 0, which is used to indicate to avoid performing abnormality reporting.

[0088] Optionally, the configuration subcircuit 306 may be a circuit capable of configuring other components in the chip. For example, the configuration subcircuit 306 may configure a preset startup duration in the timer 302. The configuration subcircuit 306 may be electrically connected to the monitoring subcircuit 304. Through the electrical connection between the configuration subcircuit 306 and the monitoring subcircuit 304, the configuration subcircuit 306 may configure the abnormality reporting configuration information in the monitoring subcircuit 304.

[0089] If the startup abnormality monitoring result of the chip is that there is a startup abnormality, and the abnormality reporting configuration information is used to indicate abnormality reporting, the monitoring subcircuit 304 can generate a startup abnormality prompt. The monitoring subcircuit 304 can also output a startup abnormality prompt. For example, if the chip is an intelligent driving chip used in the field of intelligent driving, the vehicle system may include Figure 1 In the system microcontroller (System Micro Controller Unit) 50 shown, the monitoring subcircuit 304 can report the startup abnormality prompt to the system microcontroller 50, and the system microcontroller 50 can take some processing measures for the chip, including but not limited to controlling chip reset or power-off restart.

[0090] If the startup abnormality monitoring result of the chip is that there is a startup abnormality, and the abnormality reporting configuration information is used to indicate to avoid abnormality reporting, the monitoring subcircuit 304 may not generate a startup abnormality prompt, and the monitoring subcircuit 304 may also record the startup abnormality information of the chip. For example, the monitoring subcircuit 304 may use a log form to record the startup abnormality information of the chip, and the startup abnormality information may at least include the time information of the startup abnormality being detected.

[0091] In an embodiment of the present disclosure, the configuration subcircuit 306 can configure the abnormality reporting configuration information in the monitoring subcircuit 304. In this way, when there is a startup abnormality in the chip, the monitoring subcircuit 304 can decide whether to generate and output a startup abnormality prompt or only record the startup abnormality information based on the abnormality reporting configuration information. By generating and outputting the startup abnormality prompt, the vehicle system can be notified of the startup abnormality of the chip in a timely manner, so that the vehicle system can perceive the abnormality and take corresponding processing measures, thereby reducing the risk of the vehicle system crashing and improving the stability and reliability of the vehicle system. By recording the startup abnormality information, the startup abnormality information can be consulted later when necessary.

[0092] In some optional examples, in response to the power management circuit 10 entering the running state, the power management circuit 10 is used to trigger the monitoring circuit 30 to generate the first random data according to a preset generation strategy;

[0093] In response to the processor 20 entering the running state, the processor 20 is used to trigger the monitoring circuit 30 to stop executing the timing operation, including:

[0094] In response to the processor 20 entering the running state, the processor 20 is used to generate second random data according to a preset generation strategy;

[0095] In response to the second random data being identical to the first random data, the monitoring circuit 30 stops performing the timing operation.

[0096] Optionally, the preset generation strategy may be a preset strategy for generating random data. The preset generation strategy may be in the form of a polynomial, for example. In one example, the polynomial may be: ax 4 +bx 3 +cx 2 +dx; where a, b, c, and d are pre-set coefficients. The monitoring circuit 10 and the processor 20 may be pre-configured with a preset generation strategy. In addition, the monitoring circuit 10 and the processor 20 may also be pre-configured with a preset value. The preset value may be set according to actual conditions, and the present disclosure does not limit this.

[0097] If the power management circuit 10 enters the running state, through the electrical connection between the power management circuit 10 and the monitoring circuit 30, the power management circuit 10 can send a trigger signal to the monitoring circuit 30 to trigger the monitoring circuit 30 to generate the first random data according to the preset generation strategy. For example, under the triggering of the power management circuit 10, the monitoring circuit 30 can bring the preset value as the value of x into ax 4 +bx 3 +cx 2 +dx is calculated, and the calculated result value can be used as the first random data.

[0098] Similarly, if the processor 20 enters the running state, the processor 20 can bring the preset value into ax as the value of x 4 +bx 3 +cx 2 +dx is calculated, and the calculated result value can be used as the second random data.

[0099] The monitoring circuit 30 can determine whether the second random data is the same as the first random data. If the second random data is the same as the first random data, the monitoring circuit 30 can stop executing the timing operation. If the second random data is not the same as the first random data, the monitoring circuit 30 can maintain the timing state.

[0100] In the embodiment of the present disclosure, the power management circuit 10 can trigger the monitoring circuit 30 to generate the first random data according to the preset generation strategy in response to itself entering the running state, and the processor 20 can generate the second random data according to the preset generation strategy in response to itself entering the running state. Since both the power management circuit 10 and the processor 20 generate data according to the preset generation strategy, if the chip starts normally, the processor 20 can work normally, and the first random data generated by the power management circuit 10 and the second random data generated by the processor 20 are theoretically the same. In view of this, it can be judged whether the processor 20 actually generates the second random data, and if the second random data is generated, whether the second random data is actually the same as the first random data, so as to determine whether the actual situation is consistent with the theoretical situation. If the actual situation is consistent with the theoretical situation, it can be determined that the processor 20 can work normally, then the monitoring circuit 30 can stop executing the timing operation to avoid the current timing duration reaching the preset startup duration. If the actual situation does not match the theoretical situation, it can be determined that the processor 20 cannot work normally, then the monitoring circuit 30 can maintain the timing state, and accordingly, the current timing duration can subsequently reach the preset startup duration. It is obvious that using the embodiments of the present disclosure, the numerical relationship between the current timing duration and the preset startup duration is closely related to whether the chip has a startup abnormality. Therefore, based on the numerical relationship between the current timing duration and the preset startup duration, the startup abnormality monitoring result of the chip can be effectively determined.

[0101] In some optional examples, such as Figure 5 As shown, the monitoring circuit 30 may include: a timer 302 and a linear feedback shift register (LFSR) 308;

[0102] In response to the power management circuit 10 entering the running state, the power management circuit 10 is used to trigger the monitoring circuit 30 to generate first random data according to a preset generation strategy, including:

[0103] In response to the power management circuit 10 entering the running state, the power management circuit 10 is used to trigger the linear feedback shift register 308 to generate first random data according to a preset generation strategy;

[0104] In response to the power management circuit 10 entering the running state, the power management circuit 10 is used to trigger the monitoring circuit 30 to perform a timing operation, including:

[0105] In response to the power management circuit 10 entering the running state, the power management circuit 10 is used to trigger the timer 302 to perform a timing operation;

[0106] In response to the second random data being the same as the first random data, the monitoring circuit 30 stops executing the timing operation, including:

[0107] In response to the second random data being the same as the first random data, the linear feedback shift register 308 is used to trigger the timer 302 to stop performing the timing operation.

[0108] Optionally, the linear feedback shift register 308 may be a special type of shift register. The linear feedback shift register 308 may have a pseudo-random number generation function, for example, the linear feedback shift register 308 may generate random data according to a preset generation strategy. A preset value may be pre-stored in the linear feedback shift register 308. The linear feedback shift register 308 may be electrically connected to the power management circuit 10. The linear feedback shift register 308 may also be electrically connected to the timer 302.

[0109] If the power management circuit 10 enters the running state, the power management circuit 10 can send a trigger signal to the linear feedback shift register 308 through the electrical connection between the power management circuit 10 and the linear feedback shift register 308 to trigger the linear feedback shift register 308 to generate the first random data according to the preset generation strategy. For example, the linear feedback shift register 308 can take the preset value as the value of x into ax 4 +bx 3 +cx 2 The linear feedback shift register 308 can store the first random data.

[0110] If the power management circuit 10 enters the running state, the power management circuit 10 can also trigger the timer 302 to perform a timing operation through the electrical connection between the power management circuit 10 and the timer 302 .

[0111] If the processor 20 enters the running state, the processor 20 can take the preset value as the value of x into ax 4 +bx 3 +cx 2 +dx is calculated to obtain the second random data.

[0112] The linear feedback shift register 308 can obtain the second random data generated by the processor 20, and determine whether the second random data generated by the processor 20 is the same as the first random data stored in the linear feedback shift register 308. If the second random data is the same as the first random data, the linear feedback shift register 308 can send a trigger signal to the timer 302 through the electrical connection between the linear feedback shift register 308 and the timer 302 to trigger the timer 302 to stop performing the timing operation. If the second random data is not the same as the first random data, the linear feedback shift register 308 does not send a trigger signal to the timer 302, and the timer 302 can maintain the timing state.

[0113] In the embodiment of the present disclosure, the pseudo-random number generation function of the linear feedback shift register 308 can be used to efficiently and reliably generate the first random data. When the first random data is the same as the second random data generated by the processor 20, the linear feedback shift register 308 can timely trigger the timer 302 to stop the timing operation. In this way, through the coordinated work of the timer 302, the linear feedback shift register 308 and the processor 20, the numerical relationship between the current timing duration and the preset startup duration can be closely associated with whether the chip has a startup abnormality. Therefore, according to the numerical relationship between the current timing duration and the preset startup duration, the startup abnormality monitoring result of the chip can be effectively determined.

[0114] In some optional examples, such as Figure 6 As shown, the monitoring circuit 30 may include a timer 302, a monitoring sub-circuit 304, a configuration sub-circuit 306 and a linear feedback shift register 308. The configuration sub-circuit 306 may configure the timer 302, the monitoring sub-circuit 304, the linear feedback shift register 308, etc. For example, the configuration sub-circuit 306 may configure a preset startup duration in the timer 302. For another example, the configuration sub-circuit 306 may configure the abnormality reporting configuration information in the monitoring sub-circuit 304. The timer 302 may perform a timing operation under the triggering of the power management circuit 10, and send a timeout signal to the monitoring sub-circuit 304 when the current timing duration of the timing operation reaches the preset startup duration. The linear feedback shift register 308 may trigger the timer 302 to stop the timing operation when the first random data is the same as the second random data. The monitoring sub-circuit 304 may determine the startup abnormality monitoring result of the chip based on the reception status of the timeout signal. For example, Figure 6 If the two timers 304 in the chip both send a timeout signal to the monitoring subcircuit 304, and the duration of the timeout signals corresponding to the two timers 304 respectively exceeds the preset duration, the chip startup abnormality monitoring result can be used to characterize the existence of startup abnormality in the chip.

[0115] Exemplary Methods

[0116] Figure 7 It is a flowchart of a chip startup abnormality monitoring method provided in some embodiments of the present disclosure. Figure 7 The methods shown may include:

[0117] Step 710, in response to the power management circuit in the chip entering the running state, performing a timing operation;

[0118] Step 720, in response to the processor in the chip entering the running state, stop executing the timing operation;

[0119] Step 730, determining a numerical relationship between a current timing duration of the timing operation and a preset start duration;

[0120] Step 740: Determine the startup abnormality monitoring result of the chip based on the numerical relationship.

[0121] In some optional examples, step 710 may include: in response to a power management circuit in the chip entering a running state, triggering a timer in the chip to perform a timing operation;

[0122] like Figure 8-1 As shown, step 740 may include:

[0123] Step 810, in response to the numerical relationship indicating that the current timing duration has reached the preset start duration, a timeout signal is sent to the monitoring sub-circuit in the chip via the timer;

[0124] Step 820: Determine the startup abnormality monitoring result of the chip based on the reception status of the timeout signal by the monitoring sub-circuit.

[0125] In some optional examples, the number of timers is at least two, and the preset start durations corresponding to the timers are the same;

[0126] Step 820 may include: in response to the receiving state characterization monitoring sub-circuit acquiring timeout signals from more than one timer, determining that a startup abnormality monitoring result of the chip is that a startup abnormality exists.

[0127] In some optional examples, the timer is connected to the monitoring subcircuit through at least two timeout signal transmission lines respectively;

[0128] Step 820 may include: in response to the receiving state characterization monitoring subcircuit acquiring a corresponding timeout signal through one or more timeout signal transmission lines, determining that a startup abnormality monitoring result of the chip is that a startup abnormality exists.

[0129] In some optional examples, the number of timers is at least two timers, and the preset start durations corresponding to the timers are different;

[0130] Step 820 may include: in response to the receiving state characterization monitoring subcircuit obtaining a timeout signal from each timer, and the duration of the timeout signal corresponding to each timer reaches a preset duration, determining that the startup abnormality monitoring result of the chip is that a startup abnormality exists.

[0131] In some optional examples, such as Figure 8-2 As shown, the method provided by the embodiment of the present disclosure may also include:

[0132] Step 830 , in response to the startup abnormality monitoring result of the chip indicating that there is a startup abnormality, and the abnormality reporting configuration information indicates to perform abnormality reporting, a startup abnormality prompt is generated.

[0133] In some optional examples, such as Figure 8-3 As shown, the method provided by the embodiment of the present disclosure may also include:

[0134] Step 840 , in response to the startup abnormality monitoring result of the chip indicating that there is a startup abnormality, and the abnormality reporting configuration information indicates to avoid abnormality reporting, the startup abnormality information of the chip is recorded.

[0135] In some optional examples, such as Fig. 9 As shown, the method provided by the embodiment of the present disclosure may also include:

[0136] Step 910, in response to the power management circuit entering the running state, triggering the monitoring circuit in the chip to generate first random data according to a preset generation strategy;

[0137] Step 920, in response to the processor entering the running state, generating second random data via the processor according to a preset generation strategy;

[0138] Step 930, in response to the second random data being the same as the first random data, stopping the timing operation;

[0139] The combination of step 920 and step 930 may be used as an optional implementation of step 720 of the present disclosure.

[0140] In some optional examples, step 910 may include: in response to the power management circuit entering the operating state, triggering the linear feedback shift register in the monitoring circuit to generate the first random data according to a preset generation strategy;

[0141] Step 710 may include: in response to the power management circuit entering the operating state, triggering a timer in the monitoring circuit to perform a timing operation;

[0142] Step 930 may include: in response to the second random data being the same as the first random data, triggering a timer to stop executing a timing operation via a linear feedback shift register.

[0143] In some optional examples, such as Fig.10 As shown, after the chip starts to start, if the power management circuit enters the running state, the timer can be triggered to perform the timing operation. The timer can determine whether the timing operation has timed out (that is, whether the current timing duration has reached the preset startup duration). Assuming that there are three timers in the chip, if the timing operation times out, it can be determined whether the monitoring subcircuit in the chip receives timeout signals from at least two timers. If the monitoring subcircuit receives timeout signals from at least two timers, it can be determined whether the startup abnormality of the chip needs to be reported based on the abnormality reporting configuration information. If the startup abnormality of the chip needs to be reported, a startup abnormality prompt can be generated and sent to the system microcontroller outside the chip. If the startup abnormality of the chip does not need to be reported, the startup abnormality prompt may not be generated and sent.

[0144] In summary, by adopting the embodiments of the present disclosure, it is possible to effectively monitor the startup abnormality of the chip. If the chip has a startup abnormality, it can be discovered and processed in time, thereby minimizing the potential impact of the startup abnormality on the entire vehicle system and ensuring the stability and reliability of the entire vehicle system.

[0145] In the method disclosed in the present invention, the various optional embodiments, optional implementation methods and optional examples disclosed above can be flexibly selected and combined as needed to achieve corresponding functions and effects, and the present invention does not list them one by one.

[0146] Exemplary Electronic Devices

[0147] Fig.11 The block diagram of an electronic device according to an embodiment of the present disclosure is illustrated. The electronic device 1100 includes one or more processors 1110 and a memory 1120 .

[0148] The processor 1110 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1100 to perform desired functions.

[0149] The memory 1120 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1110 may execute one or more computer program instructions to implement the methods of the various embodiments of the present disclosure described above and / or other desired functions.

[0150] In one example, the electronic device 1100 may further include: an input device 1130 and an output device 1140 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0151] The input device 1130 may also include, for example, a keyboard, a mouse, etc.

[0152] The output device 1140 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output device, etc.

[0153] Of course, to simplify, Fig.11 Only some of the components related to the present disclosure in the electronic device 1100 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application scenarios, the electronic device 1100 may also include any other appropriate components.

[0154] Exemplary computer program products and computer-readable storage media

[0155] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.

[0156] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0157] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0158] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0159] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present disclosure. The specific details disclosed above are only for the purpose of illustration and ease of understanding, not limitation. The above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0160] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A chip, comprising: Power management circuit, processor and monitoring circuit; wherein, In response to the power management circuit entering the running state, the power management circuit is used to trigger the monitoring circuit to perform a timing operation; In response to the processor entering the running state, the processor is used to trigger the monitoring circuit to stop executing the timing operation; The monitoring circuit is used to determine the numerical relationship between the current timing duration of the timing operation and the preset startup duration, and based on the numerical relationship, determine the startup abnormality monitoring result of the chip.

2. The chip according to claim 1, wherein: The monitoring circuit comprises: a timer and a monitoring subcircuit; In response to the power management circuit entering the running state, the power management circuit is used to trigger the monitoring circuit to perform a timing operation, including: In response to the power management circuit entering the running state, the power management circuit is used to trigger the timer to perform a timing operation; The monitoring circuit is used to determine the numerical relationship between the current timing duration of the timing operation and the preset startup duration, and based on the numerical relationship, determine the startup abnormality monitoring result of the chip, including: The timer is used to determine a numerical relationship between a current timing duration of the timing operation and a preset start-up duration, and in response to the numerical relationship indicating that the current timing duration reaches the preset start-up duration, send a timeout signal to the monitoring subcircuit; The monitoring subcircuit is used to determine a reception status of the timeout signal, and based on the reception status, determine a startup abnormality monitoring result of the chip.

3. The chip according to claim 2, wherein: The monitoring circuit comprises: at least two timers, each of which corresponds to the same preset start time; The monitoring subcircuit is used to determine the startup abnormality monitoring result of the chip based on the receiving state, including: In response to the reception status indicating that the monitoring sub-circuit obtains the timeout signal from more than one of the timers, the monitoring sub-circuit is configured to determine that a startup abnormality monitoring result of the chip is that a startup abnormality exists.

4. The chip according to claim 2, wherein: The timer is connected to the monitoring subcircuit via at least two timeout signal transmission lines respectively; The monitoring subcircuit is used to determine the startup abnormality monitoring result of the chip based on the receiving state, including: In response to the reception status representation, the monitoring subcircuit obtains the corresponding timeout signal through more than one timeout signal transmission line, and the monitoring subcircuit is used to determine that the startup abnormality monitoring result of the chip is that there is a startup abnormality.

5. The chip according to claim 2, wherein: The monitoring circuit comprises: at least two timers, each of which corresponds to a different preset start time; The monitoring subcircuit is used to determine the startup abnormality monitoring result of the chip based on the receiving state, including: In response to the receiving status characterizing that the monitoring subcircuit obtains the timeout signal from each of the timers, and the duration of the timeout signal corresponding to each of the timers reaches a preset duration, the monitoring subcircuit is used to determine that the startup abnormality monitoring result of the chip is that there is a startup abnormality.

6. The chip according to claim 2, wherein: The monitoring circuit further includes: a configuration subcircuit; The configuration subcircuit is used to configure the abnormality reporting configuration information in the monitoring subcircuit; The monitoring sub-circuit is used to generate a startup abnormality prompt in response to the startup abnormality monitoring result of the chip being the presence of a startup abnormality and the abnormality reporting configuration information indicating to report an abnormality; or, the monitoring sub-circuit is used to record the startup abnormality information of the chip in response to the startup abnormality monitoring result of the chip being the presence of a startup abnormality and the abnormality reporting configuration information indicating to avoid reporting an abnormality.

7. The chip according to claim 1, wherein: In response to the power management circuit entering the running state, the power management circuit is used to trigger the monitoring circuit to generate first random data according to a preset generation strategy; In response to the processor entering the running state, the processor is used to trigger the monitoring circuit to stop executing the timing operation, including: In response to the processor entering the running state, the processor is used to generate second random data according to the preset generation strategy; In response to the second random data being identical to the first random data, the monitoring circuit stops performing a timing operation.

8. The chip according to claim 7, wherein: The monitoring circuit includes: a timer and a linear feedback shift register; In response to the power management circuit entering the running state, the power management circuit is used to trigger the monitoring circuit to generate first random data according to a preset generation strategy, including: In response to the power management circuit entering the running state, the power management circuit is used to trigger the linear feedback shift register to generate first random data according to a preset generation strategy; In response to the power management circuit entering the running state, the power management circuit is used to trigger the monitoring circuit to perform a timing operation, including: In response to the power management circuit entering the running state, the power management circuit is used to trigger the timer to perform a timing operation; In response to the second random data being the same as the first random data, the monitoring circuit stops executing a timing operation, including: In response to the second random data being the same as the first random data, the linear feedback shift register is used to trigger the timer to stop performing a timing operation.

9. A method for abnormal monitoring of chip startup, comprising: In response to a power management circuit in the chip entering an operating state, performing a timing operation; In response to the processor in the chip entering a running state, stopping the execution of the timing operation; Determine a numerical relationship between a current timing duration of the timing operation and a preset start duration; Based on the numerical relationship, a startup abnormality monitoring result of the chip is determined.

10. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the chip startup abnormality monitoring method according to claim 9.

11. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the chip startup abnormality monitoring method described in claim 9 above.

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