Processing unit configured to perform parallel processing

Abstract

A processing unit configured to perform parallel processing, the processing unit comprising a parallel processing engine, the parallel processing engine comprising: a plurality of processing instances configured to process instructions in parallel; a test instruction insertion logic configured to: identify an idle period of the parallel processing engine; and inserting a test instruction to be processed by each of the plurality of processing instances during the idle period to generate a corresponding plurality of test outputs; and verification logic configured to: compare: test outputs generated by a first processing instance of the plurality of processing instances during the idle period; and a test output generated by a second processing instance of the plurality of processing instances during the idle period; and if the compared test outputs do not match, a fault signal is emitted.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to UK patent application 2315321.6 filed on October 6, 2023, which is incorporated herein by reference in its entirety. This application also claims priority to UK patent application 2315322.4 filed on October 6, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a processing unit configured to perform parallel processing, and a method of processing instructions at a processing unit configured to perform parallel processing. Background Art

[0004] In a safety critical system, at least some of the components of the system must meet safety objectives sufficient to enable the system as a whole to meet the safety level considered necessary for the system. For example, in most jurisdictions, seat belt retractors in vehicles must meet certain safety standards in order for vehicles equipped with such devices to pass safety tests. Similarly, vehicle tires must meet certain standards in order for vehicles equipped with such tires to pass safety tests appropriate for a particular jurisdiction. Safety critical systems are typically those systems whose failure would result in a significant increase in risk to the safety of personnel or the environment.

[0005] A processing system (e.g., a data processing system) often forms an integral part of a safety-critical system, either as dedicated hardware or as a processor for running safety-critical software. For example, fly-by-wire systems for aircraft, driver assistance systems, railway signaling systems, and control systems for medical devices are typically safety-critical systems that run on processing systems. Where a processing system forms an integral part of a safety-critical system, the processing system itself must meet safety objectives so that the system as a whole can meet an appropriate safety level. In the automotive industry, the safety level is typically the Automotive Safety Integrity Level (ASIL) defined in the functional safety standard ISO 26262.

[0006] Increasingly, processing systems for safety-critical systems include processors that run software. Both hardware and software elements must meet specific safety goals.

[0007] Software failures are usually systematic failures caused by programming errors or improper error handling. For software, safety goals are usually achieved through rigorous development practices, code reviews, and testing protocols.

[0008] For hardware elements of a processing system, such as a processing unit, a safety goal may be expressed as a set of metrics, such as the maximum number of failures in a given time period (often expressed as Failures in Time, or FIT), and the effectiveness of mechanisms for detecting single point failures (e.g., Single Point Fault Metric, or SPFM) and latent failures (e.g., Latent Fault Metric, or LFM). Hardware elements of a processing system may experience permanent faults. These hardware elements may not be able to recover from permanent faults (e.g., return to normal operation after occurrence). Hardware elements of a processing system may also experience transient faults. For example, transient faults may be introduced into the hardware by transient events (e.g., due to ionizing radiation, voltage spikes, or electromagnetic pulses). In a binary system, these types of transient events may cause random bit flips in memory and along the data paths of the processor. Hardware elements of a processing system may recover from transient faults (e.g., return to normal operation after occurrence). For example, this may be achieved by returning these hardware elements to a known state, such as by performing a "reset" on these hardware elements. Generally speaking, transient or permanent faults in memory or data paths that move data without transforming it can be prevented and / or corrected by error correction code (ECC) and / or parity bit error detection mechanisms. In contrast, error correction code (ECC) and parity bit error detection mechanisms are generally not useful for preventing and / or correcting transient or permanent faults in processing logic that do transform data.

[0009] Driver assistance systems and autonomous vehicle systems are examples of safety critical systems that may incorporate processing systems suitable for such safety critical applications.

[0010] In the example, driver assistance systems often provide computer-generated graphics that show hazards, lane positions and other information to the driver. Typically, this will lead vehicle manufacturers to replace conventional instrument clusters with computer-generated instrument clusters, which also means that the display of safety-critical information such as speed and vehicle fault information becomes computer-generated. Such processing requirements can be met by a processing unit that can perform parallel processing. For example, a graphics processing unit (GPU) is typically capable of performing parallel processing. A central processing unit (CPU) of the appropriate type may also be capable of performing parallel processing. Driver assistance systems typically require a processing unit that meets ASIL level B of ISO 26262.

[0011] In another example, autonomous vehicle systems typically process extremely large amounts of data (e.g., from radar, lidar, map data, and vehicle information) in real time to make hundreds of safety-critical decisions per second. Processing units (e.g., GPUs and / or CPUs) capable of performing parallel processing can also help meet such processing requirements. Autonomous vehicle systems typically require processing units that meet the most stringent ASIL level D of ISO26262.

[0012] It should be understood that driver assistance systems and autonomous vehicle systems are merely examples of safety-critical systems that use processing units capable of performing parallel processing that need to meet ASIL B or ASIL D standards of ISO 26262. It should be understood that many other safety-critical vehicle systems may use processing units capable of performing parallel processing that need to meet ASIL B or ASIL D standards of ISO 26262.

[0013] In order to be certified as meeting ASIL B or ASIL D standards of ISO 26262, it may be necessary to demonstrate that a series of different faults that may occur at a processing unit can be detected within a predetermined time period of the occurrence of these faults. As such, it is desirable to provide a method of testing a processing unit configured to perform parallel processing in order to detect faults at the processing unit.

[0014] It will also be appreciated that, in addition to the automotive applications described thus far, processing units capable of performing parallel processing may be used in other applications. For example, processing units capable of performing parallel processing may be used in supercomputing / data center applications. In such other applications, it is also desirable to provide a method of testing a processing unit configured to perform parallel processing in order to detect faults at the processing unit, e.g., so that appropriate actions may be taken in a timely manner to recover from such faults, and / or so that faulty or defective parts may be identified and replaced, regardless of whether such other applications are subject to safety standards. Summary of the invention

[0015] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0016] According to a first aspect of the present invention, there is provided a processing unit configured to perform parallel processing, the processing unit comprising a parallel processing engine, the parallel processing engine comprising: a plurality of processing instances, the plurality of processing instances being configured to process instructions in parallel; a test instruction insertion logic, the test instruction insertion logic being configured to: identify an idle cycle of the parallel processing engine; and insert a test instruction to be processed by each of the plurality of processing instances during the idle cycle so as to generate a corresponding plurality of test outputs; and a verification logic, the verification logic being configured to: compare: a test output generated by a first processing instance of the plurality of processing instances during the idle cycle; and a test output generated by a second processing instance of the plurality of processing instances during the idle cycle; and if the compared test outputs do not match, issue a fault signal.

[0017] An idle cycle may be a cycle of the parallel processing engine during which the parallel processing engine is not scheduled to process any other instructions.

[0018] One or more operand values ​​may be processed according to the test instruction, and the test instruction insertion logic may be configured to pseudo-randomly generate the one or more operand values. The test instruction insertion logic may be configured to pseudo-randomly generate the one or more operand values ​​according to one or more predetermined seeds. The test instruction insertion logic may be configured to pseudo-randomly generate the one or more operand values ​​using one or more linear feedback shift registers, the one or more linear feedback shift registers generating the one or more operand values ​​according to the one or more predetermined seeds.

[0019] The test instruction may include one or more control fields, and the test instruction insertion logic may be configured to generate the one or more control fields using constrained random generator logic.

[0020] For a test instruction control information-operand data combination, the operand data is processed according to the test instruction, and the test instruction includes control information, which defines (one or more) operations to be performed on the operand data by the multiple processing instances, and the test instruction insertion logic can be configured to insert multiple different test instruction control information-operand data combinations for processing by each of the multiple processing instances.

[0021] The plurality of different test instruction control information-operand data combinations may be configured to cumulatively cover at least a predetermined percentage of the logic included in the parallel processing engine.

[0022] The plurality of different test instruction control information-operand data combinations may include one or more test instruction control information-operand data combinations generated by the test instruction insertion logic and one or more pre-generated test instruction control information-operand data combinations stored by the test instruction insertion logic.

[0023] The test instruction insertion logic may be configured to insert each of the plurality of different test instruction control information-operand data combinations within a predetermined time period to be processed by each of the plurality of processing instances.

[0024] The test instruction insertion logic may be configured to: identify that less than a threshold amount of time remains for the predetermined time period and / or that more than a threshold number of test instruction control information-operand data combinations among the plurality of different test instruction control information-operand data combinations remain to be processed within the predetermined time period; and in response to the identification, cause one or more idle cycles of the parallel processing engine.

[0025] The test instruction insertion logic may be configured to cause one or more idle cycles of the parallel processing engine by causing a scheduler configured to schedule other instructions for processing by the parallel processing engine to not schedule other instructions for processing by the parallel processing engine during one or more cycles of the parallel processing engine.

[0026] The processing unit may include a scheduler configured to schedule other instructions to be processed by the parallel processing engine, wherein the test instruction insertion logic may be configured to identify the idle cycle and insert the test instruction for processing independently of the scheduler.

[0027] The test instruction insertion logic may be configured to identify that one or more other instructions have been processed by the parallel processing engine before identifying the idle cycle and inserting the test instruction for processing.

[0028] The plurality of test outputs may not be written to a memory external to the parallel processing engine.

[0029] The test instruction insertion logic may be implemented using fixed-function hardware. The verification logic may be implemented using fixed-function hardware.

[0030] The parallel processing engine may be an integer pipeline, a floating point pipeline or a complex pipeline.

[0031] Each process instance of the plurality of process instances may be identical to each other process instance of the plurality of process instances.

[0032] The processing unit may be a graphics processing unit (GPU) or a central processing unit (CPU).

[0033] According to a second aspect of the present invention, there is provided a method for processing instructions at a processing unit configured to perform parallel processing, the processing unit comprising a parallel processing engine, the parallel processing engine comprising a plurality of processing instances configured to process instructions in parallel, the method comprising: identifying an idle cycle of the parallel processing engine; inserting a test instruction to be processed by each of the plurality of processing instances during the idle cycle so as to generate a corresponding plurality of test outputs; comparing: a test output generated by a first processing instance of the plurality of processing instances during the idle cycle; and a test output generated by a second processing instance of the plurality of processing instances during the idle cycle; and issuing a fault signal if the compared test outputs do not match.

[0034] According to a third aspect of the present invention, there is provided a method for processing instructions at a processing unit configured to perform parallel processing, the processing unit comprising a parallel processing engine, the parallel processing engine comprising a first processing instance and a second processing instance, the method comprising: during a task cycle: processing a first set of one or more task operand values ​​at the first processing instance according to the task instruction to generate a first task output; and in parallel processing a second set of one or more task operand values ​​at the second processing instance according to the task instruction to generate a second task output; wherein the first set of the one or more task operand values ​​is different from the second set of the one or more task operand values; and during a test cycle: processing a first set of one or more test operand values ​​at the first processing instance according to a test instruction to generate a first test output; and in parallel processing a second set of one or more test operand values ​​at the second processing instance according to the test instruction to generate a second test output; wherein the first set of the one or more test operand values ​​is the same as the second set of the one or more test operand values; comparing the first test output and the second test output; and issuing a fault signal if the compared test outputs do not match.

[0035] The test cycle may occur during an idle cycle of the parallel processing engine, wherein an idle cycle is a cycle of the parallel processing engine during which the parallel processing engine is not scheduled to process any task instructions.

[0036] The method may also include identifying an idle cycle of the parallel processing engine; and inserting the instructions for processing by the first processing instance and the second processing instance during the idle cycle.

[0037] The method may include processing instructions at the parallel processing engine during a plurality of cycles of the parallel processing engine, the plurality of cycles including one or more task cycles and one or more test cycles, wherein x% of the plurality of cycles are task cycles and (100-x)% of the plurality of cycles are test cycles. For example, wherein x>50.

[0038] The task instruction may define a portion of work to be performed by the first processing instance and the second processing instance. The work may include one or more of image processing, video processing, graphics processing, and / or general processing. The work may be safety-critical work.

[0039] The first processing instance may be the same as the second processing instance.

[0040] The first test output and the second test output may not be written to a memory external to the parallel processing engine.

[0041] The method may include: using a scheduler to schedule the task instructions to be processed by the first processing instance and the second processing instance; and using test instruction insertion logic to insert the test instructions to be processed by the first processing instance and the second processing instance; wherein the test instruction insertion logic functions independently of the scheduler.

[0042] The method may also include pseudo-randomly generating the one or more test operand values ​​using test instruction insertion logic.

[0043] The test instruction insertion logic may be implemented in fixed function hardware.

[0044] The test instruction may include one or more control fields defining the operation(s) to be performed by the processing instance on its corresponding set of operand values, the one or more control fields being pre-generated.

[0045] The method may include comparing the first test output and the second test output using verification logic implemented in fixed function hardware.

[0046] The processing unit may be a graphics processing unit (GPU) or a central processing unit (CPU).

[0047] The parallel processing engine may be an integer pipeline, a floating point pipeline or a complex pipeline.

[0048] According to a fourth aspect of the present invention, there is provided a processing unit configured to perform parallel processing, the processing unit comprising a parallel processing engine, the parallel processing engine comprising a first processing instance and a second processing instance, the parallel processing engine being configured to: during a task cycle: process a first set of one or more task operand values ​​at the first processing instance according to a task instruction to generate a first task output; and in parallel process a second set of one or more task operand values ​​at the second processing instance according to the task instruction to generate a second task output; wherein the first set of the one or more task operand values ​​is different from the second set of the one or more task operand values; and during a test cycle: process a first set of one or more test operand values ​​at the first processing instance according to a test instruction to generate a first test output; and in parallel process a second set of one or more test operand values ​​at the second processing instance according to the test instruction to generate a second test output; wherein the first set of the one or more test operand values ​​is the same as the second set of the one or more test operand values; compare the first test output and the second test output; and if the compared test outputs do not match, issue a fault signal.

[0049] The processing unit may be included in hardware on an integrated circuit. A method of manufacturing a processing unit at an integrated circuit manufacturing system may be provided. An integrated circuit definition data set may be provided, the integrated circuit definition data set, when processed in the integrated circuit manufacturing system, configures the system to manufacture the processing unit. A non-transitory computer-readable storage medium may be provided, the non-transitory computer-readable storage medium having stored thereon a computer-readable description of the processing unit, the computer-readable description, when processed in the integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit including the processing unit.

[0050] An integrated circuit manufacturing system can be provided, comprising: a non-transitory computer-readable storage medium having stored thereon a computer-readable description of a processing unit; a layout processing system configured to process the computer-readable description so as to generate a circuit layout description of an integrated circuit containing the processing unit; and an integrated circuit generation system configured to manufacture the processing unit according to the circuit layout description.

[0051] Computer program code for performing any of the methods described herein may be provided.A non-transitory computer readable storage medium may be provided having computer readable instructions stored thereon which, when executed in a computer system, cause the computer system to perform any of the methods described herein.

[0052] As will be apparent to the skilled person, the above features may be combined as appropriate and may be combined with any aspect of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Examples will now be described in detail with reference to the accompanying drawings, in which:

[0054] Figure 1 An exemplary processing system is shown.

[0055] Figure 2 Exemplary processing units configured to perform parallel processing are shown.

[0056] Figure 3 An exemplary parallel processing engine including multiple processing instances is shown.

[0057] Figure 4 An exemplary parallel processing engine according to the principles described herein is shown.

[0058] Figure 5 A method of processing instructions at a processing unit configured to perform parallel processing according to principles described herein is shown.

[0059] Figure 6 A computer system is shown in which a processing unit configured to perform parallel processing may be implemented; and

[0060] Figure 7 An integrated circuit manufacturing system for producing an integrated circuit including a graphics processing system is shown.

[0061] The accompanying drawings show various examples. The skilled person will appreciate that the element boundaries (e.g., boxes, groups of boxes, or other shapes) shown in the accompanying drawings represent an example of boundaries. In some examples, it may be the case that an element can be designed as multiple elements, or multiple elements can be designed as one element. Where appropriate, common reference numerals are used throughout the accompanying drawings to indicate similar features. DETAILED DESCRIPTION

[0062] The following description is presented by way of example to enable those skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein, and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0063] Embodiments will now be described by way of example only.

[0064] Figure 1An exemplary processing system 100 is shown. The processing system 100 includes hardware in a hardware environment 104 and software in a software environment 102. Within the hardware environment 104, the processing system 100 includes a central processing unit (CPU) 116-1 and a graphics processing unit (GPU) 116-2. The GPU is generally capable of performing parallel processing. The graphics processing unit (GPU) 116-2 is described herein as an example of a processing unit configured to perform parallel processing. A CPU (e.g., a CPU of a suitable type) may also be capable of performing parallel processing. Therefore, the central processing unit (CPU) 116-1 is also described herein as an example of a processing unit configured to perform parallel processing. It should be understood that the principles described herein may also be applied to any other suitable type of processing unit configured to perform parallel processing—for example, a digital signal processing unit (e.g., DSP) capable of performing parallel processing. It should also be understood that the principles described herein do not need to be applied to a processing unit configured to perform parallel processing exclusively. That is, a processing unit configured to perform parallel processing may include some processing logic configured to perform parallel processing, and some other processing logic that is not configured to perform parallel processing. It should also be understood that the processing system does not need to include both a CPU and a GPU.

[0065] CPU 116-1 and GPU 116-2 may have any suitable architecture. CPU 116-1 and / or GPU 116-2 may be operable to perform any kind of graphics, image or video processing, general processing and / or any other type of data processing, such as processing of general computing tasks, particularly those that can be easily parallelized. Examples of general computing tasks include signal processing, audio processing, computer vision, physical simulations, statistical computing, neural networks, and encryption.

[0066] Within the hardware environment 104, the processing system 100 also includes a memory 112 and one or more data buses and / or interconnects 114, through which the CPU 116-1 and the GPU 116-2 and the memory 112 can communicate. The CPU 116-1 and / or the GPU 116-2 can be implemented on a chip (e.g., a semiconductor chip and / or an integrated circuit package), and the memory 112 may not be physically located on the same chip (e.g., a semiconductor chip and / or an integrated circuit package) as the CPU 116-1 and / or the GPU 116-2. Therefore, the memory 112 may be referred to as "off-chip memory." The memory 112 may be used to store the CPU 116-1, the GPU 116-2, and / or other processing units ( Figure 1Therefore, the memory 112 may be referred to as “system memory” and / or “global memory”. The memory 112 may be a dynamic random access memory (eg, DRAM).

[0067] Multiple processes (P0, P1, P2) 106 may be executed within the software environment 102. An operating system 108 may provide an abstraction of available hardware to the processes 106. The operating system may include drivers 110 for the CPU 116-1 and / or GPU 116-2 to expose the functionality of the CPU 116-1 and / or GPU 116-2 to the processes. All or a portion of the software environment 102 may be provided as firmware.

[0068] In an example, the processing system 100 forms part of a vehicle control system, wherein the processes each perform one or more control functions of the vehicle, such as an instrument cluster display, an entertainment system, an engine management, a climate control, a lane control, a steering correction, an automatic braking system, etc. One or more of the processes 106 may be safety critical processes. The processes 106 may include a mix of safety critical processes that must be executed according to a predefined safety level and non-safety critical processes that do not need to be executed according to a predefined safety level.

[0069] Figure 2 An exemplary processing unit 116 configured to perform parallel processing is shown. Figure 1 The CPU 116-1 and / or GPU 116-2 shown in FIG. 1 may have the same Figure 2 The same attributes as the processing unit 116 shown in FIG.

[0070] The processing unit 116 includes a plurality of parallel processing engines 222, a scheduler 218, and a local memory 220. The processing unit 116 may also include a checking unit 224. Figure 2 The memory 112 shown in FIG. 1 may have Figure 1 The same properties as the memory 112 shown in FIG.

[0071] Each parallel processing engine 222 includes multiple processing instances (e.g., "pipelines") configured to process instructions in parallel (as will be described in further detail herein). In other words, each parallel processing engine 222 can be configured to perform single instruction multiple data (SIMD) processing. Each parallel processing engine can be an integer pipeline, a floating point pipeline, a complex (e.g., special function unit) pipeline, the same multiplier within a vector processing unit or other arithmetic logic unit, or any other suitable type of parallel processing engine. The multiple parallel processing engines 222 may include multiple parallel processing engines of different types and / or multiple parallel processing engines of the same type. A processing unit configured to perform parallel processing typically includes one or more parallel processing engines. In Figure 2, processing unit 116 is shown as including three parallel processing engines—labeled 222-1, 222-2, and 222-n. It should be understood that a processing unit configured according to the principles described herein may include any suitable number of parallel processing engines (eg, including a single parallel processing engine).

[0072] Scheduler 218 may be configured to schedule instructions (e.g., "tasks" or "non-test" instructions) for processing by parallel processing engine 222. Each instruction may define a portion of work to be performed by a processing instance of a parallel processing engine. For example, the work may include one or more of image processing, video processing, graphics processing, and / or general (e.g., "compute") processing. The work may be safety-critical work.

[0073] The operand data of the set of one or more operand values ​​can be processed by the processing instance of the parallel processing engine according to the instruction. Each operand value can include one or more bits, such as 32 bits. The instruction itself can include one or more operands, and the one or more operands include references to the memory location of (one or more) storage operand data to be processed. In the processing cycle of the parallel processing engine 222 that is processing the instruction, each processing instance of the parallel processing engine 222 can operate on different operand data (e.g., different sets of one or more operand values) according to the instruction. That is, as described herein, each parallel processing engine 222 can be configured to perform single instruction multiple data (SIMD) processing. The instruction can include control information, and the control information includes one or more control fields, and the one or more control fields define (one or more) operations to be performed by each of the processing instances on its corresponding operation data, such as addition, multiplication, fusion multiplication addition and / or any other suitable type of operation.

[0074] It should be understood that in examples where the processing unit 116 includes multiple parallel processing engines 222, the scheduler 218 can be configured to schedule instructions to any (e.g., all) of the multiple parallel processing engines 222. The parallel processing engine in the multiple parallel processing engines 222 to which the scheduler 218 schedules an instruction can depend on the type of processing required for the instruction, such as integer, floating point, complex, etc.

[0075] Local memory 220 may include one or more data storage units arranged in any suitable manner. Local memory 220 may include static random access memory (e.g., SRAM) and / or dynamic random access memory (e.g., DRAM). Local memory 220 may include one or more caches, registers, and / or buffers. Processing unit 116 may be implemented on a chip (e.g., a semiconductor chip and / or an integrated circuit package), and local memory 220 may not be physically located on the same chip (e.g., a semiconductor chip and / or an integrated circuit package) as processing unit 116. Therefore, local memory 220 may be referred to as "on-chip memory". Local memory 220 may be configured to receive data (e.g., operand data) from memory 112. Parallel processing engine 222 may access local memory 220 without consuming memory bandwidth to memory 112. For example, the parallel processing engine may read operand data (e.g., a set of one or more task or non-test operand values) stored in the memory 220 in order to process an instruction (e.g., a task or non-test instruction), and / or write output data (e.g., task or non-test output data) generated during the processing of the instruction to the local memory 220. Both the memory 112 and the local memory 220 may be described as being external to the parallel processing engine 222. Each parallel processing engine 222 may include one or more "private" memory units (not shown) that are dedicated to the parallel processing engine (e.g., not accessible to any other parallel processing engine of the processing unit).

[0076] Work to be performed by a processing unit configured to perform parallel processing may be arranged into so-called “work groups” and “work items.” A work group may include multiple work items that may be processed in parallel (eg, at a parallel processing engine of the processing unit).

[0077] Workgroups may be processed independently of one another (e.g., at different parallel processing engines of a processing unit, or serially at a single parallel processing engine of a processing unit). Work items within the same workgroup may be able to share access to dedicated memory (not shown) of the parallel processing engine of the processing unit dedicated to processing the work items during their processing. That is, work items within the same workgroup may be able to share access to the memory of the parallel processing engine of the processing unit dedicated to processing the work items during their processing. In contrast, different workgroups may not be able to share access to the memory of a parallel processing engine dedicated to a processing unit during their processing.

[0078] In an example, a program can define a series of one or more instructions to be executed. The program can be executed for a data item. For example, the program can be a shader program, and the data item to be executed for the shader program can be light or pixel data. In order to utilize the SIMD capability of a parallel processing engine, a workgroup can be formed by collecting a plurality of data items (for example, a plurality of different light / pixel data) to be executed for the same program (for example, a shader program). The workgroup includes a plurality of instances / calls of a program, and each instance / call corresponds to a corresponding data item in a plurality of data items to be executed for the program. Each of the instances / calls of a program is a work item. Therefore, each work item can define a series of one or more instructions to be executed for a data item. By processing a workgroup at a parallel processing engine as described herein, the same program can be effectively executed for a plurality of different data items.

[0079] The number of work items included in a work group may be limited. In an example, a work group may include up to 128 work items. In this example, if more than 128 work items will execute the same program, more than one work group will be associated with the program. It should be understood that the "work group" and "work item" terms used herein are not intended to be limiting, and other terms may be used to describe the same concept. For example, a work item as described herein may alternatively be referred to as a "call" or "thread", and a work group as described herein may alternatively be referred to as a "thread block" or "thread group".

[0080] Figure 3 An exemplary parallel processing engine 222 including a plurality of processing instances (PIs) 3 is shown. Figure 2 Each parallel processing engine 222 shown in FIG. 2 may have Figure 3 The same properties of the parallel processing engine 222 shown in FIG.

[0081] The parallel processing engine 222 includes a plurality of processing instances (PI) 3 configured to process instructions in parallel. In other words, as described herein, the parallel processing engine 222 can be configured to perform single instruction multiple data (SIMD) processing. That is, the parallel processing engine 222 includes a first processing instance (PI1) 3-1 configured to process a first set (I1) of one or more operand values ​​to generate a first output (O1), a second processing instance (PI2) 3-2 configured to process a second set (I2) of one or more operand values ​​to generate a second output (O2), a third processing instance (PI3) 3-3 configured to process a third set (I3) of one or more operand values ​​to generate a third output (O3), a fourth processing instance (PI4) 3-4 configured to process a fourth set (I4) of one or more operand values ​​to generate a fourth output (O4), and a fifth processing instance (PI5) 3-5 configured to process a fifth set (I5) of one or more operand values ​​to generate a fourth output (O4). The invention further comprises a first processing instance (PI5) 3-5 configured to process a sixth set (I6) of one or more operand values ​​to generate a sixth output (O5), a sixth processing instance (PI6) 3-6 configured to process a seventh set (I7) of one or more operand values ​​to generate a seventh output (O7), and an eighth processing instance (PI8) 3-8 configured to process an eighth set (I8) of one or more operand values ​​to generate an eighth output (O8), wherein the eight sets (I1 to I8) of one or more operand values ​​are processed in parallel (e.g., substantially simultaneously, e.g., during the same processing cycle) according to the same instruction. Each of the first set, the second set, the third set, the fourth set, the fifth set, the sixth set, the seventh set, and the eighth set of one or more operand values ​​may be different. During a processing cycle of the parallel processing engine, a number of sets of one or more operand values ​​equal to the number of processing instances of the parallel processing engine may be processed in parallel (e.g., substantially simultaneously) according to the same instruction.

[0082] Each of the processing instances may include processing logic for performing one or more operations (e.g., addition, multiplication, fused multiplication addition, or any other suitable type of operation) or a combination thereof on operand data according to the instruction being processed by the processing instance. The processing logic may include fixed-function processing logic, configurable processing logic, or any suitable combination of fixed-function and configurable processing logic. Each processing instance included in the parallel processing engine may be identical to each other. That is, each processing instance in a plurality of processing instances may be identical to each other processing instance in a plurality of processing instances. In other words, the parallel processing engine may include a plurality of identical processing instances.

[0083] A workgroup including more work items than the number of processing instances included in a parallel processing engine may be processed in multiple batches at the parallel processing engine. For example, a workgroup including 32 work items scheduled to be processed at a parallel processing engine including eight processing instances may be processed in four batches at the parallel processing engine, e.g., such that work items 1 to 8 are processed in parallel in the first batch, work items 9 to 16 are processed in parallel in the second batch, work items 17 to 24 are processed in parallel in the third batch, and work items 25 to 32 are processed in parallel in the fourth batch.

[0084] exist Figure 3 , parallel processing engine 222 is shown as including eight processing instances 3, labeled PI1 3-1 through PI8 3-8. It should be understood that a parallel processing engine configured according to the principles described herein may include any suitable number of processing instances (e.g., only two processing instances). Typically, a parallel processing engine includes a number of processing instances that is equal to a power of two (e.g., 2 1 =2,2 2 =4,2 3 =8, etc.) or a multiple of two, but it does not have to be so.

[0085] As described herein, it is desirable to provide a method of testing a processing unit configured to perform parallel processing in order to detect faults at the processing unit. A first typical method of testing a processing unit configured to perform parallel processing involves duplicating each "task work group" received for processing so as to form a task work group and a "redundant work group." The replicated task work group may be a work group that defines "task work" to be performed by the processing unit. The task work may include one or more of image processing, video processing, graphics processing, and / or general (e.g., "computing") processing. The task work may be safety critical work. The task work may be performed by a processor in a manner that is consistent with the processing unit's performance. Figure 1 Process 106 executing at processing system 100 is shown as submitting.

[0086] Return to reference Figure 2In this first typical approach, both the task workgroup and the redundant workgroup may be processed by the parallel processing engine 222 (e.g., each processed by a different parallel processing engine of the processing unit) to form a "task result" and a "redundant result". The task result and the redundant result may be compared (e.g., by the verification unit 224), and if the task result and the redundant result do not match, a fault signal may be issued. That is, the mismatched task result and the redundant result may indicate that a fault has occurred in at least one of the parallel processing engines 222 of the processing unit 116 used to process the task workgroup and the redundant workgroup. This first typical approach may provide excellent diagnostic coverage (e.g., in terms of the percentage of faults among all possible faults detectable by the safety mechanism). Nevertheless, while there may be some optimizations, using this first typical approach roughly means doubling the time spent and the processing power used to process each workgroup received for processing by the processing unit. Therefore, this may also mean that the throughput of the processing unit processing these workgroups is halved.

[0087] A second typical method for testing a processing unit is to provide pairs of identical processing units in a dual lockstep arrangement (not shown). As in the first typical method, each task workgroup to be processed is replicated to form a task workgroup and a redundant workgroup. In the dual lockstep arrangement, one processing unit in a pair of processing units processes the task workgroup to form a task result, while the other processing unit in the pair of processing units processes the redundant workgroup to form a redundant result. The task result and the redundant result can be compared, and if the task result and the redundant result do not match, a fault signal can be issued. That is, the mismatched task result and the redundant result can indicate that a fault has occurred in at least one processing unit in a pair of processing units in the dual lockstep arrangement. However, since a second processing unit is required, the dual lockstep processing system necessarily consumes twice the chip area. In addition, as in the first typical method, the time spent processing each workgroup and the processing power used are doubled.

[0088] Processing units configured to perform parallel processing and methods of processing instructions at a processing unit configured to perform parallel processing are described herein, which are directed to addressing one or more of the problems identified in the preceding paragraphs.

[0089] Hereinafter, it will be understood that a task (eg, non-test) instruction may define a portion of a task work (as defined herein) that is performed by a processing instance of a parallel processing engine. Figure 2 The scheduler 218 shown in can be configured to schedule task instructions for processing by the parallel processing engine.It should also be understood that a "test instruction" may not define a portion of a task work (as defined herein). Figure 2 The scheduler 218 shown in FIG. 2 may not be configured to schedule test instructions for processing by the parallel processing engines.

[0090] Figure 4 An exemplary parallel processing engine 422 is shown in accordance with the principles described herein. Figure 2 Each parallel processing engine 222 shown in FIG. 2 may have Figure 4 The same properties of the parallel processing engine 422 shown in FIG.

[0091] The parallel processing engine 422 may be an integer pipeline, a floating point pipeline, a complex (e.g., special function unit) pipeline, a vector processing unit or other arithmetic logic unit, or any other suitable type of parallel processing engine. The parallel processing engine 422 includes a plurality of processing instances 3 configured to process instructions in parallel, the processing instances 3 having the same structure as described herein. Figure 3 The parallel processing engine 422 may have the same attributes as described for processing example 3. That is, the parallel processing engine 422 may be configured to perform single instruction multiple data (SIMD) processing.

[0092] The parallel processing engine 422 can be used with the Figure 3 In the same manner that the parallel processing engine 222 shown in FIG. 1 processes multiple sets of one or more operand values ​​(e.g., I1 to I8) in parallel according to instructions to generate corresponding multiple outputs (e.g., O1 to O8), multiple sets of one or more task operand values ​​are processed in parallel according to task instructions to generate corresponding multiple task outputs.

[0093] exist Figure 4 In Figure 3 As in FIG, parallel processing engine 422 is shown to include eight processing instances 3, labeled PI13-1 through PI8 3-8. It should be understood that a parallel processing engine configured according to the principles described herein may include any suitable number of processing instances (eg, only two processing instances).

[0094] The parallel processing engine 422 also includes test instruction insertion logic 424 and verification logic 438. Figure 4 , the check logic 438 is shown as including four check logic instances 438-1, 438-2, 438-3, and 438-4. The test instruction insertion logic 424 and / or the check logic 438 may advantageously be implemented using fixed-function hardware (e.g., fixed-function or dedicated circuitry, e.g., as opposed to software running on general-purpose hardware).

[0095] The test instruction insertion logic 424 is configured to insert (e.g., inject or input) test instructions for processing by each of the plurality of processing instances 3 during a processing cycle to generate a corresponding plurality of test outputs. In an example, the test instruction insertion logic 424 may insert test instructions for processing during an idle cycle of the parallel processing engine 422 (as described in further detail in the following paragraphs); and / or the test instruction insertion logic 424 may periodically insert test instructions for processing (e.g., according to a predetermined test frequency).

[0096] In the example, a test instruction can be processed by each of multiple processing instances 3 by performing the following operations in parallel according to the test instruction during a processing cycle of the parallel processing engine 422: processing a first set of one or more test operand values ​​at a first processing instance PI1 to generate a first test output; processing a second set of one or more test operand values ​​at a second processing instance PI2 to generate a second test output; processing a third set of one or more test operand values ​​at a third processing instance PI3 to generate a third test output; processing a fourth set of one or more test operand values ​​at a fourth processing instance PI4 to generate a fourth test output; processing a fifth set of one or more test operand values ​​at a fifth processing instance PI5 to generate a fifth test output; processing a sixth set of one or more test operand values ​​at a sixth processing instance PI6 to generate a sixth test output; processing a seventh set of one or more test operand values ​​at a seventh processing instance PI7 to generate a seventh test output; and processing an eighth set of one or more test operand values ​​at an eighth processing instance PI8 to generate an eighth test output. Each of the first set, second set, third set, fourth set, fifth set, sixth set, seventh set, and eighth set of one or more test operand values ​​may be a replica (e.g., a copy) of the set of one or more test operand values ​​output by the test instruction insertion logic 424. That is, each of the first set, second set, third set, fourth set, fifth set, sixth set, seventh set, and eighth set of one or more test operand values ​​may be identical (e.g., identical to one another). Therefore, it should be understood that the processing performed in parallel by each processing instance during the test processing cycle should be identical (i.e., due to processing the same set of one or more test operand values ​​according to the same test instruction). Therefore, if each of the processing instances operates without failure, the test output generated by each of these processing instances is expected to match.

[0097] Test instruction insertion logic 424 may be implemented in hardware (eg, using fixed-function or dedicated circuitry) within parallel processing engine 422. The hardware may be physically located at the input of the plurality of processing instances 3.

[0098] The test instruction insertion logic 424 can be configured to generate operand data including a set of one or more operand values ​​to be processed according to the test instruction. Each operand value may include one or more bits, such as 32 bits. The test instruction insertion logic 424 can be configured to pseudo-randomly generate a set of one or more test operand values ​​to be processed according to the test instruction. The test instruction insertion logic 424 can be configured to pseudo-randomly generate one or more operand values ​​according to one or more predetermined seeds. As will be appreciated by a skilled person, a linear feedback shift register can be used to pseudo-randomly generate an output. A seed is a predetermined value (e.g., a number) that can be used to set (e.g., pre-inject or initialize) a linear feedback shift register to a specific level in its sequence. One or more predetermined seeds can be stored in a dedicated memory 426 at the parallel processing engine 422 (in Figure 4 The test instruction insertion logic 424 may be configured to generate a set of one or more test operand values ​​pseudo-randomly using one or more linear feedback shift registers (LFSRs) 428, which generate the one or more test operand values ​​according to one or more predetermined seeds. The set of one or more test operand values ​​to be processed according to the test instruction may be output "directly" by the test instruction insertion logic 424, for example, rather than inserting a test instruction including one or more operands by the test instruction insertion logic, the one or more operands including a reference to (one or more) memory locations in a memory external to the parallel processing engine 422, where the test operand data to be processed is stored.

[0099] Additionally or alternatively, the test instruction insertion logic 424 may be configured to generate control information including one or more control fields that define the operation(s) to be performed by the processing instance on its corresponding set of operand values ​​(e.g., addition, multiplication, fused multiplication addition, and / or any other suitable type of operation). The test instruction insertion logic 424 may be configured to generate the one or more control fields using a constrained random generator logic (CRGL) 430. The constrained random generator logic (CRGL) 430 itself may include one or more linear feedback shift registers that may be pre-filled with one or more predetermined seeds.

[0100] In examples where the test instruction insertion logic 424 is configured to generate only one of operand data or control information, the other of the operand data and control information may be fixed (e.g., pre-generated). In these examples, the pre-generated set of one or more operand values ​​or the pre-generated one or more control fields may be stored in a dedicated memory 432 at the parallel processing engine 422, such as in one or more registers dedicated to the parallel processing engine 422. It should be understood that the dedicated memories 426 and 432 need not be as Figure 4 Although shown as physically separated in , this is merely illustrative and is not intended to define a strict division between dedicated memories 426 and 432 .

[0101] The controller 440 of the test instruction insertion logic 424 can be configured to control the generation of a set of one or more operand values ​​to be processed according to the test instruction and / or one or more control fields included in the test instruction. That is, the controller 440 can be configured to control one or more linear feedback shift registers (LFSR) 428 and / or constrained random generator logic (CRGL) 430. It may be advantageous to configure the test instruction insertion logic 424 in this way because it can use less memory relative to storing pre-generated operand data and pre-generated control information. The controller 440 can be configured to (e.g., by controlling multiplexers 434 and 436) select a combination of (generated or pre-generated) operand data and (generated or pre-generated) control information of the test instruction to be inserted.

[0102] The test output generated by processing the test instructions does not need to be written to a memory external to the parallel processing engine 422, for example, Figure 2 420 or memory 112. This is advantageous because it prevents test outputs from disrupting the processing of task work, for example, by shifting (e.g., relocating) task outputs in memory external to parallel processing engine 422 (e.g., a cache external to parallel processing engine 442).

[0103] Each verification logic instance 438-1, 438-2, 438-3, and 438-4 is configured to compare the test output generated by the first processing instance in the plurality of processing instances 3 with the test output generated by the second processing instance in the plurality of processing instances 3. Figure 4In: the verification logic instance 438-1 can be configured to compare the test output generated by the first processing instance (PI1) 3-1 and the test output generated by the second processing instance (PI2) 3-2; the verification logic instance 438-2 can be configured to compare the test output generated by the third processing instance (PI3) 3-3 and the test output generated by the fourth processing instance (PI4) 3-4; the verification logic instance 438-3 can be configured to compare the test output generated by the fifth processing instance (PI5) 3-5 and the test output generated by the sixth processing instance (PI6) 3-6; the verification logic instance 438-4 can be configured to compare the test output generated by the seventh processing instance (PI7) 3-7 and the test output generated by the eighth processing instance (PI8) 3-8.

[0104] Each test output may include one or more bits, such as 32 bits. Each verification logic instance 438-1, 438-2, 438-3, and 438-4 may be configured to perform a bit-by-bit comparison of two test outputs. The comparison may be performed to determine whether the two test outputs match (e.g., are the same), for example, whether the corresponding bits in each bit position of the two test outputs match (e.g., are the same).

[0105] Each of the verification logic instances 438-1, 438-2, 438-3, and 438-4 can be implemented in hardware (e.g., using fixed-function or dedicated circuitry) within the parallel processing engine 422. Each of the verification logic instances 438-1, 438-2, 438-3, and 438-4 can be physically located at the output of the plurality of processing instances 3. This is advantageous because the test outputs are located elsewhere (e.g., at Figure 2 There is no need to traverse the memory hierarchy (eg, via local memory 220 and / or memory 112) before performing comparisons at a check unit 224 external to the parallel processing engine as shown.

[0106] Each verification logic instance 438-1, 438-2, 438-3, and 438-4 is configured to issue a fault signal if (e.g., in response to determining) the test outputs of its comparison do not match (e.g., are not the same or different from each other). For example, verification logic instance 438-1 can be configured to issue a fault signal if the test output generated by the first processing instance (PI1) 3-1 and the test output generated by the second processing instance (PI2) 3-2 do not match. The fault signal can be provided as an output of the parallel processing engine 222 in any suitable manner. For example, the fault signal can be one or more of the following: control data; an interrupt; data written to the local memory 220; and / or data written to the memory 112.

[0107] When the test outputs of a pair of processing instances do not match, thereby causing the verification logic instance to issue a fault signal as described herein, the fault signal indicates that a fault occurred at one of the processing instances of the pair, but the fault signal does not indicate which processing instance of the pair experienced the fault. That is, the verification logic 438 according to the principles described herein can advantageously indicate that a fault has occurred in at least one of the processing instances that generated the compared (mismatched) test outputs. This is advantageous over the first typical test method described herein, in which the verification unit (e.g., verification unit 224) may only be able to indicate that a fault has occurred in at least one of the parallel processing engines (e.g., "as a whole") for processing the task workgroup and the redundant workgroup. That is, the verification logic according to the principles described herein can more accurately (e.g., with higher resolution) indicate where in the processing unit a fault has occurred.

[0108] It should be understood that the test outputs do not have to be "paired" for comparison, e.g. Figure 4 As shown. In another example, a selected test output in the test output can be compared with each of the other test outputs generated in the same processing cycle. For example, the verification logic can compare the test output generated by the first processing instance and the test output generated by each of the second processing instance to the eighth processing instance, and if any of these comparisons identifies a mismatching test output, a fault signal is issued. In yet another example, the processing instances can be grouped into a set of three (or more) processing instances, and for each set, the verification logic can compare the three (or more) test outputs generated by the processing instances of the set in the same processing cycle with each other, and if any of these test outputs do not match, a fault signal is issued. In this example, the fault signal can indicate where the fault occurred in the processing instance. This is because it can be assumed that a fault has occurred at a processing instance that generates a test output that does not match the test outputs generated by two or more other processing instances in the set.

[0109] The fault signal may be used in any manner by the processing unit 116 into which the parallel processing engine 422 is incorporated and / or by the processing system 100 into which the processing unit 116 is incorporated. For example, upon the verification unit 438 issuing the fault signal, the processing system 100 may: discard task output data previously formed by the processing instance(s) associated with the fault signal; cause task work previously processed by the processing instance(s) associated with the fault signal to be resubmitted to the processing unit 116 for reprocessing; and / or forward the fault signal to an external safety processing system, which may invoke a fault handling mode that renders the system including the processing system 100 safe (e.g., by causing the autonomous vehicle including the processing system 100 to safely slow down and pull over, or by switching to a redundant processing system also included by the autonomous vehicle). Alternatively or in addition, the processing unit 116 itself may use the fault signal. For example, the processing unit 116 may record fault signals and the processing instances associated with those faults, and, for example, if one or more processing instances exceed a predefined number of faults (perhaps within some defined time period), those one or more processing instances may be disabled or otherwise prevented from processing future task instructions.

[0110] Testing the processing unit according to the principles described herein is also advantageous because it enables a greater percentage of the processing power and time of the parallel processing engine to be used to perform the task work relative to the first typical test method described herein. This is because according to the principles described herein, only one processing cycle is used to process the test instruction at each of the multiple processing instances in order to generate a test output for self-comparison. In contrast, in the first typical test method described herein, both the task work group and the redundant work group must be processed as a whole in order to generate the task results and the redundant results for comparison, which may use more processing cycles.

[0111] Furthermore, the inventors have observed that, in practice, task instructions are not typically scheduled for processing during every processing cycle of a parallel processing engine. This is particularly true in an exemplary processing unit that includes multiple parallel processing engines to which a scheduler can schedule task instructions, for example, where the parallel processing engine to which an instruction is scheduled depends on the type of processing required by the instruction (e.g., integer, floating point, complex, etc.), parallel processing engines that are configured to perform other types of processing may be temporarily idle. Parallel processing engines that are not (e.g., Figure 2 The processing cycle of the parallel processing engine that is scheduled by the scheduler 218 shown in FIG. 2 to process any other (e.g., task or non-test) instructions can be referred to as an "idle cycle". The inventors have observed that the parallel processing engine typically experiences a plurality of idle cycles. This can be utilized in the preferred example.

[0112] Preferably, test instruction insertion logic 424 may be configured to identify idle cycles (as defined herein) of parallel processing engine 422. Controller 440 of test instruction insertion logic 424 may be configured to identify idle cycles (e.g., upcoming or future idle cycles) of parallel processing engine 422. For example, controller 440 may monitor an incoming task work group queue (e.g., buffer) (not shown) of parallel processing engine 442 and identify when a "gap" in the incoming queue will cause the parallel processing engine to experience one or more idle cycles.

[0113] The test instruction insertion logic 424 can be configured to insert test instructions for processing only during the identified idle cycles. Configuring the test instruction insertion logic 424 in this manner is advantageous because it can prevent the processing of test instructions from interrupting (e.g., delaying) the processing of task instructions, such as by preventing the processing of test instructions from consuming processing cycles of the parallel processing engine that would otherwise be used to process task instructions.

[0114] As described herein, the processing unit 116 may include a scheduler 218 configured to schedule other (e.g., task or non-test) instructions to be processed by the parallel processing engine 442. The test instruction insertion logic 424 may function independently of the scheduler 218. That is, the test instruction insertion logic 424 may be configured to insert test instructions for processing independently of the scheduler 218 (e.g., without the scheduler "agreeing" or "knowing"). In other words, the scheduler 218 does not need to "know" that the test instruction insertion logic 424 exists, and / or that the test instruction insertion logic 424 is inserting test instructions for processing by the parallel processing engine. In other words, in a preferred example, the test instruction insertion logic 424 is not under the control of the scheduler 218.

[0115] The test instruction insertion logic 424 can be configured to identify that one or more other (e.g., task or non-test) instructions have been processed by the parallel processing engine 422 (e.g., within a predetermined time period before the current time) before inserting the test instruction for processing. For example, the controller 440 may include a task countdown timer (not shown in the figure). The task countdown timer may be set to expire after a predetermined time period (e.g., 100ms or any other suitable time period). Each time the parallel processing engine 422 processes a task instruction, the task countdown timer may be reset to a predetermined time period. The test instruction insertion logic 424 may be configured not to insert a test instruction for processing when the task countdown timer has expired. In other words, the test instruction insertion logic 424 may be configured to determine that the parallel processing engine 422 is active (e.g., being used to perform task work) before initiating a test of the processing instance 3 of the parallel processing engine 422. It is advantageous to configure the test instruction insertion logic 424 in this way because it can save processing power (e.g., of a processing unit) by eliminating unnecessary testing of unused (e.g., inactive) parallel processing engines. This may be particularly advantageous in exemplary processing units including multiple parallel processing engines to which a scheduler may schedule task instructions. In these examples, most of the multiple parallel processing engines included in the processing unit may not be used (e.g., inactive) at any given time.

[0116] As described herein, in an automotive application example, in order to be certified as meeting ASIL B or ASIL D standards of ISO 26262, it may be necessary to demonstrate that a range of different faults that may occur at a processing unit can be detected within a predetermined time period of the occurrence of these faults.

[0117] As described herein, operand data may be processed according to a test instruction. A test instruction may include control information that defines the (one or more) operations to be performed on the operand data by a processing instance. The operand data processed according to a test instruction and the control information included in the test instruction may be referred to as a "test instruction control information-operand data combination". In other words, for a test instruction control information-operand data combination, the operand data is processed according to the test instruction, and the test instruction includes control information that defines the (one or more) operations to be performed on the operand data by multiple processing instances. The test instruction insertion logic 424 may be configured to insert multiple different test instruction control information-operand data combinations to be processed by each of the multiple processing instances (e.g., in multiple different processing cycles). Multiple different test instruction control information-operand data combinations may include: one or more different sets of operand data to be processed according to a test instruction including the same control information; sets of operand data to be processed according to one or more test instructions including different control information; and / or one or more different sets of operand data to be processed according to one or more test instructions including different control information. That is, the operand data and / or the control information may be changed between different test instruction control information-operand data combinations in a plurality of different test instruction control information-operand data combinations.

[0118] A plurality of different test instruction control information-operand data combinations can be configured to cumulatively cover (e.g., use or exercise) at least a predetermined percentage of the logic included in the parallel processing engine. The percentage can be 90%, or any other suitable percentage. Using a portion of the logic included in the parallel processing engine when processing the test instruction control information-operand data combination as described herein can expose faults in that portion of the logic. Therefore, using a plurality of different test instruction control information-operand data combinations that cover at least a predetermined percentage of the logic included in the parallel processing engine can make it possible to demonstrate that a series of different faults that may occur at the processing unit can be detected.

[0119] The plurality of different test instruction control information-operand data combinations may include one or more test instruction control information-operand data combinations generated by the test instruction insertion logic 424 (as described herein) and one or more pre-generated (e.g., "appended") test instruction control information-operand data combinations stored by the test instruction insertion logic 424. This may advantageously use less memory relative to pre-generating and storing each of the plurality of different test instruction control information-operand data combinations. At least one set of one or more pre-generated operand values ​​and at least one set of one or more pre-generated control fields may be stored in a dedicated memory 432 at the parallel processing engine 422. For example, to output the generated test instruction control information-operand data combinations, Figure 4 Multiplexers 434 and 436 shown in FIG. 4 can be set to "1" to select a set of one or more pseudo-randomly generated operand values ​​output by LFSR 428 and one or more constrained randomly generated control fields output by CRGL 430. To output a pre-generated test instruction control information-operand data combination, Figure 4 Multiplexers 434 and 436 shown in FIG. 4 can be set to “0” to select a set of one or more pre-generated operand values ​​stored in dedicated memory 432 and one or more pre-generated control fields stored in dedicated memory 432. For example, controller 440 can be configured to control multiplexers 434 and 436.

[0120] One or more predetermined seeds (e.g., as stored in "seeds" 426) and one or more pre-generated test instruction control information-operand data combinations (e.g., as stored in dedicated memory 432) may be pre-determined / pre-generated by constructing a test bench that simulates parallel processing engine 422 (e.g., including test instruction insertion logic 424, multiple processing instances 3, and verification logic 438). The test bench may be run within a fault simulation (e.g., fault injection) EDA tool that is capable of determining which faults (e.g., hardware faults in the processing logic of the parallel processing engine) will be detected by different test instruction control information-operand data combinations run in simulation. This allows for the trialing of many potential seeds and the selection of the best of these seeds (e.g., the seed that results in the detection of the greatest range of faults, and / or results in the need for the fewest additional test instruction control information-operand data combinations). It also allows for the trialing of many candidate additional test instruction control information-operand data combinations and the selection of the best of these combinations (e.g., the additional test instruction control information-operand data combination that results in the detection of the greatest range of faults, and / or that results in the need for the fewest additional test instruction control information-operand data combinations). The number of additional test instruction control information-operand data combinations selected (and their specific combinations) may vary depending on which one or more of the potential seeds are selected.

[0121] The test instruction insertion logic 424 may be configured to insert each of a plurality of different test instruction control information-operand data combinations within a predetermined time period for processing by each of a plurality of processing instances. This may enable a series of different faults that may occur at a processing unit to be detected within the predetermined time period.

[0122] For example, in a first approach, the controller 440 may include a test countdown timer (not shown). The test countdown timer may be set to expire after a predetermined time period (e.g., 100 ms or any other suitable time period). When a task instruction for processing at the parallel processing engine 422 is received, the test countdown timer may be started (e.g., a countdown is started). The test instruction insertion logic 424 may be configured to (e.g., by monitoring the started test countdown timer by the controller 440) identify a threshold amount of time remaining that is less than a predetermined time period, and / or to process a plurality of different test instruction control information-operand data combinations greater than a threshold number of test instruction control information-operand data combinations within a predetermined time period. In response to the identification, the test instruction insertion logic 424 can be configured to insert the remaining test instruction control information-operand data combinations of the plurality of different test instruction control information-operand data combinations, and make the remaining test instruction control information-operand data combinations take precedence over the scheduled task instructions, and / or cause one or more idle cycles of the parallel processing engine, into which the remaining test instruction control information-operand data combinations of the plurality of different test instruction control information-operand data combinations can be inserted. The test instruction insertion logic 424 can be configured to cause one or more idle cycles of the parallel processing engine by causing a scheduler (e.g., scheduler 218) configured to schedule other (e.g., task or non-test) instructions to be processed by the parallel processing engine during one or more cycles of the parallel processing engine not to schedule other (e.g., task or non-test) instructions to be processed by the parallel processing engine (these cycles thus become idle cycles). This can enable the test instruction insertion logic 424 to insert the remaining test instruction control information-operand data combinations of the plurality of different test instruction control information-operand data combinations into these idle cycles for processing before the expiration of the predetermined time period.

[0123] In this first example, the controller 440 may include a plurality of test countdown timers as described in the previous paragraph, each test countdown timer being set to expire after a predetermined time period (e.g., 100ms or any other suitable time period). Each time a task instruction for processing at the parallel processing engine 422 is received, a separate test countdown timer in the plurality of test countdown timers may be started (e.g., start countdown). The test instruction insertion logic 424 may use each of the test countdown timers as described in the previous paragraph. In this way, the test instruction insertion logic 424 may be configured to cause each of the plurality of test instruction control information-operand data combinations to be processed within each of the predetermined time periods set by each of the test countdown timers that are started (e.g., countdown). In addition, in this example, the test instruction insertion logic 424 may be configured to insert a test instruction to be processed by the parallel processing engine 422 only when at least one of the plurality of test countdown timers included in the controller 440 is counting down. This is another way that test instruction insertion logic 424 may be configured to determine that parallel processing engine 422 is active (eg, being used to perform task work) before inserting test instructions for processing by parallel processing engine 422 .

[0124] In a second approach, a fault detection time limit (e.g., 100 ms, as may be specified in a safety standard) may be divided by two to provide a test window (e.g., a 50 ms test window). The test instruction insertion logic 424 may be configured to determine whether the parallel processing engine 422 is active (e.g., being used to perform task work). In response to the test instruction insertion logic 424 determining that the parallel processing engine 422 is active within a test window (e.g., test window N) (e.g., at any point within the test window), the test instruction insertion logic 424 may be configured to insert each of a plurality of different test instruction control information-operand data combinations to be processed by each of a plurality of processing instances within a subsequent test window (e.g., test window N+1) (e.g., in a second approach, where the "test window" is a "predetermined time period"). This second approach may enable any fault that may be detected by a plurality of different test instruction control information-operand data combinations to be detected within a fault detection time limit (e.g., 100 ms). This second approach is particularly suitable when the number of cycles required to process a plurality of different test instruction control information-operand data combinations is significantly less than the number of cycles in a test window. For example, it can be expected that a suitable plurality of different test instruction control information-operand data combinations will require 100,000 cycles to process, while a 50 ms test window may have 50 million cycles, so the power overhead of processing a plurality of different test instruction control information-operand data combinations per 50 ms test window can be negligible.

[0125] Figure 5 A method of processing instructions at a processing unit configured to perform parallel processing according to principles described herein is shown. Figure 5 The method can be referred to in this article Figure 2 The processing unit 116 is executed, and the processing unit 116 includes the processing unit 116 as referred to in this article Figure 4 The one or more parallel processing engines 422.

[0126] As described herein, in a parallel processing engine (e.g., Figure 4 During a processing cycle of a parallel processing engine 422 (shown in ), a set of one or more operand values ​​equal to the number of processing instances of the parallel processing engine may be processed in parallel according to the same instruction. Hereinafter, a processing cycle of the parallel processing engine in which each processing instance processes task (e.g., non-test) instructions in parallel may be referred to as a "task cycle", and a processing cycle of the parallel processing engine in which each processing instance processes test instructions in parallel may be referred to as a "test cycle". Preferably, the test cycle occurs during an idle cycle (as defined herein) of the parallel processing engine, but need not be so.

[0127] return Figure 5 Optionally, in step S500, it may be determined whether the next processing cycle of the parallel processing engine is an idle cycle. As described herein, an "idle cycle" is a period during which the parallel processing engine is not being processed (e.g., Figure 2 The scheduler 218 shown in FIG. 218 is used to schedule the processing cycles of the parallel processing engine to process any other (e.g., task or non-test) instructions. Figure 4 The described test instruction insertion logic 424 may be configured to perform step S500 .

[0128] In response to determining that the next processing cycle of the parallel processing engine is not an idle cycle, no further action may be taken with respect to the next processing cycle (e.g., by the test instruction insertion logic 424). Figure 5 In step S502, during the next processing cycle, the task (e.g., non-test) instruction can be processed in parallel by multiple processing instances of the parallel processing engine to generate corresponding multiple task outputs. That is, the next processing cycle is a task cycle. After completing step S502, Figure 5 The method can return to step S500, so that Figure 5 The method is repeated in subsequent processing cycles.

[0129] During a task cycle, each of the plurality of processing instances may operate on different operand data according to the task instructions. For example, during a task cycle, eight different sets of one or more task operand values ​​may be processed in parallel at the plurality of processing instances 3 of the parallel processing engine 422 according to the task instructions. For example, for simplicity, only the first processing instance (PI1) 3-1 and the second processing instance (PI2) 3-2 are considered. Figure 5 During the task cycle shown in step S502, a first set of one or more task operand values ​​can be processed at a first processing instance (PI1) 3-1 according to a task instruction to generate a first task output, and in parallel, a second set of one or more task operand values ​​can be processed at a second processing instance (PI2) 3-2 according to a task instruction to generate a second task output, i.e., the second set of one or more task operand values ​​is different from the first set of one or more task operand values.

[0130] Alternatively, in response to determining in step S500 that the next processing cycle of the parallel processing engine 422 is an idle cycle, Figure 5 In step S504, a test instruction for processing by each of the multiple processing instances of the parallel processing engine may be inserted to generate corresponding multiple test outputs. That is, the next processing cycle is a test cycle. After completing step S504, Figure 5The method can return to step S500, so that Figure 5 The method is repeated in subsequent processing cycles.

[0131] During the test cycle, each of the multiple processing instances may operate on the same operand data according to the test instruction. For example, during the test cycle, eight identical sets of one or more test operand values ​​may be processed in parallel at the multiple processing instances 3 of the parallel processing engine 422 according to the test instruction. For example, for simplicity, only the first processing instance (PI1) 3-1 and the second processing instance (PI2) 3-2 are considered. Figure 5 During the test cycle shown in step S504, a first set of one or more test operand values ​​can be processed according to the test instruction at the first processing instance (PI1) 3-1 to generate a first test output, and in parallel, a second set of one or more test operand values ​​can be processed according to the test instruction at the second processing instance (PI2) 3-2 to generate a second test output, i.e., the first set of one or more test operand values ​​is the same as (e.g., identical to) the second set of one or more test operand values.

[0132] exist Figure 5 In step S506, test outputs generated by the plurality of processing instances during the test phase may be compared, and if (e.g., in response to determining) the compared test outputs do not match, a fault signal may be issued, as described herein. For example, again considering only the first processing instance (PI1) 3-1 and the second processing instance (PI2) 3-2 for simplicity, in step S506, a first test output generated by the first processing instance (PI1) 3-1 and a second test output generated by the second processing instance (PI2) 3-2 may be compared, and if the compared test outputs do not match, a fault signal may be issued.

[0133] As stated in this article, Figure 5Step S500 is optional. That is, in other examples, the test instruction insertion logic 424 does not need to determine whether the next processing cycle of the parallel processing engine is an idle cycle before inserting the test instruction for processing. For example, the test instruction insertion logic 424 can periodically insert test instructions for processing (e.g., independently of whether the task instruction is scheduled to be processed at the parallel processing engine during the next processing cycle). That is, the test instruction insertion logic 424 can insert test instructions for processing according to a predetermined test frequency. The test instructions can be given priority relative to the scheduled task instructions, such as delaying the processing of these scheduled task instructions, or even replacing these scheduled task instructions so that they must be resubmitted for processing in a subsequent processing cycle. Alternatively, the test instructions can be added to an instruction queue (e.g., including task instructions) to be processed at the parallel processing engine. In these examples, the next processing cycle (e.g., Figure 5 Whether the next round of processing is a task cycle (S502) or a test cycle (S504) depends on whether a test instruction has been inserted for processing during this processing cycle.

[0134] Can Figure 5 The method in performs multiple rounds. That is, instructions (e.g., tasks and test instructions) can be processed at the parallel processing engine during multiple cycles of the parallel processing engine. Therefore, the multiple cycles can include one or more task cycles and one or more test cycles. X% of the multiple cycles can be task cycles, and (100-x)% of the multiple cycles can be test cycles. In an example, x can be greater than 50. In increasingly preferred examples, x can be greater than or equal to: 55, 60, 65, 70, 75, 80, 85, 90, or 95. This reflects that, according to the principles described herein, the processing power and time of the parallel processing engine available for performing task work is greater than the percentage of processing power and time used to perform the test of the processing unit.

[0135] It should be understood that the processing unit described herein and the method of processing instructions at the processing unit described herein need not be used in safety-critical processing and / or automotive applications. For example, the processing unit described herein and / or the method of processing instructions at the processing unit described herein can be used in supercomputing applications.

[0136] Figure 6A computer system in which the processing units described herein may be implemented is shown. The computer system includes a CPU 116-1, a GPU 116-2, a memory 112, a neural network accelerator (NNA) 642, and other devices 644, such as a display 646, a speaker 648, and a camera 650. In other examples, one or more of the depicted components may be omitted from the system. The components of the computer system may communicate with each other via a communication bus 640.

[0137] Figures 1 to 4 The processing system, processing unit and parallel processing engine are shown as including multiple functional blocks. This is only schematic and is not intended to define a strict division between different logical elements of such entities. Each functional block can be provided in any suitable manner. It should be understood that the intermediate values ​​described herein as being formed by the processing system, processing unit or parallel processing engine do not need to be physically generated by the processing system, processing unit or parallel processing engine at any point in time, and may only represent logical values ​​that conveniently describe the processing performed by the processing system, processing unit or parallel processing engine between its input and output.

[0138] The processing system, processing unit or parallel processing engine described herein may be included in hardware on an integrated circuit. The processing system, processing unit or parallel processing engine described herein may be configured to perform any method described herein. Generally speaking, any of the functions, methods, techniques or components described above may be implemented in software, firmware, hardware (e.g., fixed logic circuitry) or any combination thereof. The terms "module", "function", "component", "element", "unit", "block" and "logic" may be used herein to generally represent software, firmware, hardware or any combination thereof. In the case of software implementation, a module, function, component, element, unit, block or logic represents a program code, which performs a specified task when executed on a processor. The algorithms and methods described herein may be performed by one or more processors that execute code, which causes the processor to perform the algorithm / method. Examples of computer-readable storage media include random access memory (RAM), read-only memory (ROM), optical disk, flash memory, hard disk storage, and other memory devices that may be used to store instructions or other data using magnetic, optical and other technologies and may be accessed by a machine.

[0139] As used herein, the terms computer program code and computer readable instructions refer to any kind of executable code for a processor, including code expressed in machine language, interpreted language, or scripting language. Executable code includes binary code, machine code, byte code, code that defines an integrated circuit (e.g., hardware description language or netlist), and code expressed in programming language code such as C, Java, or OpenCL. Executable code can be, for example, any kind of software, firmware, script, module, or library that, when properly executed, processed, interpreted, compiled, run in a virtual machine or other software environment, causes a processor of a computer system supporting the executable code to perform the tasks specified by the code.

[0140] A processor, computer or computer system may be any kind of device, machine or special purpose circuit, or a collection or part thereof, which has processing capabilities so that it can execute instructions. A processor may be or include any kind of general or special purpose processor, such as a CPU, GPU, NNA, system on chip, state machine, media processor, application specific integrated circuit (ASIC), programmable logic array, field programmable gate array (FPGA), etc. A computer or computer system may include one or more processors.

[0141] The present invention is also intended to cover software that defines the configuration of hardware as described herein, such as hardware description language (HDL) software for designing integrated circuits or for configuring programmable chips to perform desired functions. That is, a computer-readable storage medium may be provided on which is encoded computer-readable program code in the form of an integrated circuit definition data set, which, when processed (i.e., run) in an integrated circuit manufacturing system, configures the system to manufacture a processing system, processing unit, or parallel processing engine configured to perform any of the methods described herein, or to manufacture a processing system, processing unit, or parallel processing engine that includes any of the devices described herein. The integrated circuit definition data set may be, for example, an integrated circuit description.

[0142] Thus, a method of manufacturing a processing system, a processing unit, or a parallel processing engine as described herein at an integrated circuit manufacturing system may be provided. In addition, an integrated circuit definition data set may be provided, which, when processed in an integrated circuit manufacturing system, enables the method of manufacturing a processing system, a processing unit, or a parallel processing engine to be performed.

[0143] The integrated circuit definition data set may be in the form of computer code, for example, as a netlist, code for configuring a programmable chip, as a hardware description language that defines hardware suitable for fabrication at any level in an integrated circuit, including as register transfer level (RTL) code, as a high-level circuit representation (e.g., Verilog or VHDL), and as a low-level circuit representation (e.g., OASIS (RTM) and GDSII). The higher-level representation (e.g., RTL) that logically defines hardware suitable for fabrication in an integrated circuit may be processed at a computer system configured to generate a manufacturing definition of the integrated circuit in the context of a software environment that includes definitions of circuit elements and rules for combining those elements to generate a manufacturing definition of the integrated circuit so defined by the representation. As is typically the case with software executed at a computer system to define a machine, one or more intermediate user steps (e.g., providing commands, variables, etc.) may be required to configure the computer system to generate a manufacturing definition of the integrated circuit to execute code that defines the integrated circuit to generate the manufacturing definition of the integrated circuit.

[0144] Now about Figure 7 Examples are described of processing an integrated circuit definition data set at an integrated circuit manufacturing system to configure the system as a manufacturing processing system, processing unit, or parallel processing engine.

[0145] Figure 7 An example of an integrated circuit (IC) manufacturing system 752 is shown, which is configured to manufacture a processing system, a processing unit, or a parallel processing engine as described in any example herein. Specifically, the IC manufacturing system 752 includes a layout processing system 754 and an integrated circuit generation system 756. The IC manufacturing system 752 is configured to receive an IC definition data set (e.g., defining a processing system, a processing unit, or a parallel processing engine as described in any example herein), process the IC definition data set, and generate an IC (e.g., which includes a processing system, a processing unit, or a parallel processing engine as described in any example herein) based on the IC definition data set. Processing of the IC definition data set configures the IC manufacturing system 752 to manufacture an integrated circuit, which includes a processing system, a processing unit, or a parallel processing engine as described in any example herein.

[0146] The layout processing system 754 is configured to receive and process an IC definition data set to determine a circuit layout. Methods for determining a circuit layout based on an IC definition data set are known in the art and may, for example, involve synthesizing RTL code to determine a gate-level representation of a circuit to be generated, such as in terms of logic components (e.g., NAND, NOR, AND, OR, MUX, and FLIP-FLOP components). By determining location information for the logic components, the circuit layout may be determined by the gate-level representation of the circuit. This may be done automatically or with user involvement in order to optimize the circuit layout. When the layout processing system 754 has determined the circuit layout, the layout processing system may output the circuit layout definition to the IC generation system 756. The circuit layout definition may be, for example, a circuit layout description.

[0147] As is known in the art, IC generation system 756 generates an IC according to a circuit layout definition. For example, IC generation system 756 may implement a semiconductor device manufacturing process to generate an IC, which process may involve a multi-step sequence of photolithography and chemical processing steps during which electronic circuits are gradually formed on a wafer made of semiconductor material. The circuit layout definition may be in the form of a mask that can be used in a photolithography process to generate an IC according to the circuit definition. Alternatively, the circuit layout definition provided to IC generation system 756 may be in the form of a computer readable code that the IC generation system 756 may use to form a suitable mask for generating the IC.

[0148] The different processes performed by the IC manufacturing system 752 may all be implemented in one location, such as by one party. Alternatively, the IC manufacturing system 752 may be a distributed system such that some processes may be performed in different locations and may be performed by different parties. For example, some of the following stages may be performed in different locations and / or by different parties: (i) synthesizing RTL code representing an IC definition data set to form a gate-level representation of a circuit to be generated; (ii) generating a circuit layout based on the gate-level representation; (iii) forming a mask based on the circuit layout; and (iv) using the mask to manufacture the integrated circuit.

[0149] In other examples, processing of an integrated circuit definition data set at an integrated circuit manufacturing system may configure the system to manufacture a processing system, a processing unit, or a parallel processing engine without processing the IC definition data set to determine a circuit layout. For example, an integrated circuit definition data set may define a configuration of a reconfigurable processor such as an FPGA, and processing of the data set may configure the IC manufacturing system to generate (e.g., by loading the configuration data into the FPGA) a reconfigurable processor having the defined configuration.

[0150] In some embodiments, when processed in an integrated circuit manufacturing system, the integrated circuit manufacturing definition data set may enable the integrated circuit manufacturing system to generate an apparatus as described herein. Figure 7 An integrated circuit manufacturing system configured in the manner described can manufacture devices as described herein.

[0151] In some examples, the integrated circuit definition data set may include software that runs on, or in combination with, hardware defined at the data set. Figure 7 In the example shown, the IC generation system can be further configured by the integrated circuit definition dataset to load firmware onto the integrated circuit according to the program code defined in the integrated circuit definition dataset when manufacturing the integrated circuit, or otherwise provide the integrated circuit with program code for use with the integrated circuit.

[0152] When compared to known implementations, the implementation of the concepts set forth in this application in devices, equipment, modules and / or systems (and in the methods implemented herein) can improve performance. Performance improvements can include one or more of improved computing performance, reduced latency, increased throughput and / or reduced power consumption. During the manufacture of such devices, devices, modules and systems (e.g., in integrated circuits), a trade-off can be made between performance improvements and physical implementations to improve manufacturing methods. For example, a trade-off can be made between performance improvements and layout area to match the performance of known implementations, but using less silicon. For example, this can be accomplished by reusing functional blocks in a serial manner or sharing functional blocks between elements of devices, devices, modules and / or systems. In contrast, the concepts set forth in this application that cause improvements in the physical implementations of devices, devices, modules and systems (e.g., reduced silicon area) can be weighed against performance improvements. This can be accomplished, for example, by manufacturing multiple instances of a module within a predefined area budget.

[0153] Applicants hereby independently disclose each individual feature described herein and any combination of two or more such features, to the extent that such feature or combination can be implemented based on the specification as a whole in view of the common general knowledge of a person skilled in the art, regardless of whether such feature or combination of features solves any problem disclosed herein. In view of the foregoing description, it will be clear to a person skilled in the art that various modifications can be made within the scope of the invention.

Claims

1. A processing unit configured to perform parallel processing, the processing unit comprising a parallel processing engine, the parallel processing engine comprising: a plurality of processing instances configured to process instructions in parallel; A test instruction insertion logic, wherein the test instruction insertion logic is configured to: identifying idle cycles of the parallel processing engine; and inserting test instructions to be processed by each of the plurality of processing instances during the idle period to generate a corresponding plurality of test outputs; as well as Verification logic, the verification logic is configured to: Compare: a test output generated by a first processing instance of the plurality of processing instances during the idle period; and a test output generated by a second processing instance of the plurality of processing instances during the idle period; and If the compared test outputs do not match, a fault is signaled.

2. The processing unit according to claim 1, wherein: Idle cycles are cycles of the parallel processing engine during which the parallel processing engine is not scheduled to process any other instructions.

3. The processing unit according to claim 1 or 2, wherein: One or more operand values ​​are processed according to the test instruction, and the test instruction insertion logic is configured to pseudo-randomly generate the one or more operand values.

4. The processing unit according to claim 3, wherein: The test instruction insertion logic is configured to pseudo-randomly generate the one or more operand values ​​based on one or more predetermined seeds.

5. The processing unit according to claim 4, wherein: The test instruction insertion logic is configured to pseudo-randomly generate the one or more operand values ​​using one or more linear feedback shift registers that generate the one or more operand values ​​according to the one or more predetermined seeds.

6. The processing unit according to claim 1 or 2, wherein: The test instruction includes one or more control fields, and the test instruction insertion logic is configured to generate the one or more control fields using constrained random generator logic.

7. The processing unit according to claim 1 or 2, wherein: For a test instruction control information-operand data combination, the operand data is processed according to the test instruction, and the test instruction includes control information, which defines (one or more) operations to be performed on the operand data by the multiple processing instances, and the test instruction insertion logic is configured to insert multiple different test instruction control information-operand data combinations for processing by each of the multiple processing instances.

8. The processing unit according to claim 7, wherein: The plurality of different test instruction control information-operand data combinations are configured to cumulatively cover at least a predetermined percentage of the logic included in the parallel processing engine.

9. According to the processing unit of claim 7, the multiple different test instruction control information-operand data combinations include one or more test instruction control information-operand data combinations generated by the test instruction insertion logic and one or more pre-generated test instruction control information-operand data combinations stored by the test instruction insertion logic.

10. The processing unit of claim 7, the test instruction insertion logic being configured to insert each of the plurality of different test instruction control information-operand data combinations within a predetermined time period to be processed by each of the plurality of processing instances.

11. The processing unit according to claim 10, wherein the test instruction insertion logic is configured to: identifying that less than a threshold amount of time remains for the predetermined time period and / or greater than a threshold number of test instruction control information-operand data combinations of the plurality of different test instruction control information-operand data combinations remain to be processed within the predetermined time period; and In response to the identifying, one or more idle cycles of the parallel processing engine are caused.

12. The processing unit of claim 11 , wherein the test instruction insertion logic is configured to cause one or more idle cycles of the parallel processing engine by causing a scheduler configured to schedule other instructions to be processed by the parallel processing engine to not schedule other instructions to be processed by the parallel processing engine during one or more cycles of the parallel processing engine.

13. The processing unit according to claim 1 or 2, comprising a scheduler configured to schedule other instructions to be processed by the parallel processing engine, wherein: The test instruction insertion logic is configured to identify the idle cycle and insert the test instruction for processing independently of the scheduler.

14. The processing unit according to claim 1 or 2, wherein: The plurality of test outputs are not written to memory external to the parallel processing engine.

15. The processing unit according to claim 1 or 2, wherein the test instruction insertion logic is implemented using fixed-function hardware, and / or the verification logic is implemented using fixed-function hardware.

16. The processing unit according to claim 1 or 2, wherein: Each process instance of the plurality of process instances is identical to every other process instance of the plurality of process instances.

17. The processing unit according to claim 1 or 2, wherein the processing unit is a graphics processing unit (GPU) or a central processing unit (CPU), and / or wherein the parallel processing engine is an integer pipeline, a floating point pipeline or a complex pipeline.

18. The processing unit of claim 1 or 2, the parallel processing engine being configured to perform Single Instruction Multiple Data (SIMD) processing.

19. A method of processing instructions at a processing unit configured to perform parallel processing, the processing unit comprising a parallel processing engine, the parallel processing engine comprising a plurality of processing instances configured to process instructions in parallel, the method comprising: identifying an idle cycle of the parallel processing engine; inserting test instructions to be processed by each of the plurality of processing instances during the idle period to generate a corresponding plurality of test outputs; Compare: a test output generated by a first processing instance of the plurality of processing instances during the idle period; and a test output generated by a second processing instance of the plurality of processing instances during the idle period; and If the compared test outputs do not match, a fault is signaled.

20. An integrated circuit manufacturing system, comprising: a non-transitory computer-readable storage medium having stored thereon a computer-readable description of a processing unit; a layout processing system configured to process the computer-readable description to generate a circuit layout description of an integrated circuit including the processing unit; as well as an integrated circuit production system configured to manufacture the processing unit according to the circuit layout description; The processing unit is configured to perform parallel processing, and the processing unit includes a parallel processing engine, and the parallel processing engine includes: a plurality of processing instances configured to process instructions in parallel; A test instruction insertion logic, wherein the test instruction insertion logic is configured to: identifying idle cycles of the parallel processing engine; and inserting test instructions to be processed by each of the plurality of processing instances during the idle period to generate a corresponding plurality of test outputs; and Verification logic, the verification logic is configured to: Compare: a test output generated by a first processing instance of the plurality of processing instances during the idle period; and a test output generated by a second processing instance of the plurality of processing instances during the idle period; and If the compared test outputs do not match, a fault is signaled.

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