Cache operation method and device and electronic equipment

Abstract

The invention provides a cache operation method, a cache operation device and electronic equipment, belongs to the technical field of data storage, and aims at realizing cache operation under the condition that a first-level cache space and a second-level cache space do not contain to-be-read target data. First cache page data which is at the end of the most recently used cache page linked list and does not contain a locking mark or second cache page data which is at the end of the most rarely used cache page linked list and does not contain the locking mark is transferred from a first-level cache space to a second-level cache space, so that the system cache space is greatly expanded; meanwhile, it can be guaranteed that the locked cache page data is not transferred or eliminated, data stored in the first-level cache space and the second-level cache space can better meet actual requirements of a user, and therefore the cache hit rate of system cache can be increased, and in addition, due to the fact that the second-level cache space is a persistent memory, the cache hit rate of the system cache can be increased. Wherein the data still exist after power failure, so that the quick recovery efficiency of the application can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a cache operation method, device and electronic device. Background Art

[0002] Caching is a technology that improves data reading efficiency. For a long time, various cache mechanisms have been used to process data in memory. The emergence of persistent memory has changed the inherent memory architecture. Persistent memory has the characteristics of large capacity, persistence, byte addressing, low latency and high bandwidth. It allows the use of conventional read and write instructions to modify data, effectively absorbing the advantages of traditional memory and hard disk.

[0003] Due to memory space limitations, the current cache mechanism lacks caches that reside outside of physical memory, limiting the hit rate from being further improved. At the same time, there is a lack of the function of locking memory pages. The current cache algorithm cannot effectively choose when to clear a specified memory page from the cache, which may cause some critical data or frequently accessed data to be replaced, making the cache hit rate not high enough and the memory unable to be used more fully. Finally, the data will be lost after the memory loses power, and the power-on application recovery still needs to read the data from the hard disk, which reduces the recovery speed. Summary of the invention

[0004] In view of the above problems, embodiments of the present application provide a cache operation method, device and electronic device to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a cache operation method, which is applied to an electronic device, wherein the electronic device includes a primary cache space and a secondary cache space, and the secondary cache space is a persistent memory, and the method includes:

[0006] In response to a target read instruction, querying the first-level cache space and the second-level cache space for target data corresponding to the target read instruction;

[0007] In the case that the target data is not included in the first-level cache space and the second-level cache space, the first cache page data at the last position and not including the lock mark is transferred from the least recently used cache page linked list of the first-level cache space to the second-level cache space, and the second cache page data at the last position and not including the lock mark is transferred from the least frequently used cache page linked list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page linked list are arranged in order of the length of time of not being hit from short to long; and the cache page data in the least frequently used cache page linked list are arranged in order of the read frequency from large to small;

[0008] Based on the target read instruction, the target data is read into the first-level cache space from the target external memory space corresponding to the first-level cache space.

[0009] Optionally, the method further comprises:

[0010] In response to the target locking instruction, in the least recently used cache page linked list and / or the least frequently used cache page linked list, a locking mark is added to the third cache page data corresponding to the target locking instruction, so as to lock the third cache page data and obtain the locked third cache page data;

[0011] When a target clearing instruction corresponding to the locked third cache page data is received, the locked third cache page data is cleared from the first-level cache space in response to the target clearing instruction.

[0012] Optionally, the method further comprises:

[0013] When the missed time length of the locked third cache page data is greater than or equal to the first preset time length, and the locked third cache page data exists in the least recently used cache page linked list, deleting the lock mark of the locked third cache page data to unlock the locked third cache page data and obtain the third cache page data;

[0014] Within a second preset time period, when the access rate of the locked third cache page is less than a first threshold and the locked third cache page data exists in the least frequently used cache page linked list, the lock mark of the locked third cache page data is deleted to unlock the locked third cache page data to obtain the third cache page data.

[0015] Optionally, the transferring, from the least recently used cache page linked list of the first-level cache space, the first cache page data which is at the last position and does not contain a lock mark to the second-level cache space comprises:

[0016] When the target read instruction is a sequential read instruction and the data volume of the first cache page data is greater than or equal to a first threshold, creating a cache data sorting thread and a write operation processing thread;

[0017] Based on the cache data sorting thread, transferring the first cache page data to a plurality of data block storage spaces of 64 megabytes in size;

[0018] Based on the write operation processing thread, the first cache page data in the data block storage space is transferred to the secondary cache space.

[0019] Optionally, the method further comprises:

[0020] In a case where the target data is included in the first-level cache space, determining a first linked list where the target data is located;

[0021] In the case where the first linked list is the least recently used cache page linked list, the target data is adjusted to the first position of the least recently used cache page linked list.

[0022] Optionally, the method further comprises:

[0023] In a case where the first linked list is the least frequently used cache page linked list, adding one to the read frequency of the target data to update the read frequency of the target data to obtain an updated read frequency;

[0024] Based on the updated read frequency, the position of the target data in the least frequently used cache page linked list is re-determined.

[0025] Optionally, the method further comprises:

[0026] Determine a first hit rate of the least recently used cache page linked list and a second hit rate of the least frequently used cache page linked list;

[0027] When the first hit rate is greater than the second hit rate, increasing the length of the least recently used cache page linked list according to a preset ratio;

[0028] When the first hit rate is less than the second hit rate, increasing the length of the least frequently used cache page linked list according to the preset ratio;

[0029] When the first hit rate is equal to the second hit rate, the length of the least recently used cache page linked list and the length of the least frequently used cache page linked list are maintained unchanged.

[0030] Optionally, part of the memory space of the secondary cache space is in application direct access mode, and the remaining memory space of the secondary cache space is in memory mode, and the method further includes:

[0031] Copying the fourth cache page data whose reading frequency is greater than or equal to the preset frequency in the least frequently used cache page linked list to a portion of the memory space in the secondary cache space that is in the application direct access mode;

[0032] After the secondary cache space is powered off and powered on again, application recovery is performed based on the fourth cache page data in the portion of the memory space in the secondary cache space that is in the application direct access mode.

[0033] In a second aspect, an embodiment of the present application provides a cache operation device, which is applied to an electronic device, wherein the electronic device includes a primary cache space and a secondary cache space, wherein the secondary cache space is a persistent memory, and the device includes:

[0034] A query module, configured to query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space in response to the target read instruction;

[0035] A transfer module, configured to transfer, when the target data is not contained in the first-level cache space and the second-level cache space, a first cache page data which is at the end and does not contain a lock mark from a least recently used cache page linked list of the first-level cache space to the second-level cache space, and transfer a second cache page data which is at the end and does not contain a lock mark from a least frequently used cache page linked list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page linked list are arranged in order of a short to a long time of not being hit; and the cache page data in the least frequently used cache page linked list are arranged in order of a large to a small reading frequency;

[0036] A reading module is used to read the target data into the first-level cache space from the target external memory space corresponding to the first-level cache space based on the target reading instruction.

[0037] Optionally, the device further comprises:

[0038] a locking module, configured to, in response to a target locking instruction, add a locking mark to the third cache page data corresponding to the target locking instruction in the least recently used cache page linked list and / or the least frequently used cache page linked list, so as to lock the third cache page data and obtain the locked third cache page data;

[0039] The clearing module is used for clearing the locked third cache page data from the first-level cache space in response to receiving a target clearing instruction corresponding to the locked third cache page data.

[0040] Optionally, the device further comprises:

[0041] a first unlocking module, configured to, when a missed time length of the locked third cache page data is greater than or equal to a first preset time length and the locked third cache page data exists in the least recently used cache page linked list, delete a lock mark of the locked third cache page data, so as to unlock the locked third cache page data and obtain the third cache page data;

[0042] A second unlocking module is used to delete the locking mark of the locked third cache page data within a second preset time period, so as to unlock the locked third cache page data and obtain the third cache page data when the access rate of the locked third cache page is less than the first threshold and the locked third cache page data exists in the least frequently used cache page linked list.

[0043] Optionally, the transfer module includes:

[0044] Creating a submodule, used for creating a cache data sorting thread and a write operation processing thread when the target read instruction is a sequential read instruction and the data amount of the first cache page data is greater than or equal to a first threshold;

[0045] A first transfer submodule, configured to transfer the first cache page data to a plurality of data block storage spaces of 64 megabytes in size based on the cache data sorting thread;

[0046] The second transfer submodule is used to transfer the first cache page data in the data block storage space to the secondary cache space based on the write operation processing thread.

[0047] Optionally, the device further comprises:

[0048] A first determining module, configured to determine a first linked list where the target data is located when the first-level cache space contains the target data;

[0049] The adjustment module is used to adjust the target data to the first position of the least recently used cache page linked list when the first linked list is the least recently used cache page linked list.

[0050] Optionally, the device further comprises:

[0051] A frequency updating module, configured to, when the first linked list is the least frequently used cache page linked list, increase the read frequency of the target data by one to update the read frequency of the target data and obtain an updated read frequency;

[0052] The second determination module is used to re-determine the position of the target data in the least frequently used cache page linked list based on the updated reading frequency.

[0053] Optionally, the device further comprises:

[0054] A third determination module, used to determine a first hit rate of the least recently used cache page linked list and a second hit rate of the least frequently used cache page linked list;

[0055] A first increasing module, configured to increase the length of the least recently used cache page linked list according to a preset ratio when the first hit rate is greater than the second hit rate;

[0056] A second increasing module, configured to increase the length of the least frequently used cache page linked list according to the preset ratio when the first hit rate is less than the second hit rate;

[0057] A maintaining module is used to maintain the length of the least recently used cache page linked list and the length of the least frequently used cache page linked list unchanged when the first hit rate is equal to the second hit rate.

[0058] Optionally, part of the memory space of the secondary cache space is in application direct access mode, and the remaining memory space of the secondary cache space is in memory mode, and the device further includes:

[0059] A copy module, used for copying the fourth cache page data with a reading frequency greater than or equal to a preset frequency in the least frequently used cache page linked list to a part of the memory space in the secondary cache space in the application direct access mode;

[0060] The recovery module is used to perform application recovery based on the fourth cache page data in the partial memory space in the secondary cache space that is in the application direct access mode after the secondary cache space is powered off and powered on again.

[0061] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the cache operation method as described in any one of the above.

[0062] The specific beneficial effects are:

[0063] In an embodiment of the present application, in response to a target read instruction, the target data corresponding to the target read instruction is queried in the primary cache space and the secondary cache space. When the target data is not contained in both the primary cache space and the secondary cache space, the first cache page data which is at the end and does not contain a lock mark is transferred from the least recently used cache page linked list of the primary cache space to the secondary cache space, and the second cache page data which is at the end and does not contain a lock mark is transferred from the least frequently used cache page linked list of the primary cache space to the secondary cache space; wherein the cache page data in the least recently used cache page linked list is arranged in order from short to long according to the length of time when the page is not hit; the cache page data in the least frequently used cache page linked list is arranged in order from large to small according to the read frequency, and based on the target read instruction, the cache page data in the primary cache space is transferred from the least recently used cache page linked list to the secondary cache space. In the corresponding target external memory space, the target data is read into the first-level cache space. When neither the first-level cache space nor the second-level cache space contains the target data to be read, the first cache page data at the end of the least recently used cache page list and without a lock mark or the second cache page data at the end of the least frequently used cache page list and without a lock mark can be transferred from the first-level cache space to the second-level cache space, which greatly expands the system cache space and can ensure that the locked cache page data is not transferred or eliminated. The data stored in the first-level cache space and the second-level cache space can better meet the actual needs of users, thereby improving the cache hit rate of the system cache. In addition, since the second-level cache space is a persistent memory, the data therein still exists after power failure, which can improve the efficiency of rapid recovery of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0065] Figure 1 It is a flowchart of a cache operation method provided in an embodiment of the present application;

[0066] Figure 2 It is a flowchart of another cache operation method provided in an embodiment of the present application;

[0067] Figure 3 It is a flowchart of a method for dynamically adjusting the length of a least recently used cache page linked list and the length of a least frequently used cache page linked list provided by an embodiment of the present application;

[0068] Figure 4 It is a logic block diagram of a cache operation device provided in an embodiment of the present application;

[0069] Figure 5 It is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The exemplary embodiments of the present application will be described in more detail below in conjunction with the accompanying drawings in the embodiments of the present application. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0071] Reference Figure 1 , Figure 1 A flow chart of a cache operation method provided in an embodiment of the present application is applied to an electronic device, the electronic device includes a primary cache space and a secondary cache space, the secondary cache space is a persistent memory, and the method may include:

[0072] Step 101 , in response to a target read instruction, query the first-level cache space and the second-level cache space for target data corresponding to the target read instruction.

[0073] In the embodiments of the present application, cache is a storage technology designed to increase the speed of data retrieval, which reduces the delay of data processing by providing a fast intermediate storage layer between the central processing unit (CPU) and the memory. The existence of cache greatly improves the performance of computer systems, especially in the scenario of processing large amounts of data or complex computing tasks. The concept of cache is not limited to the hardware level, but also has a wide range of applications at the software level, such as Web browser cache, database query cache, etc. The working principle of cache is based on the strategy of "space for time", that is, using faster but more expensive storage media such as static random access memory (SRAM) to temporarily store data, thereby speeding up the access speed of data. When the CPU needs to read data, it will first try to get it from the cache. If the required data exists in the cache (called a cache hit), it will be read directly; if it does not exist (called a cache miss), it is necessary to read the data from the slower main memory or other storage device and load it into the cache for later use.

[0074] In an embodiment of the present application, if the current system receives a target read instruction initiated by a user, the system can respond to the instruction and query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space in the system. The first-level cache space and the second-level cache space can together constitute the system cache of the system.

[0075] Step 102, when the target data is not contained in the first-level cache space and the second-level cache space, the first cache page data that is at the end and does not contain a lock mark is transferred from the least recently used cache page list of the first-level cache space to the second-level cache space, and the second cache page data that is at the end and does not contain a lock mark is transferred from the least frequently used cache page list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page list are arranged in order from short to long according to the length of time that they have not been hit; and the cache page data in the least frequently used cache page list are arranged in order from large to small according to the reading frequency.

[0076] In an embodiment of the present application, the data in the cache can be stored in the cache in the form of data pages, which are called cache pages. A linked list is a data structure for non-continuous storage, consisting of a series of nodes, each node containing two parts, one part is an element for storing data, and the other part is a pointer to the next node. If the target data is not contained in the primary cache space, the cache page data in the primary cache space needs to be updated so that the target data outside the primary cache space can be read into the primary cache space. In the primary cache space, the least recently used cache page linked list and the least frequently used cache page linked list can be included. In the least recently used cache page linked list, multiple cache page data can be included, and these cache page data can be arranged in order from short to long according to the duration of not being hit. In the least frequently used cache page linked list, multiple cache page data can be included, and these cache page data can be arranged in order from large to small according to the read frequency. The primary cache space can be connected to a persistent memory space as a secondary cache space, and the secondary cache space can be used to receive data eliminated from the primary cache space, and can be directly read and called by the CPU. Therefore, the primary cache space and the secondary cache space can together constitute the system cache. In the least recently used cache page linked list, the first cache page data that is at the end and does not contain a lock mark can be transferred to the secondary cache space corresponding to the primary cache space. In the least frequently used cache page linked list, the second cache page data that is at the end and does not contain a lock mark can also be transferred to the secondary cache space corresponding to the primary cache space. The data source of the transferred cache page data can be determined by the cache elimination algorithm of the primary cache space. The lock mark is a method of locking the cache page data. After the cache page is added with the lock mark, it will be stored in the primary cache space all the time and will not participate in the cache page data elimination process. In this way, there is a cache space in the primary cache space to store the target data. The cache page data can be stored in the above two linked lists in the form of pointers. When transferring the first cache page data and the second cache page data, the first cache page data and the second cache page data can be found according to the pointers, and the first cache page data and the second cache page data and their corresponding pointers can be removed together. The pointer mentioned here refers to the element storing data in the linked list, rather than the pointer of the linked list itself used to point to other nodes. After the first cache page data and the second cache page data are transferred to the secondary cache space, they can be stored in a mirrored least recently used cache page linked list and a mirrored least frequently used cache page linked list in the secondary cache space, wherein the mirrored least recently used cache page linked list corresponds to the least recently used cache page linked list and is used to store cache page data eliminated from the least recently used cache page linked list, and the mirrored least frequently used cache page linked list can correspond to the least frequently used cache page linked list and is used to store cache page data eliminated from the least frequently used cache page linked list.

[0077] Step 103: Based on the target read instruction, read the target data from the target external memory space corresponding to the first-level cache space into the first-level cache space.

[0078] In an embodiment of the present application, the target data can be read from the target external memory space corresponding to the first-level cache space to the first-level cache space according to the target read instruction. After being read to the first-level cache space, the target data can be stored in the form of data pages.

[0079] In an embodiment of the present application, by responding to a target read instruction, the target data corresponding to the target read instruction is queried in the first-level cache space and the second-level cache space. When the target data is not contained in both the first-level cache space and the second-level cache space, the first cache page data that is at the end and does not contain a lock mark is transferred from the least recently used cache page list of the first-level cache space to the second-level cache space, and the second cache page data that is at the end and does not contain a lock mark is transferred from the least frequently used cache page list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page list is arranged in order from short to long according to the length of time that the page has not been hit; the cache page data in the least frequently used cache page list is arranged in order from large to small according to the read frequency, and based on the target read instruction, the cache page data in the first-level cache space is transferred from the least recently used cache page list to the second-level cache space. The target data is read into the first-level cache space from the target external memory space corresponding to the space. When both the first-level cache space and the second-level cache space do not contain the target data to be read, the first cache page data at the end of the least recently used cache page linked list and without a lock mark or the second cache page data at the end of the least frequently used cache page linked list and without a lock mark can be transferred from the first-level cache space to the second-level cache space, which greatly expands the system cache space and can ensure that the locked cache page data is not transferred or eliminated, so that the data stored in the first-level cache space and the second-level cache space can better meet the actual needs of users, thereby improving the cache hit rate of the system cache. In addition, since the second-level cache space is a persistent memory, the data therein still exists after power failure, which can improve the efficiency of rapid recovery of applications.

[0080] Reference Figure 2 , Figure 2 A flow chart of another cache operation method provided in an embodiment of the present application is applied to an electronic device, the electronic device includes a primary cache space and a secondary cache space, the secondary cache space is a persistent memory, and the method may include:

[0081] Step 201 , in response to a target read instruction, query the first-level cache space and the second-level cache space for target data corresponding to the target read instruction.

[0082] In the embodiments of the present application, the implementation content of this step can refer to the embodiment content of step 101, which will not be repeated here.

[0083] Step 202, when the target data is not included in the first-level cache space and the second-level cache space, the first cache page data that is at the end and does not contain a lock mark is transferred from the least recently used cache page list of the first-level cache space to the second-level cache space, or the second cache page data that is at the end and does not contain a lock mark is transferred from the least frequently used cache page list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page list are arranged in order from short to long according to the length of time that they have not been hit; and the cache page data in the least frequently used cache page list are arranged in order from large to small according to the reading frequency.

[0084] In the embodiments of the present application, the implementation content of this step can refer to the implementation content of step 102, which will not be repeated here.

[0085] Optionally, step 202 may include the following sub-steps:

[0086] Sub-step 2021, when the target read instruction is a sequential read instruction and the data volume of the first cache page data is greater than or equal to a first threshold, create a cache data sorting thread and a write operation processing thread.

[0087] In an embodiment of the present application, a sequential read instruction may refer to a sequential data read operation on a data storage device, and the initial storage addresses of the data are continuous. If the target read instruction is a sequential read instruction, and the amount of data of the first cache page data is greater than or equal to the first threshold, a cache data sorting thread and a write operation processing thread may be created to quickly write the first cache page data into the secondary cache space.

[0088] Sub-step 2022: Based on the cache data sorting thread, the first cache page data is transferred to a plurality of data block storage spaces with a size of 64 megabytes.

[0089] In an embodiment of the present application, the cache data sorting thread can first create multiple data block storage spaces of 64 megabytes (MB) in the first-level cache space. After that, the first cache page data can be transferred to the above-mentioned data block storage space according to the cache data sorting thread. If the first data block storage space is full, the remaining part of the first cache page data can continue to be stored in the second data block storage space, and so on.

[0090] Sub-step 2023: Based on the write operation processing thread, transfer the first cache page data in the data block storage space to the secondary cache space.

[0091] In an embodiment of the present application, the first cache page data stored in the data block storage space of the first-level cache space may be transferred to the second-level cache space according to the write operation processing thread.

[0092] In an embodiment of the present application, by creating a cache data sorting thread and a write operation processing thread when the target read instruction is a sequential read instruction and the data volume of the first cache page data is greater than or equal to a first threshold, based on the cache data sorting thread, the first cache page data is transferred to multiple data block storage spaces with a size of 64 megabytes, and based on the write operation processing thread, the first cache page data in the data block storage space is transferred to the secondary cache space. The cache data sorting thread and the write operation processing thread can be used to process data transfer tasks with large data volumes, thereby improving the efficiency of cache data transfer to a certain extent.

[0093] Step 203: Based on the target read instruction, read the target data from the target external memory space corresponding to the first-level cache space into the first-level cache space.

[0094] In the embodiments of the present application, the implementation content of this step can refer to the implementation content of step 104, which will not be repeated here.

[0095] Step 204: When the target data is included in the first-level cache space, determine the first linked list where the target data is located.

[0096] In an embodiment of the present application, if the target data is included in the first-level cache space, the first linked list where the target data is located can be determined. The first linked list can be one of a recently used cache page linked list, a least recently used cache page linked list, a most frequently used cache page linked list, and a least frequently used cache page linked list.

[0097] Step 205: When the first linked list is the least recently used cache page linked list, adjust the target data to the first position of the least recently used cache page linked list.

[0098] In an embodiment of the present application, if the first linked list is a least recently used cache page linked list, the position of the target data may be adjusted to the first position in the least recently used cache page linked list.

[0099] In an embodiment of the present application, by including the target data in the first-level cache space, determining the first linked list where the target data is located, and when the first linked list is the least recently used cache page linked list, adjusting the target data to the first position of the least recently used cache page linked list, when the data in the least recently used cache page linked list is hit, the position of the hit target data in the least recently used cache page linked list can be changed, which can extend the time for the data to be eliminated, so that the data in the system cache is more in line with the actual usage needs of the user, and to a certain extent improves the cache hit rate of the system cache.

[0100] Step 206: When the first linked list is the least frequently used cache page linked list, the read frequency of the target data is increased by one to update the read frequency of the target data to obtain an updated read frequency.

[0101] In an embodiment of the present application, if the first linked list is the least frequently used cache page linked list, the read frequency of the target data may be increased by one to update the read frequency of the target data, thereby obtaining an updated read frequency of the target data.

[0102] In an embodiment of the present application, there may be another method for updating the read frequency, that is, the read frequency of the target data may be calculated according to the time interval between the two most recent read times of the target data. This may make the data in the cache more in line with the user's most recent usage needs, and may improve the cache hit rate of the system cache to a certain extent.

[0103] Step 207: re-determine the position of the target data in the least frequently used cache page linked list based on the updated read frequency.

[0104] In an embodiment of the present application, after obtaining the updated reading frequency of the target data, the position of the target data in the least frequently used cache page linked list may be re-determined according to the updated reading frequency.

[0105] In an embodiment of the present application, by adding one to the read frequency of the target data when the first linked list is the least frequently used cache page linked list to update the read frequency of the target data to obtain an updated read frequency, and based on the updated read frequency, the position of the target data in the least frequently used cache page linked list is re-determined. When the target data is in the least recently used cache page linked list, the position of the target data in the least frequently used cache page linked list can be updated, which can extend the time for the most recently hit target data to be cleared from the first-level cache space, so that the data in the cache can meet the user's usage needs and the cache hit rate of the first-level cache space can be improved to a certain extent.

[0106] Step 208, in response to the target locking instruction, in the least recently used cache page linked list and / or the least frequently used cache page linked list, a locking mark is added to the third cache page data corresponding to the target locking instruction to lock the third cache page data and obtain the locked third cache page data.

[0107] In an embodiment of the present application, when a target locking instruction for cache page data is received, the third cache page data corresponding to the target locking instruction can be determined in the least recently used cache page linked list and / or the least frequently used cache page linked list in response to the target locking instruction. The third cache page data can be the cache page data that the target locking instruction wants to lock. After finding the third cache page data, the third cache page data can be locked, so that the locked third cache page data can be obtained. The locked third cache page data can be actively cleared by the user and is not restricted by the cache data elimination algorithm. In the case where the user does not actively clear it, the locked third cache page data can be stored in the first-level cache space for a long time. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether the first-level cache space and the second-level cache space do not contain the target data.

[0108] Step 209 : upon receiving a target clearing instruction corresponding to the locked third cache page data, clearing the locked third cache page data from the first-level cache space in response to the target clearing instruction.

[0109] In an embodiment of the present application, when a target clearing instruction corresponding to the locked third cache page data is received, the locked third cache page data can be cleared from the first-level cache space in response to the target clearing instruction. After clearing, the first-level cache space no longer contains the locked third cache page data, nor does it contain the third cache page data. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether the first-level cache space and the second-level cache space do not contain the target data.

[0110] In an embodiment of the present application, by responding to a target lock instruction, a lock mark is added to the third cache page data corresponding to the target lock instruction in the least recently used cache page list and / or the least frequently used cache page list, so as to lock the third cache page data and obtain the locked third cache page data. When a target clear instruction corresponding to the locked third cache page data is received, the locked third cache page data is cleared from the first-level cache space in response to the target clear instruction. The cache page data in the least recently used cache page list and / or the least frequently used cache page list in the first-level cache space can be locked, thereby preventing the locked cache page data from being eliminated by the elimination algorithm. At the same time, the locked cache page data can also be actively cleared through the target clear instruction, which can make the data in the first-level cache space more in line with the user's usage habits and improve the cache hit rate of the first-level cache space to a certain extent.

[0111] Step 210, when the missed time length of the locked third cache page data is greater than or equal to the first preset time length, and the locked third cache page data exists in the least recently used cache page linked list, unlock the locked third cache page data to obtain the third cache page data.

[0112] In an embodiment of the present application, if the missed duration of the locked third cache page data is greater than or equal to the first preset duration, the third cache page data can be unlocked, so that the third cache page data can be obtained. Among them, the missed duration of the locked third cache page data can use the missed duration of the third cache page data itself, or it can be recalculated when the locked third cache page data is obtained. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether the first-level cache space and the second-level cache space do not contain the target data.

[0113] Step 211, within a second preset time period, when the access rate of the locked third cache page is less than a first threshold and the locked third cache page data exists in the least frequently used cache page linked list, unlock the locked third cache page data to obtain the third cache page data.

[0114] In an embodiment of the present application, if the access rate of the locked third cache page data is less than the first threshold value within the second preset time length, and the locked third cache page data exists in the least frequently used cache page linked list, the locked third cache page data can be unlocked, so that the third cache page data can be obtained. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether the first-level cache space and the second-level cache space do not contain the target data.

[0115] In an embodiment of the present application, when the non-hit time length of the locked third cache page data is greater than or equal to the first preset time length and the locked third cache page data exists in the least recently used cache page linked list, the lock mark of the locked third cache page data is deleted to unlock the locked third cache page data to obtain the third cache page data. Within the second preset time length, when the access rate of the locked third cache page is less than the first threshold value and the locked third cache page data exists in the least frequently used cache page linked list, the lock mark of the locked third cache page data is deleted to unlock the locked third cache page data to obtain the third cache page data. The locked third cache page data can be unlocked when the locked third cache page data meets the preset conditions, so that the unlocked third cache page data participates in the normal data elimination process of the cache space, which can avoid the situation of user's mistaken locking to a certain extent, improve the activity of the data in the system cache, and thus improve the cache hit rate of the system cache to a certain extent.

[0116] Step 212: copy the fourth cache page data in the least frequently used cache page linked list, whose reading frequency is greater than or equal to the preset frequency, to a portion of the memory space in the secondary cache space that is in the application direct access mode.

[0117] In an embodiment of the present application, in the secondary cache space, part of the memory space can be set to the application direct access mode, and the remaining memory space can be set to the memory mode (such as 5% of the space is in the application direct access mode, and 95% of the space is in the memory mode). The cache page data with a read frequency greater than or equal to the preset frequency in the least frequently used cache page linked list can be copied to part of the memory space in the secondary cache space that is in the application direct access mode. It should be noted that this step can be implemented regardless of whether the primary cache space or the secondary cache space contains the target data, or whether the primary cache space and the secondary cache space do not contain the target data.

[0118] Step 213 , after the secondary cache space is powered off and powered on again, application recovery is performed based on the fourth cache page data in the portion of the memory space in the secondary cache space that is in the application direct access mode.

[0119] In an embodiment of the present application, data in a portion of the memory space that is in the application direct access mode can be directly read by the CPU and no longer needs to be pre-loaded in the first-level cache space. If the second-level cache space loses power and then powers on again, after powering on again, application recovery can be performed based on the fourth cache page data in the portion of the memory space in the second-level cache space that is in the application direct access mode. The restored application corresponds to the fourth cache page data. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether neither the first-level cache space nor the second-level cache space contains the target data.

[0120] In an embodiment of the present application, by copying the cache page data with a read frequency greater than or equal to the preset frequency in the least frequently used cache page linked list to the partial memory space in the secondary cache space that is in the application direct access mode, after the secondary cache space is powered off and powered on again, application recovery is performed based on the fourth cache page data in the partial memory space in the secondary cache space that is in the application direct access mode, and the cache page data that meets the conditions can be copied to the memory space in the secondary cache space that is in the application direct access mode, so as to facilitate the user to quickly load the cache page data after power failure and restart, which can improve the convenience and availability of the secondary cache space to a certain extent.

[0121] Based on the above implementation, Figure 3 , Figure 3 A flowchart of a method for dynamically adjusting the length of a least recently used cache page linked list and the length of a least frequently used cache page linked list provided in an embodiment of the present application. After step 203, the method may further include:

[0122] Step 301 : determining a first hit rate of the least recently used cache page linked list and a second hit rate of the least frequently used cache page linked list.

[0123] In an embodiment of the present application, the ratio between the number of times data in the least recently used cache page linked list is hit and the total amount of data in the linked list can be used as the first hit rate of the least recently used cache page linked list. The ratio between the number of times data in the least frequently used cache page linked list is hit and the total amount of data in the linked list can be used as the second hit rate of the least frequently used cache page linked list. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether both the first-level cache space and the second-level cache space do not contain the target data.

[0124] Step 302: when the first hit rate is greater than the second hit rate, increase the length of the least recently used cache page linked list according to a preset ratio.

[0125] In an embodiment of the present application, the ratio of the increase in the length of the linked list can be set. When the first hit rate is greater than the second hit rate, the length of the least recently used cache page linked list can be increased according to a preset ratio. For example, if the original length of the least recently used cache page linked list is 100 and the preset ratio is 10%, the length of the least recently used cache page linked list can be increased to 110. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether the first-level cache space and the second-level cache space do not contain the target data.

[0126] Step 303: when the first hit rate is less than the second hit rate, increase the length of the least frequently used cache page linked list according to the preset ratio.

[0127] In an embodiment of the present application, if the first hit rate is less than the second hit rate, the length of the least frequently used cache page linked list can be increased according to a preset ratio. For example, if the original length of the least frequently used cache page linked list is 100 and the preset ratio is 10%, the length of the least frequently used cache page linked list can be increased to 110. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data, or whether the first-level cache space and the second-level cache space do not contain the target data.

[0128] Step 304: When the first hit rate is equal to the second hit rate, the length of the least recently used cache page linked list and the length of the least frequently used cache page linked list are maintained unchanged.

[0129] In an embodiment of the present application, if the first hit rate is equal to the second hit rate, the length of the least recently used cache page linked list and the length of the least frequently used cache page linked list can be maintained unchanged. It should be noted that this step can be implemented regardless of whether the first-level cache space or the second-level cache space contains the target data or whether the first-level cache space and the second-level cache space do not contain the target data.

[0130] In an embodiment of the present application, by determining a first hit rate of the least recently used cache page linked list and a second hit rate of the least frequently used cache page linked list, when the first hit rate is greater than the second hit rate, the length of the least recently used cache page linked list is increased according to a preset ratio; when the first hit rate is less than the second hit rate, the length of the least frequently used cache page linked list is increased according to the preset ratio; when the first hit rate is equal to the second hit rate, the length of the least recently used cache page linked list and the length of the least frequently used cache page linked list are maintained unchanged; when the first hit rate of the least recently used cache page linked list is not equal to the second hit rate of the least frequently used cache page linked list, the length of the least recently used cache page linked list or the length of the least frequently used cache page linked list can be dynamically adjusted, so that the data in the first-level cache space can be more in line with the user's usage habits, and the cache hit rate of the first-level cache space and the utilization of the cache space can be improved to a certain extent.

[0131] Reference Figure 4 , Figure 4 A logical block diagram of a cache operation device provided in an embodiment of the present application is applied to an electronic device, wherein the electronic device includes a primary cache space and a secondary cache space, wherein the secondary cache space is a persistent memory, and the device 400 may include:

[0132] A query module 401, configured to query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space in response to the target read instruction;

[0133] The transfer module 402 is used for transferring, when the target data is not included in the first-level cache space and the second-level cache space, first cache page data that is at the end and does not contain a lock mark from the least recently used cache page linked list of the first-level cache space to the second-level cache space, or transferring second cache page data that is at the end and does not contain a lock mark from the least frequently used cache page linked list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page linked list are arranged in order from short to long according to the length of time when they are not hit; and the cache page data in the least frequently used cache page linked list are arranged in order from large to small according to the reading frequency;

[0134] The reading module 403 is used to read the target data into the first-level cache space from the target external memory space corresponding to the first-level cache space based on the target reading instruction.

[0135] Optionally, the device 400 further includes:

[0136] a locking module, configured to, in response to a target locking instruction, add a locking mark to the third cache page data corresponding to the target locking instruction in the least recently used cache page linked list and / or the least frequently used cache page linked list, so as to lock the third cache page data and obtain the locked third cache page data;

[0137] The clearing module is used for clearing the locked third cache page data from the first-level cache space in response to receiving a target clearing instruction corresponding to the locked third cache page data.

[0138] Optionally, the device 400 further includes:

[0139] a first unlocking module, configured to, when the missed time length of the locked third cache page data is greater than or equal to a first preset time length, delete a locking mark of the locked third cache page data, so as to unlock the locked third cache page data and obtain the third cache page data;

[0140] The second unlocking module is used to delete the locking mark of the locked third cache page data within a second preset time period and when the access rate of the locked third cache page is less than the first threshold, so as to unlock the locked third cache page data and obtain the third cache page data.

[0141] Optionally, the transfer module 402 includes:

[0142] Creating a submodule, used for creating a cache data sorting thread and a write operation processing thread when the target read instruction is a sequential read instruction and the data amount of the first cache page data is greater than or equal to a first threshold;

[0143] A first transfer submodule, configured to transfer the first cache page data to a plurality of data block storage spaces of 64 megabytes in size based on the cache data sorting thread;

[0144] The second transfer submodule is used to transfer the first cache page data in the data block storage space to the secondary cache space based on the write operation processing thread.

[0145] Optionally, the device 400 further includes:

[0146] A first determining module, configured to determine a first linked list where the target data is located when the first-level cache space contains the target data;

[0147] The adjustment module is used to adjust the target data to the first position of the least recently used cache page linked list when the first linked list is the least recently used cache page linked list.

[0148] Optionally, the device 400 further includes:

[0149] A frequency updating module, configured to, when the first linked list is the least frequently used cache page linked list, increase the read frequency of the target data by one to update the read frequency of the target data and obtain an updated read frequency;

[0150] The second determination module is used to re-determine the position of the target data in the least frequently used cache page linked list based on the updated reading frequency.

[0151] Optionally, the device 400 further includes:

[0152] A third determination module, used to determine a first hit rate of the least recently used cache page linked list and a second hit rate of the least frequently used cache page linked list;

[0153] A first increasing module, configured to increase the length of the least recently used cache page linked list according to a preset ratio when the first hit rate is greater than the second hit rate;

[0154] A second increasing module, configured to increase the length of the least frequently used cache page linked list according to the preset ratio when the first hit rate is less than the second hit rate;

[0155] A maintaining module is used to maintain the length of the least recently used cache page linked list and the length of the least frequently used cache page linked list unchanged when the first hit rate is equal to the second hit rate.

[0156] Optionally, part of the memory space of the secondary cache space is in application direct access mode, and the remaining memory space of the secondary cache space is in memory mode, and the device 400 further includes:

[0157] A copy module, used for copying the fourth cache page data with a reading frequency greater than or equal to a preset frequency in the least frequently used cache page linked list to a part of the memory space in the secondary cache space in the application direct access mode;

[0158] The recovery module is used to perform application recovery based on the fourth cache page data in the partial memory space in the secondary cache space that is in the application direct access mode after the secondary cache space is powered off and powered on again.

[0159] The cache operation device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a GPUBOX, a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0160] The cache operation device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, a Linux operating system, a Windows operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0161] The cache operation device provided in the embodiment of the present application can achieve Figures 1 to 3 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0162] The present application embodiment provides an electronic device, see Figure 5 The electronic device 50 includes: a processor 501, a memory 502, and a computer program 5021 stored in the memory 502 and executable on the processor 501. When the processor 501 executes the program, the cache operation method of the aforementioned embodiment is implemented.

[0163] The embodiment of the present application also provides a computer program product. When the computer program product is run on an electronic device, the processor is enabled to implement the steps in the cache operation method disclosed in the embodiment of the present application.

[0164] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0165] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, apparatuses, electronic devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0166] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0167] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0168] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0169] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0170] The above is a detailed introduction to a cache operation method provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A cache operation method, characterized in that: Applied to an electronic device, the electronic device includes a primary cache space and a secondary cache space, the secondary cache space is a persistent memory, and the method includes: In response to a target read instruction, querying the first-level cache space and the second-level cache space for target data corresponding to the target read instruction; In the case that the target data is not included in the first-level cache space and the second-level cache space, the first cache page data at the last position and not including the lock mark is transferred from the least recently used cache page linked list of the first-level cache space to the second-level cache space, and the second cache page data at the last position and not including the lock mark is transferred from the least frequently used cache page linked list of the first-level cache space to the second-level cache space; wherein the cache page data in the least recently used cache page linked list are arranged in order of the length of time of not being hit from short to long; and the cache page data in the least frequently used cache page linked list are arranged in order of the read frequency from large to small; Based on the target read instruction, the target data is read into the first-level cache space from the target external memory space corresponding to the first-level cache space.

2. The method according to claim 1, characterized in that: The method further comprises: In a case where the target data is included in the first-level cache space, determining a first linked list where the target data is located; In the case where the first linked list is the least recently used cache page linked list, the target data is adjusted to the first position of the least recently used cache page linked list.

3. The method according to claim 2, characterized in that The method further comprises: In a case where the first linked list is the least frequently used cache page linked list, adding one to the read frequency of the target data to update the read frequency of the target data to obtain an updated read frequency; Based on the updated read frequency, the position of the target data in the least frequently used cache page linked list is re-determined.

4. The method according to claim 1 or 2, characterized in that: The method further comprises: In response to the target locking instruction, in the least recently used cache page linked list and / or the least frequently used cache page linked list, a locking mark is added to the third cache page data corresponding to the target locking instruction, so as to lock the third cache page data and obtain the locked third cache page data; When a target clearing instruction corresponding to the locked third cache page data is received, the locked third cache page data is cleared from the first-level cache space in response to the target clearing instruction.

5. The method according to claim 4, characterized in that The method further comprises: When the missed time length of the locked third cache page data is greater than or equal to the first preset time length, and the locked third cache page data exists in the least recently used cache page linked list, unlocking the locked third cache page data to obtain the third cache page data; Within a second preset time period, when the access rate of the locked third cache page data is less than a first threshold and the locked third cache page data exists in the least frequently used cache page linked list, the locked third cache page data is unlocked to obtain the third cache page data.

6. The method according to claim 1, characterized in that The transferring of the first cache page data which is at the last position and does not contain a lock mark from the least recently used cache page linked list of the first-level cache space to the second-level cache space includes: When the target read instruction is a sequential read instruction and the data volume of the first cache page data is greater than or equal to a first threshold, creating a cache data sorting thread and a write operation processing thread; Based on the cache data sorting thread, transferring the first cache page data to a plurality of data block storage spaces of 64 megabytes in size; Based on the write operation processing thread, the first cache page data in the data block storage space is transferred to the secondary cache space.

7. The method according to claim 1 or 2, characterized in that: The method further comprises: Determine a first hit rate of the least recently used cache page linked list and a second hit rate of the least frequently used cache page linked list; When the first hit rate is greater than the second hit rate, increasing the length of the least recently used cache page linked list according to a preset ratio; When the first hit rate is less than the second hit rate, increasing the length of the least frequently used cache page linked list according to the preset ratio; When the first hit rate is equal to the second hit rate, the length of the least recently used cache page linked list and the length of the least frequently used cache page linked list are maintained unchanged.

8. The method according to claim 1 or 2, characterized in that: Part of the memory space of the secondary cache space is in application direct access mode, and the remaining memory space of the secondary cache space is in memory mode, and the method further includes: Copying the fourth cache page data whose reading frequency is greater than or equal to the preset frequency in the least frequently used cache page linked list to the secondary cache space, to a portion of the memory space in the application direct access mode; After the secondary cache space is powered off and powered on again, application recovery is performed based on the fourth cache page data in the portion of the memory space in the secondary cache space that is in the application direct access mode.

9. A cache operation device, characterized in that: Applied to an electronic device, the electronic device includes a primary cache space and a secondary cache space, the secondary cache space is a persistent memory, and the device includes: A query module, configured to query the target data corresponding to the target read instruction in the first-level cache space and the second-level cache space in response to the target read instruction; A transfer module, configured to transfer, when the target data is not contained in the first-level cache space and the second-level cache space, a first cache page data which is at the end and does not contain a lock mark from a least recently used cache page linked list of the first-level cache space to the second-level cache space, or to transfer, from a least frequently used cache page linked list of the first-level cache space, a second cache page data which is at the end and does not contain a lock mark to the second-level cache space; wherein the cache page data in the least recently used cache page linked list are arranged in order of a short to a long time of not being hit; and the cache page data in the least frequently used cache page linked list are arranged in order of a large to a small reading frequency; A reading module is used to read the target data into the first-level cache space from the target external memory space corresponding to the first-level cache space based on the target reading instruction.

10. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the cache operation method according to any one of claims 1 to 8.

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