A multi-core processor system

Abstract

The present invention discloses a multi-core processor system. The system includes a plurality of first processors, a second processor, a shared memory and a data status storage area, wherein the shared memory includes a data storage area and a data length storage area, the first processor is used to obtain a writable data block in the data storage area, and write the received data into the corresponding writable data block according to a header index, and the second processor is used to obtain a readable data block in the data storage area, and read the data according to a tail index and the data length corresponding to the data block in the data length storage area. The present invention avoids problems such as data conflicts caused by multiple processors accessing the shared memory at the same time, and also solves the problem of system performance degradation caused by frequent interrupt switching and response in communication based on shared memory and inter-core interrupts, and data transfer is directly performed in the memory, thereby improving data transmission performance and the overall efficiency of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-core processor systems and inter-core communication methods, and in particular to a multi-core processor system. Background Art

[0002] At present, multi-core processors have become the development direction of embedded technology. Multi-core embedded processors refer to embedded processors that integrate multiple processor cores on a chip. Multiple cores can handle multiple tasks at the same time. Compared with single-core processors, they can significantly improve processing speed and performance. Multi-core processors can assign different types of tasks to different cores to achieve task isolation and improve system reliability and stability.

[0003] Currently, some high-performance series products are developed on the Xilinx SOC platform. In the AMP architecture system, each processor core runs its own independent operating system, and users must divide the hardware resources used by each operating system. Therefore, multi-core communication is a key issue facing the AMP architecture.

[0004] The most commonly used communication method in the AMP architecture is currently based on shared memory and inter-core interrupts. However, frequent interrupts will cause the processor to spend a lot of time on context switching instead of actually executing task code, affecting the overall performance of the system. When multiple interrupts occur simultaneously or frequently in a short period of time, interrupt delays will occur, which means that high-priority interrupt service routines may not be able to respond in time. For some applications with high real-time requirements, it may not meet the needs. Summary of the invention

[0005] The purpose of the present invention is to provide a multi-core processor system in view of the deficiencies in the prior art.

[0006] To achieve the above-mentioned object, the present invention provides a multi-core processor system, comprising a plurality of first processors, a second processor, a shared memory connected to the first processor and the second processor respectively, and a data status storage area, wherein the shared memory comprises a data storage area and a data length storage area, wherein the data storage area is used to store data and is allocated into a plurality of data blocks, and the writing and reading of data are operated in units of data blocks, the data length storage area is used to store the corresponding data length in the data block, the data block status storage area is used to update and maintain the status of the data storage area, two of the flag bits in the data block status storage area are used to record the reset flags of the first processor and the second processor respectively, and the remaining flag bits are used to indicate the operation attributes of the data block, and the operation attributes include readable and writable; The first processor is used to communicate with an external device, and after receiving data sent by the external device, reads the operation attribute of each data block in the data block status storage area to obtain the writable data block in the data storage area, and writes the received data into the corresponding writable data block according to the header index, and after writing the data, updates the corresponding data length in the data block in the data length storage area, and updates the flag bit corresponding to the data block where the data is written in the data block status storage area to be readable; The second processor is used to read the operation attributes of each data block in the data block status storage area to obtain the readable data block in the data storage area, and read the data according to the tail index and the data length corresponding to the data block in the data length storage area. After the data is read, the data length corresponding to the data block in the data length storage area is cleared, and the flag bit corresponding to the data block for which the data reading is completed in the data block status storage area is updated to writable.

[0007] Furthermore, the data storage area adopts a circular buffer mode, and the sizes of multiple data blocks are consistent.

[0008] Furthermore, after the first processor completes writing data and the second processor completes reading data, it respectively feeds back the data writing completion status and the data reading completion status to the data block status storage area, and the data block status storage area updates the flag bit according to the data writing completion status and the data reading completion status.

[0009] Furthermore, the system is initialized after power-on, specifically as follows: Control the data storage area and the data length storage area to point to the allocated starting address, reset the contents of the data storage area and the data length storage area, and set the head and tail indexes of the first processor and the second processor to zero respectively, then set the reset flags of the first processor and the second processor in the data block status storage area to valid, and set the remaining flag positions in the data block status storage area to writable.

[0010] Further, before the first processor reads the data block status storage area to obtain the writable data block, it first reads the reset flag corresponding to the second processor from the data block status storage area. If the reset flag corresponding to the second processor is valid, the first processor sets its corresponding head index to zero and sets the reset flag corresponding to the second processor to invalid. At the same time, before the second processor reads the data block status storage area to obtain the data block allowed to be read, it first reads the reset flag corresponding to the first processor from the data block status storage area. If the reset flag corresponding to the first processor is valid, the second processor sets its corresponding tail index to zero and sets the reset flag corresponding to the first processor to invalid. When the first processor detects that its corresponding reset flag is set to invalid, it obtains the writable data block from the data block status storage area. When the second processor detects that its corresponding reset flag is set to invalid, it obtains the read-allowed data block from the data block status storage area.

[0011] Furthermore, the two highest flag bits of the control word in the data block status storage area are used to record reset flags of the first processor and the second processor respectively.

[0012] Furthermore, when a fault occurs during data reading and writing, the system is reset as follows: The processor that has encountered a fault executes a reset to set the head / tail index corresponding to the processor that has encountered a fault to zero, and sets the flag position in the data block status storage area used to represent the operational attributes of the data block to writable. After the reset is completed, the reset flag corresponding to the processor that has encountered a fault is set to valid. After another processor detects that the reset flag corresponding to the processor that has encountered a fault is set to valid, it sets its corresponding tail / head index to zero, and then sets the reset flag of the processor that has encountered a fault to invalid.

[0013] Beneficial effects: The present invention avoids problems such as data conflicts caused by multiple processors accessing shared memory at the same time, and also solves the problem of system performance degradation caused by frequent interrupt switching and response in communication based on shared memory and inter-core interrupts. Data transfer is performed directly in the memory, which improves data transmission performance and the overall efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of a multi-core processor system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0016] like Figure 1As shown, an embodiment of the present invention provides a multi-core processor system, including a plurality of first processors 1, a second processor 2, a shared memory 3 and a data status storage area 4. The first processor 1 and the second processor 2 may be one, or one of them or more than two. The plurality of first processors 1 and the second processor 2 are respectively connected to the plurality of shared memories 3 and the data status storage area 4. The plurality of first processors 1 and the plurality of second processors 2 are respectively used as a unit, wherein one unit is used to write data to the shared memory 3, and the other unit is used to read data from the shared memory 3. The shared memory 3 may use an area in the DDR, and the number of the shared memory 3 and the data status storage area 4 is related to the number of the first processors 1 and the second processors 2, specifically the product of the number of the first processors 1 and the number of the second processors 2. Figure 1 , which illustrates an embodiment of a first processor 1 and a second processor 2, and the first processor 1 is used to write data to a shared memory 3, and the second processor 2 is used to read data from the shared memory 3. In this case, one shared memory 3 is required, and the number of data status storage areas 4 is also one. If there are two first processors 1 and two second processors 2, each first processor 1 needs to be connected to two second processors 2 through one shared memory 3, and a total of four shared memories 3 are required, and the number of data status storage areas 4 is also four, and so on.

[0017] The shared memory 3 can be divided into three parts, including a data storage area 31 and a data length storage area 32. Among them, the data storage area 31 is used to store data. The data storage area 31 is allocated into multiple data blocks. The writing and reading of data are operated in units of data blocks. Each data block is a one-way channel for the first processor 1 and the second processor 2. The first processor 1 writes data and the second processor 2 reads data. Whether the data can be read and written is determined according to the flag bit of the data storage status area 4. The data length storage area 32 is used to store the corresponding data length in the data block, and the area is updated synchronously during the read and write operations. For example, the data length stored in the 8th data block is 1024 bytes, then the address corresponding to the 8th data block in the data length storage area 32 is written with the corresponding length value 1024. The data block status storage area 4 is used to update and maintain the status of the data storage area 31. Specifically, two of the flag bits in the data block status storage area 4 are used to record the reset flags of the first processor 1 and the second processor 2, respectively. The reset flag includes two states: valid and invalid. 1 can be used to indicate valid, and 0 can be used to indicate invalid. Read and write operations can only be performed when the reset flag is in the invalid state. The two highest flag bits of the control word in the data block status storage area 4 can be used to record the reset flags of the first processor 1 and the second processor 2, respectively. The remaining flag bits are used to indicate the operation attributes of the data block. The operation attributes include readable and writable. For example, 1 is used to indicate readable, and 0 is used to indicate writable. For example, the flag bits in the data block status storage area 4 are bit0-bit31, where bit0-bit29 respectively indicate the operation attributes of 30 data blocks, bit31 is the reset flag of the first processor 1, and bit30 is the reset flag of the second processor 2.

[0018] The first processor 1 is used to communicate with an external device, and after receiving data sent by the external device, it reads the operation attributes of each data block in the data block status storage area 4 to obtain the writable data block in the data storage area 31. After obtaining the writable data block in the data storage area 31, the received data is then written into the corresponding writable data block according to the header index. After the data is written, the corresponding data length in the data block in the data length storage area 32 is updated, and the flag corresponding to the data block written in the data block status storage area 4 is updated to be readable. After the flag corresponding to the data block is updated to be readable, data can no longer be written to the data block, and data can be read from the data block. In addition, if there is no writable data block in the data storage area 31, such as all the data blocks are full, and the second processor 2 is not read out in time, it is impossible to continue to write data to the data storage area 31 at this time, and the data can only be written after the second processor 2 reads out the data. It should be noted that if there are multiple first processors 1, or the first processor 1 is to send data to multiple different second processors 2, the received data needs to be split in advance and then written into different shared memories 3 respectively.

[0019] When reading data, the second processor 2 first reads the operation attributes of each data block in the data block status storage area 4 to obtain the readable data block in the data storage area 31, and reads the corresponding data according to the tail index and the data length corresponding to the data block in the data length storage area 32. After the data is read, the data length corresponding to the data block in the data length storage area 32 is cleared, and the flag corresponding to the data block for which the data reading is completed in the data block status storage area 4 is updated to be writable. In addition, the shared memory 3 is on the DDR, so after the data is read, it is not necessary to clear the data in the data block, and the original data can be directly overwritten when writing data next time.

[0020] The data storage area 31 of the embodiment of the present invention preferably adopts a ring buffer mode, and the sizes of multiple data blocks are consistent.

[0021] In order to avoid conflicts caused by the first processor 1 and the second processor 2 operating the same memory address at the same time, the first processor 1 feeds back the data writing completion status and the data reading completion status to the third processor 5 after the data writing is completed and the second processor 2 feeds back the data writing completion status and the data reading completion status respectively, and the third processor 5 updates the flag bit in the data status storage area 4 according to the data writing completion status and the data reading completion status. That is, the data status storage area 4 is handed over to a third party for management, thereby ensuring the accuracy of the data and the stability of the system.

[0022] After power-on, the system is initialized. The system initialization mainly initializes the member variables of the data channel, including controlling the data storage area 31 and the data length storage area 32 to point to the allocated starting address (the head and tail indexes are both 0), resetting the contents of the data storage area 31 and the data length storage area 32, and setting the head and tail indexes of the first processor 1 and the second processor 2 to zero respectively, and then setting the reset flags of the first processor 1 and the second processor 2 in the data block status storage area 4 to valid, and setting the remaining flag positions in the data block status storage area 4 to writable, so as to be used interactively by the first processor 1 and the second processor 2 later. In addition, during the data reading process, the address pointed to by the data length storage area 32 changes according to the data block to be read and written. Each time data is written or read, the data length will be written to the corresponding address or read from the corresponding address according to the head and tail indexes. The head and tail indexes are shared by the data storage area 31 and the data length storage area 32, and the initial head and tail indexes are both 0. For example, data storage area 31 is allocated with 16 data blocks, and the head and tail indexes are in the range of 0-15. Each time a data block is written, the head index is increased by 1. When the 16th data block is written, the head index is 15. The next time it is written, the head index becomes 0. When reading data, the tail index is changed. Each time a data block is read, the tail index is increased by 1. When the tail index is 15, the next time it is read, the tail index is 0.

[0023] Before the first processor 1 reads the data block status storage area 4 to obtain the writable data block, it also reads the reset flag corresponding to the second processor 2 from the data block status storage area 4. If the reset flag corresponding to the second processor 2 is valid, the first processor 1 sets its corresponding head index to 0 and sets the reset flag corresponding to the second processor to invalid. At the same time, before the second processor 2 reads the data block status storage area 4 to obtain the data block allowed to be read, it first reads the reset flag corresponding to the first processor 1 from the data block status storage area 4. If the reset flag corresponding to the first processor 1 is valid, the second processor 2 sets its corresponding tail index to zero and sets the reset flag corresponding to the first processor 1 to invalid. When the first processor 1 detects that its corresponding reset flag is invalid, it obtains the writable data block from the data block status storage area 4. When the second processor 2 detects that its corresponding reset flag is invalid, it obtains the data block allowed to be read from the data block status storage area 4.

[0024] When a fault occurs during data reading and writing, the system is reset as follows: The processor that encounters a fault executes a reset to set the head / tail index corresponding to the processor that encounters the fault to zero. Specifically, if the first processor 1 encounters a fault, the head index corresponding to the first processor 1 is set to zero. If the second processor 2 encounters a fault, the tail index corresponding to the second processor 2 is set to zero. The flag position used to represent the operation attribute of the data block in the data block status storage area 4 is set to writable, and then the reset flag corresponding to the processor that encounters the fault is set to valid. After another processor detects that the reset flag corresponding to the processor that encounters the fault is set to valid, it sets its corresponding tail / head index to zero, and then sets the reset flag of the processor that encounters the fault to invalid. At this time, the reset flags corresponding to the first processor 1 and the second processor 2 are both invalid, and data writing and reading operations can be performed.

[0025] The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, other parts not specifically described belong to the prior art or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A multi-core processor system, characterized in that: The invention comprises a plurality of first processors, a second processor, a shared memory connected to the first processor and the second processor respectively, and a data status storage area, wherein the shared memory comprises a data storage area and a data length storage area, wherein the data storage area is used to store data and is allocated into a plurality of data blocks, and the writing and reading of data are operated in units of data blocks, the data length storage area is used to store the corresponding data length in the data block, the data block status storage area is used to update and maintain the status of the data storage area, two flag bits of the data block status storage area are used to record the reset flags of the first processor and the second processor respectively, and the remaining flag bits are used to indicate the operation attributes of the data block, and the operation attributes include readable and writable; The first processor is used to communicate with an external device, and after receiving data sent by the external device, reads the operation attribute of each data block in the data block status storage area to obtain the writable data block in the data storage area, and writes the received data into the corresponding writable data block according to the header index, and after writing the data, updates the corresponding data length in the data block in the data length storage area, and updates the flag bit corresponding to the data block where the data is written in the data block status storage area to be readable; The second processor is used to read the operation attributes of each data block in the data block status storage area to obtain the readable data block in the data storage area, and read the data according to the tail index and the data length corresponding to the data block in the data length storage area. After the data is read, the data length corresponding to the data block in the data length storage area is cleared, and the flag bit corresponding to the data block for which the data reading is completed in the data block status storage area is updated to writable.

2. A multi-core processor system according to claim 1, characterized in that: The data storage area adopts a circular buffer mode, and the sizes of multiple data blocks are consistent.

3. The multi-core processor system according to claim 1, characterized in that: After the first processor completes writing data and the second processor completes reading data, it feeds back the data writing completion status and the data reading completion status to the third processor respectively, and the third processor updates the flag bit in the data status storage area according to the data writing completion status and the data reading completion status.

4. The multi-core processor system according to claim 1, characterized in that: After power-on, the system is initialized as follows: Control the data storage area and the data length storage area to point to the allocated starting address, reset the contents of the data storage area and the data length storage area, and set the head and tail indexes of the first processor and the second processor to zero respectively, then set the reset flags of the first processor and the second processor in the data block status storage area to valid, and set the remaining flag positions in the data block status storage area to writable.

5. A multi-core processor system according to claim 4, characterized in that: Before the first processor reads the data block status storage area to obtain the writable data block, it first reads the reset flag corresponding to the second processor from the data block status storage area. If the reset flag corresponding to the second processor is valid, the first processor sets its corresponding head index to zero and sets the reset flag corresponding to the second processor to invalid. At the same time, before the second processor reads the data block status storage area to obtain the data block allowed to be read, it first reads the reset flag corresponding to the first processor from the data block status storage area. If the reset flag corresponding to the first processor is valid, the second processor sets its corresponding tail index to zero and sets the reset flag corresponding to the first processor to invalid. When the first processor detects that its corresponding reset flag is set to invalid, it obtains the writable data block from the data block status storage area. When the second processor detects that its corresponding reset flag is set to invalid, it obtains the read-allowed data block from the data block status storage area.

6. The multi-core processor system according to claim 1, characterized in that: The two highest flag bits of the control word in the data block status storage area are used to record the reset flags of the first processor and the second processor respectively.

7. The multi-core processor system according to claim 1, characterized in that: When a fault occurs during data reading and writing, the system is reset as follows: The processor that has encountered a fault executes a reset to set the head / tail index corresponding to the processor that has encountered a fault to zero, and sets the flag position in the data block status storage area used to represent the operational attributes of the data block to writable. After the reset is completed, the reset flag corresponding to the processor that has encountered a fault is set to valid. After another processor detects that the reset flag corresponding to the processor that has encountered a fault is set to valid, it sets its corresponding tail / head index to zero, and then sets the reset flag of the processor that has encountered a fault to invalid.

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