Method, device, chip and electronic equipment for receiving and sending integrated service digital network (SDNN) data

Abstract

The invention provides a method for receiving and sending integrated service digital network data by using an SPI (Serial Peripheral Interface). The receiving method comprises the following steps: configuring an SPIMOSI pin to be in a GPIO input state or a high-resistance state, configuring an SPIMISO pin to be in a GPIO input state, and detecting edge interruption; waiting for receiving edge interruption, and after the edge interruption is received, configuring the SPIMISO pin to have an SPI function; the DMA module is configured, specifically, the DMA module is configured to transmit data received by the SPI module to a memory, and DMA transmission is started; the SPI module is configured, specifically, the SPI module is configured to be in a receiving mode, and SPI transmission is started; waiting for receiving completion interruption of the DMA module; and analyzing the data received by the SPI module in the memory. According to the invention, less CPU resources are occupied, and the data accuracy is improved.

Description

Technical Field

[0001] The present invention relates to the field of signal transmission technology, and in particular to a method, device, chip, electronic equipment, communication system and storage medium for realizing one-line data reception and transmission by using SPI. Background Art

[0002] Single interface frame (SIF) is a communication protocol widely used in electric two-wheeled vehicles for communication between controllers, lithium batteries, and chargers. SIF physically only requires one signal wire to achieve data transmission. The transmitted data consists of communication frames, and each frame of data consists of three parts: synchronization signal, main message signal, and stop signal. The definition of the frame format can be referred to the "Electric Bicycle Communication Protocol Group Standard T / JSEBA 002-2022".

[0003] At present, the common implementation method of One-line communication is that the software uses timer interrupt plus GPIO (General-purpose input / output, general input / output interface) to receive or send One-line communication protocol data, and GPIO data needs to be processed in each timer interrupt. Taking the timer with a period of Ttimer = 200us as an example, the timing diagram corresponding to the timer interrupt and the signal is as follows Figure 1 shown.

[0004] The timer interrupt plus GPIO method to achieve one-line communication has the following main problems: Since the GPIO status needs to be sampled regularly, there will be a lot of timer interrupts during the transmission process, which will occupy a lot of CPU and affect the operation of other tasks in the system.

[0005] Since GPIO status processing and signal conversion are completed in the interrupt function, the system real-time requirements are relatively high. When the CPU load is heavy, if there is no time to respond to the interrupt, the calculated signal duty cycle may be inaccurate, resulting in misjudgment. Summary of the invention

[0006] In view of this, the present invention provides a method, device, chip, electronic device, communication system and storage medium for realizing one-line data reception and transmission using SPI (Serial Peripheral Interface), which can occupy less CPU resources and improve data accuracy.

[0007] In a first aspect, the present invention provides a method for implementing one-line data reception using SPI, the method comprising: Configure the SPI_MOSI pin as GPIO input or high-impedance state, configure the SPI_MISO pin as GPIO input, and detect edge interrupts; Waiting for an edge interrupt generated by receiving GPIO, after receiving the edge interrupt, configuring the SPI_MISO pin as the SPI function; Configuring the DMA module includes: configuring the DMA module to transfer the data received by the SPI module to the memory, and starting the DMA transmission; Configuring the SPI module includes: configuring the SPI module to a receiving mode and starting SPI transmission; Waiting for receiving the receiving completion interrupt generated by the DMA module; After receiving the reception completion interrupt, the data received by the SPI module in the memory is parsed.

[0008] Optionally, configuring the SPI module further includes: setting the SPI clock, and receiving data at a rising edge of the SPI clock.

[0009] In a second aspect, the present invention provides a method for implementing one-line data transmission using SPI, the method comprising: Convert the one-line protocol data to be sent into the data to be sent by the SPI module and store it in the memory; Configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to high impedance and configure the SPI_MOSI pin as an SPI function; Configuring the DMA module includes: configuring the DMA module to transfer the data in the memory to the SPI module and starting the DMA transmission; Configuring the SPI module includes: configuring the SPI module to a transmission mode and starting SPI transmission; Wait for receiving the sending completion interrupt generated by the DMA module.

[0010] Optionally, configuring the SPI module further includes: setting the SPI clock and sending data at the falling edge of the SPI clock.

[0011] In a third aspect, the present invention provides a device for implementing one-line data reception using SPI, the device comprising: A first SPI pin configuration unit, configured to configure the SPI_MOSI pin as a GPIO input or a high impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts; An edge interrupt processing unit, used for waiting for an edge interrupt generated by a receiving GPIO, and after receiving the edge interrupt, configuring the SPI_MISO pin as an SPI function; A first DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to the memory, and starting the DMA transmission; A first SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to a receiving mode and starting SPI transmission; A first interrupt unit, used for waiting for receiving a receiving completion interrupt generated by the DMA module; The first signal conversion unit is used to parse the data received by the SPI module in the memory after receiving the reception completion interrupt.

[0012] In a fourth aspect, the present invention provides a device for implementing one-line data transmission using SPI, the device comprising: The second signal conversion unit is used to convert the one-line protocol data to be sent into the data to be sent by the SPI module and store it in the memory; The second SPI pin configuration unit is used to configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to a high impedance state and configure the SPI_MOSI pin as an SPI function; A second DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer the data in the memory to the SPI module, and starting the DMA transmission; The second SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to a transmission mode and starting SPI transmission; The second interrupt unit is used for waiting to receive the sending completion interrupt generated by the DMA module.

[0013] In a fifth aspect, the present invention provides a chip, comprising: SPI module, wherein the SPI_MISO pin of the SPI module has a function of being multiplexed as a GPIO; DMA module; Memory; A memory and a processor, wherein the memory is used to store a computer program, and the processor is used to execute the computer program to implement the method for receiving data via one-line using SPI as described in the first aspect, and / or the method for sending data via one-line using SPI as described in the second aspect.

[0014] In a sixth aspect, the present invention provides an electronic device, comprising the chip as described in the fifth aspect.

[0015] In a seventh aspect, the present invention provides a one-line communication system, comprising the electronic device as described in the sixth aspect.

[0016] In an eighth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for receiving one-line data using SPI as described in the first aspect and / or the method for sending one-line data using SPI as described in the second aspect are implemented.

[0017] The method, device, chip, electronic device, communication system and storage medium for realizing one-line data reception and transmission using SPI provided by the present invention realize the reception / transmission of one-line protocol data using SPI, and the data reception / transmission is completed by the SPI module and the DMA module, and does not occupy CPU resources. During this period, the CPU can be used for other tasks. The SPI module receives / transmits data at a fixed frequency, and the reception / transmission process will not be interrupted. The signal waveform is relatively accurate, and there is no problem of inaccurate signal duty cycle. In addition, SPI is a serial high-speed bus, and the operating frequency can be set according to the accuracy requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A signal timing diagram for realizing one-line communication with a timer solution in the prior art; Figure 2 A schematic flow chart of a method for implementing one-line data reception using SPI in one embodiment of the present invention; Figure 3 A schematic flow chart of a method for implementing one-line data transmission using SPI in one embodiment of the present invention; Figure 4 A signal timing diagram of a SPI solution implementing a one-line connection in one embodiment of the present invention; Figure 5 A schematic diagram of a device for implementing one-line data reception using SPI in one embodiment of the present invention; Figure 6 A schematic diagram of a device for implementing one-line data transmission using SPI in one embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a chip in one embodiment of the present invention; Figure 8 FIG. 1 is a schematic diagram of the structure of a one-line communication system in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0022] First of all, this application carefully studies the signal characteristics of the one-line protocol, utilizes the GPIO level detection function, and combines the working principle of SPI (Serial Peripheral interface) to design a solution for using the SPI module to receive or send one-line protocol data. Data is directly transmitted through DMA (Direct Memory Access) to reduce CPU usage. The solution is based on a chip (including but not limited to MCU) with an SPI module and the SPI_MISO pin has a GPIO (General Purpose Input Output) function. In the hardware of this solution, only two pins, SPI_MISO (pin for receiving data) and SPI_MOSI (pin for sending data) are used on the chip side. The two signal lines led out of these two pins are connected together and connected to the one-line device at the other end.

[0023] The embodiment of the present invention proposes a method for implementing one-line data reception using SPI, such as Figure 2 As shown, the method comprises the following steps: S201, configure the SPI_MOSI pin as a GPIO input or a high-impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interruption, wherein two signal lines derived from the SPI_MISO pin and the SPI_MOSI pin are connected together and connected to a one-line device at the opposite end; S202, waiting for an edge interrupt generated by receiving GPIO, and after receiving the edge interrupt, configuring the SPI_MISO pin as the SPI function; S203, configuring the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to the memory, and starting the DMA transmission; S204, configuring the SPI module, including: configuring the SPI module to a receiving mode, and starting SPI transmission; S205, waiting for the receiving completion interrupt generated by the receiving DMA module; S206, after receiving the reception completion interrupt, parsing the data received by the SPI module in the memory.

[0024] Among them, in step S201, the SPI_MOSI pin is configured as a GPIO input or a high-impedance state. The high-impedance state is a state where both the input and the output are closed, which can meet the requirements.

[0025] Further, in step S203, the DMA module is configured, including: configuring the DMA module to transfer the data in the SPI module receiving buffer to the software receiving buffer (memory), setting the DMA transmission data length, and starting the DMA transmission.

[0026] In step S204, the SPI module is configured, including: configuring the SPI module to a receiving mode, setting the SPI clock, receiving data at a rising edge of the SPI clock, setting a received data length, and starting SPI transmission.

[0027] The process of receiving data is as follows: the SPI module receives the data sent by the opposite line communication device and transfers it to the memory through DMA. After the SPI data reception is completed and the DMA data transmission is completed, the DMA module generates a reception completion interrupt and informs the CPU through system events to prepare to process the data.

[0028] In step S206, the CPU parses the data (also referred to as sampled data) received by the SPI module according to the following method. The parsing process includes: Step 1: Enter the synchronization signal analysis stage; Step 2: Read the sampled data and record the number of bits with a value of 0, marked as a, until the bit value becomes 1. Combined with the SPI clock cycle Tclk, convert a into the low level time Ta; Step 3: Read the sampled data and record the number of bits with a value of 1, recorded as b, until the bit value becomes 0. Combined with the SPI clock cycle Tclk, b is converted into a high level time Tb; Step 4: Remove the read bits from the sampled data; Step 5: Determine whether Ta and Tb meet the low level and high level time of the synchronization signal; Step 6: Enter the main message parsing stage; Step 7: Perform the same actions as step 2, read the sampled data, record the number of bits with a value of 0, and record it as a, until the bit value becomes 1. Combined with the SPI clock cycle Tclk, convert a into a low level time Ta; Step 8: Determine whether Ta is less than the maximum low level time of the data bit; Step 9: Perform the same actions as step 3, read the sampled data, record the number of bits with a value of 1, record it as b, until the bit value becomes 0, and convert b into a high level time Tb in combination with the SPI clock cycle Tclk; Step 10: Perform the same actions as step 4 and remove the read bits from the sampled data; Step 11: According to the duty cycle of the low level and high level of the data bit of the main message signal, convert Ta and Tb into data bit "0" or data bit "1"; Step 12: Return to step 7 and repeat steps 7-11 until step 8 detects that the Ta value is greater than the maximum low level time of the data bit, and then jump to step 13; Step 13: Enter the stop signal analysis stage; Step 14: Read the sampled data and record the number of bits with a value of 0, marked as a, until the bit value becomes 1. Combined with the SPI clock cycle Tclk, convert a into a low-level time Ta; determine whether Ta meets the low-level time of the stop signal; Step 15: Read the sampled data and record the number of bits with a value of 1, recorded as b, until the bit value becomes 0. Combined with the SPI clock cycle Tclk, convert b into a high-level time Tb, and determine that Tb meets the high-level time of the stop signal; Step 16: The stop signal is valid and the analysis is completed.

[0029] The above method is described by taking receiving a frame of data as an example. In order to maintain the continuity of the received data, after executing step S205, return to step S201, configure the SPI_MISO pin as GPIO input again, and detect edge interruption.

[0030] The method for realizing one-line data reception using SPI provided by the embodiment of the present invention realizes the reception of one-line protocol data using GPIO and SPI, and the GPIO level detection multiplexes the SPI_MISO pin, and the data reception is completed by the SPI module and the DMA module, and does not occupy CPU resources. During this period, the CPU can be used for other tasks. The SPI module receives data at a fixed frequency, and the receiving process will not be interrupted. The signal waveform is relatively accurate, and there is no problem of inaccurate signal duty cycle. In addition, SPI is a serial high-speed bus, and the operating frequency can be set according to the accuracy requirements.

[0031] Another embodiment of the present invention provides a method for implementing one-line data transmission using SPI, such as Figure 3 As shown, the method comprises the following steps: S301, converting the one-line protocol data to be sent into the data to be sent by the SPI module and storing it in the memory; S302, configure the SPI_MISO pin as a GPIO input and disable interruption, or configure it as a high impedance state, and configure the SPI_MOSI pin as an SPI function, wherein two signal lines derived from the SPI_MISO pin and the SPI_MOSI pin are connected together and connected to a one-line device at the opposite end; S303, configuring the DMA module, including: configuring the DMA module to transfer the data in the memory to the SPI module, and starting the DMA transmission; S304, configuring the SPI module, including: configuring the SPI module to a sending mode, and starting SPI transmission; S305, waiting for the sending completion interrupt generated by the receiving DMA module.

[0032] Furthermore, in step S301, the synchronization signal, main message signal and stop signal to be sent are converted bit by bit into data to be sent by the SPI module and stored in the memory.

[0033] The conversion process can be carried out in the following steps: Step 1: Enter the synchronization signal conversion stage; Step 2: Combined with the SPI clock cycle, convert the signal low level time into the number of bits with a value of 0, and set it to the SPI send buffer bit by bit; Step 3: Combined with the SPI clock cycle, convert the signal high level time into the number of bits with a value of 1, and set it to the SPI send buffer bit by bit; Step 4: After the synchronization signal conversion is completed, the main message signal conversion phase begins; Step 5: Read the data to be sent, and convert the main message signal according to the method of steps 2 and 3 according to whether the data bit is "0" or "1"; Step 6: Repeat step 5 until all the data to be sent are converted; Step 7: Enter the stop signal conversion stage; Step 8: Convert the stop signal according to the method of steps 2 and 3.

[0034] In step S303, the DMA module is configured, including: configuring the DMA module to transfer the data in the software send buffer (memory) to the SPI module send buffer, setting the DMA transfer data length, and starting the DMA transfer.

[0035] In step S304, the SPI module is configured, including: configuring the SPI module to a transmission mode, setting the SPI clock, transmitting data at a falling edge of the SPI clock, setting a transmission data length, and starting SPI transmission.

[0036] The process of sending data is as follows: the DMA module transfers the one-line protocol data to be sent in the memory to the SPI module, and the SPI module sends the data to the one-line device at the other end. When the DMA data transmission is completed and the SPI data transmission is completed, the DMA module generates a transmission completion interrupt and informs the CPU through a system event that the data transmission is completed.

[0037] The above method is explained by taking the sending of one frame of data as an example. One frame of data is sent at a time. After the data is sent, in order to facilitate the reception of the next frame of data, the SPI_MOSI pin is configured as a GPIO input or high-impedance state, the SPI_MISO pin is configured as a GPIO input, and edge interrupts are detected.

[0038] The method for implementing one-line data transmission using SPI provided in an embodiment of the present invention implements the transmission of one-line protocol data using SPI, and the data transmission is completed by the SPI module and the DMA module, and does not occupy CPU resources. During this period, the CPU can be used for other tasks. The SPI module sends data at a fixed frequency, and the transmission process will not be interrupted. The signal waveform is relatively accurate, and there is no problem of inaccurate signal duty cycle. In addition, SPI is a serial high-speed bus, and the operating frequency can be set according to the accuracy requirements.

[0039] Taking the SPI clock setting as 5KHz (Tclk=200us) as an example, the timing diagram corresponding to the clock waveform and signal is as follows: Figure 4 As shown, the SPI module receives data on the rising edge of the SPI clock and sends data on the falling edge of the SPI clock.

[0040] On the other hand, an embodiment of the present invention provides a device for receiving data via a single line using SPI, such as Figure 5 As shown, the device comprises: A first SPI pin configuration unit 501, configured to configure the SPI_MOSI pin as a GPIO input or a high impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts; The edge interrupt processing unit 502 is used to wait for an edge interrupt generated by a GPIO, and after receiving the edge interrupt, configure the SPI_MISO pin as an SPI function; The first DMA configuration unit 503 is used to configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to the memory, and starting the DMA transmission; The first SPI configuration unit 504 is used to configure the SPI module, including: configuring the SPI module to a receiving mode and starting SPI transmission; The first interrupt unit 505 is used to wait for a receiving completion interrupt generated by a receiving DMA module; The first signal conversion unit 506 is used to parse the data received by the SPI module in the memory after receiving the reception completion interrupt.

[0041] It can be understood that the device for implementing one-line data reception using SPI provided in the embodiment of the present invention is used to implement the above-mentioned one-line data reception method embodiment.

[0042] On the other hand, an embodiment of the present invention provides a device for implementing one-line data transmission using SPI, such as Figure 6 As shown, the device comprises: The second signal conversion unit 601 is used to convert the one-line protocol data to be sent into the data to be sent by the SPI module and store it in the memory; A second SPI pin configuration unit 602, configured to configure the SPI_MISO pin as a GPIO input and disable interruption, or to configure it to a high impedance state and configure the SPI_MOSI pin as an SPI function; The second DMA configuration unit 603 is used to configure the DMA module, including: configuring the DMA module to transfer the data in the memory to the SPI module and start the DMA transmission; The second SPI configuration unit 604 is used to configure the SPI module, including: configuring the SPI module to a transmission mode and starting SPI transmission; The second interrupt unit 605 is used to wait for the sending completion interrupt generated by the receiving DMA module.

[0043] It can be understood that the device for implementing one-line data transmission using SPI provided in the embodiment of the present invention is used to implement the above-mentioned one-line data transmission method embodiment.

[0044] On the other hand, an embodiment of the present invention provides a chip, such as Figure 7 As shown, the chip includes: SPI module 704, the SPI_MISO pin of the SPI module 704 has a GPIO function; DMA module 705; Memory 706; A processor 701, a memory 702, and a communication bus 703, wherein the processor 701 and the memory 702 communicate with each other via the communication bus 703. The processor 701 can execute a computer program in the memory 702 to implement the method for receiving data via SPI and / or the method for sending data via SPI provided in the above embodiments.

[0045] On the other hand, another embodiment of the present invention provides an electronic device, comprising the chip of the above embodiment.

[0046] On the other hand, another embodiment of the present invention provides a one-line communication system, the one-line communication system includes the electronic device of the above embodiment. Figure 8 As shown, the one-line device at the opposite end in the one-line communication system can be a battery, a charger and a controller. Two signal lines led out from the SPI_MISO pin and the SPI_MOSI pin of the electronic device are connected together and connected to the one-line device at the opposite end.

[0047] It should also be noted that the electronic device adopting the technical solution of the present application can be used as a host of the one-line communication, and can also be used as a slave of the one-line communication, without any special limitation.

[0048] Of course, in a one-line communication system, multiple one-line devices are also allowed to adopt the technical solution of the present application.

[0049] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for receiving one-line data using SPI and / or the method for sending one-line data using SPI provided in the above embodiments are implemented.

[0050] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0051] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for realizing one-line data reception using SPI, characterized in that: The method comprises: Configure the SPI_MOSI pin as GPIO input or high-impedance state, configure the SPI_MISO pin as GPIO input, and detect edge interrupts; Waiting for an edge interrupt generated by receiving GPIO, after receiving the edge interrupt, configuring the SPI_MISO pin as the SPI function; Configuring the DMA module includes: configuring the DMA module to transfer the data received by the SPI module to the memory, and starting the DMA transmission; Configuring the SPI module includes: configuring the SPI module to a receiving mode and starting SPI transmission; Waiting for receiving the receiving completion interrupt generated by the DMA module; After receiving the reception completion interrupt, the data received by the SPI module in the memory is parsed.

2. The method according to claim 1, characterized in that Configuring the SPI module also includes: setting the SPI clock and receiving data at the rising edge of the SPI clock.

3. A method for implementing one-line data transmission using SPI, characterized in that: The method comprises: Convert the one-line protocol data to be sent into the data to be sent by the SPI module and store it in the memory; Configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to high impedance and configure the SPI_MOSI pin as an SPI function; Configuring the DMA module includes: configuring the DMA module to transfer the data in the memory to the SPI module and starting the DMA transmission; Configuring the SPI module includes: configuring the SPI module to a transmission mode and starting SPI transmission; Wait for receiving the sending completion interrupt generated by the DMA module.

4. The method according to claim 3, characterized in that Configuring the SPI module also includes: setting the SPI clock and sending data on the falling edge of the SPI clock.

5. A device for realizing one-line data reception using SPI, characterized in that: The device comprises: A first SPI pin configuration unit, configured to configure the SPI_MOSI pin as a GPIO input or a high impedance state, configure the SPI_MISO pin as a GPIO input, and detect edge interrupts; An edge interrupt processing unit, used for waiting for an edge interrupt generated by a receiving GPIO, and after receiving the edge interrupt, configuring the SPI_MISO pin as an SPI function; A first DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer the data received by the SPI module to the memory, and starting the DMA transmission; A first SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to a receiving mode and starting SPI transmission; A first interrupt unit, used for waiting for receiving a receiving completion interrupt generated by the DMA module; The first signal conversion unit is used to parse the data received by the SPI module in the memory after receiving the reception completion interrupt.

6. A device for transmitting data via a single line using SPI, characterized in that: The device comprises: The second signal conversion unit is used to convert the one-line protocol data to be sent into the data to be sent by the SPI module and store it in the memory; The second SPI pin configuration unit is used to configure the SPI_MISO pin as a GPIO input and disable interrupts, or configure it to a high impedance state and configure the SPI_MOSI pin as an SPI function; A second DMA configuration unit is used to configure the DMA module, including: configuring the DMA module to transfer the data in the memory to the SPI module, and starting the DMA transmission; The second SPI configuration unit is used to configure the SPI module, including: configuring the SPI module to a transmission mode and starting SPI transmission; The second interrupt unit is used for waiting to receive the sending completion interrupt generated by the DMA module.

7. A chip, characterized in that: The chip comprises: SPI module, wherein the SPI_MISO pin of the SPI module has a function of being multiplexed as a GPIO; DMA module; Memory; A memory and a processor, the memory being used to store a computer program, the processor being used to execute the computer program to implement the method for receiving data via one-line using SPI as claimed in claim 1 or 2, and / or the method for sending data via one-line using SPI as claimed in claim 3 or 4.

8. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 7.

9. A one-line communication system, characterized in that: Comprising the electronic device as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, it implements the method for receiving data via one-line using SPI as claimed in claim 1 or 2, and / or the method for sending data via one-line using SPI as claimed in claim 3 or 4.

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