A Plug-in Universal DMA Module for AHB Bus

Abstract

The present invention discloses a plug-in general DMA module for the AHB bus, belonging to the field of semiconductor chip design. The present invention includes a first bus splitting unit, a second bus splitting unit, a third bus splitting unit, a bus interface unit, a bus reading unit, a DMA buffer, a bus writing unit, a first bus multiplexing unit, a second bus multiplexing unit, and a third bus multiplexing unit. The present invention can realize the insertion of the DMA function module without changing the original design, and the inserted DMA is a general DMA module, which can realize the transfer of data of any length on the AHB bus and meet the requirements of any different address alignments of the source address and the destination address on the AHB bus.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip design, and particularly to a plug-in general DMA module for the AHB bus, which can be used in the SoC design scenario in the semiconductor field, especially in the case where a DMA module needs to be inserted additionally in the later stage of design. Background Art

[0002] DMA can implement data transfer on the bus by itself, thus freeing the CPU from the data transfer task and effectively alleviating the pressure on the CPU. Therefore, it is widely used in various SoCs and accelerators. Depending on the application, the DMA module may have different bus interfaces, different bus transfer address alignment requirements, etc.

[0003] Since DMA only implements a data transfer function, in the design of a SoC for a specific function, DMA is in an auxiliary position. This results in the situation that DMA is often ignored in the initial stage of design and needs to be inserted in the later stage of design. However, how to implement data transfer from any source address to any destination address and any length by inserting DMA without changing the original design is a problem that has not been solved by the prior art. Summary of the Invention

[0004] In view of this, the present invention proposes a plug-in general DMA module for the AHB bus. The present invention can insert a DMA module without changing the original design, and the designed DMA module is a general DMA module that supports different address alignment requirements for the source address and the destination address.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A plug-in general DMA module for the AHB bus, which is used to be arranged between an accelerator and the AHB bus, so as to implement data transfer between the accelerator and other devices on the AHB bus under the control of the CPU; it includes a bus splitting unit 1, a bus splitting unit 2, a bus splitting unit 3, a bus interface unit, a bus read controller, a data buffer, a bus write controller, a bus multiplexer 1, a bus multiplexer 2, and a bus multiplexer 3;

[0007] Among them, the bus splitting unit 1 is respectively connected to the bus interface unit, the bus multiplexer 3, and the external CPU bus;

[0008] The bus interface unit is also respectively connected to the bus read controller and the bus write controller;

[0009] The data buffer is respectively connected to the bus read controller and the bus write controller;

[0010] The bus read controller is also connected to the bus splitting unit 2;

[0011] The bus write controller is also connected to the bus splitting unit 3;

[0012] The bus multiplexer 1 is respectively connected to the bus splitting unit 2, the bus splitting unit 3, and the bus multiplexer 3;

[0013] The bus multiplexer 2 is respectively connected to the bus splitting unit 2, the bus splitting unit 3, and an external accelerator;

[0014] The bus multiplexer 3 is also externally connected through a multiplexed bus.

[0015] Furthermore, the data buffer includes a circular buffer composed of a single-slot first-in first-out unit (FIFO) of D bytes. The head of the circular buffer has a write pointer, and the tail of the circular buffer has a read pointer; the data read from the bus is written into the data buffer and the write pointer is modified; when a write request is issued on the bus, the data is taken out from the data buffer and sent to the bus;

[0016] The single-slot FIFO has a data register, a data valid flag register Reg, a NOT gate, and an OR gate; the input information of the single-slot first-in first-out unit includes an input valid flag, input data, and an input ready flag, and the output information includes an output valid flag, output data, and an output ready flag. Among them, the input ready flag is generated by the output ready flag and the output valid flag through the following combinational logic:

[0017] Input ready = Output ready ||!Output valid

[0018] In the formula, || is the OR gate, and! is the NOT gate.

[0019] Furthermore, the bus splitting unit 1, the bus splitting unit 2, and the bus splitting unit 3 have the same structure and are collectively referred to as the bus splitting unit;

[0020] The bus splitting unit includes an address decoding unit and a delay and selection unit. The address decoding unit determines whether the bus enable signals of branch bus 1 and branch bus 2 - bus 1 enable and bus 2 enable - are valid according to the address ranges of the two split branch buses - bus 1 address and bus 2 address; the delay and selection unit first delays the sent valid read / write signal, and then selects the bus ready signals of the two branches - bus 1 ready, bus 2 ready - and the bus read data signals - bus 1 read data, bus 2 read data - according to the branch to which the valid read / write signal belongs. The bus 1 address and the bus 2 address are the same as the initially requested bus address.

[0021] Furthermore, the bus multiplexer 1, the bus multiplexer 2, and the bus multiplexer 3 have the same structure and are collectively referred to as the bus multiplexer;

[0022] The bus multiplexer includes an arbiter, a latch, and a delay and selection unit; the arbiter selects one from three branches of bus requests, namely the bus 1 signal, the bus 2 signal from two branch buses and the latched bus request (latched bus signal), and authorizes the downstream access; the latch latches the received but unauthorized bus request signal (rejected bus signal) in a register; the delay and selection unit delays the authorized bus signal and indicates which branch the bus ready signal and the bus read data should be sent to, that is, whether the bus ready signal and the bus read signal are sent to the bus 1 ready signal and the bus 1 read data signal or the bus 2 ready signal and the bus 2 read data signal.

[0023] Furthermore, the bus read controller includes a DMA read state machine, a synchronous FIFO unit, and a combinational logic unit; the DMA read state machine obtains control information from the bus interface unit, initiates a read request to the bus, stores the read-back data into the synchronous FIFO unit, and finally sends it to the data buffer; the size of the synchronous FIFO unit is the data volume of two time slots; the combinational logic unit is used to calculate the state of the synchronous FIFO unit and determine whether the synchronous FIFO unit is empty or is becoming empty; after the DMA read state machine initiates the first read request, only when the synchronous FIFO unit is empty or is becoming empty can it continue to initiate subsequent read requests.

[0024] Furthermore, the bus write controller includes a DMA write state machine, a single-time slot FIFO unit, a delay unit, and an AND gate; the DMA write state machine obtains control information from the bus interface unit, initiates a read data request to the data buffer through byte enable, and simultaneously initiates a write request to the bus; the single-time slot FIFO unit delays the data read back from the data buffer for one time slot; the delay unit samples and delays the valid bus write request, and after the delayed bus write request signal and the bus ready signal pass through the AND gate, they form the output ready signal of the single-time slot FIFO unit; the output data of the single-time slot FIFO is directly used as the bus write data.

[0025] Furthermore, the bus interface unit is used to convert the bus signal of one branch of the bus splitting unit 1 into register read and write signals to realize the control of the bus read controller and the bus write controller.

[0026] The beneficial effects of the present invention are as follows:

[0027] 1) Without changing the original architecture and accelerator design, it realizes zero-modification insertion into the original design.

[0028] 2) It can meet different address alignment requirements from the source address to the destination address.

[0029] 3) General applicability of the DMA function: It can achieve data transfer of any length from any address to any address.

[0030] 4) General applicability of the bus interface: The configuration bus interface of the DMA, the data read interface of the DMA, the data write interface, the interface with the CPU, and the interface with the accelerator are all standard AHB bus interfaces, which are easy to integrate. Description of the Drawings

[0031] Figure 1 is a schematic diagram of the SoC architecture without DMA;

[0032] Figure 2 is a schematic diagram of the SoC architecture after inserting DMA;

[0033] Figure 3 is the overall architecture diagram of a plug-in general DMA module for the AHB bus in an embodiment of the present invention;

[0034] Figure 4 is Figure 3 the schematic diagram of the architecture of the data buffer part in;

[0035] Figure 5 is Figure 4 the schematic diagram of the structure of the single-slot FIFO unit in;

[0036] Figure 6 is Figure 3 the schematic diagram of the structure of the bus splitting unit in;

[0037] Figure 7 is Figure 3 the schematic diagram of the structure of the bus multiplexer in;

[0038] Figure 8 is Figure 3 the schematic diagram of the structure of the bus read controller in;

[0039] Figure 9 is Figure 3 the schematic diagram of the structure of the bus write controller in. Detailed Embodiments

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0041] Figure 1 shows a situation where DMA is ignored in the initial stage of the design. In Figure 1, there are three accelerators - Accelerator 1, Accelerator 2, and Accelerator 3 - attached to a CPU bus. Accelerator 1 is an accelerator specifically designed for tasks, and Accelerator 2 and Accelerator 3 are some general accelerators or peripheral interfaces, such as an Ethernet interface, an LCD display accelerator, etc. In the later stage of the design, due to the need for data transfer in Accelerator 1, a DMA module needs to be added to achieve data transfer between Accelerator 1, Accelerator 2, Accelerator 3, and the main memory controller, that is, to achieve Figure 2 the shown effect. For this purpose, this embodiment proposes a pluggable general-purpose DMA module for the AHB bus, that is Figure 2 the DMA and bus multiplexer in

[0042] As Figure 3 shown, a pluggable general-purpose DMA module for the AHB bus includes a bus splitting unit 1, a bus splitting unit 2, a bus splitting unit 3, a bus interface unit, a bus read controller, a data buffer, a bus write controller, a bus multiplexer 1, a bus multiplexer 2, and a bus multiplexer 3;

[0043] Among them, the bus splitting unit 1 is respectively connected to the bus interface unit, the bus multiplexer 3, and the external CPU bus;

[0044] The bus interface unit is also respectively connected to the bus read controller and the bus write controller;

[0045] The data buffer is respectively connected to the bus read controller and the bus write controller;

[0046] The bus read controller is also connected to the bus splitting unit 2;

[0047] The bus write controller is also connected to the bus splitting unit 3;

[0048] The bus multiplexer 1 is respectively connected to the bus splitting unit 2, the bus splitting unit 3, and the bus multiplexer 3;

[0049] The bus multiplexer 2 is respectively connected to the bus splitting unit 2, the bus splitting unit 3, and the external accelerator;

[0050] The bus multiplexer 3 is also connected to the outside through a multiplexed bus;

[0051] Among them, the bus read controller, the data buffer, and the bus write controller constitute the core part of the DMA data transfer.

[0052] As Figure 4As shown, the data buffer includes a circular buffer composed of D-byte single-slot FIFO units. There is a write pointer at the head of the circular buffer and a read pointer at the tail of the circular buffer. The data read from the bus is written into the data buffer and the write pointer is modified. When the bus issues a write request, data is taken out from the data buffer and sent to the bus. Due to the requirement of bus address alignment, the source address for reading data and the destination address for writing data may have different read and write packet sizes. The data buffer plays a role in adjusting the sizes of the written and read packets here. For a 32-bit AHB bus, the minimum value of D here is 8, that is, at least 8 single-slot FIFO units are required.

[0053] As Figure 5 shown, the single-slot FIFO unit has a data register, a data valid flag register Reg, a NOT gate, and an OR gate. The input direction of the single-slot FIFO unit includes three signals: input valid flag, input data, and input ready flag; the output direction includes output data valid flag, output data, and output ready flag. Among them, the input ready flag is generated by the output ready flag and the output data valid flag through combinational logic, and their relationship is as follows:

[0054] Input ready = Output ready ||!Output data valid

[0055] Here, || is the OR gate and! is the NOT gate.

[0056] An important feature of the single-slot FIFO unit is that new data can be input while the data is output.

[0057] As Figure 6 shown, the bus splitting unit includes a bus address decoding unit and a delay and selection unit. The address decoding unit determines the validity of the bus enable signals for the branches - Bus 1 enable and Bus 2 enable according to the address ranges of the two split branches - Bus 1 and Bus 2. The delay and selection unit first delays the sent valid read and write signals, and then selects the Bus 1 ready signal, Bus 2 ready signal, Bus 1 read data signal, and Bus 2 read data signal of the two branches according to the branch to which the valid read and write signal belongs.

[0058] As Figure 7As shown in the figure, the bus multiplexer includes an arbiter, a latch, and a delay and selection unit. The arbiter selects one from the bus requests applied for and latched from two branch buses (a total of three branches) and authorizes it to access downward. The latch latches the received but unauthorized bus requests in a register. The delay selection unit delays the authorized bus requests and indicates which path the bus ready signal and the bus read data should be sent to. It should be noted here that the latched bus request signal can only belong to one of the two external sources, so there are only two output paths for the output bus ready signal and the bus read data.

[0059] As Figure 8 shown, the bus read controller includes a DMA read state machine, a synchronous FIFO unit, and a combinational logic unit. The DMA read state machine obtains control information from the bus interface unit, initiates a read request to the bus, stores the read-back data into the synchronous first-in-first-out unit, and finally sends it to the data buffer. The size of the synchronous first-in-first-out unit is the data volume of two time slots. The combinational logic unit is mainly used to calculate the state of the synchronous first-in-first-out unit. It judges whether the synchronous first-in-first-out unit is empty or is becoming empty. After the DMA read state machine initiates the first read request, subsequent read requests can only be initiated when the synchronous first-in-first-out unit is empty or is becoming empty.

[0060] As Figure 9 shown, the bus write controller includes a DMA write state machine, a single-time-slot FIFO unit, a delay unit, and an AND gate. The DMA write state machine obtains control information from the bus interface unit, initiates a read data request to the DMA buffer, and simultaneously initiates a write request to the bus. Since the write data of the AHB bus is delayed by one clock cycle compared to the write request, the bus write unit uses a single-time-slot first-in-first-out unit to delay the data read back from the DMA buffer by one time slot. The delay unit samples the valid bus write request and delays it. The delayed bus write request signal and the bus ready signal pass through an AND gate to form the output ready signal of the single-time-slot FIFO unit.

[0061] It should be noted here that the DMA write state machine is the master controller. It reads data from the DMA buffer and sends a write application to the bus at the same time. However, the bus write application only sends an effective write request to the external bus when the read data from the DMA buffer arrives, and then can continue to send the write request for the next data packet.

[0062] The DMA module has four working modes, as Figure 3 shown, and are described as follows:

[0063] Mode 1:

[0064] The DMA module reads data from the multiplexed bus and writes it to the accelerator bus.

[0065] Mode 2:

[0066] The DMA module reads data from the accelerator bus and writes data to the multiplexed bus.

[0067] Mode 3:

[0068] The DMA module reads data from the multiplexed bus and writes data to the multiplexed bus.

[0069] Mode 4:

[0070] The DMA module reads data from the accelerator bus and writes data to the accelerator bus.

[0071] In summary, the present invention can realize the insertion of the DMA function module without changing the original design, and the inserted DMA is a general DMA module, which can realize the transfer of data of any length on the AHB bus and meet the requirements of any different address alignments of the source address and the destination address on the AHB bus.

[0072] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A plug-in general DMA module for AHB bus, characterized in that: Used to be set between the accelerator and the AHB bus, so as to realize data movement between the accelerator and other devices on the AHB bus under the control of the CPU; including a first bus splitting unit, a second bus splitting unit, a third bus splitting unit, a bus interface unit, a bus reading unit, a DMA buffer, a bus writing unit, a first bus multiplexing unit, a second bus multiplexing unit, and a third bus multiplexing unit; Wherein, the first bus splitting unit is connected to the bus interface unit, the third bus multiplexing unit and the external CPU respectively; The bus interface unit is also connected to the bus reading unit and the bus writing unit respectively; The DMA buffer is connected to the bus reading unit and the bus writing unit respectively; The bus reading unit is also connected to the second bus splitting unit; The bus write unit is also connected to the third bus splitting unit; The first bus multiplexing unit is respectively connected to the second bus splitting unit, the third bus splitting unit and the third bus multiplexing unit; The second bus multiplexing unit is respectively connected to the second bus splitting unit, the third bus splitting unit and the external accelerator; The third bus multiplexing unit is also connected to an external bus.

2. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The DMA buffer includes a circular buffer composed of D bytes of single-slot first-in-first-out units, the head of the circular buffer has a write pointer Write_Pointer, and the tail of the circular buffer has a read pointer Read_Pointer; the data read from the bus is written into the DMA buffer and the write pointer Write_Pointer is modified; when the bus issues a write request, the data is taken out of the DMA buffer and sent to the bus; The single-slot FIFO unit has a data register Dat Reg, a data valid flag register VldReg, a NOT gate Not, and an OR gate Or; the input information of the single-slot FIFO unit includes an input valid flag Valid_in, input data Data_in, and an input register available flag Ready_in, and the output information includes an output data valid flag Valid_out, output data Data_out, and an output destination buffer available signal Ready_out, wherein Ready_in is generated by Ready_out and Valid_out through the following combinational logic: Ready_in = Ready_out || !Valid_out In the formula, || is an OR gate and ! is a NOT gate.

3. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The first bus splitting unit, the second bus splitting unit, and the third bus splitting unit have the same structure; The bus splitting unit includes a bus address decoding unit and a delay selection unit. The address decoding unit determines whether the htrans signal of the branch is valid according to the address range of the two branches split out; the delay selection unit first delays the valid read and write signals sent out, and then selects the ready signals hready and read data signals hrdata of the two branches according to the branches to which the valid read and write signals belong.

4. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The first bus multiplexing unit, the second bus multiplexing unit and the third bus multiplexing unit have the same structure; The bus multiplexing unit includes an arbiter, a latch and a delay selection unit; the arbiter selects one of the three branches from the two branch bus applications and the latched bus application, and authorizes the downward access; the latch latches the received but unauthorized bus application in the register; the delay selection unit delays the authorized bus application and indicates to which branch hready and read data hrdata should be sent.

5. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The bus read unit includes a DMA read state machine, a synchronous first-in-first-out unit and a combinational logic unit; the DMA read state machine obtains control information from the bus interface unit, initiates a read request to the bus, and stores the read data in the synchronous first-in-first-out unit, and finally sends it to the DMA buffer; the size of the synchronous first-in-first-out unit is the amount of data in 2 time slots; the combinational logic unit is used to calculate the state of the synchronous first-in-first-out unit and determine whether the synchronous first-in-first-out unit is empty or is becoming empty; after the DMA read state machine initiates the first read request, subsequent read requests can only be initiated if the synchronous first-in-first-out unit is empty or is becoming empty.

6. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The bus write unit includes a DMA write state machine, a single-slot first-in-first-out unit, a delayer and an AND gate; the DMA write state machine obtains control information from the bus interface unit, initiates a read data request to the DMA buffer, and simultaneously initiates a write request to the bus; the single-slot first-in-first-out unit delays the data read back from the DMA buffer by one time slot; the delayer samples the effective bus write request and delays it, and the delayed bus write request signal and the bus hready signal pass through the AND gate to form the output destination buffer available signal of the single-slot first-in-first-out unit.

7. The AHB bus-oriented plug-in general DMA module according to claim 1, characterized in that: The bus interface unit is used to convert the bus signal of a branch of the first bus splitting unit into a register read / write signal to realize the control of the bus read state machine and the bus write state machine.

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