FPGA-based multi-communication driving circuit

Abstract

The application discloses a kind of based on FPGA multi-communication driving circuit, including communication driving circuit and FPGA communication circuit;The communication driving circuit includes CAN line driving circuit, LINE line driving circuit and serial port driving circuit;The CAN line driving circuit, LINE line driving circuit are connected with FPGA communication circuit respectively, and the data of OBD interface is transmitted to FPGA communication circuit;FPGA communication circuit converts and processes data to the protocol received, and forwards data to MCU by serial port driving circuit, while also receiving the instruction sent by MCU through serial port, selects different protocol to communicate, and realizes different protocol communication.The application realizes the flexible conversion of multi-communication protocol mode and circuit driving.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of automobile fault diagnosis, in particular to a multi-communication driving circuit based on FPGA. BACKGROUND

[0002] Modern automobile electronic systems have become increasingly complex, covering multiple fields such as engine management, ABS, body control, and infotainment systems. These systems usually implement effective data exchange between internal and external devices through various communication protocols. In this process, the role of the automobile fault diagnosis system is particularly important, as it can monitor and analyze the running state of each electronic component of the vehicle in real time, promptly discover and diagnose potential faults, and thus improve the safety, reliability, and maintenance efficiency of the vehicle.

[0003] Currently, automobile fault diagnosis systems mainly rely on standard diagnostic communication protocols such as CAN (Controller Area Network), LIN (Local Interconnect Network), and serial communication (RS232 or RS485). These communication protocols provide a standard for data exchange between various control modules within the vehicle, but there are differences between different protocols in terms of transmission methods, signal characteristics, etc. In order to achieve interconnection and intercommunication between multiple protocols, automobile fault diagnosis systems often need to rely on specialized hardware circuits or middleware for protocol conversion and signal driving. This increases the design complexity of the system and may affect the diagnosis efficiency.

[0004] Therefore, there is an urgent need for a multi-communication driving circuit based on FPGA that can quickly convert between multiple communication protocols and directly drive different types of communication lines, in order to improve the flexibility and adaptability of the automobile fault diagnosis system. SUMMARY

[0005] To solve the above technical problems, the present application provides a multi-communication driving circuit based on FPGA, which can realize the interconnection and intercommunication of different communication protocols in automobile fault diagnosis, and convert OBD interface data into serial communication mode through the FPGA communication circuit to transmit to the MCU, thereby improving the fault diagnosis efficiency.

[0006] To solve the above technical problems, the present application adopts the following technical solutions:

[0007] A multi-communication driving circuit based on FPGA, comprising a communication driving circuit and a FPGA communication circuit; the communication driving circuit comprises a CAN line driving circuit, a LINE line driving circuit, and a serial port driving circuit; the CAN line driving circuit and the LINE line driving circuit are respectively connected to the FPGA communication circuit, and data of the OBD interface is transmitted to the FPGA communication circuit;

[0008] The FPGA communication circuit converts and processes the received protocol and forwards the data to the MCU through the serial port driving circuit, and also receives the instructions sent by the MCU through the serial port, selects the CAN line driving circuit or the LINE line driving circuit to realize different protocol communication.

[0009] Further technical solutions, the FPGA communication circuit includes FPGA chip and communication control module inside the FPGA chip;The communication control module multiplexes the output of the plurality of pins of the FPGA, selects different signal paths and controls the state of the communication protocol, to realize the control of the bus communication.

[0010] Further technical solutions, the FPGA chip includes LINE0 serial port receiving pin, LINE0 serial port sending pin, CAN1 serial port receiving pin, CAN1 serial port sending pin, LINE1 serial port receiving pin, LINE1 serial port sending pin, MCU serial port 5 sending pin, MCU serial port 5 receiving pin, CAN0 serial port receiving pin, CAN0 serial port sending pin and GPIO pin;The MCU serial port 5 sending pin communicates with the receiving MCU serial port, receives the command, and makes logical switching according to the received command;The MCU serial port 5 receiving pin communicates with the MCU serial port, returns the command, and returns the parameter after executing the command;The LINE0 serial port receiving pin, the LINE0 serial port sending pin, the LINE1 serial port receiving pin and the LINE1 serial port sending pin are connected with the LINE line driving circuit, and the LINE line communication is carried out;The CAN1 serial port receiving pin, the CAN1 serial port sending pin, the CAN0 serial port receiving pin and the CAN0 serial port sending pin are connected with the CAN line driving circuit, and the CAN line communication is realized;

[0011] The communication control module includes a first register, a second register and a pin output control register arranged in the FPGA chip;The addresses of the first register and the second register are different, and the first register and the second register are used for storing the control information sent by the MCU, which is used for configuring the pin output control register, and then controlling the pin state of the FPGA chip, realizing the CAN line communication or the LINE line communication. By controlling the high and low levels of the CAN0 pin and the CAN1 pin on the FPGA chip, different communication modes are selected, and by adjusting the different high four bits and fourth bits of the second register, the output of the LINE0 pin and the LINE1 pin on the FPGA chip is controlled.

[0012] Further technical solutions, the first register controls the high and low levels of the CAN0 pin and the CAN1 pin on the FPGA chip, and different communication modes are selected, specifically:

[0013] The address of the first register is 0x03, the reset value is 0x00, the 7th, 6th and 3rd bits of the register are reserved, the 5th and 4th bits are set as CAN1_PHY_SEL[1:0], different CAN transceivers are selected by setting the parameters of the 5th and 4th bits, so as to control the output of the CAN1 pin on the FPGA chip to be high or low, and communicate with the CAN line driving circuit to realize CAN line communication; the 2nd, 1st and 0th of the first register are set as CAN0_PHY_SEL[2:0], and the values of the three bits are set to configure the output of the CAN0 pin on the FPGA chip to be high or low;

[0014] The output of the LINE0 pin and the LINE1 pin on the FPGA chip is controlled by the different values of the high four bits and the fourth bit of the second register, specifically:

[0015] The address of the second register is 0x04, the reset value is 0x00, the high four bits of the 7th, 6th, 5th and 4th of the register are set as LINE_RX_SEL[3:0], the pin output register adjusts the phase selection of the LINE receiving signal pin on the FPGA chip by setting the different values of the four bits, and realizes the communication of the LINE line; the low four bits of the 3rd, 2nd, 1st and 0th of the second register are set as LINE_TX_SEL[3:0], the pin output register adjusts the phase selection of the LINE transmitting signal pin on the FPGA chip by setting the different values of the four bits, and realizes the communication of the LINE line.

[0016] Further technical solutions, the CAN line driving circuit includes a CAN line initial level driving circuit, a CAN line sending driving circuit and a CAN line conversion serial port receiving driving circuit, the CAN line initial level driving circuit controls the level of the CAN bus to be in an idle state, the CAN line sending driving circuit transmits the data sent by the FPGA through the CAN bus, and the CAN line conversion serial port receiving driving circuit converts the received CAN data into a serial signal and transmits the serial signal to the MCU through the FPGA communication circuit.

[0017] Further technical solutions, the CAN line initial level driving circuit includes an analog switch chip U14, the pins on the analog switch chip U14 adjust CAN_H and CAN_L by receiving the control signal transmitted by the FPGA chip, and provide the initial state of the level for the CAN line sending driving circuit, so as to ensure that there is no misoperation in the communication process.

[0018] The analog switch chip U14 includes a first input pin IN1, a second input pin IN2, a third input pin IN3, a fourth input pin IN4, a first control pin D1, a second control pin D2, a third control pin D3, a fourth control pin D4, a first output pin S1, a second output pin S2, a third output pin S3, a fourth output pin S4, a pin V-, a pin GND, a pin V+, and a pin VL; the first input pin IN1, the second input pin IN2, the third input pin IN3, and the fourth input pin IN4 are respectively connected with a first 24V CAN uplink level driving pin, a second 24V CAN uplink level driving pin, a second 24V CAN downlink level driving pin, and a first 24V CAN downlink level control pin; the first control pin D1 is connected with the cathode of a diode D15 through a resistor R133; the second control pin D2 is connected with the cathode of the diode D15 through a resistor R134; the anode of the diode D15 is connected with a VCC_IN power input end; the third control pin D3 and the fourth control pin D4 are respectively connected with a resistor R138 and a resistor R139 and then grounded; the first output pin S1 and the fourth output pin S4 are respectively connected with a CAN1_H pin of a CAN line sending driving circuit; the second output pin S2 and the third output pin S3 are respectively connected with a CAN1_L pin of the CAN line sending driving circuit; the pin V- and the pin GND are grounded; the pin V+ and the pin VL are respectively connected with a VCC_IN end and a VCC_5V power supply and are then grounded through a connection C114 capacitor and a C115 capacitor.

[0019] Further technical solutions, the CAN line sending driving circuit forms a differential level circuit by driving CAN_H / CAN_L to send data to the CAN line receiving driving circuit of the serial port; the CAN line sending driving circuit includes MOSFET tubes Q4, Q3, and Q5; the gate of the MOSFET tube Q4 is connected with a 24VCAN_UP0 pin of an FPGA chip through a resistor R135, a C112 capacitor is connected with the resistor R135 in parallel, the gate of the MOSFET tube Q4 is connected with a pull-down resistor R136 and then grounded; the source of the MOSFET tube Q4 is grounded; the drain of the MOSFET tube Q4 is connected with the gate of a high-side driving part MOSFET tube Q3 through a current-limiting resistor R132; the gate of the MOSFET tube Q3 is connected with a power supply VCC_IN through a resistor R131, and the power supply VCC_IN is then grounded through a connection C111 capacitor; a diode D14 is connected with the resistor R131 in parallel; the source of the MOSFET tube Q3 is connected with the power supply VCC_IN; the drain of the Q3 is connected with a diode D16 and a resistor R137 in series to form a CAN1_H signal output end;

[0020] In the CAN_L part, the gate of the MOSFET tube Q5 is connected with the 24VCAN_PD0 pin of the FPGA chip through the current-limiting resistor R141, used for receiving the digital logic signal transmitted from the FPGA chip, the resistor R141 is connected with the capacitor C113 in parallel, at the same time, the gate of the MOSFET tube Q5 is connected with the ground through the pull-down resistor R142, ensuring the signal stability; the capacitor C113 is connected with the resistor R141 in parallel for filtering high-frequency noise and improving signal stability, the source of the MOSFET tube Q5 is grounded, and the drain of the MOSFET tube Q5 is connected with the current-limiting resistor R140 to form the CAN_L output end. When the 24VCAN_PD0 pin changes from low to high, the MOSFET tube Q5 is turned on, the drain voltage of Q5 is pulled low, and the CAN_L signal line is driven to output low level.

[0021] Further technical solutions, the CAN line conversion serial port receiving drive circuit includes CAN transceiver chip U16 and switch chip J16, the CAN transceiver chip U16 includes pin TXD, pin RXD, pin CANH, pin CANL, pin VSS, pin S, pin VDD, pin VIO; the pin TXD and the pin RXD are connected with the pin CAN1_TXD and the pin CAN1_RXD of the FPGA chip respectively, the pin CAN1_TXD is used for receiving the digital signal from the FPGA chip, and the pin CAN1_RXD is used for transmitting the digital signal on the CAN bus; the pin CANH and the pin CANL are connected with the CAN1_H and the CAN1_L differential signals of the CAN line sending drive circuit respectively, one end of the pin CANH is connected with the capacitor C125, one end of the pin CANL is connected with the capacitor C124, and the other end of the capacitor C124 is connected with the other end of the capacitor C125 and then grounded; the pin VSS and the pin S are grounded; the pin VDD is connected with the VCC_5V power supply, and is connected with the capacitor C122 and then grounded; stable power supply is guaranteed; the VIO pin is connected with the 3.3V power supply, matched with the logic level of the MCU, and connected with the capacitor C123 and then grounded, bypassing the noise;

[0022] The 2nd pin of the switch chip J16 is designed as CAN120_SW1, and is used for transmitting the CAN signal corresponding to different channels; the 1st pin of the J16 chip is connected with the 3.3V power supply, the 3rd pin and the 4th pin are connected with the CAN1_H and the CAN1_L differential signals of the CAN line sending drive circuit through the matching resistor R145 and the matching resistor R146 respectively, and the 3rd pin is connected with the capacitor C121 and then grounded.

[0023] Further technical solutions, the FPGA chip is of the GW1N-4K-LQFP100 type.

[0024] Further technical solutions, the model of the analog switch chip U14 is DG445 / SGM4512.R133 and R139 resistance value is 1.8K, R134 and R138 resistance value is 910 ohms.

[0025] Further technical solutions, the model of the MOSFET tube Q4 is 2N7002, the model of the MOSFET tube Q3 is LP2309LT1G, the model of the MOSFET tube Q5 is CJ2310, R138 and R134 resistance value is 910 ohms, R137 and R140 resistance value is 220 ohms.

[0026] Further technical solutions, the CAN transceiver chip U16 chip model is MCP2558FD-H / SN.

[0027] The FPGA communication circuit of the application carries out data processing and protocol control with MCU, and the CAN line driving circuit is responsible for converting the data into physical signals of the CAN bus and sending the data to the bus. The two work together to realize efficient communication between FPGA and MCU through signal control and timing coordination control. Timing coordination refers to that FPGA first receives the command from MCU, and then controls CAN or LINE communication. When no communication instruction from MCU is received, CAN communication is stabilized in a state ready to send by the CAN initial level driving circuit. The FPGA communication circuit includes port design of the FPGA chip connected to MCU, and the FPGA chip converts CAN protocol and LINE protocol data into serial port and sends to the MCU port. After the connection between the FPGA chip and MCU is established, the driving function is determined by MCU. Through the use of FPGA chip pin multiplexing output, according to the instruction, the function of MCU interface is multiplexed to FPGA IO pin to realize multiplexing function or logic function. Advantages

[0028] Compared with the prior art, the application has the following obvious advantages:

[0029] 1. The application converts and transmits OBD interface data to MCU port by using FPGA circuit, and only one driving circuit is needed to realize multi-mode, multi-protocol and multi-channel communication, greatly improving the convenience and flexibility of diagnosis.

[0030] 2. The application sets a reasonable initial level through the CAN line initial level driving circuit, which can prevent data errors or false triggering caused by bus noise and unstable level, and ensure that the CAN bus is in a stable state when idle, thereby improving the stability and anti-interference ability of the whole communication system.

[0031] 3. In this invention, the CAN line transmission drive circuit uses a high-efficiency transmission drive circuit, which can ensure that data is transmitted quickly and stably under high-frequency switching conditions, reduce signal reflection and loss, and reduce power consumption.

[0032] 4. In this invention, the CAN line to serial port driver circuit enables CAN bus devices to interconnect and exchange data with serial communication devices through effective signal conversion, thereby improving the system's flexibility and applicability.

[0033] 5. This invention enables free switching between CAN and LINE lines by setting two 8-bit registers and adjusting different communication parameters of the registers. The transmission and reception methods are flexible and efficient, and it is suitable for multi-channel communication driving. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the present invention;

[0035] Figure 2 This is the circuit diagram of an FPGA chip.

[0036] Figure 3 Diagram of the CAN line initial level drive circuit;

[0037] Figure 4(a) shows the CAN_H circuit diagram of the CAN line transmission drive circuit;

[0038] Figure 4(b) shows the CAN_L circuit diagram of the CAN line transmission drive circuit;

[0039] Figure 5 CAN line level logic diagram;

[0040] Figure 6 This is a diagram of a CAN bus to serial port driver. Detailed Implementation

[0041] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. Example

[0042] like Figures 1-5 As shown, the FPGA chip receives information from the vehicle's OBD port by controlling the receiving circuit on the CAN bus interface. This information is transmitted via the CAN protocol, and the FPGA decodes it for further data processing, analysis, or storage. The FPGA chip converts the CAN bus data into serial signals as needed, or exchanges data with other modules via the LINE bus when necessary. When the system needs to transmit data to external devices (such as a PC or diagnostic tools) via the serial port, the FPGA processes the CAN signals and sends the data out according to the serial communication protocol. In this case, the serial port provides a low-speed communication channel for configuration, diagnostics, or data logging.

[0043] A multi-communication driving circuit based on FPGA, comprising a communication driving circuit and a FPGA communication circuit;The communication driving circuit comprises a CAN line driving circuit, a LINE line driving circuit and a serial port driving circuit;The CAN line driving circuit, the LINE line driving circuit are connected with the FPGA communication circuit respectively, and the data of the OBD interface is transmitted to the FPGA communication circuit;

[0044] The FPGA communication circuit converts and processes the received protocol, and forwards the data to the MCU through the serial port driving circuit, while also receiving the instructions sent by the MCU through the serial port, selects different protocols for communication, and realizes different protocol communication;

[0045] The FPGA communication circuit comprises a FPGA chip and a communication control module inside the FPGA chip;The communication control module multiplexes the output of the multiple pins of the FPGA, selects different signal paths and controls the state of the communication protocol, so as to realize the control of the bus communication.

[0046] The FPGA chip model is GW1N-4K-LQFP100, and the FPGA chip comprises a LINE0 serial port receiving pin PZ07_LINE0_RXD, a LINE0 serial port transmitting pin PZ06_LINE0_TXD, a CAN1 serial port receiving pin PZ05_CAN1_RXD, a CAN1 serial port transmitting pin PZ04_CAN1_TXD, a LINE1 serial port receiving pin PZ03_LINE1_RXD, a LINE1 serial port transmitting pin PZ02_LINE1_TXD, a MCU serial port 5 transmitting pin PB8_UART5_TXD, a MCU serial port 5 receiving pin PB9_UART5_RXD, a CAN0 serial port receiving pin PC10_CAN0_RXD, a CAN0 serial port transmitting pin PC09_CAN0_TXD and a GPIO pin PY5_FPGA_GPIO;The MCU serial port 5 transmitting pin communicates with the receiving MCU serial port, receives the command, and makes logical switching according to the received command;The MCU serial port 5 receiving pin communicates with the MCU serial port, returns the command, and returns the parameter after executing the command;The LINE0 serial port receiving pin, the LINE0 serial port transmitting pin, the LINE1 serial port receiving pin and the LINE1 serial port transmitting pin are connected with the LINE line driving circuit, and the LINE line communication is carried out;The CAN1 serial port receiving pin, the CAN1 serial port transmitting pin, the CAN0 serial port receiving pin and the CAN0 serial port transmitting pin are connected with the CAN line driving circuit, and the CAN line communication is realized;The FPGA chip further comprises other pins, which are not described in detail in the patent.

[0047] The communication control module comprises a first register, a second register and a pin output control register arranged in the FPGA chip;

[0048] The first register and the second register are used for storing control information sent by the MCU, and the control information is used for configuring the pin output control register, thereby controlling the pin state of the FPGA chip to realize CAN line communication or LINE line communication.

[0049] The address of the first register is 0x03, and the reset value is 0x00. The 7th, 6th and 3rd bits of the register are reserved, the 5th and 4th bits are set as CAN1_PHY_SEL[1:0], and the parameters of the 5th and 4th bits are set to select different CAN transceivers (including fault-tolerant CAN transceivers, CANFD0 transceivers and the like), thereby controlling the CAN1 pin on the FPGA chip to output high or low and realizing CAN line communication with the CAN line driving circuit.

[0050] The specific settings of the 5th and 4th bits of the first register are as follows: 10: selecting 24V CAN transceiver E6 pin; 01: selecting CANFD1 transceiver E6 pin; and 00: not selecting CAN transceiver. The specific settings of the 2nd, 1st and 0th are as follows: 100: selecting fault-tolerant CAN transceiver 2 (LINE0 LINE1 simulation); 011: single-wire CAN transceiver LINE0; 010: selecting fault-tolerant CAN transceiver 1 (fault-tolerant CAN dedicated chip); 001: selecting CANFD0 transceiver LINE01; and 000: not selecting CAN transceiver.

[0051] The output of the LINE0 pin and the LINE1 pin on the FPGA chip is controlled by the different high four bits and the fourth bit of the second register, and the specific settings are as follows:

[0052] The address of the second register is 0x04, and the reset value is 0x00. The 7th, 6th, 5th and 4th high four bits of the register are set as LINE_RX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE receiving signal pin on the FPGA chip by setting the different four bits, thereby realizing LINE line communication. The 3rd, 2nd, 1st and 0th low four bits of the second register are set as LINE_TX_SEL[3:0], and the pin output register adjusts the phase selection of the LINE transmitting signal pin on the FPGA chip by setting the different four bits, thereby realizing LINE line communication.

[0053] The 7th, 6th, 5th, 4th high four bits LINE_RX_SEL[3:0] of the second register are specifically set as: 1011: LINE_DIFF_RXD positive phase; 1010: LINE_DIFF_RXD positive phase; 1001: select industrial CAN transceiver (national five exempt from disassembly); 1000: LINE0_RXD, LINE1_RXD differential negative phase; 0111: LINE0_RXD, LINE1_RXD differential positive phase; 0110: LINE01_RXD negative phase; 0101: LINE01_RXD positive phase; 0100: LINE1_RXD negative phase; 0011: LINE1_RXD positive phase; 0010: LINE0_RXD negative phase; 0001: LINE0_RXD positive phase; and 0000: not selected. The 3rd, 2nd, 1st, 0th low four bits LINE_TX_SEL[3:0] are specifically set as: 1001: select industrial CAN transceiver (national five exempt from disassembly); 1000: LINE0, LINE1 differential, LINE1 positive phase, LINE0 negative phase; 0111: LINE0, LINE1 differential, LINE0 positive phase, LINE1 negative phase; 0110: LINE0 negative phase, LINE1 negative phase; 0101: LINE0 positive phase, LINE1 positive phase; 0100: LINE1 negative phase, LINE0 suspended; 0011: LINE1 positive phase, LINE0 suspended; 0010: LINE0 negative phase, LINE1 suspended; 0001: LINE0 positive phase, LINE1 suspended; and 0000: LINE0 suspended, LINE1 suspended. In the register setting, single-wire CAN and LINEPHY cannot be selected at the same time.

[0054] The CAN line driving circuit comprises a CAN line initial level driving circuit, a CAN line sending driving circuit and a CAN line conversion serial port receiving driving circuit.

[0055] The CAN line initial level driving circuit comprises an analog switch chip U14, pins on the chip of the analog switch chip U14 adjust CAN_H and CAN_L by receiving a control signal transmitted from the FPGA chip, and provide an initial state of the level for the CAN line sending driving circuit, so as to ensure that there is no misoperation in the communication process.

[0056] The analog switch chip U14 includes a first input pin IN1, a second input pin IN2, a third input pin IN3, a fourth input pin IN4, a first control pin D1, a second control pin D2, a third control pin D3, a fourth control pin D4, a first output pin S1, a second output pin S2, a third output pin S3, a fourth output pin S4, a pin V-, a pin GND, a pin V+, and a pin VL; the first input pin IN1, the second input pin IN2, the third input pin IN3, and the fourth input pin IN4 are connected with a first 24VCAN uplink level driving pin (No. 6 pin), a second 24VCAN uplink level driving pin (No. 17 pin), a second 24VCAN downlink level driving pin (No. 18 pin), and a first 24VCAN downlink level control pin (No. 7 pin) of the FPGA chip respectively, the first control pin D1 is connected with a cathode of a diode D15 through a resistor R133; the second control pin D2 is connected with the cathode of the diode D15 through a resistor R134, an anode of the diode D15 is connected with a VCC_IN power input end; the third control pin D3 and the fourth control pin D4 are connected with a resistor R138 and a resistor R139 respectively and then grounded; the first output pin S1 and the fourth output pin S4 are connected with a CAN1_H pin of a CAN line sending driving circuit respectively; the second output pin S2 and the third output pin S3 are connected with a CAN1_L pin of the CAN line sending driving circuit respectively; the pin V- and the pin GND are grounded; the pin V+ and the pin VL are connected with a VCC_IN end and a VCC_5V power source respectively, and the VCC_IN power end and the VCC_5V power end are connected with a connection C114 capacitor and a C115 capacitor and then grounded.

[0057] The model of the analog switch chip U14 is DG445 / SGM4512. The resistance values of R133 and R139 are 1.8K, and the resistance values of R134 and R138 are 910 ohms. The pins IN1, IN2, IN3, and IN4 on the U14 chip are defined as 24VCAN_UP1, 24VCAN_UP2, 24VCAN_PD2, and 24VCAN_PD1 respectively, when 24VCAN_UP1 / 24VCAN_PD1 and 24VCAN_UP2 / 24VCAN_PD2 are high at the same time, the 24VCAN circuit is driven, the resistor R133 and the resistor R138 are connected in series, and the resistor R134 and the resistor R139 are connected in series. At this time, the CAN_H (CAN high) initial level satisfies formula 1, that is, the voltage is about 8V:

[0058] VCAN_H=[R138 / (R133+R138)]*VCC_IN =[910 / (1800+910)]*VCC_IN=8V (Formula 1)

[0059] CAN_L(CAN low) initial level meets formula 2, i.e. the voltage is about 16V.

[0060] VCAN_L= R139 / (R134+R139)*VCC_IN=[1800 / (910+1800)]*VCC_IN=16V (formula 2)

[0061] The drive is turned off when 24VCAN_UP1 / 24VCAN_PD1 and 24VCAN_UP2 / 24VCAN_PD2 are low at the same time.

[0062] The circuit adjusts CAN_H and CAN_L by receiving the control signal from the FPGA chip, provides the initial state of the level for the CAN line sending drive circuit, and ensures that there is no misoperation in the communication process.

[0063] The CAN line sending drive circuit forms a differential level circuit by driving CAN_H / CAN_L to send data to the CAN line receiving drive circuit of the serial port; the CAN line sending drive circuit comprises MOSFET tubes Q4, Q3 and Q5; the gate of the MOSFET tube Q4 is connected with the 24VCAN_UP0 pin of the FPGA chip through the resistor R135, the C112 capacitor is connected with the resistor R135 in parallel to provide a filtering function for the input signal and reduce noise interference, and the gate of the MOSFET tube Q4 is connected with the pull-down resistor R136 and then grounded; the source of the MOSFET tube Q4 is grounded; the drain of the MOSFET tube Q4 is connected with the gate of the high-side drive part MOSFET tube Q3 through the current-limiting resistor R132; the gate of the MOSFET tube Q3 is connected with the power supply VCC_IN through the resistor R131, and the power supply VCC_IN is connected with the ground through the C111 capacitor; the diode D14 is connected with the resistor R131 in parallel; the source of the MOSFET tube Q3 is connected with the power supply VCC_IN; the drain of the Q3 is connected with the diode D16 and the resistor R137 in series to form a CAN1_H signal output end; in the circuit, the D14 diode is connected with the resistor R131 in parallel to protect the MOSFET tube Q3 from being damaged by current or voltage. When the 24VCAN_UP0 pin changes from low to high, the MOSFET tubes Q4 and Q3 are turned on to drive the CAN_H output high level.

[0064] In the CAN_L part, the gate of the MOSFET tube Q5 is connected with the 24VCAN_PD0 pin of the FPGA chip through the current-limiting resistor R141, used for receiving the digital logic signal transmitted from the FPGA chip, the resistor R141 is connected with the capacitor C113 in parallel, at the same time, the gate of the MOSFET tube Q5 is connected with the ground through the pull-down resistor R142, ensuring the signal stability; the capacitor C113 is connected with the resistor R141 in parallel for filtering high-frequency noise and improving the signal stability, the source of the MOSFET tube Q5 is connected with the ground, and the drain of the MOSFET tube Q5 is connected with the current-limiting resistor R140 to form the CAN_L output end. When the 24VCAN_PD0 pin changes from low to high, the MOSFET tube Q5 is turned on, the drain voltage of Q5 is pulled low, and the CAN_L signal line is driven to output low level.

[0065] After the initial state of the CAN communication bus is set by the CAN line initial level driving circuit, it is ensured that the logic level of the CAN bus is in a stable and initial state meeting the protocol requirements before the communication starts, and then the CAN line sending driving circuit can start to work, as shown in Fig. 4, the CAN line sending driving circuit drives the CAN_H / CAN_L to form a differential level circuit to send data. The differential signal level conversion is shown in Fig. 5. Figure 5 As can be seen from the figure, in the CAN bus differential signal, how the level relationship of the two signal lines CAN_H and CAN_L differential signals expresses the logic "0" (dominant, dominant state) and the logic "1" (recessive, recessive state). Among them, when the bus state is in the dominant state, the CAN_H level is higher, and the CAN_L level is lower. In the bus arbitration, the dominant state has higher priority and can cover the recessive state. When there is communication demand, this state is used; when the bus is in the recessive state, the CAN_H level is lower, and the CAN_L level is higher, or there is no differential voltage between the two, and this state is used when the bus is idle.

[0066] The model of the MOSFET tube Q4 is 2N7002, the model of the MOSFET tube Q3 is LP2309LT1G, the model of the MOSFET tube Q5 is CJ2310, the resistance values of R138 and R134 are 910 ohms, and the resistance values of R137 and R140 are 220 ohms.

[0067] The CAN line transmission drive circuit drives CAN_H / CAN_L to form a differential level circuit to transmit data. In the CAN_H part, 24VCAN_UP0 is a signal receiving end connected to the 24VCAN_UP0 pin of the FPGA chip to receive the digital logic signal transmitted from the FPGA chip. The 24VCAN_PD0 pin is connected to the 24VCAN_PD0 pin of the FPGA chip to receive the digital logic signal transmitted from the FPGA chip. When VCC_IN=24V level, 24VCAN_UP0 is changed from low to high, MOS tubes Q4 and Q3 are turned on, CAN1_H signal is driven from the initial level to satisfy VCAN_H voltage of about 8V to about 16V, and the calculation formula is shown in formula 3:

[0068] VCAN_H=[R138 / (R137+R138)]*VCC_IN=[910 / (220+910)]*VCC_IN=19.3V (formula 3)

[0069] When 24VCAN_UD0 is changed from low to high, MOS tube Q5 is turned on, CAN1_L signal is driven from the initial level to satisfy VCAN_L voltage of about 16V to about 8V, and the calculation formula is shown in formula 4:

[0070] VCAN_L=[R140 / (R140+R134)]*VCC_IN=[220 / (220+910)]*VCC_IN=4.7V (formula 4)

[0071] When VCC_IN=12V level is applied at the same time, 12VCAN_UP0 / 24VCAN_UD0 transmits according to the CAN bus TX signal protocol, that is, it meets the CAN protocol standard. The highest baud rate can reach 125K.

[0072] The CAN line conversion serial port receiving drive circuit comprises a CAN transceiver chip U16 and a switch chip J16, the U16 chip is of a model MCP2558FD-H / SN, and is used for converting signals of serial ports and CAN bus communication. The CAN transceiver chip U16 comprises a pin TXD, a pin RXD, a pin CANH, a pin CANL, a pin VSS, a pin S, a pin VDD and a pin VIO; the pin TXD and the pin RXD are connected with a pin CAN1_TXD and a pin CAN1_RXD of the FPGA chip respectively, the pin CAN1_TXD is used for receiving digital signals from the FPGA chip, and the pin CAN1_RXD is used for sending digital signals on the CAN bus; the pin CANH and the pin CANL are connected with CAN1_H and CAN1_L differential signals of the CAN line sending drive circuit respectively, one end of the pin CANH is connected with one end of a capacitor C125, one end of the pin CANL is connected with one end of a capacitor C124, and the other end of the capacitor C124 is connected with the other end of the capacitor C125 and then grounded; the pin VSS and the pin S are grounded; the pin VDD is connected with a VCC_5V power supply and then grounded after being connected with a capacitor C122, so as to guarantee stable power supply; the VIO pin is connected with a 3.3V power supply, matches the logic level of the MCU, and is grounded after being connected with a capacitor C123, so as to bypass noise.

[0073] The No. 2 pin of the switch chip J16 is designed as CAN120_SW1, and is used for transmitting CAN signals corresponding to different channels; the No. 1 pin of the J16 chip is connected with a 3.3V power supply, the No. 3 pin and the No. 4 pin are connected with CAN1_H and CAN1_L differential signals of the CAN line sending drive circuit through matching resistors R145 and R146 respectively, and are used for terminal matching, and the No. 3 pin is connected with a capacitor C121 and then grounded.

[0074] The line line drive circuit adopts an existing circuit in the prior art, for example, a prior application patent of the applicant: patent number CN202320607364.0, and the invention name is: a K line drive circuit suitable for an automobile bus, which can be used as the line line drive circuit. The serial port drive circuit can adopt a common RS485 and RS232 circuit.

[0075] The FPGA multi-communication drive circuit of the application, the communication system realizes data transmission and processing of different communication protocols through a plurality of circuit modules, and the specific working method is as follows:

[0076] (1) First, the OBD data is transmitted to the FPGA communication circuit, and after the FPGA recognizes the data protocol type and processes it, it is sent to the MCU; the MCU selects CAN communication or LINE communication according to the transmitted data and sends a switching protocol instruction to the FPGA chip through the serial port;

[0077] (2) When the MCU receives the CAN communication data, the CAN line initial level circuit provides a certain voltage to keep the level stable during system initialization, that is, before CAN protocol communication, drives the CAN bus to the preparation communication state, and ensures that the CAN bus is in a stable state when it is idle;

[0078] (3) When the FPGA chip receives the data to be sent by the MCU, the CAN line sending drive circuit controls the level change of CAN_H and CAN_L signals, and the data is transmitted to the CAN bus through differential signals, that is, CAN_H and CAN_L will change the differential voltage during signal transmission according to the data 1 and 0 values;

[0079] (4) The data on the CAN bus is sent to the FPGA chip through the CAN line conversion serial port receiving drive circuit, and then sent to the MCU through the serial port.

[0080] (5) When sending data on the CAN bus, the CAN line conversion receiving drive circuit will receive the differential signal from the CAN_H and CAN_L pins on the CAN bus, and the received differential signal will be converted to a single-ended signal, that is, converted to serial data and transmitted to the FPGA chip. Through the coordinated work of the three circuits, the system can realize the conversion from the CAN bus to the serial port communication, and support multiple protocol data exchange.

Claims

1. An FPGA-based multi-communication driving circuit comprising a communication driving circuit, characterized in that: The FPGA communication circuit is further included; the communication driving circuit includes a CAN line driving circuit, a LINE line driving circuit and a serial port driving circuit; the CAN line driving circuit and the LINE line driving circuit are connected with the FPGA communication circuit respectively, and data of the OBD interface is transmitted to the FPGA communication circuit; The FPGA communication circuit converts and processes the received protocol, transmits the data to the MCU through the serial port driving circuit, receives the instructions sent by the MCU through the serial port, selects the CAN line driving circuit or the LINE line driving circuit to communicate, and realizes different protocol communication; The FPGA communication circuit includes an FPGA chip and a communication control module arranged in the FPGA chip; the communication control module multiplexes outputs of a plurality of pins of the FPGA, selects different signal paths and controls states of communication protocols, so as to realize control of bus communication; The FPGA chip includes a LINE0 serial port receiving pin, a LINE0 serial port sending pin, a CAN1 serial port receiving pin, a CAN1 serial port sending pin, a LINE1 serial port receiving pin, a LINE1 serial port sending pin, an MCU serial port 5 sending pin, an MCU serial port 5 receiving pin, a CAN0 serial port receiving pin, a CAN0 serial port sending pin and a GPIO pin; the MCU serial port 5 sending pin communicates with an MCU serial port, receives a command, and makes logical switching according to the received command; the MCU serial port 5 receiving pin communicates with the MCU serial port, returns a command, and returns a parameter after executing the command; the LINE0 serial port receiving pin, the LINE0 serial port sending pin, the LINE1 serial port receiving pin and the LINE1 serial port sending pin are connected with the LINE line driving circuit, and LINE line communication is realized; the CAN1 serial port receiving pin, the CAN1 serial port sending pin, the CAN0 serial port receiving pin and the CAN0 serial port sending pin are connected with the CAN line driving circuit, and CAN line communication is realized; The communication control module includes a first register, a second register and a pin output control register arranged in the FPGA chip; the first register and the second register are used for storing control information sent by the MCU, and the information is used for configuring the pin output control register, so as to control states of pins of the FPGA chip, and realize CAN line communication or LINE line communication.

2. The FPGA multi-communication driving circuit according to claim 1, characterized in that: the first register is used for controlling high and low levels of the CAN0 pin and the CAN1 pin on the FPGA chip, and different communication modes are selected, and the specific steps are as follows: The address of the first register is 0x03, the reset value is 0x00, the 7th, 6th and 3rd bits of the register are reserved, the 5th and 4th bits are set as CAN1_PHY_SEL[1:0], different CAN transceivers are selected by setting the parameters of the 5th and 4th bits, so as to control the output of the CAN1 pin on the FPGA chip to be high or low, and realize CAN line communication by communicating with the CAN line driving circuit; the 2nd, 1st and 0th bits of the first register are set as CAN0_PHY_SEL[2:0], and the output of the CAN0 pin on the FPGA chip is configured to be high or low by setting the values of the three bits; The output of the LINE0 pin and the LINE1 pin on the FPGA chip is controlled by the different high four bits and the fourth bit of the second register, specifically: The address of the second register is 0x04, the reset value is 0x00, the high four bits of the 7th, 6th, 5th and 4th bits of the register are set as LINE_RX_SEL[3:0], the pin output register adjusts the phase selection of the LINE receiving signal pin on the FPGA chip by setting the different four bits, and realizes the communication of the LINE line; the low four bits of the 3rd, 2nd, 1st and 0th bits of the second register are set as LINE_TX_SEL[3:0], the pin output register adjusts the phase selection of the LINE transmitting signal pin on the FPGA chip by setting the different four bits, and realizes the communication of the LINE line.

3. The FPGA-based multi-communication driving circuit according to claim 1, characterized in that: The CAN line driving circuit includes a CAN line initial level driving circuit, a CAN line sending driving circuit and a CAN line conversion serial port receiving driving circuit, the CAN line initial level driving circuit controls the level of the CAN bus to be in an idle state, the CAN line sending driving circuit transmits the data sent by the FPGA through the CAN bus, and the CAN line conversion serial port receiving driving circuit converts the received CAN data into a serial port signal and transmits it to the MCU through the FPGA communication circuit.

4. The FPGA-based multi-communication driving circuit according to claim 3, characterized in that: The CAN line initial level driving circuit includes an analog switch chip U14, the pins on the chip receive the control signal transmitted by the FPGA chip to adjust CAN_H and CAN_L, and provide the initial state of the level for the CAN line sending driving circuit, so as to ensure that there is no misoperation in the communication process. The analog switch chip U14 includes a first input pin IN1, a second input pin IN2, a third input pin IN3, a fourth input pin IN4, a first control pin D1, a second control pin D2, a third control pin D3, a fourth control pin D4, a first output pin S1, a second output pin S2, a third output pin S3, a fourth output pin S4, a pin V-, a pin GND, a pin V+ and a pin VL; the first input pin IN1, the second input pin IN2, the third input pin IN3 and the fourth input pin IN4 are connected with the first 24VCAN uplink level driving pin, the second 24VCAN uplink level driving pin, the second 24VCAN downlink level driving pin and the first 24VCAN downlink level control pin of the FPGA chip respectively, the first control pin D1 is connected with the cathode of the diode D15 through the resistor R133; the second control pin D2 is connected with the cathode of the diode D15 through the resistor R134, the anode of the diode D15 is connected with the VCC_IN power input end; the third control pin D3 and the fourth control pin D4 are connected with the resistor R138 and the resistor R139 respectively and then grounded; the first output pin S1 and the fourth output pin S4 are connected with the CAN1_H pin of the CAN line sending driving circuit respectively; the second output pin S2 and the third output pin S3 are connected with the CAN1_L pin of the CAN line sending driving circuit respectively; the pin V- and the pin GND are grounded; the pin V+ and the pin VL are connected with the VCC_IN end and the VCC_5V power respectively, and the VCC_IN power end and the VCC_5V power end are connected with the C114 capacitor and the C115 capacitor and then grounded.

5. The FPGA-based multi-communication driving circuit according to claim 3, characterized in that: The CAN line sending driving circuit forms a differential level circuit through driving CAN_H / CAN_L to send data to the CAN line receiving driving circuit of the serial port; the CAN line sending driving circuit includes MOSFET tubes Q4, Q3 and Q5; the gate of the MOSFET tube Q4 is connected with the 24VCAN_UP0 pin of the FPGA chip through the resistor R135, the C112 capacitor is connected with the resistor R135 in parallel, the gate of the MOSFET tube Q4 is connected with the pull-down resistor R136 and then grounded; the source of the MOSFET tube Q4 is grounded; the drain of the MOSFET tube Q4 is connected with the gate of the high-side driving part MOSFET tube Q3 through the current-limiting resistor R132; the gate of the MOSFET tube Q3 is connected with the power supply VCC_IN through the resistor R131, and the power supply VCC_IN is connected with the C111 capacitor and then grounded; the diode D14 is connected with the resistor R131 in parallel; the source of the MOSFET tube Q3 is connected with the power supply VCC_IN; the drain of the Q3 is connected with the diode D16 and the resistor R137 in series to form a CAN1_H signal output end; In the CAN_L part, the gate of the MOSFET tube Q5 is connected with the 24VCAN_PD0 pin of the FPGA chip through the current-limiting resistor R141, used for receiving the digital logic signal transmitted from the FPGA chip, the resistor R141 is connected with the capacitor C113 in parallel, and the gate of the MOSFET tube Q5 is connected with the ground through the pull-down resistor R142; the capacitor C113 is connected with the resistor R141 in parallel, the source of the MOSFET tube Q5 is connected with the ground, and the drain of the MOSFET tube Q5 is connected with the current-limiting resistor R140 to form the CAN_L output end.

6. The FPGA-based multi-communication driving circuit according to claim 3, characterized in that: The CAN line conversion serial port receiving driving circuit comprises a CAN transceiver chip U16 and a switch chip J16, the CAN transceiver chip U16 comprises a TXD pin, an RXD pin, a CANH pin, a CANL pin, a VSS pin, a S pin, a VDD pin and a VIO pin; the TXD pin and the RXD pin are connected with the CAN1_TXD pin and the CAN1_RXD pin of the FPGA chip respectively, the CAN1_TXD pin is used for receiving the digital signal from the FPGA chip, and the CAN1_RXD pin is used for transmitting the digital signal on the CAN bus; the CANH pin and the CANL pin are connected with the CAN1_H and CAN1_L differential signals of the CAN line transmitting driving circuit respectively, one end of the capacitor C125 is connected with the CANH pin, one end of the capacitor C124 is connected with the CANL pin, and the other end of the capacitor C124 is connected with the other end of the capacitor C125 and then connected with the ground; the VSS pin and the S pin are grounded; the VDD pin is connected with the VCC_5V power supply and then connected with the ground through the capacitor C122; the VIO pin is connected with the 3.3V power supply, matched with the logic level of the MCU, and then connected with the ground through the capacitor C123. The 2nd pin of the switch chip J16 is designed as CAN120_SW1 and is used for transmitting the CAN signal corresponding to different channels; the 1st pin of the J16 chip is connected with the 3.3V power supply, the 3rd pin and the 4th pin are connected with the CAN1_H and CAN1_L differential signals of the CAN line transmitting driving circuit through the matching resistor R145 and the matching resistor R146 respectively, and the 3rd pin is connected with the capacitor C121 and then grounded.

7. The FPGA-based multi-communication driving circuit according to claim 1, characterized in that: The FPGA chip is of the GW1N-4K-LQFP100 type.

8. The FPGA-based multi-communication driving circuit according to claim 4, characterized in that: The analog switch chip U14 is of the DG445 / SGM4512 type, the resistance values of the R133 and R139 are 1.8K, and the resistance values of the R134 and R138 are 910 ohms.

9. The FPGA-based multi-communication driving circuit according to claim 5, characterized in that: The MOSFET tube Q4 is of the 2N7002 type, the MOSFET tube Q3 is of the LP2309LT1G type, the MOSFET tube Q5 is of the CJ2310 type, and the resistance values of the R137 and R140 are 220 ohms.

10. The FPGA-based multi-communication driving circuit according to claim 6, characterized in that: The CAN transceiver chip U16 is of the MCP2558FD-H / SN type.

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