PCIe device and test method of PCIe device

Abstract

The invention provides PCIe (Peripheral Component Interconnect Express) equipment and a test method of the PCIe equipment. The PCIe equipment comprises a PCIe controller and a loopback test enabling selector, the PCIe controller comprises a TX channel module and an RX channel module; the output of the TX channel module is connected to the first input of the loopback test enabling selector through a set type output link; and when the loopback test enable signal is enabled, the loopback test enable selector selects to send the output of the TX channel module to the RX channel module through a set type input link. According to the technical scheme provided by the invention, the influence of link signal quality and opposite-end equipment behaviors can be effectively eliminated, the problem boundary that the PCIe equipment cannot establish a link is quickly defined, and the correctness of receiving and sending logic of a physical layer module of a local-end PCIe controller is tested.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a PCIe device and a testing method for the PCIe device. Background Art

[0002] With the development of PCIe technology, especially after entering the PCIe 5.0 era, the improvement of PCIe performance has made it increasingly difficult to meet the needs of signal transmission integrity, stability and reliability. The link establishment process involves not only the physical layer module of the local PCIe controller, but also the PCS (Physical Coding Sublayer) and PMA (Physical Medium Attachment) of the local PHY (physical layer interface), as well as the behavior of the peer device and the link signal quality. Locating the link establishment problem itself is complex. If the test environment cannot meet the test conditions of the test tool (protocol analyzer, etc.), a method is needed to quickly define the problem party that currently causes the link failure. In this way, you can quickly and accurately invest your energy to solve the problem efficiently. Summary of the invention

[0003] The purpose of the present application is to provide a PCIe device and a test method for the PCIe device, aiming to solve the problem in the related art that when the local PHY is abnormal or the link signal quality is poor, the PCIe controller may not be able to enter the loopback test state, resulting in the inability to perform the expected test.

[0004] According to a first aspect of the present application, there is provided a PCIe device, comprising: a PCIe controller and a loopback test enable selector;

[0005] The PCIe controller includes a TX channel module and a RX channel module;

[0006] The output of the TX channel module is connected to the first input of the loopback test enable selector through a set type output link, and the output of the loopback test enable selector is connected to the RX channel module through a set type input link;

[0007] When the loopback test enable signal is enabled, the loopback test enable selector selects to send the output of the TX channel module to the RX channel module through the set type input link.

[0008] In an optional implementation, the PCIe device further includes: a link training module, a loopback test training signal enabling module, and a loopback test training signal selector;

[0009] The link training module is used to generate a first link training signal and a second link training signal;

[0010] The first link training signal is a default link training signal that enables a link state machine of the PCIe device to normally jump from a current state to a next state when the PCIe device is in a configuration stage as a DP device;

[0011] The second link training signal is a modified link training signal that enables a link state machine of the PCIe device to jump from a current state to a next state when the PCIe device is in a configuration stage as a UP device;

[0012] The loopback test training signal enabling module enables the training enabling signal when the loopback test enabling signal is enabled during the configuration phase of the PCIe device as a UP device;

[0013] When the training enable signal is enabled, the loopback test training signal selector selects to send the second link training signal to the TX channel module.

[0014] In an optional implementation, the output of the TX channel module is also connected to a transmission link to a peer device, and the second input of the loopback test enable selector is connected to a reception link from the peer device.

[0015] In an optional implementation, the set type output link includes a PIPE output interface of the PCIe controller; the set type input link includes a PIPE input interface of the PCIe controller.

[0016] In an optional embodiment, the PCIe device also includes a PHY device; the PHY device includes a PCS module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module and the output interface of the PCS module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module and the input interface of the PCS module on the receiving channel.

[0017] In an optional embodiment, the PCIe device also includes a PHY device; the PHY device includes a PMA module, the set type output link includes a PIPE output interface of the PCIe controller, the PCS module, the output interface of the PCS module on the sending channel, the PMA module and the SerDes TX interface of the PMA module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, the input interface of the PCS module on the sending channel, the PMA module and the SerDes RX interface of the PMA module on the receiving channel.

[0018] According to a first aspect of the present application, a method for testing a PCIe device is provided, wherein the PCIe device includes a PCIe controller and a loopback test enable selector, and the PCIe controller includes a TX channel module and an RX channel module; the method includes:

[0019] In the configuration stage, the TX channel module receives the first link training signal or the second link training signal, processes the received first link training signal or the second link training signal, and sends the obtained output to the first input of the loopback test enable selector through the set type output link;

[0020] If the loopback test enable signal is enabled, the loopback test enable selector sends the output of the TX channel module received by the first input to the RX channel module through a set type input link.

[0021] In an optional implementation manner, if the PCIe device is used as a UP device, the PCIe device further includes: a link training module, a loopback test training signal enabling module, and a loopback test training signal selector; the method further includes:

[0022] In the configuration stage, the link training module generates a first link training signal and a second link training signal; wherein the first link training signal is a default link training signal that enables the link state machine of the PCIe device to normally jump from a current state to a next state when the PCIe device is in the configuration stage as a DP device; and the second link training signal is a modified link training signal that enables the link state machine of the PCIe device to jump from a current state to a next state when the PCIe device is in the configuration stage as a UP device;

[0023] The loopback test training signal enabling module detects the enabling state of the loopback test enabling signal;

[0024] If the loopback test enable signal is enabled, the loopback test training signal enable module enables the training enable signal;

[0025] The loopback test enable selector outputs the second link training signal to the TX channel module under the control of the training enable signal.

[0026] In an optional embodiment, the method further comprises:

[0027] The TX channel module also sends the output obtained by processing the first link training signal or the second link training signal to the transmission link to the opposite end device;

[0028] When the loopback test enable signal is not enabled, the loopback test enable selector selects to output data received by the second input from the receiving link of the opposite device to the RX channel module.

[0029] In an optional implementation, the set type output link includes a PIPE output interface of the PCIe controller; the set type input link includes a PIPE input interface of the PCIe controller.

[0030] In an optional embodiment, the testing method of the PCIe device also includes a PHY device; the PHY device includes a PCS module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module and the output interface of the PCS module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module and the input interface of the PCS module on the receiving channel.

[0031] In an optional embodiment, the testing method of the PCIe device also includes a PHY device; the PHY device includes a PMA module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module, the output interface of the PCS module on the sending channel, the PMA module and the SerDesTX interface of the PMA module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, the input interface of the PCS module on the sending channel, the PMA module and the SerDes RX interface of the PMA module on the receiving channel.

[0032] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0033] The loopback self-link test solution proposed in this application can perform independent and flexible loopback self-testing without relying on the operation of the opposite device under the condition that the link building detection complies with the PCIe protocol. It can effectively eliminate the influence of link signal quality and the behavior of the opposite device, quickly define the problem boundary of the PCIe device's inability to build a link, and test the correctness of the receiving and sending logic of the physical layer module of the local PCIe controller.

[0034] This application can also cooperate with the loopback method (PCS loopback test and SerDes loopback test) inside the PHY device, and through the self-building link method, check one by one whether the reason for the failure to build the link is related to PCS or PMA. This application can be applied in the FPGA stage and the sample test link stage to quickly determine whether the current link building anomaly is a PCIe device problem, which is conducive to focusing on locating link quality problems: it can also be applied in screening and factory testing to efficiently give a conclusion on whether there are problems with the sending and receiving of PCIe devices.

[0035] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 It is a schematic diagram of a link building structure of a PCIe device according to the related technology.

[0038] Figure 2 It is a schematic diagram of the link establishment structure of a PCIe device according to an exemplary embodiment of the present application.

[0039] Figure 3 2 is another schematic diagram of a link establishment structure of a PCIe device according to an exemplary embodiment of the present application.

[0040] Figure 4 It is another schematic diagram of a link establishment structure of a PCIe device according to an exemplary embodiment of the present application.

[0041] Figure 5 It is another schematic diagram of a link establishment structure of a PCIe device according to an exemplary embodiment of the present application.

[0042] Figure 6 It is a flowchart of a method for testing a PCIe device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] The process of establishing a link in the state machine is a negotiation process between the PCIe devices on both sides of the link. Figure 1 , the two sides of the PCIe link are DP (Downstream port, downstream data device, that is, the device where the data flows away from the RP) device and UP (Upstream port, upstream data device, that is, the device where the data flows to the RP) device. During the link establishment process, the DP device and the UP device cooperate with each other to complete the negotiation of link width and supported rate. However, during the negotiation process, the DP device is the active party (actively initiates the negotiation process, sends out the supported link width and supported rate), and the UP device is the passive party (receives the TS information sent by the DP, and then sends out TS, which contains the link width and supported rate supported by the current device). The link establishment process needs to distinguish between the UP and DP modes, and the main differences are reflected in the following states:

[0045] 1. CFG_LINKWIDTH_START stage

[0046] As a DP device, it needs to receive 2 consecutive TS1s and the LINKNUM in the received TS1 is non-PAD and the LANENUM is PAD. It needs to send TS1 and the LINKNUM in the sent TS1 is the selected specific value (non-PAD) and the LANENUM is PAD.

[0047] As a UP device, it needs to receive 2 consecutive TS1s and the LINKNUM in the received TS1 is non-PAD and the LANENUM is PAD; it needs to send TS1 and the LINKNUM and LANENUM in the sent TS1 are both PAD.

[0048] 2. CFG_LINKWIDTH_ACCEPT stage

[0049] As a DP device, it needs to receive two consecutive TS1s and the LINKNUM in the received TS1 is not PAD (which is consistent with the sent LINKNUM), and LANENUM is not important. It is required that all LANEs (channels) on the sending side send TS1s and the LINKNUM and LANENUM in TS1 are both non-PAD (each LANE has a unique LANENUM);

[0050] As a UP device, it needs to receive 2 consecutive TS1s and the LINKNUM and LANENUM in the received TS1 are not PADs. It needs to send TS1 and the LINKNUM and LANENUM in the sent TS1 are the values ​​sent by the received DP.

[0051] 3. CFG_LANENUM_WAIT phase

[0052] All LANEs receive two consecutive TSs, and the LINKNUM and LANENUM in the received TSs are consistent with the sent ones; among them, as a DP device, TS2 is sent and TS1 is received; as a UP device, TS1 is sent and TS2 is received.

[0053] 4. CFG_LANENUM_ACCEPT stage

[0054] All LANEs receive 2 consecutive TSs and the LINKNUM and LANENUM in the received TSs are both non-PAD, and the LINKNUM and LANENUM are consistent with the sent ones; among them, as a DP device, TS2 is sent and TS1 is received; as a UP device, TS1 is sent and TS2 is received.

[0055] According to the PCIe protocol, LOOPBACK (loopback) can satisfy the return of data from the MASTER (active party in loopback mode) to the MASTER, and verify the stability and correctness of the link by comparing the data returned by the MASTER. However, the application of the protocol description of the LOOPBACK state has a flaw, and the cooperation of the devices on both sides of the link is required to complete this test function. If the link signal quality is poor or the opposite device is abnormal or the local PHY is abnormal, the link cannot enter LOOPBACK, which will cause the LOOPBACK test to be impossible. In order to eliminate the influence of link signal quality and PHY, LOOPBACK needs to be limited to the local PCIe controller side.

[0056] According to the above knowledge, when the PIPE interface loops back, due to the particularity of link building, the DP device interface loopback can meet the link building requirements, but the UP device cannot meet the link building conditions. This application proposes a loopback self-building link method to make the LOOPBACK test more flexible, and can perform self-loopback tests independently without relying on the opposite device and link conditions. When the LOOPBACK self-building link is enabled, modify the TS code stream sent by the UP device test, and loop back the data of the TX channel to the RX channel to test the self-building link of the local device, thereby defining whether the current local device behavior meets expectations.

[0057] The LOOPBACK scheme described in the current PCIe protocol is that when the controller is in the Configuration phase (configuration phase) or the Recovery phase (recovery phase), the LOOPBACK MASTER (loopback active party) sends TS1 to the LOOPBACK SLAVE (loopback passive party) and sets the LOOPBACK bit (loopback bit) in the TS1 training control field (Training Control). When the loopback passive party receives two TS1 sequences with the LOOPBACK bit set in succession, it enters the LOOPBACK state and then resends any subsequent received content to the MASTER (loopback active party). The MASTER will check the received content and compare it with the previously sent content. If the content is consistent after being encoded (decoded) by both parties, it means that the link can pass the loop verification and there is no problem with integrity. However, as described above, this scheme has a flaw and requires both sides of the link to cooperate to enter the LOOPBACK state. If there is a signal quality problem in the link and the data transmission cannot be correctly returned to the MASTER, the result of this scheme cannot meet the verification of the correctness of the MASTER.

[0058] In some related technologies, the main implementation method is similar to that specified in the protocol, which proposes a special method of sending TLP (Transaction Layer Packet) and comparing TLP. However, this solution also has known defects: 1. It depends on both sides of the link entering the LOOPBACK state, which may not be met in actual scenarios, resulting in the inability to continue the test.

[0059] In other related technologies, adaptation and modification are performed on the general state machine for link establishment, and by modifying the state machine and trigger conditions, the data sent by the transmitter and the data received can complete the handshake. In these related technologies, flexible configuration of state machine trigger conditions and configuration of state machine states are proposed, which can complete the handshake when the PHY on both sides is normal. However, this solution has the following defects: 1. The link establishment conditions can be configured, resulting in the state machine being a non-actual working state machine, and the trigger conditions are not actually required conditions, and the correctness of the trigger conditions and state machine jumps in the actual scenario cannot be verified. 2. The link establishment process relies on negotiation between the two sides of the link. If the link signal quality is poor or the PHY is abnormal, the handshake link establishment cannot be completed, so the physical layer verification cannot continue.

[0060] The core concept of the technical solution of this application is as follows: Through the analysis of the above-mentioned related technologies, it can be seen that the related solutions mainly rely on the LOOPBACK state specified in the protocol to implement loopback testing. The solution has a prerequisite: that is, the controller can complete the negotiation with the other end and enter the LOOPBACK state. However, in actual situations, if the PHY on the local end is abnormal or the link signal quality is poor, the controller may not be able to enter the LOOPBACK state, resulting in the inability to perform the expected test.

[0061] See also Figure 2 As shown, the present application exemplarily proposes a PCIe device, including: a PCIe controller and a loopback test enable selector;

[0062] The PCIe controller includes a TX channel module and a RX channel module;

[0063] The output of the TX channel module is connected to the first input of the loopback test enable selector through a set type output link;

[0064] When the loopback test enable signal is enabled, the loopback test enable selector selects to send the output of the TX channel module to the RX channel module through the set type input link.

[0065] The loopback self-building chain method proposed in this application has the following optimizations: This application loops the TX channel back to the RX channel through the set type output link and set type input interface on the PCIe device, and relies on the existing state machine and physical layer channel to perform state machine training. The purpose of this is to verify the correctness of the state machine and physical layer logic.

[0066] For example, the PCIe device acts as a DP device, as a downlink data device (DP device), and sends data to the peer device on the PCIe link (i.e., the uplink data device of the UP device, i.e., the UP device). In the configuration phase (Configuration phase) of the link establishment process with the peer device, the PCIe device negotiates with the peer device about the PCIe link width, rate, etc. supported by each of them by sending TS. In order to realize the loopback test, the output of the TX channel module PL_TX_DATA of the PCIe controller of the present application is connected to the first input of the loopback test enable selector through the setting type output link, and the output of the loopback test enable selector is connected to the input of the RX channel module PL_RX_DATA of the PCIe controller, so that under the control of the loopback test enable signal cfg_dfx_lpbk_en, the TX channel of the PCIe device is looped back to the RX channel of the PCIe device, so that the TS sent by the TX channel module PL_TX_DATA is received by the PCIe device as the input of the RX channel module PL_RX_DATA, so that the LTSSM state machine determines whether the TS received after the loopback meets the expectations to complete the verification, so as to test the abnormal status of each PCIe module passed by the TS code stream and the link signal quality, etc. The loopback test enable signal can be configured through software, that is, in the loopback test mode, the loopback test enable signal can be configured to an enabled state through software, so that the loopback test enable selector can be enabled by the loopback test enable signal to select the output of the TX channel module to be sent to the RS channel module.

[0067] For example, Figure 2 The figure shows a feasible implementation structure of the PCIe device proposed in the present application. In the structure, the TS code stream is looped back from the TX channel to the RX channel at the PIPE interface. There are two results:

[0068] The DP device (that is, the PCIe device as a DP device) can establish a link normally, because the DP device, as the initiator, can actively send the required TS code stream and return the default value to meet the link establishment conditions.

[0069] The UP device (i.e., the PCIe device as the UP device) cannot establish a link because the UP device is the passive party and needs to return the required TS according to the TS sent by the DP device. If the PIPE interface is simply looped back, the TS currently received by the controller is the TS data sent by this device, and the UP state machine waits for the required TS in the CFG stage until TIMEOUT.

[0070] Therefore, in order to loop back and self-build a link when the PCIe device is used as a UP device, in some optional embodiments, the PCIe device further includes: a link training module, a loopback test training signal enabling module, and a loopback test training signal selector;

[0071] The link training module is used to generate a first link training signal and a second link training signal;

[0072] The first link training signal is a default link training signal that enables the link state machine of the PCIe device to normally jump from the current state to the next state when the PCIe device is in the configuration stage as a DP device;

[0073] The second link training signal is a modified link training signal that enables the link state machine of the PCIe device to jump from the current state to the next state when the PCIe device is in the configuration stage as a UP device;

[0074] The loopback test training signal enabling module enables the training enabling signal when the loopback test enabling signal is enabled during the configuration phase of the PCIe device as a UP device;

[0075] When the training enable signal is enabled, the loopback test training signal selector selects to send the second link training signal to the TX channel module.

[0076] Exemplarily, the present application modifies the sent TS code stream (non-protocol specified TS) so that the TS sent by the UP device in the PIPE interface loopback mode is a TS that can meet the link establishment requirements, so that when the data output by the TX channel is looped back to the RX channel, the controller can establish the link normally.

[0077] Exemplarily, the link training signal TS of the present application is generated by a link training module. In the related art, a PCIe device generates a default link training signal. Figure 3 As shown, exemplarily, the present application generates a modified link training signal LPBK_TS and a default link training signal TS, and through a loopback test training signal selector, in the configuration stage when the PCIe device is used as a UP device, selects to output the modified link training signal to the TX channel module of the PCIe controller, thereby achieving the TS code stream sent by the UP device by modifying the TS code stream to be sent, so that the TS code stream to be sent is sent to the PIPE output interface of the physical layer of the PCIe controller after data encoding, scrambling, and data reorganization of the TX channel module, and is received by the RX channel module through the PIPE input interface of the physical layer of the PCIe controller after loopback, and is sent to the state machine module LTSSMSTATE for TS correctness judgment after data reorganization, descrambling, and decoding of the TX channel module, thereby completing the link self-establishment, thereby verifying the physical layer logic correctness of the controller when the PCIe device is used as a UP device.

[0078] For example, during the configuration phase of the PCIe device as a UP device, the TS code stream LPBK_TS (i.e., the second link training signal) modified to implement the loopback test is as follows:

[0079] 1. At CFG_LINKWIDTH_START, LINKNUM in LPBK_TS can be non-PAD.

[0080] 2. In CFG_LINKWIDTH_ACCEPT, LANENUM in LPBK_TS can be non-PAD.

[0081] 3. In CFG_LANENUM_WAIT, LPBK_TS is TS2 specified by the PCIe protocol.

[0082] 4. In CFG_LANENUM_ACCEPT, LPBK_TS is TS2 specified by the PCIe protocol.

[0083] It should be noted that the first link training signal is a default link training signal that enables the link state machine of the PCIe device to normally jump from the current state to the next state when the PCIe device is configured as a DP device, that is, the default link training signal specified by the PCIe protocol, as follows:

[0084] 1. CFG_LINKWIDTH_START stage

[0085] As a DP device, it needs to receive 2 consecutive TS1s and the LINKNUM in the received TS1 is non-PAD and the LANENUM is PAD. It needs to send TS1 and the LINKNUM in the sent TS1 is the selected specific value (non-PAD) and the LANENUM is PAD.

[0086] 2. CFG_LINKWIDTH_ACCEPT stage

[0087] As a DP device, it needs to receive two consecutive TS1s and the LINKNUM in the received TS1 is not PAD (which is consistent with the sent LINKNUM), and LANENUM is not important. It is required that all LANEs (channels) on the sending side send TS1s and the LINKNUM and LANENUM in TS1 are both non-PAD (each LANE has a unique LANENUM);

[0088] 3. CFG_LANENUM_WAIT phase

[0089] All LANEs receive 2 consecutive TSs, and the LINKNUM and LANENUM in the received TSs are consistent with the sent ones; among them, the DP device sends TS2 and receives TS1.

[0090] 4. CFG_LANENUM_ACCEPT stage

[0091] All LANEs receive 2 consecutive TSs and the LINKNUM and LANENUM in the received TSs are both non-PAD, and the LINKNUM and LANENUM are consistent with the sent ones; among them, the DP device sends TS2 and receives TS1.

[0092] In some optional embodiments, the output of the TX channel module is also connected to a transmission link to the opposite device, and the second input of the loopback test enable selector is connected to a reception link from the opposite device.

[0093] For example, see Figure 2 and Figure 3 As shown, in the non-loopback test mode, the output of the TX channel module is connected to the transmission link of the opposite device, so that when the loopback test enable signal is not enabled, the data, such as the TS code stream, is sent to the opposite device through the transmission link; at the same time, the second input of the loopback test enable selector is connected to the receiving link from the opposite device, so that when the loopback test enable signal is not enabled, data is received from the opposite device from the receiving link, and the received data is selected to be output to the RX channel module, so that normal data transmission with the opposite device is achieved. Therefore, in the non-loopback test mode, the loopback test enable signal is configured by software to be in a non-enabled state, so that the loopback test enable selector selects to send the data received from the opposite device to the RX channel module when the loopback test enable signal is not enabled, and the output of the TX channel module is sent to the opposite device through the transmission link.

[0094] In some optional embodiments, the set type output link includes a PIPE output interface of a PCIe controller; the set type input link includes a PIPE input interface of a PCIe controller.

[0095] For example, see Figure 2 and Figure 3As shown, the type of output link is set to the PIPE interface of the PCIe controller, that is, after the TS code stream output by the TX channel module is output to the loopback test enable selector at the output interface PIPE interface of the PCIe controller (when the PCIe device is in DP mode, it can be the first link training signal, and when the PCIe device is in UP mode, it can be the second link training signal), the loopback test enable selector, under the control of the loopback test enable signal, selects to send the TS code stream to the RX channel module through the PIPE input interface of the PCIe controller, so that the loopback test of the PCIe controller can be realized.

[0096] In some optional embodiments, the PCIe device also includes a PHY device; the PHY device includes a PCS module; the set type output link includes the PIPE output interface of the PCIe controller, the PCS module and the output interface of the PCS module on the sending channel; the set type input link includes the PIPE input interface of the PCIe controller, the PCS module and the input interface of the PCS module on the receiving channel.

[0097] For example, see Figure 4 As shown, the PCIe controller is connected to the PCS module of the PHY device, and the loopback test mode proposed in this application is also applicable to the loopback test of the PCS module at this end. In order to implement the PCS loopback test at this end, the output of the TX channel module can be connected to the input interface of the PCS module through the loopback test enable selector at the output interface of the PCS module, so that the output of the TX channel module is processed by the output of the PCS module at the output interface of the PCS module, and then looped back to the RX channel module after the input processing of the PCS module. Of course, for the PCIe device as a UP device, the modified LPBK_TS, that is, the second link training signal, can be sent during the configuration phase, so that the link establishment requirements can be met. This method can quickly confirm whether the PCIe controller and PCS module are abnormal.

[0098] In some optional embodiments, the PCIe device also includes a PHY device; the PHY device includes a PMA module, the set type output link includes the PIPE output interface of the PCIe controller, the PCS module, the output interface of the PCS module on the sending channel, the PMA module and the SerDes TX interface of the PMA module on the sending channel; the set type input link includes the PIPE input interface of the PCIe controller, the PCS module, the input interface of the PCS module on the sending channel, the PMA module and the SerDes RX interface of the PMA module on the receiving channel.

[0099] For example, see Figure 5As shown, the loopback test mode proposed in the present application is also applicable to the loopback test of the SerDes interface at this end, wherein the PCS module is connected to the PMA module. In order to implement the loopback test of the SerDes interface at this end, the output of the TX channel module can be connected to the input interface of the PMA module, i.e., the SerDes input interface, through the loopback test enable selector at the output interface of the PMA module of the PHY device, i.e., the SerDes output interface, so that the output of the TX channel module is processed by the output of the PCS module and the PMA module at the SerDes output interface, and then looped back to the RX channel module after the input processing of the PMA module and the PCS module. Of course, for the PCIe device as a UP device, the modified LPBK_TS, i.e., the second link training signal, can be sent in the configuration phase, so that the link establishment requirements can be met. This method can quickly confirm whether the PCI controller and the PHY device are abnormal.

[0100] The present application proposes a loopback self-establishing link test solution. Under the condition that the link establishment detection complies with the PCIe protocol, it can independently and flexibly perform loopback self-test without relying on the operation of the opposite device. It can effectively eliminate the influence of link signal quality and the behavior of the opposite device, quickly define the problem boundary of the PCIe device's inability to establish a link, and test the correctness of the receiving and sending logic of the physical layer module of the local PCIe controller.

[0101] This application can also cooperate with the loopback method (PCS loopback test and SerDes loopback test) inside the PHY device, and through the self-building link method, check one by one whether the reason for the failure to build the link is related to PCS or PMA. This application can be applied in the FPGA test and sample test link stage to quickly determine whether the current link building anomaly is a PCIe device problem, which is conducive to focusing on locating link quality problems; it can also be applied in screening and factory testing to efficiently give a conclusion on whether there are problems with the sending and receiving of PCIe devices.

[0102] Accordingly, see Figure 6 As shown, the present application exemplarily proposes a test method for a PCIe device, the PCIe device includes a PCIe controller and a loopback test enable selector, the PCIe controller includes a TX channel module and an RX channel module; the method includes:

[0103] In step S601, in the configuration stage, the TX channel module receives the first link training signal or the second link training signal, processes the received first link training signal or the second link training signal, and sends the obtained output to the first input of the loopback test enable selector through the set type output link;

[0104] In step S602, if the loopback test enable signal is enabled, the loopback test enable selector sends the output of the TX channel module received by the first input to the RX channel module through the set type input link.

[0105] In some optional embodiments, if the PCIe device is used as a UP device, the PCIe device further includes: a link training module, a loopback test training signal enabling module and a loopback test training signal selector; the method further includes:

[0106] In the configuration stage, the link training module generates a first link training signal and a second link training signal; wherein the first link training signal is a default link training signal that enables the link state machine of the PCIe device to normally jump from the current state to the next state when the PCIe device is in the configuration stage as a DP device; the second link training signal is a modified link training signal that enables the link state machine of the PCIe device to jump from the current state to the next state when the PCIe device is in the configuration stage as a UP device;

[0107] The loopback test training signal enabling module detects the enabling state of the loopback test enabling signal;

[0108] If the loopback test enable signal is enabled, the loopback test training signal enable module enables the training enable signal;

[0109] The loopback test enable selector outputs the second link training signal to the TX channel module under the control of the training enable signal.

[0110] In some optional embodiments, the method further comprises:

[0111] The TX channel module also sends the output obtained by processing the first link training signal or the second link training signal to the transmission link to the opposite end device;

[0112] When the loopback test enable signal is not enabled, the loopback test enable selector selects to output data received by the second input from the receiving link of the opposite device to the RX channel module.

[0113] In some optional embodiments, the set type output link includes a PIPE output interface of a PCIe controller; the set type input link includes a PIPE input interface of a PCIe controller.

[0114] In some optional embodiments, the testing method of the PCIe device also includes a PHY device; the PHY device includes a PCS module; the set type output link includes the PIPE output interface of the PCIe controller, the PCS module and the output interface of the PCS module on the sending channel; the set type input link includes the PIPE input interface of the PCIe controller, the PCS module and the input interface of the PCS module on the receiving channel.

[0115] In some optional embodiments, the testing method of the PCIe device also includes a PHY device; the PHY device includes a PMA module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module, the output interface of the PCS module on the sending channel, the PMA module and the SerDes TX interface of the PMA module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, the input interface of the PCS module on the sending channel, the PMA module and the SerDes RX interface of the PMA module on the receiving channel.

[0116] The above method can be implemented by the PCIe device provided in the above embodiment. The specific implementation method can refer to the description of the PCIe device in the above embodiment, which will not be repeated here.

[0117] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0118] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIe device, characterized in that: include: PCIe controller and loopback test enable selector; The PCIe controller includes a TX channel module and a RX channel module; The output of the TX channel module is connected to the first input of the loopback test enable selector through a set type output link; When the loopback test enable signal is enabled, the loopback test enable selector selects to send the output of the TX channel module to the RX channel module through a set type input link.

2. The PCIe device according to claim 1, characterized in that: The PCIe device also includes: a link training module, a loopback test training signal enabling module and a loopback test training signal selector; The link training module is used to generate a first link training signal and a second link training signal; The first link training signal is a default link training signal that enables a link state machine of the PCIe device to normally jump from a current state to a next state when the PCIe device is in a configuration stage as a DP device; The second link training signal is a modified link training signal that enables a link state machine of the PCIe device to jump from a current state to a next state when the PCIe device is in a configuration stage as a UP device; The loopback test training signal enabling module enables the training enabling signal when the loopback test enabling signal is enabled during the configuration phase of the PCIe device as a UP device; When the training enable signal is enabled, the loopback test training signal selector selects to send the second link training signal to the TX channel module.

3. The PCIe device according to claim 1 or 2, characterized in that: The output of the TX channel module is also connected to a transmission link to a peer device, and the second input of the loopback test enable selector is connected to a reception link from the peer device.

4. The PCIe device according to claim 1 or 2, characterized in that: The set type output link includes a PIPE output interface of the PCIe controller; the set type input link includes a PIPE input interface of the PCIe controller.

5. The PCIe device according to claim 1 or 2, characterized in that: The PCIe device also includes a PHY device; the PHY device includes a PCS module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module and an output interface of the PCS module on a sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module and an input interface of the PCS module on a receiving channel.

6. The PCIe device according to claim 1 or 2, characterized in that: The PCIe device also includes a PHY device; the PHY device includes a PMA module, the set type output link includes a PIPE output interface of the PCIe controller, the PCS module, the output interface of the PCS module on the sending channel, the PMA module and the SerDes TX interface of the PMA module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, the input interface of the PCS module on the sending channel, the PMA module and the SerDes RX interface of the PMA module on the receiving channel.

7. A method for testing a PCIe device, characterized in that: The PCIe device includes a PCIe controller and a loopback test enable selector, and the PCIe controller includes a TX channel module and an RX channel module; the method includes: In the configuration stage, the TX channel module receives the first link training signal or the second link training signal, processes the received first link training signal or the second link training signal, and sends the obtained output to the first input of the loopback test enable selector through the set type output link; If the loopback test enable signal is enabled, the loopback test enable selector sends the output of the TX channel module received by the first input to the RX channel module through a set type input link.

8. The method for testing a PCIe device according to claim 7, wherein: If the PCIe device is used as a UP device, the PCIe device further includes: a link training module, a loopback test training signal enabling module and a loopback test training signal selector; the method further includes: In the configuration stage, the link training module generates a first link training signal and a second link training signal; wherein the first link training signal is a default link training signal that enables the link state machine of the PCIe device to normally jump from a current state to a next state when the PCIe device is in the configuration stage as a DP device; and the second link training signal is a modified link training signal that enables the link state machine of the PCIe device to jump from a current state to a next state when the PCIe device is in the configuration stage as a UP device; The loopback test training signal enabling module detects the enabling state of the loopback test enabling signal; If the loopback test enable signal is enabled, the loopback test training signal enable module enables the training enable signal; The loopback test enable selector outputs the second link training signal to the TX channel module under the control of the training enable signal.

9. The method for testing a PCIe device according to claim 7 or 8, characterized in that: The method further comprises: The TX channel module also sends the output obtained by processing the first link training signal or the second link training signal to the transmission link to the opposite end device; When the loopback test enable signal is not enabled, the loopback test enable selector selects to output data received by the second input from the receiving link of the opposite device to the RX channel module.

10. The method for testing a PCIe device according to claim 7 or 8, characterized in that: The set type output link includes a PIPE output interface of the PCIe controller; the set type input link includes a PIPE input interface of the PCIe controller.

11. The method for testing a PCIe device according to claim 7 or 8, characterized in that: The testing method of the PCIe device also includes a PHY device; the PHY device includes a PCS module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module and the output interface of the PCS module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module and the input interface of the PCS module on the receiving channel.

12. The method for testing a PCIe device according to claim 7 or 8, characterized in that: The testing method of the PCIe device also includes a PHY device; the PHY device includes a PMA module; the set type output link includes a PIPE output interface of the PCIe controller, the PCS module, the output interface of the PCS module on the sending channel, the PMA module and the SerDes TX interface of the PMA module on the sending channel; the set type input link includes a PIPE input interface of the PCIe controller, the PCS module, the input interface of the PCS module on the sending channel, the PMA module and the SerDes RX interface of the PMA module on the receiving channel.

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