A multi-channel output pulse synchronization device with adjustable delay time

Abstract

The invention discloses a multi-channel output pulse synchronization device with adjustable delay time, which relates to the field of power systems. The invention comprises an FPGA, an SMA connector, a host computer, a serial communication terminal, and an output channel. The FPGA serves as a central controller, and a pulse trigger input from the SMA connector terminal is given to the FPGA, and the output of the FPGA is given to the output channel. The FPGA communicates with the host computer via the serial port to set the delay data in each channel register. When the FPGA receives an input pulse signal, it reads the delay data stored in the register according to the setting of the program, and outputs the pulse to the PIN pin of each output channel. The multi-channel output pulse synchronization device with adjustable delay time of the invention has an adjustable minimum accuracy of 52ps, and each channel can independently adjust the output delay time, and has strong controllability and adaptability.

Description

Technical Field

[0001] The invention relates to the field of power systems, and in particular to a multi-channel output pulse synchronization device with adjustable delay time. Background Art

[0002] In the prior art, when a device receives a trigger pulse, the device's multi-channel output pulses are sent simultaneously from multiple output ports. This causes the time it takes for the pulses to reach the terminal device to be affected by the length of the wiring. If multiple terminals want to receive pulses synchronously, they need to arrange the same wiring length, which is difficult and complicated under some conditions. If multiple terminal devices need to receive pulses with a certain time difference, it is even more difficult. Therefore, a device is needed to set the time delay of the output pulse. To this end, we propose a multi-channel output pulse synchronization device with adjustable delay time. Summary of the Invention

[0003] The main purpose of the present invention is to provide a multi-channel output pulse synchronization device with adjustable delay time, which solves the problems raised in the background technology by achieving adjustable delay synchronization pulses.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is: a multi-channel output pulse synchronization device with adjustable delay time, including an FPGA, an SMA connector, a host computer, a serial communication end, and an output channel. The FPGA serves as a central controller, and a pulse trigger input from the SMA connector end is given to the FPGA, and the output of the FPGA is given to the output channel. The FPGA communicates with the host computer through the serial port to set the delay data in each channel register. When the FPGA receives the input pulse signal, it reads the delay data stored in the register according to the program setting and outputs the pulse to the PIN pin of each output channel.

[0005] The output channels include multiple ones, one pulse trigger input is given to the FPGA, and the output of the FPGA is given to multiple output channels.

[0006] The synchronization device further includes a power supply, and an output end of the power supply is electrically connected to the FPGA.

[0007] The multi-output pulse synchronization device includes a delay section and a host computer and FPGA communication section. In the delay section, the FPGA selects the system clock. When the delay time is a multiple of the system clock period, the delay is achieved by counting the number of rising edges of the system clock. For example, if the system clock is 250MHz, the minimum adjustable delay time accuracy is 4ns.

[0008] In the delay part, for finer-grained delay adjustment within the system clock cycle, the primitive module I / Odelay provided by the FPGA is instantiated to implement precise tap coefficient control to adjust the delay. The tap coefficient precision of the I / Odelay primitive is 32 bits. Given REFCLK = 300 MHz, each tap is 52 ps, with a total of 31 taps. The maximum delay time of each Idelay is 31 x 52 ps = 1.612 ns. Multiple I / Odelay modules can be cascaded to achieve a maximum delay time exceeding the system clock cycle, thus covering delay data within the system clock cycle.

[0009] In the communication part between the host computer and FPGA, the host computer and FPGA communicate with each other via a serial port. The host computer calculates the number of system clock cycles and the number of 52ps to be delayed based on the information in the user interface, and transmits these two values ​​to the FPGA through the serial port using an agreed protocol. The FPGA updates the register values ​​of each channel based on the received data. Once completed, it can output the corresponding delayed pulse when the next pulse arrives.

[0010] The present invention has the following beneficial effects:

[0011] The multi-output pulse synchronization device with adjustable delay time of the present invention can greatly reduce the arrangement time and make precise adjustments when multiple terminals want to receive the same pulse at the same time or receive the same pulse with a fixed delay time. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing the operating principle of the multi-channel output pulse synchronization device with adjustable delay time of the present invention;

[0013] Figure 2 This is a logic block diagram of the multi-channel output pulse synchronization device with adjustable delay time of the present invention. DETAILED DESCRIPTION

[0014] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0015] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0016] Please refer to Figure 1-Figure 2 As shown, this solution uses a field programmable gate array as a central controller, a pulse trigger input is given to the field programmable gate array, and the output of the field programmable gate array is given to multiple output channels; the field programmable gate array has a register for each channel, which stores data such as whether the channel is enabled to output pulses and the delay time of the output pulse relative to other channels;

[0017] The field programmable gate array communicates with the host computer through the serial port to set the data in each channel register. The host computer sends the data of whether to turn on the output pulse and the delay time of the output pulse relative to other channels to the field programmable gate array in a certain format according to the user setting of the user interface; the field programmable gate array stores the data in the register after parsing.

[0018] When the field programmable gate array receives an input pulse signal, it reads the delay data stored in the register according to the program settings and outputs the pulse to each output PIN pin; it can also be sent out through an op amp or a high-speed comparator.

[0019] The multi-channel output pulse synchronization device includes a delay part and a communication part between the host computer and FPGA:

[0020] Delayed part of the plan:

[0021] When the FPGA selects a specific system clock, such as 250MHz, and the delay is a multiple of the system clock period, it is achieved by counting the rising edges of the system clock. The minimum adjustable delay precision is the system clock period. For finer delay precision within the system clock period, the FPGA's I / Odelay primitive module can be instantiated to achieve precise tap coefficient control to adjust the delay. The I / Odelay primitive has a tap coefficient precision of 32 bits. Given the REFCLK, each tap is 52ps or 78ps, for a total of 32 taps. Taking 52ps as an example, the maximum delay of each I / Odelay is 31 x 50ps = 1.612ns. For example, if the minimum system clock period is 4ns, three I / Odelay modules can be cascaded to achieve a maximum delay of 4.8ns, thus covering delay data within 4ns. The minimum accuracy of the I / O delay module can be achieved. For example, the reference clock REFCLK used for the I / O delay is 300MHz, and the minimum accuracy is 52ps.

[0022] Therefore, the delay time data stored in the register includes the number of system clock cycles and the number of minimum precision of the I / O delay module. When an input trigger pulse is detected, the field programmable gate array outputs each channel through the delay data stored in each channel register.

[0023] Communication between host computer and FPGA:

[0024] The host computer and FPGA communicate via a serial port. Based on the information from the user interface, the host computer calculates the number of system clock cycles that need to be delayed and the number of minimum precision of the I / O delay module, and transmits these two values ​​to the FPGA via the serial port using an agreed protocol. The FPGA updates the register values ​​of each channel based on the received data. Once completed, it can output the corresponding delayed pulse when the next pulse arrives.

[0025] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0026] The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Obviously, many modifications and variations are possible based on the contents of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A multi-channel output pulse synchronization device with adjustable delay time, characterized in that: The invention comprises an FPGA, an SMA connector, a host computer, a serial communication end and an output channel. The FPGA is used as a central controller. A pulse trigger input from the SMA connector end is given to the FPGA, and the output of the FPGA is given to the output channel. The FPGA communicates with the host computer through the serial port to set the delay data in each channel register. When the FPGA receives an input pulse signal, it reads the delay data stored in the register according to the setting of the program and outputs the pulse to the PIN pin of each output channel.

2. A multi-channel output pulse synchronization device with adjustable delay time according to claim 1, characterized in that: The output channels include multiple ones, one pulse trigger input is given to the FPGA, and the output of the FPGA is given to multiple output channels.

3. A multi-channel output pulse synchronization device with adjustable delay time according to claim 1, characterized in that: The synchronization device also includes a power supply, and the output end of the power supply is electrically connected to the FPGA.

4. A multi-channel output pulse synchronization device with adjustable delay time according to claim 1, characterized in that: The multi-channel output pulse synchronization device includes a delay part and a host computer and FPGA communication part. In the delay part, the FPGA selects the system clock. When the delay time is a multiple of the system clock cycle, the delay is achieved by counting the number of rising edges of the system clock. For example, if the system clock is selected as 250MHz, the minimum adjustable delay time accuracy is 4ns.

5. A multi-channel output pulse synchronization device with adjustable delay time according to claim 4, characterized in that: In the delay part, the delay adjustment with smaller precision within the system clock cycle is implemented by instantiating the primitive module I / Odelay provided by FPGA to achieve precise tap coefficient control to adjust the delay. The minimum precision of this module is 52ps, and the number of module delays of 52ps can be set according to the corresponding parameters of the module. A single module can be set with a maximum of 31 minimum precisions, that is, a maximum delay of 1612ps for a module. Multiple modules can be cascaded to achieve a delay time covering the system clock cycle.

6. A multi-channel output pulse synchronization device with adjustable delay time according to claim 4, characterized in that: In the communication part between the host computer and FPGA, the host computer and FPGA communicate with each other via a serial port. The host computer calculates the number of system clock cycles and the number of 52ps to be delayed based on the information of the user interface, and transmits these two values ​​to the FPGA through the serial port using an agreed protocol. The FPGA updates the register values ​​of each channel based on the received data, and after completion, it can output the corresponding delayed pulse when the next pulse arrives.

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