Control circuit and clock synchronization method for serial port transceiver circuit

Abstract

The present application discloses a control circuit and clock synchronization method for a serial port transceiver circuit, belonging to the field of data communication technology. The circuit includes a clock synchronization circuit and a register value generation circuit, wherein the output end of the register value generation circuit is connected to the first input end of a first selector in the transceiver circuit; the clock synchronization circuit outputs a reference clock rising edge based on the received slow reference clock; the register value generation circuit counts the master clock based on the reference clock rising edge and outputs an adaptive baud rate count value; the first selector selects the adaptive baud rate count value and the configuration signal of the register group and outputs a selection signal; the transceiver module drives the data transmission and reception between the register group according to the clock corresponding to the selection signal to adjust the master clock. This circuit can reduce the impact of the deviation between the calculated preset value and the actual value on communication accuracy when the device master clock is unstable.

Description

Technical Field

[0001] The present application belongs to the field of data communication technology, and in particular relates to a control circuit and a clock synchronization method for a serial port transceiver circuit. Background Art

[0002] In recent years, the increasing frequency of data exchange between various electronic devices has led to increasingly higher communication speeds, specifically higher baud rates for serial port protocols. Furthermore, with the rapid development of Artificial Intelligence of Things (AIoT) applications, the operating environment of electronic devices has become increasingly harsh, increasing the impact of the environment on their clock frequencies.

[0003] Therefore, there is a great demand for frequency adaptive asynchronous communication systems. Currently, the baud rate in serial devices is generally determined by calculating the required baud rate register preset value based on the device's main clock frequency, and then using the preset value as the counting cycle to generate pulses for sending and receiving data.

[0004] However, if the device's main clock frequency is unstable, this can cause a deviation between the calculated preset value and the actual value. This deviation is more serious when using a high baud rate, causing the actual baud rate to deviate too much from the preset value, resulting in communication errors. Summary of the Invention

[0005] This application aims to solve at least one of the technical problems existing in the prior art. To this end, this application proposes a control circuit and clock synchronization method for a serial port transceiver circuit, which can reduce the impact of the deviation between the calculated preset value and the actual value on communication accuracy when the device master clock is unstable.

[0006] In a first aspect, the present application provides a control circuit for a serial port transceiver circuit, the circuit comprising a clock synchronization circuit and a register value generation circuit connected in sequence, wherein an output end of the register value generation circuit is connected to a first input end of a first selector in the transceiver circuit;

[0007] The transceiver circuit includes: a register group, a transceiver module and a first selector, wherein the register group is connected to the second input end of the first selector;

[0008] The clock synchronization circuit is used to output a reference clock rising edge according to the received slow reference clock;

[0009] The register value generating circuit is used to count the main clock based on the rising edge of the reference clock and output the adaptive baud rate count value;

[0010] The first selector is configured to select the adaptive baud rate count value and the configuration signal of the register group and output a selection signal;

[0011] The transceiver module is used to drive data transmission and reception between the register group according to the clock corresponding to the selection signal, so as to adjust the main clock.

[0012] According to one embodiment of the present application, a register value generating circuit includes a main clock counter, an adder, a second selector, a clock gating, a sampling register, and a multiplier;

[0013] The clock input end of the master clock counter is connected to the input end of the master clock, and the output end of the master clock counter is connected to the input end of the adder and the data input end of the sampling register respectively;

[0014] The output end of the adder is connected to the input end of the second selector;

[0015] The output end of the second selector is connected to the baud rate selection input end of the main clock counter;

[0016] The first input end of the clock gate is connected to the input of the main clock, and the output end of the clock gate is connected to the clock input end of the sampling register;

[0017] The control terminal of the second selector and the second input terminal of the clock gate are connected to the input of the rising edge of the reference clock;

[0018] The output end of the sampling register is connected to the multiplier, and the output end of the multiplier is connected to the output end of the register value generating circuit.

[0019] According to one embodiment of the present application, the transceiver module includes a pulse generation module and a serial port protocol stack connected in sequence;

[0020] The register group is connected to the serial port protocol stack, and the output end of the first selector is connected to the serial port protocol stack through the pulse generating module;

[0021] A pulse generating module, used for generating transmit and receive pulses according to a selection signal;

[0022] A serial port protocol stack is used to adjust the master clock according to the transceiver pulses.

[0023] According to one embodiment of the present application, the register group includes a control register, a status register, a transmit data register, a receive data register, and a baud rate configuration register;

[0024] The output end of the baud rate configuration register is connected to the second input end of the first selector;

[0025] The control register, status register, send data register, and receive data register are respectively connected to the serial port protocol stack.

[0026] According to one embodiment of the present application, the control register is used to send a control signal to the serial port protocol stack, and the serial port protocol stack returns a status signal to the control register in response to the control signal;

[0027] The sending data register is used to output the sending data value to the serial port protocol stack;

[0028] The received data register is used to output the received data value to the serial port protocol stack;

[0029] The baud rate configuration register is used to send configuration information to the first selector.

[0030] According to one embodiment of the present application, the baud rate configuration register is configured by the user to write the calculation formula:

[0031]

[0032] Where baudrate is the desired baud rate, Fref is the frequency of the slow reference clock, and LPUART_DIV is the value to be written to the baud rate configuration register as configuration information.

[0033] According to one embodiment of the present application, the clock synchronization circuit includes a first trigger, a second trigger, and a third trigger that are cascaded in sequence, as well as an inverter and an AND gate;

[0034] The output end of the third trigger is connected to the input end of the AND gate through the inverter;

[0035] The other input end of the AND gate is connected to the data input end of the third trigger, and the output end of the AND gate is used to output a rising edge of a reference clock.

[0036] According to one embodiment of the present application, the register group is read and written through the address bus, the read data bus and the write data bus to determine the working mode, working status, temporary storage of sent and received data and baud rate preset of the register group.

[0037] According to one embodiment of the present application, the frequency of the slow reference clock is less than or equal to 1 / 3 of the frequency of the master clock.

[0038] In a second aspect, the present application provides a clock synchronization method, which is applied to the control circuit of the serial port transceiver circuit as described in the first aspect above, and the method includes:

[0039] Output the reference clock rising edge according to the received slow reference clock through the clock synchronization circuit;

[0040] Counting the master clock based on the rising edge of the reference clock by a register value generating circuit, and outputting an adaptive baud rate count value;

[0041] Selecting the adaptive baud rate count value and the configuration signal of the register group through a first selector, and outputting a selection signal;

[0042] The transceiver module drives data transmission and reception between the register group according to the clock corresponding to the selection signal, so as to adjust the main clock.

[0043] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application.

[0044] The present application provides a control circuit and clock synchronization method for a serial port transceiver circuit, which have the following advantages over the prior art:

[0045] (1) Through the coordinated work of the clock synchronization circuit, the register value generation circuit, the first selector and the transceiver circuit, the master clock is dynamically adjusted based on the received slow reference clock signal to affect the communication rate. This can effectively cope with the requirements of different baud rates and ensure the reliability and flexibility of serial port data transmission. It is suitable for communication scenarios that require dynamic baud rate adjustment and can well keep the error between the actual baud rate and the expected baud rate within the error specified by the serial port transceiver protocol, thereby ensuring accurate, stable and reliable data transmission and reception. In the case of unstable master clock of the device, the influence of the deviation between the calculated preset value and the actual value on the communication accuracy can be reduced.

[0046] (2) The control circuit structure of the serial port transceiver circuit is simple, with a small area and low power consumption. It can stabilize the baud rate of data transmission and reception when the main clock frequency changes drastically, and the baud rate can be freely configured to cover all currently commonly used baud rates. In particular, when a larger baud rate is required and the clock frequency is unstable, the transceiver circuit can well maintain the error between the actual baud rate and the expected baud rate within the error specified by the serial port transceiver protocol, thereby ensuring accurate, stable and reliable data transmission and reception. It can not only be used as an ordinary serial port under normal conditions, but can also adapt to clock frequency changes under clock deviation in harsh environments to maintain a normal baud rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0048] Figure 1 1 is a schematic structural diagram of a control circuit of a serial port transceiver circuit provided in an embodiment of the present application;

[0049] Figure 2 is a structural diagram of a value generating circuit provided in an embodiment of the present application;

[0050] Figure 3 is a schematic structural diagram of a clock synchronization circuit provided in an embodiment of the present application;

[0051] Figure 4 is a structural diagram of a transceiver circuit provided in an embodiment of the present application;

[0052] Figure 5 Schematic diagram of the clock synchronization method provided in the embodiment of the present application;

[0053] Reference numerals:

[0054] Serial port transceiver circuit control circuit 100; clock synchronization circuit 110; register value generation circuit 120;

[0055] Transceiver circuit 200 ; register group 210 ; transceiver module 220 ; first selector 230 . DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0057] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0058] The control circuit and clock synchronization method of the serial port transceiver circuit provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0059] like Figure 1 As shown, the control circuit 100 of the serial port transceiver circuit includes a clock synchronization circuit 110 and a register value generating circuit 120 connected in sequence, and the output end of the register value generating circuit 120 is connected to the first input end of the first selector in the transceiver circuit 200;

[0060] The transceiver circuit 200 includes: a register group 210, a transceiver module 220 and a first selector 230, wherein the register group is connected to the second input terminal of the first selector;

[0061] The clock synchronization circuit 110 is configured to output a reference clock rising edge according to the received slow reference clock;

[0062] The register value generating circuit 120 is configured to count the master clock based on the rising edge of the reference clock and output an adaptive baud rate count value;

[0063] The first selector is configured to select the adaptive baud rate count value and the configuration signal of the register group and output a selection signal;

[0064] The transceiver module is used to drive data transmission and reception between the register group according to the clock corresponding to the selection signal, so as to adjust the main clock.

[0065] It can be understood that the reference clock is a stable pulse signal, and extracting the rising edge of the reference clock facilitates determining a complete reference clock cycle.

[0066] In serial communication, baud rate is the unit of data transmission rate, usually expressed as the number of bits per second (bps).

[0067] Adaptive Baud Rate Counter: It is used to dynamically adjust the communication rate to ensure the correct reception and transmission of data.

[0068] The control circuit 100 generates a suitable adaptive baud rate count value through the clock synchronization circuit 110 and the register value generation circuit 120 to adjust the clock of the serial port transceiver circuit 200 to adapt to the baud rate requirement of the transceiver circuit 200 .

[0069] The clock synchronization circuit 110 receives an external slow reference clock, extracts the rising edge of the reference clock, determines the frequency of the master clock through the slow reference clock, and provides a basis for adjusting the master clock.

[0070] The clock synchronization circuit 110 receives a slower reference clock from an external device and extracts the rising edge of the reference clock, which serves as a reference in timing and is used to adjust and synchronize the master clock.

[0071] The rising edge of the reference clock is used to control the timing of the subsequent register value generating circuit 120 to ensure that data processing can be carried out stably according to the predetermined timing.

[0072] The register value generating circuit 120 uses the reference clock rising edge and the main clock to determine the number of main clock pulses between two adjacent reference clock rising edges through a counter, and generates an adaptive baud rate count value.

[0073] Among them, the adaptive baud rate count value will automatically adjust according to the actual communication needs to match the baud rate requirements of different devices.

[0074] For example, if the frequency of the master clock is 3 MHz and the frequency of the slow reference clock is 1 MHz, the register value generation circuit generates an adaptive baud rate count value for the transceiver circuit 200 to adjust the master clock and control the baud rate within an appropriate range.

[0075] The transceiver circuit 200 is used to drive the transmission and reception of data according to a selection signal, and includes a register group, a transceiver module and a first selector.

[0076] The first selector selects a suitable clock source from the adaptive baud rate count value and the configuration signal in the register group, and outputs a selection signal according to the state of the selection signal.

[0077] The register group stores configuration data, such as baud rate information, data bits, stop bits, etc. The transceiver module transmits and receives data according to the selection signal.

[0078] The transceiver module determines the clock source to be used according to the selection signal, adjusts the timing of data transmission and reception, and transmits and receives data with the register group.

[0079] For example, when the adaptive baud rate count value is selected, the transceiver module will perform data communication at the adapted baud rate; when the configuration signal is selected, the transceiver module will perform data transmission at the preset baud rate corresponding to the configuration signal.

[0080] According to the control circuit of the serial port transceiver circuit provided in the embodiment of the present application, through the coordinated work of the clock synchronization circuit, the register value generating circuit, the first selector and the transceiver circuit, the master clock is dynamically adjusted based on the received slow reference clock signal to affect the communication rate. It can effectively cope with the requirements of different baud rates, ensure the reliability and flexibility of serial port data transmission, and is suitable for communication scenarios that require dynamic baud rate adjustment. It can well keep the error between the actual baud rate and the expected baud rate within the error specified by the serial port transceiver protocol, thereby ensuring accurate, stable and reliable data transmission and reception. When the main clock of the device is unstable, it can reduce the impact of the deviation between the calculated preset value and the actual value on the communication accuracy.

[0081] In some embodiments, the frequency of the slow reference clock is less than or equal to 1 / 3 of the frequency of the master clock.

[0082] The frequency of the slow reference clock can be set to 1 / 3, 1 / 4 or 1 / 5 of the frequency of the main clock.

[0083] In this embodiment, by setting a reasonable slow reference clock frequency, it is possible to effectively avoid the slow reference clock being too fast, resulting in insufficient adjustment accuracy of the master clock, and the slow reference clock being too slow, resulting in untimely adjustment of the master clock.

[0084] In some embodiments, as Figure 2 As shown, the register value generating circuit 120 includes a main clock counter, an adder, a second selector, a clock gating, a sampling register and a multiplier;

[0085] The clock input end of the master clock counter is connected to the input end of the master clock, and the output end of the master clock counter is connected to the input end of the adder and the data input end of the sampling register respectively;

[0086] The output end of the adder is connected to the input end of the second selector;

[0087] The output end of the second selector is connected to the baud rate selection input end of the main clock counter;

[0088] The first input end of the clock gate is connected to the input of the main clock, and the output end of the clock gate is connected to the clock input end of the sampling register;

[0089] The control terminal of the second selector and the second input terminal of the clock gate are connected to the input of the rising edge of the reference clock;

[0090] The output end of the sampling register is connected to the multiplier, and the output end of the multiplier is connected to the output end of the register value generating circuit 120 .

[0091] The register value generating circuit 120 uses a stable low-frequency slow reference clock as a reference to count the number of main clock cycles within a period of the slow reference clock, and accordingly changes the baud rate register value (adaptive baud rate count value) to achieve the purpose of stabilizing the baud rate.

[0092] The second selector (0,1) selects 0 when each rising edge of the reference clock arrives, and counts according to the main clock (fast clock) at other times.

[0093] Register value generation circuit 120 includes a second counter, a sampling register, and a small-bit multiplier. It counts the high-speed, unstable clock using a slow reference clock, samples each rising edge of the reference clock, and then multiplies the result by a coefficient in the multiplier to obtain the final baud rate register value. As can be seen, regardless of how the fast clock frequency fluctuates, a new baud rate register value can be generated based on the fluctuation, ultimately stabilizing the baud rate.

[0094] The main clock counter input is connected to the signal source of the main clock, and is used to receive the main clock signal, count the cycles of the clock signal, and output the count value for subsequent baud rate calculation.

[0095] The output end of the main clock counter is connected to the input end of the adder and the data input end of the sampling register respectively.

[0096] The input end of the adder is connected to the output end of the main clock counter, and is used to add the output of the main clock counter and 1, and provide the output to the second selector as one of the selectable input signals.

[0097] The control end of the second selector receives a rising edge signal from a reference clock and is used to adjust the baud rate selection and select the output of the adder or 0 as a baud rate selection input signal.

[0098] The input of the second selector receives the output signal of the adder, and the output is connected to the baud rate selection input of the master clock counter. The control end of the second selector receives the rising edge signal of the reference clock, so that the appropriate baud rate value can be selected according to the synchronization information of the reference clock.

[0099] Clock gating controls the clock input of the sampling register according to the rising edge signal of the reference clock, ensuring that the sampling register can be sampled according to the timing of the reference clock to control the transmission of the main clock signal.

[0100] The sampling register samples the count value of the master clock counter at the rising edge of the reference clock. By controlling the input signal of the master clock counter, the corresponding count value is captured and stored each time the rising edge of the reference clock arrives for subsequent baud rate calculation.

[0101] The multiplier is used to calculate a final baud rate count value according to the output of the sampling register, which serves as the adaptive baud rate count value finally output by the register value generating circuit 120 .

[0102] In this embodiment, the register value generating circuit can generate a count value adapted to the baud rate requirement by utilizing modules such as the master clock counter, adder, and sampling register under the control of the reference clock, thereby realizing a flexible baud rate adaptive mechanism. The baud rate is dynamically adjusted according to the coordination of the master clock and the reference clock to provide an appropriate clock signal for the transceiver circuit 200. The baud rate can be dynamically adjusted according to the external reference clock signal, providing precise timing control for the serial port transceiver circuit, and ensuring the stability and reliability of data transmission.

[0103] In some embodiments, as Figure 3 As shown, the transceiver module includes a pulse generating module and a serial port protocol stack connected in sequence;

[0104] The register group is connected to the serial port protocol stack, and the output end of the first selector is connected to the serial port protocol stack through the pulse generating module;

[0105] A pulse generating module, used for generating transmit and receive pulses according to a selection signal;

[0106] A serial port protocol stack is used to adjust the master clock according to the transceiver pulses.

[0107] The transceiver pulse may be a baud tick pulse signal.

[0108] The transceiver module generates appropriate transmit and receive pulses based on the selection signal, thereby dynamically adjusting the main clock frequency to automatically match the baud rate of the serial communication. The serial port protocol stack sends and receives data at the specified baud rate and handles all functions of the communication protocol layer. The pulse generation module generates transmit and receive pulses based on the selection signal and adjusts the frequency of the main clock.

[0109] The register group stores key parameters such as the set baud rate, main clock frequency, selection signal, etc., and transmits the configuration signal to the first selector.

[0110] The first selector selects a suitable input signal according to the control signal and outputs it to the pulse generating module.

[0111] The master clock is the clock source, and the dynamic change of frequency is achieved through the adjustment of the pulse generation module.

[0112] In this embodiment, by integrating the pulse generation module, the serial port protocol stack, the register group and the first selector, the baud rate can be dynamically adjusted according to the external slow reference clock, thereby realizing adaptive control of the serial port baud rate, and being able to flexibly adjust the baud rate according to different communication needs, adapt to different communication rate requirements, and ensure the correctness and efficiency of data transmission.

[0113] In some embodiments, as Figure 3 As shown, the register group includes a control register, a status register, a transmit data register, a receive data register and a baud rate configuration register;

[0114] The output end of the baud rate configuration register is connected to the second input end of the first selector;

[0115] The control register, status register, send data register, and receive data register are respectively connected to the serial port protocol stack.

[0116] In some embodiments, the control register is used to send a control signal to the serial port protocol stack, and the serial port protocol stack returns a status signal to the control register in response to the control signal;

[0117] The sending data register is used to output the sending data value to the serial port protocol stack;

[0118] The received data register is used to output the received data value to the serial port protocol stack;

[0119] The baud rate configuration register is used to send configuration information to the first selector.

[0120] In the register group, through the interaction of the control register, status register, transmit data register, receive data register and serial port protocol stack, the baud rate configuration register controls the sending and receiving of data and the baud rate configuration through the first selector.

[0121] In actual implementation, the receiving and transmitting circuit 200 manages and controls the sending and receiving of data and the configuration of the baud rate through the register group.

[0122] In the register group, the control register is used to send control signals to the serial port protocol stack to configure the working mode and status of the serial port; the status register is used to feedback the working status of the serial port; the send data register outputs the send data value to the serial port protocol stack; the receive data register is used to output the receive data value to the serial port protocol stack; the baud rate configuration register is used to set the baud rate and pass the baud rate setting to the first selector.

[0123] The serial port protocol stack generates transmit and receive pulses according to the configured expected baud rate. The frequency of the transmit and receive pulses determines the actual baud rate.

[0124] The first selector selects a suitable clock frequency input signal according to the baud rate value provided by the baud rate configuration register.

[0125] The baud rate configuration register is used to store a configured baud rate value and provide the value to the first selector as a configuration signal.

[0126] The control signal is sent from the control register to the serial port protocol stack, and the status signal is returned from the serial port protocol stack to the status register to indicate the operation status.

[0127] Each register in the register group is initialized to its default value. In particular, the baud rate configuration register sets the default communication baud rate, the control register sets the default serial port operating mode, and the transmit data register and receive data register prepare corresponding data buffers. When the baud rate needs to be modified, the external controller can programmatically update the baud rate configuration register value.

[0128] An output terminal of the baud rate configuration register is connected to a second input terminal of the first selector to provide a new baud rate configuration.

[0129] The control register can send instructions to the serial port protocol stack through control signals, such as starting data transmission, starting data reception, configuring communication mode, etc. The serial port protocol stack responds to the control signal and performs the corresponding operation.

[0130] After the serial port protocol stack completes the corresponding operation, it will feedback the operation result to the control register through the status signal. For example, the status signal can be data transmission success, data reception completion, error status, etc.

[0131] In this embodiment, by integrating the control register, status register, transmit data register, receive data register and baud rate configuration register into a register group, and cooperating with the serial port protocol stack to control data transmission and reception, through effective management of registers and interaction with the serial port protocol stack, data transmission and baud rate adjustment can be flexibly and efficiently performed in multiple communication modes, providing efficient hardware control and flexible configuration options, and can adapt to various data transmission requirements.

[0132] In some embodiments, the register group is read and written via an address bus, a read data bus, and a write data bus to determine the working mode, working status, temporary storage of received and sent data, and baud rate preset of the register group.

[0133] The register group is read and written via the bus to determine the working mode, working status, temporary storage of received and sent data, and baud rate setting;

[0134] The serial port protocol stack is the physical layer of the serial port protocol, which is used to implement the serial port protocol, including data transmission and reception, data verification and other functions;

[0135] The transceiver module generates a baud tick pulse signal as the transmit and receive pulse through the baud rate configuration register.

[0136] The register bank is read and written via the address bus, read data bus, and write data bus to determine the register bank's operating mode, operating status, temporary storage of transmit and receive data, and baud rate preset. This design is based on a hypothetical hardware platform capable of implementing serial communication functions and using register banks to interact with the system.

[0137] A set of registers is used to manage the configuration and data flow of serial port communication, which can realize the working mode setting (sending mode or receiving mode), working status monitoring (whether it is busy or whether an error occurs), data temporary storage (sending data buffer and receiving data buffer) and baud rate preset (configuring communication baud rate).

[0138] External devices interact with the register group through the address bus, read data bus and write data bus to control the behavior of the serial communication module.

[0139] The external controller specifies the target register address through the address bus, configures the register using the write data bus, or reads the status or data in the register through the read data bus. The controller can realize the baud rate configuration, working mode setting, data sending and receiving, and status monitoring of serial communication.

[0140] In this embodiment, the register group provides a flexible and clear interface to manage different functions of the serial port communication, so that the serial port communication control module can be efficiently and easily managed.

[0141] In some embodiments, the baud rate configuration register is configured by the user and written into the calculation formula:

[0142]

[0143] Where baudrate is the desired baud rate, Fref is the frequency of the slow reference clock, and LPUART_DIV is the value to be written to the baud rate configuration register as configuration information.

[0144] The register group controls the working status of the serial port; the status register stores the working status of the serial port module. The user can read the register to obtain the real-time status of the serial port; the send and receive data registers cache the sent and received data;

[0145] The transceiver module includes the complete protocol stack, including the physical layer and protocol layer of the serial port protocol, and the baud rate generation logic. The protocol stack uses baud rate pulses as signals to transmit and receive data.

[0146] The desired baud rate can be set by the user, and LPUART_DIV is used to determine the final baud rate.

[0147] In some embodiments, as Figure 4 As shown, the clock synchronization circuit 110 includes a first trigger, a second trigger, and a third trigger, which are cascaded in sequence, as well as an inverter and an AND gate;

[0148] The output end of the third trigger is connected to the input end of the AND gate through the inverter;

[0149] The other input end of the AND gate is connected to the data input end of the third trigger, and the output end of the AND gate is used to output a rising edge of a reference clock.

[0150] The clock synchronization module is cascaded through three fixed triggers. All the clock input terminals Clk of the triggers are the faster main clocks, and the first-stage data input terminal D is a slower reference clock with a lower frequency. The slow reference clock and the main clock are synchronized, and then the output of the second-stage trigger and the non-signal output of the third-stage trigger are ANDed through an inverter and an AND gate to extract the rising edge of the reference clock. Since the slow reference clock and the main clock differ in phase by one cycle of the fast clock, the rising edge of the slow reference clock can be extracted and the occurrence of metastable state can be prevented.

[0151] In this embodiment, the control circuit structure of the serial port transceiver circuit is simple, the area is small, and the power consumption is low. It can stabilize the baud rate of data transmission and reception when the main clock frequency changes drastically, and the baud rate can be freely configured to cover all currently commonly used baud rates. In particular, when a larger baud rate is required and the clock frequency is unstable, the transceiver circuit can well maintain the error between the actual baud rate and the expected baud rate within the error specified by the serial port transceiver protocol, thereby ensuring accurate, stable and reliable data transmission and reception. It can not only be used as an ordinary serial port under normal conditions, but can also adapt to clock frequency changes under clock deviations in harsh environments to maintain a normal baud rate.

[0152] The embodiment of the present application also provides a clock synchronization method, which is applied to the control circuit of the serial port transceiver circuit in the above embodiment, such as Figure 5 As shown, the method includes:

[0153] Step 510: Output a reference clock rising edge according to the received slow reference clock through the clock synchronization circuit;

[0154] Step 520: Count the master clock based on the rising edge of the reference clock through the register value generating circuit, and output an adaptive baud rate count value;

[0155] Step 530: Select the adaptive baud rate count value and the configuration signal of the register group through a first selector, and output a selection signal;

[0156] Step 540: Drive data transmission and reception between the transceiver module and the register group according to the clock corresponding to the selection signal to adjust the main clock.

[0157] According to the control circuit of the serial port transceiver circuit provided in the embodiment of the present application, through the coordinated work of the clock synchronization circuit, the register value generating circuit, the first selector and the transceiver circuit, the master clock is dynamically adjusted based on the received slow reference clock signal to affect the communication rate. It can effectively cope with the requirements of different baud rates, ensure the reliability and flexibility of serial port data transmission, and is suitable for communication scenarios that require dynamic baud rate adjustment. It can well keep the error between the actual baud rate and the expected baud rate within the error specified by the serial port transceiver protocol, thereby ensuring accurate, stable and reliable data transmission and reception. When the main clock of the device is unstable, it can reduce the impact of the deviation between the calculated preset value and the actual value on the communication accuracy.

[0158] In the description of this application, "first feature" and "second feature" may include one or more such features.

[0159] In the description of this application, “plurality” means two or more.

[0160] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

[0161] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0162] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A control circuit for a serial port transceiver circuit, characterized in that: It includes a clock synchronization circuit and a register value generating circuit connected in sequence, wherein the output end of the register value generating circuit is connected to the first input end of the first selector in the transceiver circuit; The transceiver circuit includes: a register group, a transceiver module and a first selector, wherein the register group is connected to the second input end of the first selector; The clock synchronization circuit is used to output a reference clock rising edge according to the received slow reference clock; The frequency of the slow reference clock is less than or equal to 1 / 3 of the frequency of the master clock; The register value generating circuit is used to count the main clock based on the rising edge of the reference clock and output the adaptive baud rate count value; The first selector is configured to select the adaptive baud rate count value and the configuration signal of the register group and output a selection signal; The transceiver module is used to drive data transmission and reception between the register group according to the clock corresponding to the selection signal, so as to adjust the main clock.

2. The control circuit of the serial port transceiver circuit according to claim 1, characterized in that: a register value generating circuit, comprising a main clock counter, an adder, a second selector, a clock gating, a sampling register and a multiplier; The clock input end of the master clock counter is connected to the input end of the master clock, and the output end of the master clock counter is connected to the input end of the adder and the data input end of the sampling register respectively; The output end of the adder is connected to the input end of the second selector; The output end of the second selector is connected to the baud rate selection input end of the main clock counter; The first input end of the clock gate is connected to the input of the main clock, and the output end of the clock gate is connected to the clock input end of the sampling register; The control terminal of the second selector and the second input terminal of the clock gate are connected to the input of the rising edge of the reference clock; The output end of the sampling register is connected to the multiplier, and the output end of the multiplier is connected to the output end of the register value generating circuit.

3. The control circuit of the serial port transceiver circuit according to claim 1, wherein: The transceiver module includes a pulse generating module and a serial port protocol stack connected in sequence; The register group is connected to the serial port protocol stack, and the output end of the first selector is connected to the serial port protocol stack through the pulse generating module; A pulse generating module, used for generating transmit and receive pulses according to a selection signal; A serial port protocol stack is used to adjust the master clock according to the transceiver pulses.

4. The control circuit of the serial port transceiver circuit according to claim 3, characterized in that: The register group includes a control register, a status register, a transmit data register, a receive data register and a baud rate configuration register; The output end of the baud rate configuration register is connected to the second input end of the first selector; The control register, status register, send data register, and receive data register are respectively connected to the serial port protocol stack.

5. The control circuit of the serial port transceiver circuit according to claim 4, characterized in that: The control register is used to send a control signal to the serial port protocol stack, and the serial port protocol stack returns a status signal to the control register in response to the control signal; The sending data register is used to output the sending data value to the serial port protocol stack; The received data register is used to output the received data value to the serial port protocol stack; The baud rate configuration register is used to send configuration information to the first selector.

6. The control circuit of the serial port transceiver circuit according to claim 5, characterized in that: The baud rate configuration register is configured by the user and the calculation formula is: ； in, is the desired baud rate, is the frequency of the slow reference clock, The value that needs to be written to the baud rate configuration register as configuration information.

7. The control circuit of the serial port transceiver circuit according to claim 1, characterized in that: The clock synchronization circuit includes a first trigger, a second trigger, and a third trigger connected in cascade sequence, an inverter, and an AND gate; The output end of the third trigger is connected to the input end of the AND gate through the inverter; The other input end of the AND gate is connected to the data input end of the third trigger, and the output end of the AND gate is used to output a rising edge of a reference clock.

8. The control circuit of the serial port transceiver circuit according to claim 1, characterized in that: The register group is read and written via the address bus, the read data bus and the write data bus to determine the working mode, working status, temporary storage of received and sent data and baud rate preset of the register group.

9. A clock synchronization method, characterized in that: The control circuit applied to the serial port transceiver circuit according to any one of claims 1 to 8, the method comprising: Output the reference clock rising edge according to the received slow reference clock through the clock synchronization circuit; The frequency of the slow reference clock is less than or equal to 1 / 3 of the frequency of the master clock; Counting the master clock based on the rising edge of the reference clock by a register value generating circuit, and outputting an adaptive baud rate count value; Selecting the adaptive baud rate count value and the configuration signal of the register group through a first selector, and outputting a selection signal; The transceiver module drives data transmission and reception between the register group according to the clock corresponding to the selection signal, so as to adjust the main clock.

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