Network-on-chip simulation information analysis method, device and equipment and storage medium

Abstract

The invention provides a network-on-chip simulation information analysis method and device, electronic equipment and a computer readable storage medium, when a network-on-chip design file is verified, simulation signal data generated in the verification process is obtained and stored in a hard disk, and when integrity detection is carried out, the simulation signal data are stored in the hard disk; the integrity detection can be realized by reading the simulation data signal stored in the hard disk without keeping communication with the verification platform during the integrity detection, so that the offline analysis of the simulation signal data is realized, and the integrity detection is completed in the offline state without integrating a checker on the verification platform. Therefore, restrictions on resource performance and compatibility when the checker is integrated on the verification platform are avoided, the restrictions can be avoided by using the off-line checker, components integrated on the verification platform are reduced, the system complexity is reduced, the operation efficiency is improved, and meanwhile, due to getting rid of dependence on the verification platform, the verification efficiency is improved. The development mode can be selected more flexibly, and the development cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, electronic device and computer-readable storage medium for analyzing network-on-chip simulation information. Background Art

[0002] When verifying the design files of the Network-on-Chip (NOC), it is necessary to analyze the integrity of the simulation operation when the design files are being simulated, so as to determine whether the various modules designed by the design files work as expected.

[0003] When analyzing the integrity of a simulation run, a checker is needed to collect data for integrity testing, so the checker is often integrated into the verification platform.

[0004] As the functions implemented by design files become more and more complex, the verification platform integrates more and more components, and there are compatibility issues between components, making it difficult to integrate checkers and thus difficult to perform integrity testing. Summary of the invention

[0005] The embodiments of the present application provide a method, device, electronic device and computer-readable storage medium for analyzing network-on-chip simulation information to solve the problems in the related art.

[0006] In a first aspect, an embodiment of the present application provides a method for analyzing network-on-chip simulation information, the method comprising: In the process of verifying the on-chip network design file, the simulation signal data is obtained and stored in the hard disk; the simulation signal data records the signal changes of the on-chip network design file during the simulation operation; Offline analysis of the simulation signal data stored in the hard disk to obtain the corresponding relationship between the request data and the response result in the simulation signal data; According to the corresponding relationship between the request data and the response result, the integrity check of the simulation signal data is performed.

[0007] In a second aspect, an embodiment of the present application provides an on-chip network simulation information analysis device, the device comprising: A storage module is used to obtain simulation signal data and store it in a hard disk during the verification of the on-chip network design file; the simulation signal data records the signal changes of the on-chip network design file during the simulation operation; The parsing module is used to parse the simulation signal data stored in the hard disk offline to obtain the corresponding relationship between the request data and the response result in the simulation signal data; The integrity detection module is used to perform integrity detection of the simulation signal data according to the corresponding relationship between the request data and the response result.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of one or more methods described in the embodiments of the present application are implemented.

[0009] In a fourth aspect, an embodiment of the present application provides a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute one or more methods described in the embodiments of the present application.

[0010] In an embodiment of the present application, when verifying the on-chip network design file, the simulation signal data generated in the verification process is obtained and stored in the hard disk. When performing integrity testing, the simulation data signal stored in the hard disk is read to implement integrity testing. There is no need to maintain communication with the verification platform during the integrity test, thereby realizing offline analysis of the simulation signal data. Completing the integrity test in an offline state does not require the checker to be integrated on the verification platform, thereby avoiding the constraints of interface protocols, system complexity, resource performance and compatibility that are imposed on the checker when integrated on the verification platform. Using an offline checker can avoid the above constraints, thereby reducing the components integrated on the verification platform, reducing system complexity, and improving operating efficiency. At the same time, because it is free from dependence on the verification platform, it is possible to more flexibly choose development methods and reduce development costs.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0013] Figure 1 It is a flowchart of the steps of a method for analyzing network-on-chip simulation information provided by an embodiment of the present application; Figure 2 is a flowchart of another method for analyzing network-on-chip simulation information provided by an embodiment of the present application; Figure 3 This is a data analysis schematic diagram provided in an embodiment of the present application; Figure 4 This is an integrity detection flow chart provided by an embodiment of the present application; Figure 5 is a performance analysis flow chart provided in an embodiment of the present application; Figure 6 It is a flow chart of network-on-chip simulation information analysis provided by an embodiment of the present application; Figure 7 It is a block diagram of an on-chip network simulation information analysis device provided in an embodiment of the present application; Figure 8 is a block diagram of an electronic device provided in an embodiment of the present application; Fig. 9 It is a block diagram of another electronic device according to another embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0016] With the rapid development of semiconductor technology, the scale of multi-core processors and system-level chips continues to expand. As the core communication infrastructure in multi-core systems, the network on chip (NoC) undertakes the important tasks of inter-core data exchange and system collaboration. However, with the improvement of chip integration and the reduction of process size, the network on chip faces increasingly severe signal integrity challenges. Specifically, due to the influence of process deviations, electromagnetic interference, crosstalk noise and other factors, bit errors, timing deviations, routing failures and other problems may occur during data transmission, and in severe cases, even system function failures. Therefore, how to effectively verify the integrity of the network on chip and ensure the correctness, consistency and reliability of data transmission has become a technical problem that needs to be solved urgently in this field.

[0017] In some related technologies, the verification method based on simulation simulates the behavior of the on-chip network to verify the correctness of data transmission and the functional integrity. Through hardware description languages, such as SystemVerilog, an accurate model of the on-chip network is constructed. Designers make accurate logical descriptions based on the various components in the on-chip network, such as routers, links, processing units, etc., to form a complete hardware model. For example, for router components, HDL code is used to describe its routing algorithm, data packet forwarding logic, and cache mechanism. At the same time, when verifying the on-chip network design file, it is necessary to integrate the checker to collect simulation signal data, so as to complete the integrity detection of the simulation signal data. However, when integrating the checker, due to the large number of components of the verification platform, the checker is restricted by compatibility and other reasons. Integration on the verification platform will cause the verification platform to reduce its operating efficiency. At the same time, after the integrity detection, the on-chip network design file is analyzed again. When determining the cause of the problem, other components need to be integrated, which further reduces the efficiency of the on-chip network verification.

[0018] Figure 1 is a flowchart of a method for analyzing network-on-chip simulation information provided by an embodiment of the present application. Figure 1 As shown, the method may include: Step 101 , in the process of verifying the on-chip network design file, obtaining simulation signal data and storing it in a hard disk.

[0019] Among them, the simulation signal data records the signal changes of the on-chip network design file during the simulation operation. During the operation of the on-chip network, each node and link will generate various electrical signals, such as clock signals, data signals, control signals, etc. By recording and storing these signals that change over time, it is convenient for subsequent analysis of the working status and performance of the on-chip network.

[0020] In some embodiments, a waveform file is used as simulation signal data. A waveform file is a file used to record and store the time-varying conditions of electrical signals. It is widely used in electronic design, testing, verification, and other fields. The waveform file uses a specific data structure and format to record the amplitude values ​​of electrical signals (such as voltage, current, etc.) in continuous time in chronological order, so that people can intuitively observe and analyze the characteristics of the signal, such as frequency, amplitude, phase, pulse width, etc.

[0021] In an embodiment of the present application, during the verification of the on-chip network design file, the acquired simulation signal data is stored in a hard disk, so that the simulation signal data can be permanently saved. When the integrity check of the simulation signal data is required, it can be read from the hard disk, thereby reducing the real-time data transmission between the verification platform and the checker that implements the integrity check, thereby alleviating the data transmission pressure during the verification of the on-chip network design file, investing more performance resources in the verification process, and improving the verification efficiency.

[0022] Step 102: offline analyze the simulation signal data stored in the hard disk to obtain the corresponding relationship between the request data and the response result in the simulation signal data.

[0023] Among them, the simulation signal data is the constantly changing signal data generated when the on-chip network design file is verified. The data type of the simulation signal data can be divided into request type, response type, transmission type and listening type. The simulation signal data of the request type is the request data, and the response results corresponding to the request data are scattered in other data in the simulation signal data except the request data.

[0024] In an embodiment of the present application, offline reading of the simulation signal data is completely realized by offline parsing the simulation signal data stored in the hard disk. Therefore, when the simulation signal data is obtained offline, offline integrity detection can be realized. When performing integrity detection, there is no need to transmit real-time data with the verification platform. Therefore, there is no need to integrate a checker in the verification platform, thereby avoiding concessions for compatibility, performance, resources, interface protocols and system complexity due to the integration of the checker in the verification platform. Not only the labor cost of the integrated checker is reduced, but also the complexity of the verification platform is reduced, the operating efficiency is improved, and the cost of debugging is reduced due to the simplification of the components integrated on the verification platform.

[0025] In some embodiments, since there is no need to integrate a checker on the verification platform, there is no need to develop a checker using a hardware description language bound to the on-chip network framework as in the related art, and the function of performing offline integrity detection can be developed in a variety of ways. For example, the integrity detection function can be developed using the Python language. Compared with the hardware description language bound to the on-chip network framework, Python as a software language has richer open source resources, which facilitates the implementation of more complex logical functions, thereby reducing R&D costs.

[0026] Step 103: Perform integrity detection of the simulation signal data according to the corresponding relationship between the request data and the response result.

[0027] It should be noted that the integrity detection of simulation signal data is a key technical means to ensure the normal and efficient operation of the network on chip (NoC), which is of great significance in the field of integrated circuit design. From the perspective of functional integrity, it is necessary to verify whether the network on chip can accurately transmit data according to established protocols and rules. It is necessary to ensure the accurate transmission of data packets from the source node to the target node, eliminate data loss, errors or disorder, and ensure the normal functioning of functions such as routing and flow control. For example, in a multi-core processor chip, the data interaction between the cores depends on the network on chip. If the function is incomplete, the calculation result will be wrong; from the performance integrity aspect, the main evaluation is whether the performance indicators of the network on chip meet the design requirements. Bandwidth utilization, delay time and throughput are all key indicators. High bandwidth utilization means that the network can make full use of resources, low latency can ensure fast data transmission, and sufficient throughput can meet the processing needs of large amounts of data. For example, in image and video processing chips, if the performance of the network on chip is poor, problems such as screen freeze will occur; reliability focuses on the ability of the network on chip to cope with interference and anomalies. It needs to have an effective error detection and correction mechanism that can automatically adjust the route when some nodes or links fail to maintain the continuity of communication. For example, for chips working in complex electromagnetic environments, a reliable on-chip network can ensure that data transmission is not interfered with.

[0028] In the embodiment of the present application, the request data in the simulation signal data is parsed, including the key information such as the source address, destination address, data content, and timestamp of the request, and then a format check is performed. According to the communication protocol adopted by the on-chip network, the format of the request data is checked to see whether it is compliant. Finally, it is analyzed whether the request data has a response return and whether there is data returned. Specifically, it is necessary to carefully analyze whether the request data has a response return. If there is a response, further check whether it carries valid data. At the same time, it is necessary to pay attention to whether the request data triggers a retry request. When the request data has neither a retry return nor other forms of response return, this is very likely to mean that there are problems such as communication failures, node anomalies, or protocol errors in the on-chip network. At this time, the error handling mechanism should be started immediately, and the error information should be accurately recorded, including the characteristics of the request data, the time of occurrence, etc., so as to facilitate subsequent in-depth investigation and repair to ensure the stable and reliable operation of the on-chip network.

[0029] Among them, retry is an important mechanism to deal with abnormal data transmission and ensure communication reliability. The retry mechanism means that during the data transmission process, when the sender detects that the data packet has not been successfully transmitted to the receiver, it will resend the data packet until the data is correctly received or the maximum number of retries is reached. Although retry ensures the stability of communication, because each retry requires additional time, it increases the delay of data transmission, and also occupies a certain amount of network bandwidth resources, reducing the overall efficiency of the network.

[0030] In summary, in the embodiments of the present application, when verifying the on-chip network design file, the simulation signal data generated during the verification process is obtained and stored in the hard disk. When performing integrity testing, the simulation data signal stored in the hard disk is read to implement integrity testing. There is no need to maintain communication with the verification platform during the integrity test, thereby realizing offline analysis of the simulation signal data. Completing the integrity test in an offline state does not require the checker to be integrated on the verification platform, thereby avoiding the constraints of interface protocols, system complexity, resources, performance and compatibility that are imposed on the checker when integrated on the verification platform. Using an offline checker can avoid the above constraints, thereby reducing the components integrated on the verification platform, reducing system complexity, and improving operating efficiency. At the same time, because it is free from dependence on the verification platform, it is possible to more flexibly choose development methods and reduce development costs.

[0031] Figure 2 , is a flowchart of the specific steps of a method for analyzing network-on-chip simulation information provided by an embodiment of the present application, such as Figure 2 As shown, the method may include: Step 201, in the process of verifying the on-chip network design file, obtain simulation signal data and store it in a hard disk. The simulation signal data records the signal changes of the on-chip network design file during the simulation operation.

[0032] This step may specifically refer to the above step 101, which will not be described in detail here.

[0033] Optionally, step 201 may specifically include: Sub-step 2011, detecting the clock signal of the on-chip network.

[0034] Sub-step 2012, when the clock signal jumps from a low level to a high level, detecting the control signal of the simulation signal data. The high level indicates that the simulation task is in the execution end state, thereby ensuring that the simulation signal data is in a data consistency state.

[0035] Sub-step 2013, when the control signal of the simulation signal data is in a valid state, reading the simulation signal data from the verification platform and storing it in the hard disk.

[0036] For sub-steps 2011 to 2013, the clock signal of the on-chip network is a periodic electrical signal that provides a unified time reference for each component of the on-chip network. It is generated by a clock generator and changes with a fixed frequency and phase. During data transmission, the receiving end needs to sample the data at the appropriate time, and the clock signal is required to provide an accurate time point for data sampling. In addition, the status of each module of the on-chip network also needs to be converted and updated according to the clock signal. For example, the cache module determines when to write new data or read out stored data based on the clock signal to maintain the correct reading and writing order of data.

[0037] In an embodiment of the present application, the change characteristics of the clock signal are detected. The clock signal has two signal characteristics: a rising edge and a falling edge. The rising edge refers to the clock signal jumping from a low level to a high level, and the falling edge refers to the clock signal jumping from a high level to a low level. The present application detects the rising edge characteristics of the clock signal. In some embodiments, the falling edge characteristics can also be detected. This application does not make any limitation here.

[0038] It should be noted that the rising edge and the falling edge are the key moments of the clock signal change, which can provide a unified time reference for each module. By triggering the sampling, storage or transmission operation of data at the rising edge or the falling edge, each module can work at the same beat to avoid data confusion caused by time inconsistency. For example, in a synchronous circuit of an on-chip network, multiple components can sample the input simulation signal data at the rising edge of the clock signal at the same time, ensuring that the simulation signal data obtained by each component is at the same time, thereby maintaining the consistency of the simulation signal data.

[0039] In addition, the control signal (valid) of the simulation signal data is used to indicate whether the data is valid. During the data transmission process of the on-chip network, the simulation signal data is not valid in every clock cycle. As a control flag, the control signal clearly indicates whether the simulation signal data transmitted at the current moment is meaningful. When the control signal is in a valid state, it indicates that the simulation signal data transmitted at this time is valid and can be sampled and subsequently processed; when the control signal is in an invalid state, it means that the current simulation signal data may be random, uninitialized or useless, and no sampling operation is performed at this time, thereby avoiding processing of invalid data and saving system resources.

[0040] In an embodiment of the present application, the simulation signal data is sampled when the clock signal jumps from a low level to a high level to ensure that the received simulation signal data is consistent with the data received by other components. At the same time, sampling is performed when the control signal of the simulation signal data is in a valid state to ensure the validity of the sampled simulation signal data and increase the reliability of the sampled data.

[0041] Optionally, step 201 may specifically include: Sub-step 2014, acquiring data units constituting the simulation signal data, and recording the acquisition time of each data unit.

[0042] Sub-step 2015, arranging the data units in the time sequence of the acquisition moments, obtaining the simulation signal data and storing them in the hard disk.

[0043] For sub-steps 2014 and 2015, when transmitting simulation signal data in the on-chip network, since the simulation signal data is too long, in order to facilitate routing and transmission in the on-chip network, the simulation signal data is divided into basic division units that are easy to transmit, namely data units (flits). The smaller flit size makes the router more flexible and efficient when making routing decisions. The router can quickly determine the forwarding direction of each flit based on the header information of each flit without waiting for the arrival of the entire data packet, thereby improving the throughput and response speed of the network. In addition, in the on-chip network, bandwidth resources are limited, and data transmission in units of flits can be more finely allocated and managed. For example, when a link is congested, only the transmission of the current flit can be suspended without affecting the scheduling of other flits.

[0044] In the embodiment of the present application, when flits are obtained, the acquisition time of each flit is recorded at the same time. For example, the obtained data format is in the form of "time + data unit". By sorting the recorded acquisition times, the flit with correct timing can be obtained, and these flits can be integrated together to obtain simulation signal data, and the simulation signal data is stored in the hard disk.

[0045] Step 202: offline analyze the simulation signal data stored in the hard disk to obtain the corresponding relationship between the request data and the response result in the simulation signal data.

[0046] This step may be specifically referred to as the above step 102, which will not be described in detail here.

[0047] Optionally, step 202 may specifically include: Sub-step 2021, classifying the simulation signal data according to data type.

[0048] Sub-step 2022: according to the data type, the simulation signal data is split and stored in files corresponding to the data type. The files include request files, response files, transmission files and listening files.

[0049] Sub-step 2023, read the request file to obtain the request data.

[0050] For sub-steps 2021 to 2023, if Figure 3 As shown, when storing the simulation signal data of the on-chip network, the number of simulation signals can be split according to the organization method of the on-chip network design concept and architecture, that is, the hierarchy, and the corresponding data types such as request type, transmission type, response type and listening type included in the simulation signal are stored in the corresponding request file, response file, transmission file and listening file.

[0051] In an embodiment of the present application, when performing an integrity check on the simulation signal data, it is necessary to obtain the request data in the simulation signal data, and query whether there is a response result corresponding to the request data in the remaining data of the simulation signal data. The integrity check is performed based on the request data and its corresponding response result. When obtaining the request data in the simulation signal data, it is sufficient to read the data content stored in the request file.

[0052] Step 203, according to the correspondence between the request data and the response results, count the request data with corresponding response results and the target request data without corresponding response results from all the request data, and locate the position of the target request data in the simulation signal data.

[0053] In the embodiment of the present application, according to the corresponding relationship between the request data and the response result, the request data with the corresponding response result is counted from the request data, wherein the response result records the information such as the request data obtaining the corresponding delay value, which is used for integrity detection. In addition, there is a request result that does not have a corresponding response result after querying. At this time, the reason for the request data not being responded to needs to be investigated, and the request data is used as the target request data to be located in the simulation signal data.

[0054] It should be noted that when determining the request data and the corresponding response results for integrity detection, it is necessary to determine the delay value of the request data, the request retry, and the incomplete request, which will affect the performance and reliability of the on-chip network. The delay value refers to the time it takes for the request data to be transmitted from the source node to the target node in the on-chip network, which includes the time for transmission in the link, the time for routing decisions and queuing in the router, etc.; request retry is a mechanism to deal with abnormal data transmission. When the sender detects that the request data has not been successfully transmitted to the receiver, it will resend the request data until the request data is correctly received or the maximum number of retries is reached; the incomplete request (outstanding) means that the request data is in an "incomplete", "unprocessed" or "unresponsive" state. When a request data is sent out, before the corresponding response is received, the request is called an "outstanding" request; for the request data being transmitted, it is also in an "outstanding" state before it reaches the destination and is confirmed.

[0055] In some embodiments, integrity analysis is performed on the delay value of request data in obtaining a response result, request retries, and incomplete requests, so that it can be detected whether the delay value is stable and reasonable when the request data is transmitted in the on-chip network, thereby ensuring the efficient operation of the on-chip network. By detecting the integrity of the delay value, congestion points, link failures and other problems can be discovered in a timely manner, which helps to optimize the on-chip network topology and routing algorithms and improve the overall performance of the on-chip network; by performing integrity detection on request retries, the root causes of data transmission errors, such as link noise, node failures, etc., can be found, and targeted measures can be taken to solve them and improve the reliability of the network; by performing integrity detection on incomplete requests, network resources can be effectively managed, network congestion can be avoided, and the stable operation of the network can be ensured.

[0056] For example, for applications with high real-time requirements, the delay value needs to be strictly controlled within a very small range. When the network load suddenly increases, the delay value may increase accordingly, but it should be within an acceptable range.

[0057] Optionally, the request data includes a first target field for searching for a corresponding response result, wherein the first target field represents a task identifier of the request data. Step 203 may specifically include: Sub-step 2031, setting the concurrent quantity.

[0058] Sub-step 2032, for one of the query tasks executed simultaneously, the request data is sent to the data tracking process to obtain a completion signal of the current query task.

[0059] Sub-step 2033, when a corresponding response result is found according to the first target field of the request data, the tracking process converts the completion signal into a completed signal.

[0060] With respect to sub-steps 2031-2033, in the embodiment of the present application, the simulation signal data is stored in the hard disk, and is also read from the hard disk when reading, so that the offline integrity detection of the simulation signal data is realized. Therefore, the function of integrity detection does not need to be integrated in the on-chip network, and the integrity detection can be realized offline through python. By setting the number of concurrent tasks, the number of query tasks executed simultaneously is controlled. The query task is a task to find the response result according to the request data. The outstanding status of the request sent by the central processing unit (CPU) is simulated, so that the offline integrity detection is closer to the actual situation, and the outstanding status of the request data is obtained, so as to evaluate the on-chip network design file more comprehensively.

[0061] In an embodiment of the present application, the request data is sent to the tracking process, and the tracking process tracks the response result corresponding to the request data in the current query task. In the current query task (transaction), there is a unique number assigned to the current transaction, namely, the transaction identifier (txnid, Transaction ID). This transaction identifier remains unchanged throughout the life cycle of the query task and is used to uniquely identify the query task in the integrity test. Among them, the first target field can be a transaction identifier. When the corresponding response result is found according to the first target field of the request data, the tracking process converts the completion signal to completed, and completes the query task to find the response result corresponding to the request data through the tracking process, thereby increasing the cohesion of the tracking process.

[0062] like Figure 4The figure shows the integrity detection flow chart. After reading the corresponding types of data from the four files, they are stored in the buffer queue, and the request data is sent to the tracking process. The tracking process searches for the response results in other types of data according to the first target field, and the corresponding relationship between the searched request data and the response results is sent to the integrity detection module for detection, and finally the integrity report is exported.

[0063] Optionally, the method further includes: Sub-step 2034, when the corresponding response result is not found from the first target field of the request data, the tracking process converts the completion signal into an incomplete signal.

[0064] Sub-step 2035: marking the request data with the incomplete signal as the target request data, and locating the request position of the target request data.

[0065] For sub-steps 2034-2035, when the corresponding response result is not found according to the first target field of the request data, it indicates that the request data at this time may have exceeded the maximum number of request retries, or the request data has been in an unfinished state for a long time, and there may be a problem with the request. The tracking process converts the completion signal that does not find the corresponding response result into an unfinished signal. Since the request data at this time deviates greatly from expectations, the request data is used as the target request data, and the request position of the target request data is preliminarily located, so as to subsequently investigate the reasons for the unexpected situation.

[0066] Optionally, the request data includes a second target field for searching for a corresponding response result, and the method further includes: Sub-step 2036, when executing the query task, when the corresponding response result is found according to the first target field or the second target field of the request data, the tracking process converts the completion signal into a completed signal.

[0067] Sub-step 2037, when no corresponding response result is found according to the first target field and the second target field of the request data, the tracking process converts the completion signal into an incomplete signal.

[0068] For sub-steps 2036 and 2037, in the query task of the network on chip, the query task also includes a database identifier (dbid, Database ID), which is a unique identifier used to identify the database or data storage area associated with the query task. The dbid can be used to quickly and accurately locate the specific database or storage area where the data to be accessed is located. For example, if a transaction needs to read a specific type of data, the dbid can be used to directly find the database that stores the data of this type, thereby improving data access efficiency. The second target field can be a database identifier.

[0069] In an embodiment of the present application, the corresponding response result of the request data is searched by using the first target field and the second target field, which is similar to using the first target field to search for the response result. When the corresponding response result is found according to the first target field and the second target field, the tracking process converts the completion signal into a completed signal. When the corresponding response result is not found, the tracking process converts the completion signal into an uncompleted signal. Searching through two target fields can shorten the search process and improve operating efficiency.

[0070] For example, first use the database identifier (dbid) of the requested data to find the database storing the corresponding response data, and then use the transaction identifier (txnid) to search, avoiding invalid searches in areas where no response results are stored, shortening the time required for searches and improving search efficiency.

[0071] Optionally, the method further includes: Step 204: All the request data are sent to a performance statistics module, and the performance data of all the request data are counted by the performance statistics module.

[0072] Among them, the performance statistics module is used to receive request data and count the performance data of all request data. The performance data includes the delay value of the request data to receive a response, the retry status of the request data, the incomplete status of the request data, data throughput, packet loss rate, and broadband utilization, etc.

[0073] In the embodiment of the present application, by counting the performance data of all request data, the quality and stability of data transmission during on-chip network verification can be mastered. By analyzing the delay value, the efficiency of the system in the data transmission process can be understood, and the performance bottlenecks that may exist in the system, such as network congestion, insufficient device processing capacity, etc., can also be found; the number and frequency of retries can be analyzed to understand the reliability of data transmission in the system. If the number of retries is too many, it may indicate that the network environment is unstable, the device has a fault, or the protocol design is unreasonable. Analyzing the number and status of unfinished request data helps to reasonably allocate system resources, and can evaluate and optimize the processing capacity of the system to ensure that the system can efficiently process various requests. Analyzing the throughput can evaluate the overall performance and processing capacity of the system and determine whether the system meets business needs. Analyzing the packet loss rate can find out the reasons for packet loss, such as network interference, link failure, etc., and take corresponding measures to repair and optimize, so as to improve the reliability of data transmission. Analyzing the bandwidth utilization rate can understand whether the network bandwidth has been fully utilized and whether there is a waste or shortage of resources.

[0074] Step 205 , analyzing the on-chip network design file according to the request location of the request data for which no corresponding response result is obtained in the integrity detection and the performance data, to obtain a performance analysis result.

[0075] In an embodiment of the present application, the request location is determined based on the request data for which the corresponding response result is not obtained. There may be certain problems at the request location that lead to no response result. Combined with the performance data, the on-chip network design file can be analyzed to find out the reason for the lack of response result. The design file can be analyzed to see whether there is an unreasonable design and whether there are faults and interferences in the design based on the retry situation and packet loss rate of the request data. By analyzing performance data such as the retry situation and packet loss rate, the reliability of on-chip network data transmission can be improved. By analyzing performance data such as the incomplete status of request data and bandwidth utilization, the resource allocation strategy can be optimized to improve system operation efficiency.

[0076] like Figure 5 The figure shows the performance analysis flow chart. After reading the corresponding types of data from the four files, they are stored in the buffer queue, and the request data is sent to the global counting module. The performance data of the simulation running data is obtained through the global counting module, and all the performance data are sent to the performance statistics module for integration, and finally the performance analysis report is exported.

[0077] Step 206: Determine defects in the on-chip network design file based on the performance analysis result.

[0078] In some embodiments, to perform performance analysis on the simulation signal data of the on-chip network design file, it is necessary to integrate a performance analysis component in addition to the checker component integrated on the verification platform to realize the function of analyzing performance. The more components integrated on the verification platform, the greater the compatibility impact. At the same time, the complexity of verification will also increase, affecting the verification efficiency. The present application realizes offline analysis by performing offline integrity detection on the simulation signal data and offline statistics on the performance data of the simulation signal data. There is no need for real-time data interaction with the verification platform. Therefore, there is no need to integrate a performance analysis component on the verification platform, which reduces the burden on the verification platform integrated components and optimizes the operating efficiency of the verification environment.

[0079] like Figure 6 The figure shows a flow chart for implementing integrity detection and performance analysis. After collecting the simulation signal data generated by the verification environment, the simulation signal data is parsed and then integrity detection and performance analysis are performed. The location of the request where the corresponding response data is not found is obtained through integrity detection, and the problem location of not finding the corresponding response data is sent to the performance problem location module. Combined with the performance data in the module, the defects of the on-chip network design file are finally analyzed and optimized.

[0080] In summary, in the embodiments of the present application, when verifying the on-chip network design file, the simulation signal data generated in the verification process is obtained and stored in the hard disk. When performing integrity testing, the simulation signal data stored in the hard disk is read to implement integrity testing. There is no need to maintain communication with the verification platform during the integrity test, thereby realizing offline parsing of the simulation signal data and using the simulation signal data for offline performance analysis. Completing the integrity test and performance analysis in an offline state does not require the checker to be integrated on the verification platform, thereby reducing the burden of integrating the checker and performance analysis components on the verification platform. There is no need to consider the compatibility, interface protocols, etc. considered when integrating the checker and performance analysis components, thereby reducing development costs and getting rid of dependence on the verification platform. The development method can be selected more flexibly. At the same time, due to the reduction of components integrated on the verification platform, the system complexity is reduced and the operating efficiency is improved.

[0081] Figure 7 : is a block diagram of an on-chip network simulation information analysis device provided by an embodiment of the present application, the device comprising: The storage module 301 is used to obtain simulation signal data and store it in a hard disk during the verification of the on-chip network design file. The simulation signal data records the signal changes of the on-chip network design file during the simulation operation.

[0082] The analysis module 302 is used to analyze the simulation signal data stored in the hard disk offline to obtain the corresponding relationship between the request data and the response result in the simulation signal data.

[0083] The integrity detection module 303 is used to perform integrity detection of the simulation signal data according to the corresponding relationship between the request data and the response result.

[0084] Optionally, the integrity detection module 303 may specifically include: An integrity detection submodule, for counting the request data with corresponding response results and the target request data without corresponding response results from all the request data according to the corresponding relationship between the request data and the response results, and locating the position of the target request data in the simulation signal data Optionally, the storage module 301 may specifically include: The clock submodule is used to detect the clock signal of the on-chip network.

[0085] The high level submodule is used to detect the control signal of the simulation signal data when the clock signal jumps from a low level to a high level. The high level indicates that the simulation task is in the execution end state, thereby ensuring that the simulation signal data is in a data consistency state.

[0086] The valid state submodule is used to read the simulation signal data from the verification platform and store it in the hard disk when the control signal of the simulation signal data is in a valid state.

[0087] Optionally, the storage module 301 may specifically include: The data unit submodule is used to obtain the data units constituting the simulation signal data and record the acquisition time of each data unit. The data unit is the smallest division unit for transmitting the simulation signal data.

[0088] The storage submodule is used to arrange the data units in the time sequence of the acquisition moments, obtain the simulation signal data and store them in a hard disk.

[0089] Optionally, the parsing module 302 may specifically include: The data type submodule is used to classify the simulation signal data according to data types. The data types include request type, transmission type, response type and listening type.

[0090] The classification storage submodule is used to split the simulation signal data according to the data type and store them in files corresponding to the data type. The files include request files, response files, transmission files and listening files.

[0091] The request reading submodule is used to read the request file and obtain the request data.

[0092] Optionally, the integrity detection submodule may specifically include: The concurrency unit is used to set the concurrency number, and the concurrency number is used to control the number of query tasks executed simultaneously. The query task is a task to find the response result according to the request data.

[0093] The query unit is used to send the request data to the data tracking process for one of the query tasks executed simultaneously, and obtain a completion signal of the current query task.

[0094] The first completed unit is used for converting the completion signal into a completed signal by the tracking process when a corresponding response result is found according to the first target field of the request data.

[0095] Optionally, the device further comprises: The first incomplete unit is used for, when the corresponding response result is not found from the first target field of the request data, the tracking process converts the completion signal into an incomplete signal.

[0096] The positioning unit is used to mark the request data with the incomplete signal as the target request data and locate the request position of the target request data.

[0097] Optionally, the device further comprises: The second completed unit is used for converting the completion signal into a completed signal by the tracking process when the corresponding response result is found according to the first target field or the second target field of the request data when the query task is executed.

[0098] The second incomplete unit is configured to convert the completion signal into an incomplete signal by the tracking process when no corresponding response result is found according to the first target field and the second target field of the request data.

[0099] Optionally, the device further comprises: The performance statistics module is used to send all the request data to the performance statistics module, and the performance data of all the request data is counted by the performance statistics module.

[0100] The performance analysis module is used to analyze the on-chip network design file according to the request position of the request data that has not obtained a corresponding response result in the integrity detection and the performance data to obtain a performance analysis result.

[0101] The troubleshooting module is used to determine defects in the on-chip network design file according to the performance analysis result.

[0102] In summary, in the embodiments of the present application, when verifying the on-chip network design file, the simulation signal data generated during the verification process is obtained and stored in the hard disk. When performing integrity testing, the simulation data signal stored in the hard disk is read to implement integrity testing. There is no need to maintain communication with the verification platform during the integrity test, thereby realizing offline analysis of the simulation signal data. Completing the integrity test in an offline state does not require the checker to be integrated on the verification platform, thereby avoiding the constraints of interface protocols, system complexity, resource performance and compatibility that are imposed on the checker when integrated on the verification platform. Using an offline checker can avoid the above constraints, thereby reducing the components integrated on the verification platform, reducing system complexity, and improving operating efficiency. At the same time, because it is free from dependence on the verification platform, it is possible to more flexibly choose development methods and reduce development costs.

[0103] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0104] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0105] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0106] An embodiment of the present application provides a data row protection device for a dynamic random access memory, comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the methods described in the above-mentioned embodiments.

[0107] Figure 8 is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0108] Reference Figure 8 , the electronic device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output (I / O) interface 612 , a sensor component 614 , and a communication component 616 .

[0109] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0110] The memory 604 is used to store various types of data to support the operation of the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, multimedia, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0111] The power supply component 606 provides power to the various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 600.

[0112] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0113] The audio component 610 is used to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), and when the electronic device 600 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0114] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0115] The sensor assembly 614 includes one or more sensors for providing various aspects of status assessment for the electronic device 600. For example, the sensor assembly 614 can detect the open / closed state of the electronic device 600, the relative positioning of the components, such as the display and keypad of the electronic device 600, and the sensor assembly 614 can also detect the position change of the electronic device 600 or a component of the electronic device 600, the presence or absence of contact between the user and the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 614 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0116] The communication component 616 is used to facilitate wired or wireless communication between the electronic device 600 and other devices. The electronic device 600 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0117] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0118] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the instructions can be executed by a processor 620 of an electronic device 600 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0119] Fig. 9 is a block diagram of an electronic device 700 according to an exemplary embodiment. For example, the electronic device 700 may be provided as a server. Fig. 9 The electronic device 700 includes a processing component 722, which further includes one or more processors, and a memory resource represented by a memory 732 for storing instructions that can be executed by the processing component 722, such as an application. The application stored in the memory 732 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0120] The electronic device 700 may also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input / output (I / O) interface 758. The electronic device 700 may operate based on an operating system stored in the memory 732, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, FreeBSD TM or the like.

[0121] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0122] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0123] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for analyzing network-on-chip simulation information, characterized in that: The method comprises: In the process of verifying the on-chip network design file, the simulation signal data is obtained and stored in the hard disk; the simulation signal data records the signal changes of the on-chip network design file during the simulation operation; Offline analysis of the simulation signal data stored in the hard disk to obtain the corresponding relationship between the request data and the response result in the simulation signal data; According to the corresponding relationship between the request data and the response result, the integrity check of the simulation signal data is performed.

2. The method according to claim 1, characterized in that The integrity detection of the simulation signal data is performed according to the corresponding relationship between the request data and the response result, including: According to the correspondence between the request data and the response results, the request data with corresponding response results and the target request data without corresponding response results are counted from all the request data, and the position of the target request data in the simulation signal data is located.

3. The method according to claim 1, characterized in that In the process of verifying the on-chip network design file, obtaining the simulation signal data and storing it in the hard disk includes: Detecting a clock signal of the on-chip network; When the clock signal jumps from a low level to a high level, a control signal of the simulation signal data is detected; the high level indicates that the simulation task is in an execution end state, thereby ensuring that the simulation signal data is in a data consistency state; When the control signal of the simulation signal data is in a valid state, the simulation signal data is read from the verification platform and stored in the hard disk.

4. The method according to claim 1, characterized in that: In the process of verifying the on-chip network design file, obtaining the simulation signal data and storing it in the hard disk includes: Acquire data units constituting the simulation signal data, and record the acquisition time of each data unit; the data unit is a segmentation unit for transmitting the simulation signal data; The data units are arranged in the time sequence of the acquisition moments, and the simulation signal data are obtained and stored in a hard disk.

5. The method according to claim 1, characterized in that The offline analysis of the simulated signal data stored in the hard disk includes: Classifying the simulation signal data according to data types; the data types include request type, transmission type, response type and listening type; According to the data type, the simulation signal data is split and stored in files corresponding to the data type; the files include request files, response files, transmission files and listening files; The request file is read to obtain the request data.

6. The method according to claim 2, characterized in that The request data includes a first target field for searching for a corresponding response result, wherein the first target field represents a task identifier of the request data. The step of counting request data having corresponding response results from all the request data according to the corresponding relationship between the request data and the response results includes: Setting the number of concurrent tasks, which is used to control the number of query tasks executed simultaneously, wherein the query task is a task for searching the response result according to the request data; For one of the query tasks executed simultaneously, the request data is sent to the data tracking process to obtain a completion signal of the current query task; When a corresponding response result is found according to the first target field of the request data, the tracking process converts the completion signal into a completed signal.

7. The method according to claim 6, characterized in that The method further comprises: When no corresponding response result is found from the first target field of the request data, the tracking process converts the completion signal into an incomplete signal; The request data having the incomplete signal is marked as the target request data, and the request position of the target request data is located.

8. The method according to claim 6, characterized in that The request data includes a second target field for searching a corresponding response result, and the method further includes: When executing the query task, when a corresponding response result is found according to the first target field or the second target field of the request data, the tracking process converts the completion signal into a completed signal; When no corresponding response result is found according to the first target field and the second target field of the request data, the tracking process converts the completion signal into an incomplete signal.

9. The method according to claim 1, characterized in that: The method further comprises: Sending all the request data to a performance statistics module, and using the performance statistics module to count the performance data of all the request data; Analyze the network on chip design file according to the request location of the request data for which no corresponding response result is obtained in the integrity detection, and the performance data, to obtain a performance analysis result; Defects existing in the on-chip network design file are determined according to the performance analysis result.

10. A network-on-chip simulation information analysis device, characterized in that: The device comprises: A storage module is used to obtain simulation signal data and store it in a hard disk during the verification of the on-chip network design file; the simulation signal data records the signal changes of the on-chip network design file during the simulation operation; The parsing module is used to parse the simulation signal data stored in the hard disk offline to obtain the corresponding relationship between the request data and the response result in the simulation signal data; The integrity detection module is used to perform integrity detection of the simulation signal data according to the corresponding relationship between the request data and the response result.

11. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a program or instruction that can be run on the processor, and when the program or instruction is executed by the processor, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of method claims 1 to 9.

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