A chip clock design optimization method based on Multi-Point CTS

Abstract

The present invention discloses a chip clock design optimization method based on Multi-Point CTS, which relates to the technical field of chip clock design optimization. The method comprises the following steps: using a hardware description language VHDL to write RTL code describing circuit behavior; using a Synopsys DC EDA tool to convert the RTL code into a logic netlist; using a standard algorithm H-Tree to construct a preliminary clock tree structure layout to obtain a preliminary clock tree topology diagram; introducing a Multi-Point CTS method, using multiple clock sources to optimize the preliminary clock tree topology diagram to obtain an optimized clock tree topology diagram; using a static timing analysis tool PrimeTime to analyze the optimized clock tree topology diagram to obtain a timing analysis result; identifying the longest path from the clock source to the register in the optimized clock tree topology diagram according to the timing analysis result, marking it as a critical path, and using a heuristic search algorithm to find the optimal position for placing a buffer in the critical path; and using PrimeTime again to calculate the difference between the actual delay and the maximum allowable delay of the optimized clock tree topology diagram.

Description

Technical Field

[0001] The present invention relates to the technical field of chip clock design optimization, in particular to a chip clock design optimization method based on Multi-Point CTS. Background Art

[0002] Chip clock design optimization refers to a series of processes and technologies that ensure that clock signals can be efficiently and reliably transmitted to all logic units that need them through the design, implementation and verification of the clock distribution network during the chip design phase, while meeting the design's timing requirements, reducing power consumption, reducing area occupancy, and improving manufacturability.

[0003] In the existing technology, there may be time differences when the clock signal arrives at different registers, which is called clock skew. This phenomenon will cause synchronization errors or increase the system's minimum clock period, thereby affecting system performance. In large-scale integrated circuits, due to factors such as path delays and process variations, setup time and hold time violations will occur, affecting the functional correctness of the circuit. At the same time, on high-density integrated circuits, wiring resources are limited, which can easily cause congestion, thereby affecting the quality and efficiency of the clock distribution network. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a chip clock design optimization method based on Multi-PointCTS to solve the problem that wiring resources are limited on high-density integrated circuits, which easily causes congestion and thus affects the quality and efficiency of the clock distribution network.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] In the first aspect, the present invention provides a chip clock design optimization method based on Multi-Point CTS, which includes using the hardware description language VHDL to write RTL code that describes circuit behavior, using Synopsys's DC EDA tool to convert the RTL code into a logic netlist, and using the standard algorithm H-Tree to build a preliminary clock tree structure layout to obtain a preliminary clock tree topology diagram; introducing Multi-Point The CTS method uses multiple clock sources to optimize the preliminary clock tree topology to obtain the optimized clock tree topology; the static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology to obtain the timing analysis results; based on the timing analysis results, the longest path from the clock source to the register in the optimized clock tree topology is identified and marked as the critical path, and a heuristic search algorithm is used to find the best location for placing the buffer in the critical path; PrimeTime is used again to calculate the difference between the actual delay and the maximum allowable delay of the optimized clock tree topology, and the position of the buffer is adjusted according to the difference to update the clock tree topology; the power consumption of the updated clock tree topology is evaluated to obtain the power consumption sensitivity analysis results, and based on the power consumption sensitivity analysis results, the high-power buffer is replaced with a low-power buffer; the DRC tool Mentor's Calibre is used to identify and correct the violations of physical rules in the updated clock tree topology, timing analysis results, and power consumption sensitivity analysis results, and generate a verification report for the chip clock design optimization.

[0008] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the RTL code describing the circuit behavior is written using the hardware description language VHDL, the RTL code is converted into a logic netlist using the Synopsys DCEDA tool, and a preliminary clock tree structure layout is constructed using the standard algorithm H-Tree to obtain a preliminary clock tree topology diagram. The specific steps include: using the hardware description language VHDL to write a behavioral level description of the circuit to obtain VHDL RTL code; importing the VHDL RTL code into Synopsys DC EDA, performing logic synthesis, converting the RTL code into a logic netlist based on a standard cell library, saving the synthesized design in a logic netlist format, and using PrimeTime to identify all registers requiring clock signals and determine the clock source and register location; and calculating the chip center point based on the clock source and register location, using the expression:

[0009]

[0010] Where W is the width, H is the height, C is the center point, and the coordinates of the center point C are C(C x ,C y); Set the center point as the starting point of the clock tree H-Tree, and place the trunk buffer from the clock source to the center point as the root node of the H-Tree, and set the location of the clock source to CLK (CLK x ,CLK y ), find the best path from CLK to C to place the backbone buffer, and calculate the distance from the clock source to the center point. The expression is:

[0011]

[0012] Among them, d CLK-C is the distance from the clock source to the center of the chip, C x and C y They are the coordinates of the chip center point on the x-axis and y-axis, CLK x and CLK y are the coordinates of the clock source on the x-axis and y-axis respectively; starting from the root node, the chip area is divided into two equal parts, corresponding to the two branches of the clock tree, and a buffer is placed in the center of each partition as the new node of the branch. The expression is;

[0013]

[0014]

[0015] P y (t i )=(1-t i )·CLK y +t i ·C y ;

[0016] Where N is the number of buffers planned to be placed, Δd is the interval between buffers, and t i is the relative position of each buffer i on the path, P x (t i ) is the coordinate of the i-th buffer on the x-axis, P y (t i ) is the coordinate of the i-th buffer on the y-axis;

[0017] Repeat the recursive partitioning and buffer placement steps until each partition contains only one register and the clock tree H-Tree is constructed. After the clock tree H-Tree is constructed, check to confirm that no registers are missed and all clock paths are correctly connected. Save the constructed clock tree in a logic netlist format to generate a preliminary clock tree topology diagram.

[0018] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, the Multi-Point CTS method is introduced to optimize the preliminary clock tree topology using multiple clock sources to obtain an optimized clock tree topology. The specific steps are: selecting a multi-point CTS strategy based on region division and dynamic buffer insertion as the preferred solution; dividing the entire chip into several sub-regions based on the preliminary clock tree topology, each sub-region will be configured with one or more clock sources, and determining the optimal clock source position for each sub-region. The expression is:

[0019]

[0020] Among them, S eff is the effectiveness index of the clock source, A and B are the starting point and end point of the integration interval respectively, ρ(r) is the load density function at distance r, dT(r) is the clock transmission delay differential at distance r, N is the number of clock sources, f i is the frequency of the i-th clock source; select the maximum value S eff , as the best clock source location for each sub-area, and obtain the optimized clock tree topology.

[0021] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, the static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology diagram to obtain the timing analysis results. The specific steps are: using the static timing analysis tool STA in PrimeTime, defining a delay calculation expression, and calculating the delay of all clock paths in the entire clock tree. The expression is:

[0022] D elem =f(T input ,T output ,C load );

[0023] Among them, D elem is the delay of a single component or network segment, T input is the arrival time of the input signal, T output is the departure time of the output signal, C load is the load capacitance, f is the delay calculation function; then the arrival time of the input signal at each node is calculated incrementally along each path, and the expression is:

[0024]

[0025] Among them, T arrival (P,i) represents the arrival time of the input signal at the i-th node on the clock path P, T arrival(P,i-1) is the arrival time of the input signal of the previous node on the clock path P, is the delay of the i-th element or segment on the path; calculate the time required for the output signal, which is the time the data must reach the flip-flop before the clock edge and the time it remains unchanged after the clock edge. The expression is:

[0026] T required (P,j)=T clk -S req ;

[0027] T required (P,j)=H req ;

[0028] Among them, T clk is the target clock period, S req and H req They are setup time and hold time requirements, P refers to a specific clock path, j refers to the register or logic unit on the path, T required (P, j) represents the time required for the output signal of the jth register or logic unit on path P. Based on the above calculation results, set time violation and hold time violation to compare the input signal arrival time and the output signal required time, and obtain the timing analysis result based on the compared values. The expression is:

[0029] Setup Violation P =T required (P,j)-T arrival (P,j);

[0030] Hold Violation P =T arrival (P,j)-T required (P,j);

[0031] Among them, Setup Violation P To set a time violation, Hold Violation P To keep time violation.

[0032] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, the method further comprises: identifying the longest path from the clock source to the register in the optimized clock tree topology diagram based on the timing analysis results, marking it as the critical path, and using a heuristic search algorithm to find the optimal location for placing the buffer in the critical path. The specific steps are: based on the obtained timing analysis results, finding the path with the maximum delay from the clock source to the register, which is the critical path, and the expression is:

[0033]

[0034] T crit =max(D P );

[0035] Among them, P is each path, D P is the total delay on each path P, is the number of elements or segments on the path, T crit The critical path with the maximum delay is identified. According to the critical path in the clock tree topology, all possible buffer placement locations are identified. Among the placement locations, several locations are randomly selected to place the buffers. An initial buffer placement plan is generated, and a fitness function is defined to evaluate the fitness of each buffer placement location. The expression is:

[0036] S={s i |∈L,i=1,2,...,n};

[0037] F(S)=w1·ΔE-w2·ΔM-w3·C b ;

[0038] Where ΔE is the delay reduction after placing the buffer, ΔM is the power consumption increase after placing the buffer, and C b is the routing congestion level on the path after buffer placement, L represents the set of all possible buffer placement locations, S represents the buffer placement plan, F(S) is the fitness value of the buffer placement plan S, w1, w2, and w3 are weight coefficients; the plan with the higher fitness value is selected as the new placement plan, and the crossover and mutation operations are used to iteratively optimize the placement plan. The expression is as follows:

[0039] S c =S a [:R]+S b [R:],S d =S b [:R]+S a [R:];

[0040]

[0041] Among them, S c and S d is the newly generated offspring solution, R is the location of the intersection, S' is the solution after mutation, s i is the position to be replaced, l j is a new position randomly selected from the set L of all possible buffer placement positions, P mut is the mutation probability; after iteration, the buffer placement scheme with the highest fitness value is obtained, which is the optimal location for placing the buffer, and the expression is:

[0042]

[0043] L opt ={l j |∈S opt};

[0044] Among them, S opt is the optimal buffer placement scheme obtained after the iteration, Final Population represents the final population at the end of the iteration, F(S) is the fitness value of the buffer placement scheme S, and L opt The best location for placing the buffer.

[0045] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: PrimeTime is used again to calculate the difference between the actual delay and the maximum allowable delay of the clock tree topology diagram, and the position of the buffer is adjusted according to the difference value, and the clock tree topology diagram is updated. The specific steps are: using PrimeTime to extract the actual delay time of the critical path from the timing analysis results as T arrival (P,i); set the maximum allowed delay D on the path max , and compare it with the actual delay time of the critical path to calculate the difference value, the expression is:

[0046] ΔD=T arrival (P,i)-D max ;

[0047] Where ΔD is the difference between the actual delay and the maximum allowed delay, T arrival (P,i) is the arrival time of the input signal at the i-th node on path P, D max The maximum allowable delay is set on the path; the path with the largest delay difference is selected as the priority adjustment object, and buffers are placed at several positions on this path; for each newly placed buffer position, the actual delay and difference value of its path are recalculated; the smallest difference value is selected as the optimal configuration for placing buffers on the entire path; the selected optimal configuration is applied to the clock tree topology diagram, the buffer positions are updated, and an updated clock tree topology diagram is obtained.

[0048] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the power consumption of the updated clock tree topology is evaluated to obtain the power consumption sensitivity analysis result, and the high-power consumption buffer is replaced with a low-power consumption buffer based on the power consumption sensitivity analysis result. The specific steps are: using Redhawk to evaluate the power consumption of the updated clock tree topology and generate a power consumption report; according to the power consumption report, the power consumption sensitivity score of each buffer is calculated, and the expression is:

[0049]

[0050] in, Score the power consumption sensitivity, is the estimated power consumption of buffer ∪, is the sum of the power consumption estimates for all buffers, is the routing congestion level of buffer ∪, is the sum of the routing congestion levels of all buffers, N is the total number of buffers; according to the power sensitivity score Sort all buffers and select those with higher power consumption. For buffers with higher power sensitivity scores, find alternatives with similar electrical characteristics but lower power consumption. Replace buffers with higher power sensitivity scores with buffers with lower power consumption.

[0051] As a preferred solution of the chip clock design optimization method based on Multi-Point CTS described in the present invention, wherein: the DRC tool Mentor's Calibre is used to identify and correct violations of physical rules in the updated clock tree topology diagram, timing analysis results, and power sensitivity analysis results, and generate a verification report for the chip clock design optimization. The specific steps are: using Mentor's Calibre to configure a DRC rule file according to the target manufacturing process node; using Mentor's Calibre to check the design, find potential physical rule violations, and generate a report; based on the violation report, introduce an impact factor evaluation formula to calculate the impact of each violation item to obtain the impact factor, which is expressed as:

[0052] I f =o1·Y impact +o2·K fix +o3·B risk ;

[0053] Among them, I f is the impact factor of the violation, Y impact is the impact score of the violation on the design performance, K fix is the complexity score required to fix the violation, B riskis the risk score brought by the violation, o1, o2, and o3 are weight coefficients, corresponding to performance impact, repair complexity, and risk importance, respectively; based on Mentor's Calibre violation report and impact factors, manually correct the violation problems in the design; integrate the updated clock tree topology diagram, timing analysis results, power sensitivity analysis results, and physical violation verification report to obtain a verification report for chip clock design optimization.

[0054] In a second aspect, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: when the computer program is executed by the processor, any step of the chip clock design optimization method based on Multi-PointCTS as described in the first aspect of the present invention is implemented.

[0055] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the chip clock design optimization method based on Multi-Point CTS as described in the first aspect of the present invention.

[0056] The present invention has the following beneficial effects: using the hardware description language VHDL to write RTL code describing circuit behavior and construct a preliminary clock tree topology diagram, achieving the first step of the transition from high-level design description to physical implementation, thereby ensuring design accuracy and consistency. The static timing analysis tool PrimeTime is used to analyze the preliminary clock tree topology diagram to identify critical paths. By defining a delay calculation expression, the input signal arrival time of each node is incrementally calculated to ensure that all registers receive clock signals within the specified time, providing a clear target for subsequent optimization. By placing multiple clock sources in different sub-regions, clock signals can be more evenly distributed, thereby reducing the time difference between registers receiving clock signals. A heuristic search algorithm is used to find the optimal location for placing buffers in the critical path, effectively optimizing the critical path, minimizing critical path delay, and improving overall performance. Using PrimeTime, the difference between the actual delay and the maximum allowable delay of the clock tree topology diagram is calculated, and the buffer position is adjusted to achieve further optimization of the clock tree topology diagram, ensuring that all paths meet timing requirements. Power consumption is evaluated on the updated clock tree topology diagram, and high-power buffers are replaced, thereby reducing overall power consumption and improving energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0058] Figure 1 This is a flowchart of the chip clock design optimization method based on Multi-Point CTS in Example 1.

[0059] Figure 2 This is a flow chart of the impact factors in Example 1. DETAILED DESCRIPTION

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0061] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0062] Secondly, the term "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive of other embodiments.

[0063] Example 1, with reference to Figure 1 and Figure 2 , which is the first embodiment of the present invention, provides a chip clock design optimization method based on Multi-Point CTS, comprising the following steps:

[0064] S1. Use the hardware description language VHDL to write RTL code that describes the circuit behavior. Use Synopsys' DC EDA tool to convert the RTL code into a logic netlist. Use the standard H-Tree algorithm to build a preliminary clock tree structure layout and obtain a preliminary clock tree topology diagram.

[0065] Furthermore, the RTL code describing the circuit behavior is written using the hardware description language VHDL. Synopsys' DC EDA tool is used to convert the RTL code into a logic netlist. The standard algorithm H-Tree is used to construct a preliminary clock tree structure layout to obtain a preliminary clock tree topology diagram. The specific steps include: using the hardware description language VHDL to write a behavioral-level description of the circuit to obtain VHDL RTL code; importing the VHDL RTL code into Synopsys DC EDA, performing logic synthesis, converting the RTL code into a logic netlist based on a standard cell library, saving the synthesized design in a logic netlist format, and using PrimeTime to identify all registers requiring clock signals and determine the clock source and register location; and calculating the chip center point based on the clock source and register location. The expression is:

[0066]

[0067] Where W is the width, H is the height, C is the center point, and the coordinates of the center point C are C(C x ,C y ); Set the center point as the starting point of the clock tree H-Tree, and place the trunk buffer from the clock source to the center point as the root node of the H-Tree, and set the location of the clock source to CLK (CLK x ,CLK y ), find the best path from CLK to C to place the backbone buffer, and calculate the distance from the clock source to the center point. The expression is:

[0068]

[0069] Among them, d CLK-C is the distance from the clock source to the center of the chip, C x and C y They are the coordinates of the chip center point on the x-axis and y-axis, CLK x and CLK y are the coordinates of the clock source on the x-axis and y-axis respectively; starting from the root node, the chip area is divided into two equal parts, corresponding to the two branches of the clock tree, and a buffer is placed in the center of each partition as the new node of the branch. The expression is;

[0070]

[0071] P x (t i )=(1-t i )·CLK x +t i ·C x ;

[0072] Py (t i )=(1-t i )·CLK y +t i ·C y ;

[0073] Where N is the number of buffers planned to be placed, Δd is the interval between buffers, and t i is the relative position of each buffer i on the path, P x (t i ) is the coordinate of the i-th buffer on the x-axis, P y (t i ) is the coordinate of the i-th buffer on the y-axis;

[0074] Repeat the recursive partitioning and buffer placement steps until each partition contains only one register and the clock tree H-Tree is constructed. After the clock tree H-Tree is constructed, check to confirm that no registers are missed and all clock paths are correctly connected. Save the constructed clock tree in a logic netlist format to generate a preliminary clock tree topology diagram.

[0075] It should be noted that the standard algorithm H-Tree is used to construct the preliminary clock tree structure layout, which ensures the uniform distribution and low skewness of the clock signal on the chip. This method not only improves the quality of the clock signal, but also simplifies the subsequent optimization work. The construction of the preliminary clock tree provides a solid foundation for subsequent optimization, reduces uncertainty, and ensures the consistency and accuracy of the clock distribution network.

[0076] S2. Introducing the Multi-Point CTS method, using multiple clock sources to optimize the preliminary clock tree topology to obtain the optimized clock tree topology;

[0077] Furthermore, the Multi-Point CTS method is introduced to optimize the preliminary clock tree topology using multiple clock sources to obtain the optimized clock tree topology. The specific steps are as follows: the multi-point CTS strategy based on region division and dynamic buffer insertion is selected as the preferred solution; based on the preliminary clock tree topology, the entire chip is divided into several sub-regions, each of which will be configured with one or more clock sources. The optimal clock source position for each sub-region is determined by the expression:

[0078]

[0079] Among them, S eff is the effectiveness index of the clock source, A and B are the starting point and end point of the integration interval respectively, ρ(r) is the load density function at distance r, dT(r) is the clock transmission delay differential at distance r, N is the number of clock sources, fi is the frequency of the i-th clock source; select the maximum value S eff , as the best clock source location for each sub-area, and obtain the optimized clock tree topology.

[0080] It should be noted that the multi-point CTS strategy based on regional division and dynamic buffer insertion was chosen based on comprehensive considerations of reducing clock skew, reducing jitter, and minimizing power consumption. The strategy allows designers to customize clock distribution according to the specific conditions of different regions, thereby improving the reliability of the overall system. Dividing the chip into multiple sub-regions is to better manage complexity and ensure the quality of clock signals in each local region. In this way, the clock delay and load balancing of each part can be more accurately controlled, thereby improving global timing convergence.

[0081] S3. Use the static timing analysis tool PrimeTime to analyze the optimized clock tree topology and obtain the timing analysis results.

[0082] Furthermore, the static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology to obtain the timing analysis results. The specific steps are: using the static timing analysis tool STA in PrimeTime, defining the delay calculation expression, and calculating the delay of all clock paths in the entire clock tree. The expression is:

[0083] D elem =f(T input ,T output ,C load );

[0084] Among them, D elem is the delay of a single component or network segment, T input is the arrival time of the input signal, T output is the departure time of the output signal, C load is the load capacitance, f is the delay calculation function; then the arrival time of the input signal at each node is calculated incrementally along each path, and the expression is:

[0085]

[0086] Among them, T arrival (P,i) represents the arrival time of the input signal at the i-th node on the clock path P, T arrival (P,i-1) is the arrival time of the input signal of the previous node on the clock path P, is the delay of the i-th element or segment on the path; calculate the time required for the output signal, which is the time the data must reach the flip-flop before the clock edge and the time it remains unchanged after the clock edge. The expression is:

[0087] T required (P,j)=T clk -S req ;

[0088] T required (P,j)=H req ;

[0089] Among them, T clk is the target clock period, S req and H req They are setup time and hold time requirements, P refers to a specific clock path, j refers to the register or logic unit on the path, T required (P, j) represents the time required for the output signal of the jth register or logic unit on path P. Based on the above calculation results, set time violation and hold time violation to compare the input signal arrival time and the output signal required time, and obtain the timing analysis result based on the compared values. The expression is:

[0090] Setup Violation P =T required (P,j)-T arrival (P,j);

[0091] Hold Violation P =T arrival (P,j)-T required (P,j);

[0092] Among them, Setup Violation P To set a time violation, Hold Violation P To keep time violation.

[0093] It should be noted that by defining a delay calculation expression, the arrival time of the input signal of each node is calculated incrementally, and the timing performance of the entire clock tree is evaluated based on this data, including considering factors such as the delay of components or network segments and load capacitance. By accurately calculating the delay of all clock paths, it is ensured that all registers can receive the clock signal within the specified time, thereby meeting the design timing requirements and improving the reliability and performance of the system.

[0094] S4. Identify the longest path from the clock source to the register in the optimized clock tree topology diagram based on the timing analysis results, mark it as the critical path, and use a heuristic search algorithm to find the best location to place the buffer in the critical path;

[0095] Furthermore, based on the timing analysis results, the longest path from the clock source to the register in the optimized clock tree topology is identified and marked as the critical path. A heuristic search algorithm is then used to find the optimal location for placing the buffer in the critical path. The specific steps are as follows: Based on the obtained timing analysis results, the path with the maximum delay from the clock source to the register is found, which is the critical path. The expression is:

[0096]

[0097] T crir =max(D P );

[0098] Among them, P is each path, D P is the total delay on each path P, is the number of elements or segments on the path, T crit The critical path with the maximum delay is identified. According to the critical path in the clock tree topology, all possible buffer placement locations are identified. Among the placement locations, several locations are randomly selected to place the buffers. An initial buffer placement plan is generated, and a fitness function is defined to evaluate the fitness of each buffer placement location. The expression is:

[0099] S={s i |∈L,i=1,2,...,n};

[0100] F(S)=w1·ΔE-w2·ΔM-w3·C b ;

[0101] Where ΔE is the delay reduction after placing the buffer, ΔM is the power consumption increase after placing the buffer, and C b is the routing congestion level on the path after buffer placement, L represents the set of all possible buffer placement locations, S represents the buffer placement plan, F(S) is the fitness value of the buffer placement plan S, w1, w2, and w3 are weight coefficients; the plan with the higher fitness value is selected as the new placement plan, and the crossover and mutation operations are used to iteratively optimize the placement plan. The expression is as follows:

[0102] S c =S a [:R]+S b [R:],S d =S b [:R]+S a [R:];

[0103]

[0104] Among them, S c and S dis the newly generated offspring solution, R is the location of the intersection, S' is the solution after mutation, s i is the position to be replaced, l j is a new position randomly selected from the set L of all possible buffer placement positions, P mut is the mutation probability; after iteration, the buffer placement scheme with the highest fitness value is obtained, which is the optimal location for placing the buffer, and the expression is:

[0105]

[0106] L opt ={l j |∈S opt};

[0107] Among them, S opt is the optimal buffer placement scheme obtained after the iteration, Final Population represents the final population at the end of the iteration, F(S) is the fitness value of the buffer placement scheme S, and L opt The best location for placing the buffer.

[0108] It should be noted that through a heuristic search algorithm, the optimal buffer placement location is found on the critical path, and a fitness function is defined to evaluate each possible solution. The solution with the highest fitness value is selected as the final configuration, minimizing the delay on the critical path while taking power consumption and routing congestion into consideration, thereby improving the overall performance and reliability of the chip and ensuring the optimal configuration of the design.

[0109] S5. Use PrimeTime again to calculate the difference between the actual delay and the maximum allowed delay of the optimized clock tree topology, adjust the position of the buffer according to the difference, and update the clock tree topology.

[0110] Furthermore, PrimeTime is used again to calculate the difference between the actual delay and the maximum allowed delay of the optimized clock tree topology. The buffer position is adjusted according to the difference value and the clock tree topology is updated. The specific steps are as follows: Use PrimeTime to extract the actual delay time of the critical path from the timing analysis results as T arrival (P,i); set the maximum allowed delay D on the path max , and compare it with the actual delay time of the critical path to calculate the difference value, the expression is:

[0111] ΔD=T arrival (P,i)-D max ;

[0112] Where ΔD is the difference between the actual delay and the maximum allowed delay, T arrival(P,i) is the arrival time of the input signal at the i-th node on path P, D max The maximum allowable delay is set on the path; the path with the largest delay difference is selected as the priority adjustment object, and buffers are placed at several positions on this path; for each newly placed buffer position, the actual delay and difference value of its path are recalculated; the smallest difference value is selected as the optimal configuration for placing buffers on the entire path; the selected optimal configuration is applied to the clock tree topology diagram, the buffer positions are updated, and an updated clock tree topology diagram is obtained.

[0113] It should be noted that PrimeTime is reused to calculate the difference between the actual delay and the maximum allowed delay, and the position of the buffer is adjusted according to the difference, especially for those critical paths whose delay exceeds the allowed value, to ensure that all critical paths meet the specified maximum allowed delay, further optimizing the clock tree topology and improving the system's timing performance and stability.

[0114] S6. Perform power consumption evaluation on the updated clock tree topology to obtain power consumption sensitivity analysis results. Based on the power consumption sensitivity analysis results, replace the high power consumption buffer with a low power consumption buffer.

[0115] Furthermore, the updated clock tree topology is subjected to power consumption evaluation to obtain power consumption sensitivity analysis results. Based on the power consumption sensitivity analysis results, high-power buffers are replaced with low-power buffers. The specific steps are as follows: Use Redhawk to evaluate the power consumption of the updated clock tree topology and generate a power consumption report; Based on the power consumption report, calculate the power consumption sensitivity score of each buffer, which is expressed as:

[0116]

[0117] in, Score the power consumption sensitivity, is the estimated power consumption of buffer ∪, is the sum of the power consumption estimates for all buffers, is the routing congestion level of buffer ∪, is the sum of the routing congestion levels of all buffers, N is the total number of buffers; according to the power sensitivity score Sort all buffers and select those with higher power consumption. For buffers with higher power sensitivity scores, find alternatives with similar electrical characteristics but lower power consumption. Replace buffers with higher power sensitivity scores with buffers with lower power consumption.

[0118] It should be noted that Redhawk was used to evaluate the power consumption of the updated clock tree, generate a detailed power consumption report, identify and replace high-power buffers based on the power sensitivity score, and select alternatives with lower power consumption but similar electrical characteristics, thereby reducing overall power consumption, improving the chip's energy efficiency, reducing heat generation, extending the life of the equipment, and reducing operating costs.

[0119] S7. Use Mentor's Calibre DRC tool to identify and correct violations of physical rules in the updated clock tree topology, timing analysis results, and power sensitivity analysis results, and generate a verification report for the chip clock design optimization.

[0120] Furthermore, Mentor's Calibre, a DRC tool, is used to identify and correct violations of physical rules in the updated clock tree topology, timing analysis results, and power sensitivity analysis results, and to generate a verification report for chip clock design optimization. The specific steps are as follows: Use Mentor's Calibre to configure the DRC rule file based on the target manufacturing process node; Mentor's Calibre checks the design to identify potential physical rule violations and generates a report; Based on the violation report, an impact factor evaluation formula is introduced to calculate the impact of each violation item, obtaining the impact factor, which is expressed as:

[0121] I f =o1·Y impact +o2·K fix +o3·B risk ;

[0122] Among them, I f is the impact factor of the violation, Y impact is the impact score of the violation on the design performance, K fix is the complexity score required to fix the violation, B risk is the risk score brought by the violation, o1, o2, and o3 are weight coefficients, corresponding to performance impact, repair complexity, and risk importance, respectively; based on Mentor's Calibre violation report and impact factors, manually correct the violation problems in the design; integrate the updated clock tree topology diagram, timing analysis results, power sensitivity analysis results, and physical violation verification report to obtain a verification report for chip clock design optimization.

[0123] It should be noted that Mentor's Calibre is used to load the updated design data, configure the DRC rule file, and perform a comprehensive physical rule check to discover and correct potential physical rule violations, ensuring that the design meets the manufacturing process requirements, improving the manufacturability of the design, reducing uncertainty and risk in the production process, improving the yield and product quality, and ensuring the successful mass production of the design.

[0124] This embodiment also provides a computer device, which is applicable to the chip clock design optimization method based on Multi-Point CTS, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute computer-executable instructions to implement the chip clock design optimization method based on Multi-Point CTS proposed in the above embodiment.

[0125] The computer device may be a terminal, comprising a processor, a memory, a communication interface, a display screen and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner may be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer device may be a liquid crystal display or an electronic ink display screen, and the input device of the computer device may be a touch layer covering the display screen, or a button, trackball or touchpad provided on the housing of the computer device, or an external keyboard, touchpad or mouse.

[0126] In summary, the present invention uses the hardware description language VHDL to write RTL code describing circuit behavior and constructs a preliminary clock tree topology diagram, achieving the first step of the transition from high-level design description to physical implementation, thereby ensuring design accuracy and consistency. The static timing analysis tool PrimeTime is used to analyze the preliminary clock tree topology diagram to identify critical paths. By defining delay calculation expressions, the input signal arrival time of each node is incrementally calculated to ensure that all registers receive clock signals within the specified time, providing a clear target for subsequent optimization. By placing multiple clock sources in different sub-regions, clock signals can be more evenly distributed, thereby reducing the time difference in receiving clock signals between registers. A heuristic search algorithm is used to find the optimal location for buffers in the critical path, effectively optimizing the critical path, minimizing critical path delay, and improving overall performance. PrimeTime is used to calculate the difference between the actual delay and the maximum allowable delay of the clock tree topology diagram, and the buffer positions are adjusted to further optimize the clock tree topology diagram, ensuring that all paths meet timing requirements. Power consumption is evaluated for the updated clock tree topology diagram, and high-power buffers are replaced, reducing overall power consumption and improving energy efficiency.

[0127] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A chip clock design optimization method based on Multi-Point CTS, characterized by: include, Use the hardware description language VHDL to write RTL code that describes the circuit behavior. Use Synopsys' DC EDA tool to convert the RTL code into a logic netlist. Use the standard H-Tree algorithm to build a preliminary clock tree structure layout and obtain a preliminary clock tree topology diagram. The Multi-Point CTS method is introduced to optimize the preliminary clock tree topology using multiple clock sources to obtain the optimized clock tree topology. The specific steps are as follows: Select the multi-point CTS strategy based on region partitioning and dynamic buffer insertion as the preferred solution; Based on the preliminary clock tree topology, the entire chip is divided into several sub-areas. Each sub-area will be configured with one or more clock sources. The optimal clock source location for each sub-area is determined using the following expression: ； in, is the validity indicator of the clock source, and are the starting and ending points of the integration interval, For distance The load density function at For distance The clock propagation delay differential at , is the number of clock sources, For the The frequency of a clock source; Select the maximum value , as the best clock source location for each sub-area, and obtain the optimized clock tree topology; Use the static timing analysis tool PrimeTime to analyze the optimized clock tree topology and obtain the timing analysis results; Based on the timing analysis results, the longest path from the clock source to the register in the optimized clock tree topology is identified and marked as the critical path. A heuristic search algorithm is used to find the best location for placing the buffer in the critical path. PrimeTime is used again to calculate the difference between the actual delay and the maximum allowed delay of the optimized clock tree topology. The buffer position is adjusted based on the difference, and the clock tree topology is updated. Perform power consumption evaluation on the updated clock tree topology to obtain power consumption sensitivity analysis results. Based on the power consumption sensitivity analysis results, replace high-power consumption buffers with low-power consumption buffers. Use Mentor's DRC tool Calibre to identify and correct violations of physical rules in the updated clock tree topology diagram, timing analysis results, and power sensitivity analysis results, and generate a verification report for chip clock design optimization.

2. The chip clock design optimization method based on Multi-Point CTS according to claim 1, characterized in that: The RTL code describing the circuit behavior is written using the hardware description language VHDL, the RTL code is converted into a logic netlist using Synopsys's DC EDA tool, and a preliminary clock tree structure layout is constructed using the standard H-Tree algorithm to obtain a preliminary clock tree topology diagram. The specific steps include: Use the hardware description language VHDL to write a behavioral level description of the circuit and obtain VHDL RTL code; Import the VHDL RTL code into Synopsys DC, perform logic synthesis, convert the RTL code into a logic netlist based on the standard cell library, save the synthesized design in logic netlist format, and use PrimeTime to identify all registers that require clock signals, determine the clock source and register location; According to the clock source and register location, the chip center point is calculated as follows: ; ; in, is the width, is the height, Center point, center point The coordinates are ; The center point is used as the starting point of the clock tree H-Tree, and the backbone buffer is placed from the clock source to the center point as the root node of the H-Tree. The location of the clock source is set to , find arrive The best path to place the trunk buffer is to calculate the distance from the clock source to the center point. The expression is: ; in, is the distance from the clock source to the center of the chip, and are the coordinates of the chip center point on the x-axis and y-axis respectively, and are the coordinates of the clock source on the x-axis and y-axis respectively; Starting from the root node, the chip area is divided into two equal parts, corresponding to the two branches of the clock tree. A buffer is placed in the center of each partition as a new node of the branch. The expression is; ； ； ; ; in, is the number of buffers planned to be placed, is the buffer interval, For each buffer on the path The relative position of For the A buffer in The coordinates on the axis, For the A buffer in Coordinates on the axis; Repeat the recursive partitioning and buffer placement steps until each partition contains only one register and the clock tree H-Tree is constructed; After the clock tree H-Tree is built, check to confirm that no registers are missing and all clock paths are correctly connected; Save the constructed clock tree in logic netlist format to generate a preliminary clock tree topology diagram.

3. The chip clock design optimization method based on Multi-Point CTS according to claim 2, characterized in that: The static timing analysis tool PrimeTime is used to analyze the optimized clock tree topology diagram to obtain the timing analysis results. The specific steps are as follows: Use static timing analysis (STA) in PrimeTime to define a delay calculation expression and calculate the delay of all clock paths in the entire clock tree. The expression is: ； in, is the delay of a single component or network segment, is the arrival time of the input signal, is the departure time of the output signal, is the load capacitance, It is the delay calculation function; Then, the arrival time of the input signal at each node is calculated incrementally along each path, and the expression is: ; in, Indicates the clock path Previous The arrival time of the input signal at each node, is the clock path The arrival time of the input signal of the previous node, It is the first Delay of a component or network segment; Calculate the time required for the output signal, which is the time the data must reach the flip-flop before the clock edge and the time it remains unchanged after the clock edge. The expression is: ； ； in, is the target clock period, and They are setup time and hold time requirements, Refers to a specific clock path, Refers to the register or logic unit on the path, Indicates the path Previous The time required for the output signal of a register or logic unit; According to the above calculation results, set time violation and hold time violation to compare the input signal arrival time and the output signal required time, and obtain the timing analysis result based on the compared values. The expression is: ； ； in, To set a time violation, To keep time violation.

4. The chip clock design optimization method based on Multi-Point CTS according to claim 1, characterized in that: The method further comprises the following steps: identifying the longest path from the clock source to the register in the optimized clock tree topology diagram based on the timing analysis results, marking it as the critical path, and using a heuristic search algorithm to find the optimal location for placing the buffer in the critical path. According to the obtained timing analysis results, find the maximum delay path from the clock source to the register, which is the critical path. The expression is: ; ； in, For each path, For each path The total delay on is the number of elements or segments on the path, is the critical path with the maximum delay; According to the critical path in the clock tree topology, all possible buffer placement locations are identified. Among the placement locations, several locations are randomly selected to place the buffers. An initial buffer placement plan is generated, and a fitness function is defined to evaluate the fitness of each buffer placement location. The expression is: ; ; in, is the delay reduction after placing the buffer, is the increase in power consumption after placing the buffer, is the routing congestion level on the path after the buffer is placed, represents the set of all possible buffer placement locations, represents the buffer placement scheme, Buffer placement scheme The fitness value of , , is the weight coefficient; The fitness with a higher value is selected as the new placement plan, and the crossover and mutation operations are used to iteratively optimize the placement plan. The expression is as follows: ； ; in, and is the newly generated offspring solution, is the location of the intersection, This is the mutated solution. is the position to be replaced, is the set of all possible buffer placement positions A new position randomly selected from is the mutation probability; After iteration, the buffer placement solution with the highest fitness value is obtained, which is the optimal location for placing the buffer. The expression is: ； ； in, is the optimal buffer placement solution obtained after the iteration, represents the final population at the end of the iteration, Buffer placement scheme The fitness value of The best location for placing the buffer.

5. The chip clock design optimization method based on Multi-Point CTS according to claim 4, characterized in that: The method again uses PrimeTime to calculate the difference between the actual delay of the clock tree topology and the maximum allowed delay, adjusts the position of the buffer according to the difference, and updates the clock tree topology. The specific steps are as follows: The actual delay time of the critical path is extracted from the timing analysis results using PrimeTime. ; Set the maximum allowed delay on the path , and compare it with the actual delay time of the critical path to calculate the difference value, the expression is: ； in, is the difference between the actual delay and the maximum allowed delay, For path Previous The arrival time of the input signal at each node, The maximum allowed delay set on the path; Select the path with the largest delay difference as the priority adjustment object, and place buffers at several locations on this path; For each newly placed buffer location, recalculate the actual delay and variance values ​​of its path; The smallest difference value is selected as the optimal configuration for placing buffers along the entire path; Apply the selected optimal configuration to the clock tree topology diagram, update the position of the buffer, and obtain an updated clock tree topology diagram.

6. The chip clock design optimization method based on Multi-Point CTS according to claim 5, characterized in that: The power consumption of the updated clock tree topology is evaluated to obtain a power consumption sensitivity analysis result, and a high power consumption buffer is replaced with a low power consumption buffer according to the power consumption sensitivity analysis result. The specific steps are as follows: Use Redhawk to evaluate the power consumption of the updated clock tree topology and generate a power consumption report. Based on the power consumption report, the power consumption sensitivity score of each buffer is calculated as follows: ; in, Score the power consumption sensitivity, For buffer The estimated power consumption of is the sum of the power consumption estimates for all buffers, For buffer The degree of wiring congestion, is the sum of the routing congestion levels of all buffers, is the total number of buffers; Score by power consumption sensitivity Sort all buffers and select the one with higher power consumption; For buffers with high power sensitivity scores, find alternatives with similar electrical characteristics but lower power consumption. Replace buffers with higher power sensitivity scores with lower power buffers.

7. The chip clock design optimization method based on Multi-Point CTS according to claim 6, characterized in that: The DRC tool Mentor's Calibre is used to identify and correct violations of physical rules in the updated clock tree topology, timing analysis results, and power sensitivity analysis results, and to generate a verification report for chip clock design optimization. The specific steps are as follows: Mentor's Calibre configures the DRC rule file based on the target manufacturing process node; Use Mentor's Calibre to check the design, identify potential physical rule violations, and generate a report; According to the violation report, the impact factor evaluation formula is introduced to calculate the impact of each violation and obtain the impact factor, which is expressed as: ; in, is the impact factor of the violation, is the score of the violation’s impact on the design performance, is the complexity score required to fix the violation, is the risk score brought by the violation, , , are weight coefficients corresponding to the importance of performance impact, repair complexity, and risk respectively; Manually correct design violations based on Mentor's CalibrePT violation reports and impact factors; The updated clock tree topology diagram, timing analysis results, power sensitivity analysis results, and physical violation verification report are integrated to obtain a verification report for chip clock design optimization.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the chip clock design optimization method based on Multi-Point CTS according to any one of claims 1 to 7 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip clock design optimization method based on Multi-Point CTS according to any one of claims 1 to 7 are implemented.

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