Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in a first direction and including a pixel circuit. The optical sensing pixel includes a sensor circuit. A first data line connected to the first sub-pixel extends in the second direction. The second data line is connected to the second sub-pixel and extends in the second direction. A third data line is connected to the third sub-pixel and extends in the second direction. Readout lines connected to the optical sensing pixels extend in the second direction. The first additional line is connected to the optical sensing pixel and extends in the second direction, and receives the reset voltage. The first additional line is disposed in the same layer as the first data line, the second data line, and the third data line. The read-out line is disposed in a different layer from the first data line, the second data line, the third data line, and the first additional line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0133742, filed on October 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device and an electronic device including the display device. Background Art

[0004] Recently, with the increasing interest in information display, research and development of display devices has continued. One advancement in the field of display devices is to provide a display panel that can display images and simultaneously recognize input of touch events (such as human touch or touch of an electronic stylus). Such a device may be referred to as a touch screen display device.

[0005] Touch screen display devices may utilize data lines for realizing images on the display device and readout lines for collecting touch information. However, as touch screen display devices are manufactured with higher resolutions and smaller sizes, these lines may interfere with each other due to a phenomenon known as parasitic capacitance. Summary of the invention

[0006] The display device includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in a first direction and each including a pixel circuit. The optical sensing pixel includes a sensor circuit. The first data line extends in a second direction intersecting the first direction and is electrically connected to the first sub-pixel. The second data line extends in the second direction and is electrically connected to the second sub-pixel. The third data line extends in the second direction and is electrically connected to the third sub-pixel. The readout line extends in the second direction and is electrically connected to the optical sensing pixel. The first additional line extends in the second direction and is electrically connected to the optical sensing pixel, and is configured to receive a reset voltage. The first additional line is arranged in the same layer as each of the first data line, the second data line, and the third data line. The readout line is arranged in a layer different from the layer of the first data line, the second data line, the third data line, and the first additional line.

[0007] The readout line may be disposed on the first data line, the second data line, the third data line, and the first additional line.

[0008] The readout line may overlap with the first additional line and may be disposed on the first additional line.

[0009] The first additional line may be disposed between the second data line and the third data line.

[0010] The optical sensing pixel may be disposed between the second sub-pixel and the third sub-pixel.

[0011] Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may further include a light emitting element configured to emit light. The optical sensing pixel may further include a light receiving element configured to output a sensing signal corresponding to the light emitted from the light emitting element.

[0012] The optical sensing pixel may further include a bridge pattern electrically connected to the light receiving element. The bridge pattern and the readout line may be provided in the same layer and spaced apart from each other.

[0013] The first additional line may have a width greater than that of the readout line.

[0014] The display device may further include a second additional line extending in the first direction, the second additional line being electrically connected to the first additional line and configured to receive a reset voltage. The first additional line may be disposed on the second additional line with an insulating layer interposed therebetween.

[0015] The display device may further include a third additional line electrically connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel and configured to receive the first power voltage. The third additional line may be arranged in the same layer as each of the first data line, the second data line, the third data line, and the first additional line.

[0016] The readout line may not overlap with the third additional line.

[0017] The sensor circuit may include: a light receiving element; a first sensor transistor configured to control a current flowing to a readout line in response to a voltage of one electrode of the light receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line; and a third sensor transistor electrically connected between the first additional line and one electrode of the light receiving element and including a gate electrode connected to a reset control line. Each of the first sensor transistor and the second sensor transistor may include a first type semiconductor. The third sensor transistor may include a second type semiconductor different from the first type semiconductor.

[0018] Each of the first sensor transistor and the second sensor transistor may include a silicon semiconductor. The third sensor transistor may include an oxide semiconductor.

[0019] The display device may include a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, an eighth insulating layer, and a ninth insulating layer sequentially arranged on the substrate. The first additional layer may be arranged between the substrate and the first insulating layer. The second additional layer may be arranged between the first insulating layer and the second insulating layer. The third additional layer may be arranged between the second insulating layer and the third insulating layer. The fourth additional layer may be arranged between the third insulating layer and the fourth insulating layer. The fifth additional layer may be arranged between the fourth insulating layer and the fifth insulating layer. The sixth additional layer may be arranged between the fifth insulating layer and the sixth insulating layer. The seventh additional layer may be arranged between the sixth insulating layer and the seventh insulating layer. The eighth additional layer may be arranged between the seventh insulating layer and the eighth insulating layer. The ninth additional layer may be arranged between the eighth insulating layer and the ninth insulating layer. The eighth additional layer may include a first additional line, a first data line, a second data line, and a third data line. The ninth additional layer may include a readout line.

[0020] The display device includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in a first direction and each including a pixel circuit. The optical sensing pixel includes a sensor circuit. The first data line extends in a second direction intersecting the first direction and is electrically connected to the first sub-pixel. The second data line extends in the second direction and is electrically connected to the second sub-pixel. The third data line extends in the second direction and is electrically connected to the third sub-pixel. The readout line extends in the second direction and is electrically connected to the optical sensing pixel. The first additional line extends in the second direction and is electrically connected to the optical sensing pixel, and is configured to receive a reset voltage. The second additional line is electrically connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and is configured to receive a first power voltage. The second additional line is arranged in the same layer as each of the first data line, the second data line, and the third data line. The readout line and the first additional line are arranged in a common layer. The readout line and the first additional line are arranged in a layer different from the layer of the first data line, the second data line, the third data line, and the second additional line.

[0021] The readout line may overlap the second additional line.The first additional line may be disposed between the second data line and the third data line, and may be disposed on the second data line and the third data line.

[0022] The first additional lines may include horizontal lines extending in the first direction and vertical lines extending in the second direction. The horizontal lines and the vertical lines may together form a mesh structure.

[0023] The readout line may be spaced apart from the horizontal and vertical lines.

[0024] The optical sensing pixel may be disposed between the first sub-pixel and the second sub-pixel.

[0025] An electronic device: comprising a processor configured to provide input image data to a display device; and a display device configured to display an image based on the input image data. The display device comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in a first direction and each comprising a pixel circuit. The optical sensing pixel comprises a sensor circuit. The first data line extends in a second direction intersecting the first direction and is electrically connected to the first sub-pixel. The second data line extends in the second direction and is electrically connected to the second sub-pixel. The third data line extends in the second direction and is electrically connected to the third sub-pixel. The readout line extends in the second direction and is electrically connected to the optical sensing pixel. The first additional line extends in the second direction and is electrically connected to the optical sensing pixel, and is configured to receive a reset voltage. The first additional line is arranged in the same layer as each of the first data line, the second data line, and the third data line. The readout line is arranged in a layer different from the layer of the first data line, the second data line, the third data line, and the first additional line. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] A more complete understanding of the present disclosure and some of its attendant aspects will be readily obtained as the present disclosure and some of its attendant aspects will be better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0027] Figure 1 is a schematic block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is shown Figure 1 A schematic block diagram of an embodiment of a display device.

[0029] Figure 3 is shown in the included Figure 2 A schematic diagram of an example of arrangement of pixel circuits and sensing circuits in a display area of ​​a display panel in a display device.

[0030] Figure 4 It is shown that the Figure 2 A schematic diagram of an example of a display area of ​​a display panel in a display device.

[0031] FIG. 5A to FIG. 5C is a schematic plan view showing one region of a display region included in a display device according to an embodiment.

[0032] Figure 6 It is shown that the Figure 1 Schematic circuit diagram of an example of sub-pixels and optical sensing pixels in a display area of ​​.

[0033] Figure 7 is a schematic cross-sectional view showing one region of a display device according to an embodiment.

[0034] Figure 8 It is shown Figure 7 Schematic cross-sectional view of the reflection path of light in a display device.

[0035] Fig. 9 is a schematic plan view showing a sub-pixel and an optical sensing pixel according to an embodiment.

[0036] Fig.10 It is shown that the Fig. 9 Schematic plan view of the components in the first additional layer.

[0037] Fig.11 It is shown that the Fig. 9 Schematic plan view of components in the second additional layer and the third additional layer.

[0038] Fig.12 It is shown that the Fig. 9 Schematic plan view of the components in the fourth additional layer.

[0039] Fig.13 It is shown that the Fig. 9 Schematic plan view of components in the fifth additional layer and the sixth additional layer in.

[0040] Fig.14 It is shown that the Fig. 9 Schematic plan view of the components in the seventh additional layer.

[0041] Fig.15 It is shown that the Fig. 9 Schematic plan view of the components in the eighth additional layer.

[0042] Fig.16 It is shown that the Fig. 9 Schematic plan view of the components in the ninth additional layer.

[0043] Figures 17 to 19 It is along Fig. 9 A schematic cross-sectional view taken along line II'.

[0044] Fig. 20 is a schematic plan view showing a sub-pixel and an optical sensing pixel according to an embodiment.

[0045] Fig.21 It is shown that the Fig. 20 Schematic plan view of the components in the first additional layer.

[0046] Fig. 22 It is shown that the Fig. 20 Schematic plan view of components in the second additional layer and the third additional layer.

[0047] Fig.23 It is shown that the Fig. 20 Schematic plan view of the components in the fourth additional layer.

[0048] Fig.24 It is shown that the Fig. 20 Schematic plan view of components in the fifth additional layer and the sixth additional layer in.

[0049] Fig.25 It is shown that the Fig. 20 Schematic plan view of the components in the seventh additional layer.

[0050] Fig.26 It is shown that the Fig. 20 Schematic plan view of the components in the eighth additional layer.

[0051] Fig. 27 It is shown that the Fig. 20 Schematic plan view of the components in the ninth additional layer.

[0052] Fig.28 It is shown that the Fig. 20 Schematic plan view of components in the second additional layer and the ninth additional layer.

[0053] Fig.29 It is along Fig. 20 A schematic cross-sectional view taken along line II-II'.

[0054] Fig.30 is a schematic plan view showing a sub-pixel and an optical sensing pixel according to an embodiment.

[0055] Fig.31 It is shown that the Fig.30 Schematic plan view of components in the second additional layer and the ninth additional layer.

[0056] Fig.32 It is along Fig.30 A schematic cross-sectional view taken along line III-III'.

[0057] Fig.33 is a schematic block diagram illustrating an electronic device according to an embodiment.

[0058] Fig.34 It is shown Fig.33 A schematic diagram of an example in which the electronic device is implemented as a smart phone.

[0059] Fig.35 It is shown Fig.33 A schematic diagram of an example in which the electronic device is implemented as a tablet computer. DETAILED DESCRIPTION

[0060] Since the present disclosure allows various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not necessarily intended to limit the present disclosure to a specific mode of practice, and it will be understood that all changes, equivalents and substitutes that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0061] Throughout the present disclosure, in each of the drawings and embodiments of the present disclosure, the same reference numerals may refer to the same parts. Although each of the drawings may represent one or more specific embodiments of the present disclosure, drawn to scale, relative length, thickness and angle may be inferred therefrom, it will be understood that the present invention is not necessarily limited to the relative length, thickness and angle shown. These values ​​may be changed within the spirit and scope of the present disclosure, for example, to allow manufacturing restrictions, etc. It will be understood that, although the terms "first", "second" etc. may be used herein to describe various elements, these elements should not necessarily be limited by these terms. These terms are used to distinguish an element from another element. For example, without departing from the teaching of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0062] It will also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, in the case where a first part such as a layer, film, region or plate is disposed on a second part, the first part may not only be directly disposed on the second part, but also a third part may be interposed between them. In addition, in the case where a first part such as a layer, film, region or plate is expressed as being formed on a second part, the surface of the second part on which the first part is formed is not necessarily limited to the upper surface of the second part, but may include other surfaces such as the side surface or lower surface of the second part. On the contrary, in the case where a first part such as a layer, film, region or plate is below the second part, the first part may not only be directly below the second part, but also a third part may be interposed between them.

[0063] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings in order to describe the present disclosure in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form unless explicitly provided otherwise.

[0064] Figure 1 is a schematic block diagram showing a display device 1 according to an embodiment of the present disclosure.

[0065] refer to Figure 1 , the display device 1 may include a display panel 100 and a driving circuit 200. In an implementation, the driving circuit 200 may include a panel driver 210 and a sensor driver 220.

[0066] The display device 1 may be implemented as a self-emitting display device including a plurality of self-emitting elements. For example, the display device 1 may be an organic light emitting diode (OLED) display device including an organic light emitting element. However, the present disclosure is not necessarily limited to the above examples, and the display device 1 may be implemented as a display device including an inorganic light emitting element, a display device including a light emitting element formed by a combination of an inorganic material and an organic material, a display device that displays an image using quantum dots, etc.

[0067] The display device 1 may be a flat display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, or a rollable display device. In addition, the display device 1 may be applied to a transparent display device, a head-mounted display device, a wearable display device, and the like.

[0068] The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may be an area in which a sub-pixel SPX (or pixel) is disposed. The sub-pixel SPX may include at least one light emitting element. For example, the light emitting element may include a light emitting layer (e.g., an organic light emitting layer). A portion that may be emitted by the light emitting element may be defined as an emission area. The display device 1 may drive the sub-pixel SPX in response to image data, thereby displaying an image in the display area DA.

[0069] The non-display area NDA may be an area disposed around the display area DA. For example, the non-display area NDA may at least partially surround the display area DA. In an embodiment, the non-display area NDA may collectively refer to the remaining areas on the display panel 100 except the display area DA. For example, the non-display area NDA may include a line area, a pad area, and various dummy areas.

[0070] The optical sensing pixel PSR may be included in the display area DA. The optical sensing pixel PSR may be referred to as an optical sensor. The optical sensing pixel PSR may include a light receiving element including a light receiving layer. In the display area DA, the light receiving layer of the light receiving element may be spaced apart from the light emitting layer of the light emitting element.

[0071] In the entire area of ​​the display area DA, a plurality of optical sensing pixels PSR may be distributed to be spaced apart from each other. However, the present disclosure is not necessarily limited to the above example, and only one area of ​​the display area DA may be set as a sensing area, and the optical sensing pixels PSR may be set in the corresponding sensing area. In addition, the optical sensing pixels PSR may also be set in at least a portion of the non-display area NDA.

[0072] The optical sensing pixel PSR can sense light emitted from a light source (e.g., a light emitting element of a sub-pixel SPX) and reflected by an external object (e.g., a user's finger). For example, a user's fingerprint can be sensed by the optical sensing pixel PSR. Although hereinafter, the optical sensing pixel PSR is described as being used for fingerprint sensing, for example, in various embodiments, the optical sensing pixel PSR can sense various types of biometric information, such as iris information or vein information.

[0073] The driving circuit 200 may include a panel driver 210 and a sensor driver 220. The panel driver 210 and the sensor driver 220 may be implemented as integrated circuits independent of each other. In an embodiment, the driving circuit 200 may be implemented as a single integrated circuit. In this case, at least a portion of the sensor driver 220 may be included in the panel driver 210 or interlocked with the panel driver 210.

[0074] The panel driver 210 may scan the sub-pixels SPX in the display area DA and provide data signals corresponding to image data (or an image) to the sub-pixels SPX. The display panel 100 may display an image corresponding to the data signals.

[0075] The panel driver 210 may provide a drive signal for light sensing (e.g., fingerprint sensing) to the sub-pixel SPX. A drive signal may be provided so that the sub-pixel SPX emits light and operates as a light source for the optical sensing pixel PSR. The panel driver 210 may also provide a drive signal and / or multiple drive signals for light sensing to the optical sensing pixel PSR. However, the present disclosure is not necessarily limited to the above examples. The drive signal for light sensing may be provided to the optical sensing pixel PSR by the sensor driver 220.

[0076] The sensor driver 220 may detect biometric information related to a fingerprint of a user, etc. based on a sensing signal received from the optical sensing pixel PSR. In an embodiment, the sensor driver 220 may provide a driving signal to the optical sensing pixel PSR and / or the sub-pixel SPX.

[0077] The panel driver 210 may provide a readout control signal RCS to the sensor driver 220. Interlocked with the panel driver 210, the sensor driver 220 may read out (or sample) the sensing signal based on the readout control signal RCS. For example, the sensor driver 220 may read out or sample the sensing signal in units of at least one pixel row (or horizontal line) in response to the readout control signal RCS.

[0078] Figure 2 It is shown Figure 1 A schematic block diagram of an embodiment of a display device 1 is shown in FIG.

[0079] refer to Figure 1 and Figure 2 , the display device 1 may include a display panel 100 and a driving circuit 200 .

[0080] The display panel 100 may include signal lines, sub-pixels SPX, and optical sensing pixels PSR. The signal lines may include scan lines S1 to Sn, data lines D1 to Dm, readout lines RX1 to RXo, and reset lines RSTL (or reset control lines). Here, n, m, and o may each be a positive integer.

[0081] The sub-pixel SPX may be disposed or positioned in an area (e.g., a pixel area) defined by the scan lines S1 to Sn and the data lines D1 to Dm. The optical sensing pixel PSR may be disposed or positioned in an area defined by the scan lines S1 to Sn and the readout lines RX1 to RXo. The sub-pixel SPX and the optical sensing pixel PSR may be arranged in a two-dimensional array in the display area DA of the display panel 100, but the present disclosure is not necessarily limited thereto.

[0082] The subpixel SPX may be electrically connected to at least one of the scan lines S1 to Sn and one of the data lines D1 to Dm. The optical sensing pixel PSR may be electrically connected to one of the scan lines S1 to Sn, one of the readout lines RX1 to RXo, and a reset line RSTL. Figure 6 The connection configuration between the sub-pixel SPX, the optical sensing pixel PSR, and the signal is described.

[0083] Power voltages VDD, VSS, VRST, and VCOM required to drive the subpixels SPX and the optical sensing pixels PSR may be provided to the display panel 100. The power voltages VDD, VSS, VRST, and VCOM may be provided by a power supply. The power supply may be implemented as a power management IC (PMIC).

[0084] The driving circuit 200 may include a scan driver 211, a data driver 212, a controller 213, a reset circuit 221, and a readout circuit 222. For example, the scan driver 211, the data driver 212, and the controller 213 may be included in the panel driver 210. The reset circuit 221 and the readout circuit 222 may be included in the sensor driver 220. However, the present disclosure is not necessarily limited thereto. In an embodiment, the reset circuit 221 may be included in the panel driver 210.

[0085] The scan driver 211 may be electrically connected to the sub-pixels SPX and the optical sensing pixels PSR through the scan lines S1 to Sn. The scan driver 211 may generate a scan signal based on the scan control signal SCS and provide the scan signal to the scan lines S1 to Sn. The scan control signal SCS may include a start signal, a clock signal, etc., and may be provided to the scan driver 211 from the controller 213. For example, the scan driver 211 may be implemented as a shift register configured to sequentially shift a pulse-type start signal based on a clock signal and generate a scan signal, and output the generated scan signal to the scan lines S1 to Sn. The scan driver 211 may selectively drive the sub-pixels SPX and the optical sensing pixels PSR while scanning the display panel 100.

[0086] Although the scan driver 211 may be formed together with the sub-pixel SPX of the display panel 100, the present disclosure is not necessarily limited thereto. In an embodiment, the scan driver 211 may be implemented as an integrated circuit.

[0087] The sub-pixel SPX selectively driven by the scan driver 211 may emit light at a brightness corresponding to a data signal supplied to a corresponding data line among the data lines D1 to Dm. The optical sensing pixel PSR selectively driven by the scan driver 211 may output an electrical signal (e.g., a sensing signal) corresponding to the sensed light to a corresponding readout line. For example, the sub-pixel SPX selectively driven by the i-th scan line Si may emit light at a brightness corresponding to a data signal supplied to the j-th data line Dj (here, i and j are each a positive integer). For example, the optical sensing pixel PSR selectively driven by the i-th scan line Si may output an electrical signal corresponding to the sensed light to the k-th readout line RXk (here, k is a positive integer).

[0088] The data driver 212 may generate a data signal (or data voltage) based on the image data DATA2 and the data control signal DCS provided from the controller 213, and provide the data signal to the display panel 100 (or the sub-pixel SPX) through the data lines D1 to Dm. The data control signal DCS may be a signal for controlling the operation of the data driver 212, and includes a data enable signal (or load signal) for indicating that a valid data signal is to be output, a horizontal start signal, a data clock signal, etc. For example, the data driver 212 may include: a shift register configured to shift the horizontal start signal in synchronization with the data clock signal and generate a sampling signal; a latch configured to latch the image data DATA2 in response to the sampling signal; a digital-to-analog converter (or decoder) configured to convert the latched image data (e.g., digital data) into an analog data signal; and a buffer (or amplifier) ​​configured to output the data signal to a corresponding data line (e.g., the j-th data line Dj).

[0089] The controller 213 may receive input image data DATA1 and a control signal CS from an external device (e.g., a graphics processor, an application processor, or a first processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and generate image data DATA2 by converting the input image data DATA1. Here, the control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a reference clock signal, etc. The vertical synchronization signal may refer to the beginning of a frame data (i.e., data corresponding to a frame period in which one frame image is displayed). The horizontal synchronization signal may refer to the beginning of a data row (i.e., one data row among a plurality of data rows included in the frame data). The controller 213 may convert the input image data DATA1 into image data DATA2 having a format corresponding to the pixel arrangement in the display panel 100.

[0090] Furthermore, the controller 213 may generate a reset control signal and a readout control signal RCS based on the control signal CS.

[0091] The reset circuit 221 may be commonly connected to all optical sensing pixels PSR provided in the display panel 100 through one reset line RSTL. The reset circuit 221 may provide a reset signal RST to all optical sensing pixels PSR simultaneously in response to a reset control signal. Since the reset signal RST is provided to all optical sensing pixels PSR simultaneously, the reset signal RST may be referred to as a global reset signal.

[0092] The readout circuit 222 may receive sensing signals from the optical sensing pixels PSR through the readout lines RX1 to RXo and perform a signal processing operation on the sensing signals.

[0093] For example, the readout circuit 222 may perform a correlated double sampling (CDS) operation to remove noise from the sensing signal provided by the optical sensing pixel PSR. The timing of the CDS operation of the readout circuit 222 may be determined by the readout control signal RCS. The readout circuit 222 may convert the analog sensing signal into a digital signal (or digital value). A configuration for CDS operation and analog-to-digital conversion may be provided for each of the readout lines RX1 to RXo. The readout circuit 222 may process the sensing signals provided from the readout lines RX1 to RXo in parallel.

[0094] The processed sensing signal (i.e., the read sensing signal) may be transmitted to an external device (e.g., an application processor) as part of the sensing data (or biometric information), so that biometric authentication (e.g., fingerprint authentication, etc.) may be performed based on the sensing data. In an embodiment, the read sensing signal may be provided to the controller 213, so that the biometric authentication may be performed in the controller 213.

[0095] Figure 3 It is shown that the Figure 2 1 is a schematic diagram of an example of arrangement of pixel circuits and sensing circuits in a display area DA of a display panel 100 in a display device 1. Figure 4 It is shown that the Figure 2 Schematic diagram of an example of a display area DA of a display panel 100 in a display device 1. FIG. 5A to FIG. 5C is a schematic plan view showing one region of a display area DA included in the display device 1 according to an embodiment.

[0096] FIG. 5A to FIG. 5C The implementation method involves Figure 3 The embodiments are modified regarding the number of pixel circuits provided between two sensor circuits adjacent to each other, etc.

[0097] refer to Figures 1 to 5C , the sub-pixels SPX1 to SPX4 and the plurality of optical sensing pixels PSR may be disposed in the display area DA of the display panel 100 .

[0098] The display area DA may be divided into pixel rows R1 to R4. Each of the pixel rows R1 to R4 may extend in the first direction DR1 and may be arranged in the second direction DR2. Each of the pixel rows R1 to R4 may include sub-pixels SPX1 to SPX4. Each of the sub-pixels SPX1 to SPX4 may include one of the pixel circuits PXC11 to PXC18, PXC21 to PXC28, PXC31 to PXC38, and PXC41 to PXC48 and one of the light emitting elements LED1 to LED4.

[0099] In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of a first color, light of a second color, and light of a third color, respectively. The light of the first color, the light of the second color, and the light of the third color may be lights of different colors. Each of the light of the first color, the light of the second color, and the light of the third color may be one of red light, green light, and blue light. A first light-emitting element LED1 configured to emit light of the first color may be located in the first sub-pixel SPX1. A second light-emitting element LED2 configured to emit light of the second color may be located in the second sub-pixel SPX2. A third light-emitting element LED3 configured to emit light of the third color may be located in the third sub-pixel SPX3. A fourth light-emitting element LED4 configured to emit light of the second color may be located in the fourth sub-pixel SPX4. The second light-emitting element LED2 and the fourth light-emitting element LED4 may emit light of the same color.

[0100] exist Figure 4 In the embodiment, each of the light emitting elements LED1 to LED4 can be understood as corresponding to the emission area of ​​the light emitting layer. However, the above is provided for the convenience of explanation, and the color of the light emitted from each of the light emitting elements LED1 to LED4 or the position, surface area, shape, etc. of each of the light emitting elements LED1 to LED4 are not necessarily limited thereto.

[0101] In an embodiment, on each of the odd pixel rows including the first pixel row R1 (or the first horizontal line) and the third pixel row R3 (or the third horizontal line), the subpixels SPX1 to SPX4 may be arranged in the first direction DR1 in the order of a first subpixel SPX1 configured to emit red light, a second subpixel SPX2 configured to emit green light, a third subpixel SPX3 configured to emit blue light, and a fourth subpixel SPX4 configured to emit green light.

[0102] On each of the even pixel rows including the second pixel row R2 (or the second horizontal line) and the fourth pixel row R4 (or the fourth horizontal line), the subpixels SPX1 to SPX4 may be arranged in the first direction DR1 in the order of the third subpixel SPX3, the fourth subpixel SPX4, the first subpixel SPX1, and the second subpixel SPX2.

[0103] In an embodiment, the first sub-pixel SPX1 and the second sub-pixel SPX2 may form a first sub-pixel unit SPU1. The third sub-pixel SPX3 and the fourth sub-pixel SPX4 may form a second sub-pixel unit SPU2. On each of the odd pixel rows R1 and R3, the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 may be alternately disposed. On each of the even pixel rows R2 and R4, the second sub-pixel unit SPU2 and the first sub-pixel unit SPU1 may be alternately disposed in a manner opposite to that of the odd pixel rows R1 and R3.

[0104] The first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 adjacent to each other can be understood as constituting a pixel unit PU. Figure 4 The pixel unit PU on each of the first pixel row R1 and the second pixel row R2 is shown. The present disclosure is not necessarily limited to the above-described example, and the arrangement of the sub-pixels SPX1 to SPX4 may be changed in various ways.

[0105] On the first pixel row R1, pixel circuits PXC11 to PXC18 corresponding to the sub-pixels SPX1 to SPX4 of the first pixel row R1, respectively, may be arranged in the first direction DR1. On the second pixel row R2, pixel circuits PXC21 to PXC28 corresponding to the sub-pixels SPX1 to SPX4 of the second pixel row R2, respectively, may be arranged in the first direction DR1. On the third pixel row R3, pixel circuits PXC31 to PXC38 corresponding to the sub-pixels SPX1 to SPX4 of the third pixel row R3, respectively, may be arranged in the first direction DR1. On the fourth pixel row R4, pixel circuits PXC41 to PXC48 corresponding to the sub-pixels SPX1 to SPX4 of the fourth pixel row R4, respectively, may be arranged in the first direction DR1.

[0106] exist Figure 3 In the embodiment, the first pixel circuit PXC11, the second pixel circuit PXC12, the third pixel circuit PXC13 and the fourth pixel circuit PXC14 of the first pixel row R1 may be included in one pixel unit PU, and the fifth pixel circuit PXC15, the sixth pixel circuit PXC16, the seventh pixel circuit PXC17 and the eighth pixel circuit PXC18 of the first pixel row R1 may be included in another pixel unit PU.

[0107] Similarly, the first pixel circuit PXC21 to the fourth pixel circuit PXC24 of the second pixel row R2, the fifth pixel circuit PXC25 to the eighth pixel circuit PXC28 of the second pixel row R2, the first pixel circuit PXC31 to the fourth pixel circuit PXC34 of the third pixel row R3, the fifth pixel circuit PXC35 to the eighth pixel circuit PXC38 of the third pixel row R3, the first pixel circuit PXC41 to the fourth pixel circuit PXC44 of the fourth pixel row R4, and the fifth pixel circuit PXC45 to the eighth pixel circuit PXC48 of the fourth pixel row R4 may also be included in corresponding different pixel units PU.

[0108] In an embodiment, each of the pixel rows R1 to R4 may include light receiving elements LRD1 to LRD4. Figure 4 In the embodiment, it can be understood that each of the light receiving elements LRD1 to LRD4 corresponds to a light receiving area of ​​the light receiving layer. However, the above example is provided for the convenience of explanation, and the position, surface area, shape, etc. of the light receiving elements LRD1 to LRD4 may be changed in various ways.

[0109] Each of the light receiving elements LRD1 and LRD2 of the first pixel row R1 may overlap with at least some of the pixel circuits PXC11 to PXC14 of the first pixel row R1 and the sensor circuits SC11 and SC12 of the first pixel row R1. Each of the light receiving elements LRD3 and LRD4 of the second pixel row R2 may overlap with at least some of the pixel circuits PXC21 to PXC24 of the second pixel row R2 and the sensor circuits SC21 and SC22 of the second pixel row R2.

[0110] In an embodiment, the first light receiving element LRD1 may overlap at least a portion of the first sensor circuit SC11 of the first pixel row R1. The third light receiving element LRD3 may overlap at least a portion of the first sensor circuit SC21 of the second pixel row R2.

[0111] In addition, the second light receiving element LRD2 may overlap at least a portion of the second sensor circuit SC12 of the first pixel row R1. The fourth light receiving element LRD4 may overlap at least a portion of the second sensor circuit SC22 of the second pixel row R2.

[0112] The light receiving elements LRD1 to LRD4 can be configured as follows: Figure 4 The arrangement shown in FIG. 1 is formed in the display area DA.

[0113] In an embodiment, the sensor circuits SC11 to SC14, SC21 to SC24, SC31 to SC34, and SC41 to SC44 may be electrically connected to corresponding light receiving elements. The first sensor circuit SC11 of the first pixel row R1 may be electrically connected to the first light receiving element LRD1, thereby forming a first optical sensing pixel PSR1. For example, the first sensor circuit SC11 and the first light receiving element LRD1 may form a first optical sensing pixel PSR1. The second sensor circuit SC12 of the first pixel row R1 may be electrically connected to the second light receiving element LRD2, thereby forming a second optical sensing pixel PSR2. For example, the second sensor circuit SC12 and the second light receiving element LRD2 may form a second optical sensing pixel PSR2. The first sensor circuit SC21 of the second pixel row R2 may be electrically connected to the third light receiving element LRD3, thereby forming a third optical sensing pixel PSR3. For example, the first sensor circuit SC21 and the third light receiving element LRD3 may form a third optical sensing pixel PSR3. The second sensor circuit SC22 of the second pixel row R2 may be electrically connected to the fourth light receiving element LRD4, thereby forming a fourth optical sensing pixel PSR4. For example, the second sensor circuit SC22 and the fourth light receiving element LRD4 may form a fourth optical sensing pixel PSR4. However, the present disclosure is not necessarily limited to the above examples. In an embodiment, only some of the sensor circuits SC11 to SC14, SC21 to SC24, SC31 to SC34, and SC41 to SC44 may be provided, and the some sensor circuits may be connected to a plurality of light receiving elements.

[0114] The first sensor circuit SC11 of the first pixel row R1 may be disposed between the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 included in the pixel unit PU. For example, the first pixel circuit PXC11 and the second pixel circuit PXC12 of the first pixel row R1 may be included in the first sub-pixel unit SPU1. The third pixel circuit PXC13 and the fourth pixel circuit PXC14 of the first pixel row R1 may be included in the second sub-pixel unit SPU2. Therefore, at least two pixel circuits (e.g., the third pixel circuit PXC13 and the fourth pixel circuit PXC14) may be disposed between the first sensor circuit SC11 and the second sensor circuit SC12 adjacent to each other on the first pixel row R1.

[0115] The second sensor circuit SC12 of the first pixel row R1, the first sensor circuit SC21 of the second pixel row R2, and the second sensor circuit SC22 of the second pixel row R2 may be arranged between the first sub-pixel unit SPU1 and the second sub-pixel unit SPU2 in a manner similar to that of the first sensor circuit SC11 of the first pixel row R1. The arrangement of the sensor circuits SC11 to SC14, SC21 to SC24, SC31 to SC34, and SC41 to SC44 is not necessarily limited to the above example. In an embodiment, as Figure 5A As shown in , four pixel circuits (e.g., a third pixel circuit PXC13, a fourth pixel circuit PXC14, a fifth pixel circuit PXC15, and a sixth pixel circuit PXC16) may be disposed between the first sensor circuit SC11 and the second sensor circuit SC12 adjacent to each other on the first pixel row R1. Figure 5B As shown in , a pixel circuit (eg, a second pixel circuit PXC12) may be disposed between a first sensor circuit SC11 and a second sensor circuit SC12 adjacent to each other on a first pixel row R1. Figure 5C As shown in the figure, six pixel circuits (for example, a third pixel circuit PXC13, a fourth pixel circuit PXC14, a fifth pixel circuit PXC15, a sixth pixel circuit PXC16, a seventh pixel circuit PXC17 and an eighth pixel circuit PXC18) can be arranged between a first sensor circuit SC11 and a second sensor circuit SC12 that are adjacent to each other on a first pixel row R1.

[0116] Figure 6 It is shown that the Figure 1 Schematic circuit diagram of an example of a sub-pixel SPX and an optical sensing pixel PSR in a display area DA. For ease of description, Figure 6 A sub-pixel SPX located on an i-th horizontal line (or i-th pixel row) and connected to a j-th data line Dj is shown.

[0117] refer to Figure 1 and Figure 6 , the sub-pixels SPX and the optical sensing pixels PSR may be disposed on an i-th horizontal line.

[0118] The subpixel SPX may include a light emitting element LED and a pixel circuit PXC. In an embodiment, the pixel circuit PXC may include first, second, third, fourth, fifth, sixth, and seventh transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a boost capacitor Cbst.

[0119] The first transistor T1 (or driving transistor) may be connected between the first power line PL1 and the first electrode (or anode electrode) of the light emitting element LED. The first transistor T1 may include a gate electrode electrically connected to the first node N1. The first transistor T1 may control the amount of current (or driving current) flowing from the first power line PL1 to the electrode EP (or power line) via the light emitting element LED based on the voltage of the first node N1. The first power voltage VDD may be provided to the first power line PL1. The second power voltage VSS may be provided to the electrode EP. The first power voltage VDD may be set to a voltage higher than the second power voltage VSS.

[0120] The second transistor T2 may be electrically connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 may be connected to the 1i-th scan line S1i (or the first scan line). In the case where the first scan signal GW[i] (e.g., the low-level first scan signal GW[i]) is provided to the 1i-th scan line S1i, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the second node N2. In the case where each of the first transistor T1 and the third transistor T3 is turned on, the second transistor T2 may transmit the data signal of the j-th data line Dj to the second node N2 in response to the first scan signal GW[i].

[0121] The third transistor T3 may be electrically connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 may be electrically connected to the 4i-th scan line S4i (or the third scan line). When the fourth scan signal GC[i] is provided to the 4i-th scan line S4i, the third transistor T3 may be turned on. If the third transistor T3 is turned on, the first transistor T1 may have a diode connection form.

[0122] The fourth transistor T4 may be electrically connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 may be electrically connected to the 2i-th scan line S2i (or the second scan line). The first initialization power voltage Vint1 may be provided to the second power line PL2. The fourth transistor T4 may be turned on by the second scan signal GI[i] provided to the 2i-th scan line S2i. If the fourth transistor T4 is turned on, the first initialization power voltage Vint1 may be provided to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0123] The fifth transistor T5 may be electrically connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 may be electrically connected to the i-th emission control line Ei. The sixth transistor T6 may be electrically connected between the third node N3 and the light emitting element LED (or the fourth node N4). The gate electrode of the sixth transistor T6 may be electrically connected to the i-th emission control line Ei. When the emission control signal EM[i] (e.g., the emission control signal EM[i] of a high level) is provided to the i-th emission control line Ei, the fifth transistor T5 and the sixth transistor T6 may be turned off, and may be turned on in other cases.

[0124] The seventh transistor T7 may be electrically connected between the first electrode (i.e., the fourth node N4) of the light emitting element LED and the third power line PL3. The gate electrode of the seventh transistor T7 may be electrically connected to the 3i-th scan line S3i. The second initialization power voltage Vint2 may be provided to the third power line PL3. In an embodiment, the second initialization power voltage Vint2 may be different from the first initialization power voltage Vint1. The seventh transistor T7 may be turned on by the third scan signal GB[i] provided to the 3i-th scan line S3i to provide the second initialization power voltage Vint2 to the first electrode of the light emitting element LED.

[0125] The storage capacitor Cst may be connected or formed between the first power line PL1 and the first node N1.

[0126] The boosting capacitor Cbst (or capacitor) may be connected or formed between the gate electrode of the second transistor T2 and the gate electrode of the first transistor T1 .

[0127] The optical sensing pixel PSR may include a sensor circuit SC and a light receiving element LRD. The sensor circuit SC may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.

[0128] The eighth transistor T8 and the tenth transistor T10 may be connected in series between the fifth power line PL5 and a kth readout line RXk (where k is a positive integer).

[0129] The eighth transistor T8 (or the first sensor transistor) may be electrically connected between the fifth power line PL5 and the tenth transistor T10. The gate electrode of the eighth transistor T8 may be electrically connected to the fifth node N5 (or the sensor node). The eighth transistor T8 may control the current flowing from the fifth power line PL5 to the kth readout line RXk through the tenth transistor T10 in response to the voltage of the fifth node N5. The common voltage VCOM may be provided to the fifth power line PL5.

[0130] In an embodiment, the fifth power line PL5 may be electrically connected to the third power line PL3 or formed integrally with the third power line PL3. The common voltage VCOM applied to the fifth power line PL5 may be the same as the second initialization power voltage Vint2. However, the present disclosure is not necessarily limited to the above example. In an embodiment, the fifth power line PL5 may be electrically connected to the second power line PL2 or formed integrally with the second power line PL2. The common voltage VCOM applied to the fifth power line PL5 may be the same as the first initialization power voltage Vint1.

[0131] The tenth transistor T10 ("second sensor transistor" or "switch transistor") may be electrically connected between the eighth transistor T8 and the kth readout line RXk. The gate electrode of the tenth transistor T10 may be connected to the 1ith scan line S1i. For example, the gate electrode of the tenth transistor T10 and the gate electrode of the second transistor T2 may share the 1ith scan line S1i.

[0132] The ninth transistor T9 (or the third sensor transistor) may be electrically connected between the fourth power line PL4 (or the reference power line) and the fifth node N5. The gate electrode of the ninth transistor T9 may be electrically connected to the reset line RSTL. The reset voltage VRST may be provided to the fourth power line PL4. The reset voltage VRST may be a DC voltage having a constant level. For example, the reset voltage VRST may be about -7V, but is not necessarily limited thereto.

[0133] At least one light receiving element LRD may be electrically connected between the fifth node N5 and the electrode EP to which the second power voltage VSS is supplied.

[0134] The light receiving element LRD can generate a charge (or current) based on the incident light. For example, the light receiving element LRD can perform a function of photoelectric conversion. For example, the light receiving element LRD can be implemented as a photodiode. The light receiving element LRD can be configured to output a sensing signal corresponding to the light emitted from the light emitting element LED.

[0135] If the ninth transistor T9 is turned on in response to the reset signal RST provided to the reset control line RSTL, the reset voltage VRST may be provided to the fifth node N5. For example, the voltage of the fifth node N5 may be reset by the reset voltage VRST. After the reset voltage VRST is applied to the fifth node N5, the light receiving element LRD may perform a function of photoelectric conversion.

[0136] The voltage of the fifth node N5 can be changed by the operation of the light receiving element LRD. The voltage of the fifth node N5 (or the charge or current generated from the light receiving element LRD) can be changed according to the intensity of light incident on the light receiving element LRD or the time of light incidence (or the time the light receiving element LRD is exposed).

[0137] If the tenth transistor T10 is turned on by the first scan signal GW[i] supplied to the li-th scan line S1i, a detection value (current and / or voltage) generated based on the voltage of the fifth node N5 may flow to the k-th readout line RXk.

[0138] In an embodiment, each of the pixel circuit PXC and the sensor circuit SC may include a P-type transistor and an N-type transistor. Each of the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be formed by an oxide semiconductor transistor including an oxide semiconductor (or a second type semiconductor). For example, each of the third transistor T3, the fourth transistor T4, and the ninth transistor T9 may be formed by an N-type oxide semiconductor transistor and include an oxide semiconductor layer as an active layer, but is not necessarily limited thereto.

[0139] Each of the other transistors (e.g., the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10) may be formed by a polysilicon transistor including a silicon semiconductor (or a first type semiconductor), and may include a polysilicon semiconductor layer as an active layer. For example, the active layer may be formed by a low temperature polysilicon (LTPS) process.

[0140] In the following, reference Figure 7 and Figure 8 , the following description will focus on the stacked structure (or cross-sectional structure) of the sub-pixel SPX including the light emitting element LED and the optical sensing pixel PSR including the light receiving element LRD.

[0141] Figure 7 is a schematic cross-sectional view showing one region of the display device 1 according to the embodiment. Figure 8 It is shown Figure 7 Schematic cross-sectional view of the reflection path of light in the display device 1.

[0142] Figure 7 and Figure 8 Shows Figure 6 , a cross section of a portion of the first to seventh transistors T1 to T7 corresponding to the sixth transistor T6 and a cross section of a portion of the eighth to tenth transistors T8 to T10 corresponding to the ninth transistor T9 are shown.

[0143] refer to Figures 1 to 8 , the display device 1 may include sub-pixels SPX and optical sensing pixels PSR provided in a region of a substrate SUB.

[0144] The pixel circuit layer PCL of the sub-pixel SPX and the pixel circuit layer PCL of the optical sensing pixel PSR may be disposed on the substrate SUB. One or more insulating layers may be disposed in the pixel circuit layer PCL. The insulating layer may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, a fifth insulating layer INS5, a sixth insulating layer INS6, a seventh insulating layer INS7, an eighth insulating layer INS8, and a ninth insulating layer INS9.

[0145] The first insulating layer INS1 (or buffer layer) may be disposed on the surface of the substrate SUB. The first insulating layer INS1 may prevent impurities from diffusing into the sixth transistor T6 and the ninth transistor T9. The first insulating layer INS1 may be formed of an inorganic layer including an inorganic material (or substance). The first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and / or aluminum oxide (AlO x Although the first insulating layer INS1 may have a single-layer structure, the first insulating layer INS1 may also have a multi-layer structure including two or more layers. Depending on the material or process conditions of the substrate SUB, the first insulating layer INS1 may be omitted.

[0146] The second insulating layer INS2 (or the first gate insulating layer) may be disposed on the surface of the first insulating layer INS1. The second insulating layer INS2 may include the same material as the first insulating layer INS1, or may include a suitable (or selected) material among the materials exemplified as the constituent material of the first insulating layer INS1. For example, the second insulating layer INS2 may be formed of an inorganic layer including an inorganic material.

[0147] The third insulating layer INS3 (or second gate insulating layer) may be disposed on the surface of the second insulating layer INS2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials among the materials exemplified as constituent materials of the first insulating layer INS1.

[0148] The fourth insulating layer INS4 (or the first interlayer insulating layer) may be disposed on the surface of the third insulating layer INS3. The fourth insulating layer INS4 may be an inorganic layer including an inorganic material or an organic layer including an organic material.

[0149] The fifth insulating layer INS5 (or the third gate insulating layer) may be disposed on the surface of the fourth insulating layer INS4. The fifth insulating layer INS5 may be an inorganic layer including an inorganic material or an organic layer including an organic material.

[0150] The sixth insulating layer INS6 (or the second interlayer insulating layer) may be disposed on the surface of the fifth insulating layer INS5. The sixth insulating layer INS6 may be an inorganic layer including an inorganic material or an organic layer including an organic material.

[0151] The seventh insulating layer INS7 (or the first through hole layer) may be disposed on the surface of the sixth insulating layer INS6. The seventh insulating layer INS7 may be an inorganic layer including an inorganic material or an organic layer including an organic material. The inorganic layer may include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) and / or aluminum oxide (AlO x ). The organic layer may include, for example, a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and / or a benzocyclobutene resin.

[0152] The eighth insulating layer INS8 (or the second through-hole layer) may be disposed on the surface of the seventh insulating layer INS7. The eighth insulating layer INS8 may include the same material as the seventh insulating layer INS7, or may include one or more suitable (or selected) materials among the materials exemplified as the constituent materials of the seventh insulating layer INS7. For example, the eighth insulating layer INS8 may be an organic layer including an organic material.

[0153] The ninth insulating layer INS9 (or the third through-hole layer) may be disposed on the surface of the eighth insulating layer INS8. The ninth insulating layer INS9 may include the same material as the seventh insulating layer INS7, or may include one or more suitable (or selected) materials among the materials exemplified as the constituent materials of the seventh insulating layer INS7. For example, the ninth insulating layer INS9 may be an organic layer including an organic material.

[0154] The pixel circuit layer PCL may include a plurality of layers disposed between the aforementioned insulating layers. For example, the pixel circuit layer PCL may include a first additional layer FL, a second additional layer SL, a third additional layer TL, a fourth additional layer FOL, a fifth additional layer FIL, a sixth additional layer SIL, a seventh additional layer SEL, an eighth additional layer EIL, and a ninth additional layer NIL.

[0155] The first additional layer FL may be disposed between the substrate SUB and the first insulating layer INS1 and form a first conductive layer CL1. The second additional layer SL may be disposed between the first insulating layer INS1 and the second insulating layer INS2 and form a first semiconductor layer SCL1. The third additional layer TL may be disposed between the second insulating layer INS2 and the third insulating layer INS3 and form a second conductive layer CL2. The fourth additional layer FOL may be disposed between the third insulating layer INS3 and the fourth insulating layer INS4 and form a third conductive layer CL3. The fifth additional layer FIL may be disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5 and form a second semiconductor layer SCL2. The sixth additional layer SIL may be disposed between the fifth insulating layer INS5 and the sixth insulating layer INS6 and form a fourth conductive layer CL4. The seventh additional layer SEL may be disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7 and form a fifth conductive layer CL5. The eighth additional layer EIL may be disposed between the seventh insulating layer INS7 and the eighth insulating layer INS8 and form a sixth conductive layer CL6. The ninth additional layer NIL may be disposed between the eighth insulating layer INS8 and the ninth insulating layer INS9 and form the seventh conductive layer CL7.

[0156] The first semiconductor layer SCL1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The first semiconductor layer SCL1 includes low-temperature polycrystalline silicon, but is not necessarily limited thereto. The first semiconductor layer SCL1 may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant. An N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region or a region doped at a lower concentration than the first region. The conductivity of the first region may be greater than the conductivity of the second region. The first region may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active pattern (or channel region) of a corresponding transistor. A portion of the first semiconductor layer SCL1 may be an active region of a transistor. Another portion of the first semiconductor layer SCL1 may be a source or a drain of a transistor. Another portion of the first semiconductor layer SCL1 may be a connecting electrode or a connecting signal line. However, the present disclosure is not necessarily limited to the above examples.

[0157] The second semiconductor layer SCL2 may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions distinguished from each other according to whether the metal oxide has been reduced. The region where the metal oxide has been reduced (hereinafter referred to as the "reduction region") may have a relatively high conductivity compared to the region where the metal oxide has not been reduced (hereinafter referred to as the "unreduced region"). The reduction region may be substantially used as a source / drain or a signal line of a corresponding transistor. The unreduced region may substantially correspond to an active pattern (or channel region) of a transistor. A portion of the second semiconductor layer SCL2 may be an active pattern of a transistor. Another portion of the second semiconductor layer SCL2 may be a source region / drain region of a transistor. Another portion of the second semiconductor layer SCL2 may be a signal transmission region. However, the present disclosure is not necessarily limited to the above examples.

[0158] The sixth transistor T6 and the ninth transistor T9 may be disposed in the pixel circuit layer PCL. The sixth transistor T6 may include a first gate electrode GE1, a first semiconductor pattern SCP1, a first terminal TE1, and a second terminal TE2. The ninth transistor T9 may include a second gate electrode GE2, a fourth semiconductor pattern SCP4, a third terminal TE3, and a fourth terminal TE4.

[0159] The first semiconductor pattern SCP1 may correspond to the second additional layer SL disposed on the first insulating layer INS1. The first semiconductor pattern SCP1 may be formed of the first semiconductor layer SCL1. The first semiconductor pattern SCP1 may include a channel region, a first contact region contacting a first end of the channel region, and a second contact region contacting a second end of the channel region. The second insulating layer INS2 may be disposed on the first semiconductor pattern SCP1.

[0160] The first gate electrode GE1 may correspond to a third additional layer TL disposed on the second insulating layer INS2. The first gate electrode GE1 may be formed of a second conductive layer CL2. The second conductive layer CL2 may be formed of a single layer structure or a multilayer structure made of molybdenum (Mo), copper (Cu), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and oxides or alloys thereof. For example, the second conductive layer CL2 may be formed as a multilayer structure formed by sequentially or repeatedly stacking titanium, copper, and / or indium tin oxide, but is not necessarily limited thereto. The first gate electrode GE1 may overlap with a region of the first semiconductor pattern SCP1. A region of the first semiconductor pattern SCP1 that overlaps with the first gate electrode GE1 may be a channel region of the sixth transistor T6.

[0161] A third insulating layer INS3 may be disposed on the first gate electrode GE1 .

[0162] The first terminal TE1 and the second terminal TE2 may correspond to the seventh additional layer SEL disposed on the sixth insulating layer INS6. The first terminal TE1 and the second terminal TE2 may be formed by a fifth conductive layer CL5. The fifth conductive layer CL5 may be formed as a single layer or multilayer structure formed of molybdenum, copper, aluminum, chromium, gold, silver, titanium, nickel, neodymium, indium, tin, and oxides or alloys thereof.

[0163] The first terminal TE1 may be electrically connected to the second contact region of the first semiconductor pattern SCP1 through a first contact portion CNT1 passing through the second insulating layer INS2, the third insulating layer INS3, the fourth insulating layer INS4, the fifth insulating layer INS5, and the sixth insulating layer INS6. The first terminal TE1 may be electrically connected to the anode electrode AE ​​of the light emitting element LED. The second terminal TE2 may be electrically connected to the first contact region of the first semiconductor pattern SCP1 through another first contact portion CNT1 passing through the second insulating layer INS2, the third insulating layer INS3, the fourth insulating layer INS4, the fifth insulating layer INS5, and the sixth insulating layer INS6.

[0164] A seventh insulating layer INS7 may be disposed on the first and second terminals TE1 and TE2 .

[0165] The fourth semiconductor pattern SCP4 may correspond to the fifth additional layer FIL disposed on the fourth insulating layer INS4. The fourth semiconductor pattern SCP4 may be formed of the second semiconductor layer SCL2. The fourth semiconductor pattern SCP4 may include a channel region, a first contact region contacting a first end of the channel region, and a second contact region contacting a second end of the channel region. A fifth insulating layer INS5 may be disposed on the fourth semiconductor pattern SCP4.

[0166] The second gate electrode GE2 may correspond to the sixth additional layer SIL disposed on the fifth insulating layer INS5. The second gate electrode GE2 may be formed by the fourth conductive layer CL4. The fourth conductive layer CL4 may include the same material as the second conductive layer CL2 or the fifth conductive layer CL5, or may include a suitable (or selected) material among the materials exemplified as the material of the second conductive layer CL2 or the fifth conductive layer CL5. The second gate electrode GE2 may overlap with a region of the fourth semiconductor pattern SCP4. A region of the fourth semiconductor pattern SCP4 overlapping with the second gate electrode GE2 may be a channel region of the ninth transistor T9.

[0167] A sixth insulating layer INS6 may be disposed on the second gate electrode GE2 .

[0168] The third terminal TE3 and the fourth terminal TE4 may correspond to a seventh additional layer SEL disposed on the sixth insulating layer INS6. The third terminal TE3 and the fourth terminal TE4 may be formed of a fifth conductive layer CL5.

[0169] The third terminal TE3 may be electrically connected to the first contact region of the fourth semiconductor pattern SCP4 through the second contact portion CNT2 passing through the fifth insulating layer INS5 and the sixth insulating layer INS6. The third terminal TE3 may be electrically connected to the first electrode EL1 of the light receiving element LRD. The fourth terminal TE4 may be electrically connected to the second contact region of the fourth semiconductor pattern SCP4 through another second contact portion CNT2 passing through the fifth insulating layer INS5 and the sixth insulating layer INS6.

[0170] A seventh insulating layer INS7 may be disposed on the third and fourth terminals TE3 and TE4.

[0171] The bottom metal pattern BML may be disposed in the pixel circuit layer PCL. The bottom metal pattern BML may correspond to a first additional layer FL disposed on the substrate SUB. The bottom metal pattern BML may be formed by the first conductive layer CL1 and overlap with the sixth transistor T6, but is not necessarily limited thereto. The first conductive layer CL1 may include the same material as the second conductive layer CL2 or the fifth conductive layer CL5, or may include a suitable (or selected) material among the materials exemplified as the material of the second conductive layer CL2 or the fifth conductive layer CL5. In an embodiment, the bottom metal pattern BML may be electrically connected to the sixth transistor T6, thereby stabilizing the channel region of the sixth transistor T6.

[0172] The storage capacitor Cst may be provided in the pixel circuit layer PCL. The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0173] The lower electrode LE may correspond to the third additional layer TL disposed on the second insulating layer INS2. The lower electrode LE may be formed of the second conductive layer CL2 and disposed in the same layer as the first gate electrode GE1, but is not necessarily limited thereto. A third insulating layer INS3 may be disposed on the lower electrode LE.

[0174] The upper electrode UE may correspond to the fourth additional layer FOL disposed on the third insulating layer INS3. The upper electrode UE may be formed by the third conductive layer CL3, but is not necessarily limited thereto. The third conductive layer CL3 may include the same material as the second conductive layer CL2 or the fifth conductive layer CL5, or may include a suitable (or selected) material among the materials exemplified as the materials of the second conductive layer CL2 or the fifth conductive layer CL5. The upper electrode UE may overlap with the lower electrode LE, with the third insulating layer INS3 interposed therebetween, thereby forming a capacitor.

[0175] The first connection line CNL1 , the second connection line CNL2 , the first bridge pattern BRP1 , and the second bridge pattern BRP2 may be disposed in the pixel circuit layer PCL.

[0176] The first connection wires CNL1 and the second connection wires CNL2 may correspond to the eighth additional layer EIL disposed on the seventh insulating layer INS7. The first connection wires CNL1 and the second connection wires CNL2 may be formed of the sixth conductive layer CL6. The sixth conductive layer CL6 may include the same material as the second conductive layer CL2 or the fifth conductive layer CL5, or may include a suitable (or selected) material among the materials exemplified as the materials of the second conductive layer CL2 or the fifth conductive layer CL5.

[0177] The first connection line CNL1 and the second connection line CNL2 may be spaced apart from each other on the seventh insulating layer INS7. The first connection line CNL1 may be electrically connected to the first terminal TE1 of the sixth transistor T6 by passing through a first through hole VIH1 of the seventh insulating layer INS7. The second connection line CNL2 may be electrically connected to the third terminal TE3 of the ninth transistor T9 by passing through another first through hole VIH1 of the seventh insulating layer INS7.

[0178] An eighth insulating layer INS8 may be disposed on the first and second connection lines CNL1 and CNL2 .

[0179] The first bridge pattern BRP1 and the second bridge pattern BRP2 may correspond to the ninth additional layer NIL disposed on the eighth insulating layer INS8. The first bridge pattern BRP1 and the second bridge pattern BRP2 may be formed of the seventh conductive layer CL7. The seventh conductive layer CL7 may include the same material as the second conductive layer CL2 or the fifth conductive layer CL5, or may include a suitable (or selected) material among the materials exemplified as the materials of the second conductive layer CL2 or the fifth conductive layer CL5.

[0180] The first bridge pattern BRP1 and the second bridge pattern BRP2 may be disposed at positions spaced apart from each other on the eighth insulating layer INS8. The first bridge pattern BRP1 may be electrically connected to the first connection line CNL1 via a second through hole VIH2 passing through the eighth insulating layer INS8. The second bridge pattern BRP2 may be electrically connected to the second connection line CNL2 via another second through hole VIH2 passing through the eighth insulating layer INS8.

[0181] A ninth insulating layer INS9 may be disposed on the first and second bridge patterns BRP1 and BRP2.

[0182] The display element layer DPL may be disposed on the pixel circuit layer PCL of the sub-pixel SPX. The sensor layer SSL may be disposed on the pixel circuit layer PCL of the optical sensing pixel PSR.

[0183] The light emitting element LED and the bank BNK may be disposed in the display element layer DPL. The light emitting element LED may include an anode electrode AE ​​(or a pixel electrode), a light emitting layer EML, and a cathode electrode CE (or a common electrode). The light emitting element LED may be electrically connected to the sixth transistor T6 through the first bridge pattern BRP1 and the first connection line CNL1. The light emitting layer EML may include a hole transport layer, an organic material layer (or a light generating layer), and an electron transport layer.

[0184] The light receiving element LRD and the bank BNK may be provided in the sensor layer SSL. The light receiving element LRD may be an optical fingerprint sensor. The light receiving element LRD may identify the fingerprint by sensing the light reflected by the ridge FR of the finger F and the valley FV between the ridges FR. For example, if the user's finger F touches the window WD, the first light L1 output from the light emitting element LED (or the light emitting layer EML) is reflected by the ridge FR or the valley FV of the finger F, and the reflected second light L2 may reach the light receiving element LRD (or the light receiving layer OPL) of the sensor layer SSL. The light receiving element LRD may distinguish between the second light L2 reflected by the ridge FR of the finger F and the second light L2 reflected by the valley FV of the finger F, thereby identifying the pattern of the user's fingerprint. The light receiving element LRD may be electrically connected to the ninth transistor T9. The light receiving element LRD may include a first electrode EL1 (or a first sensor electrode), a light receiving layer OPL (or a photoelectric conversion layer), and a second electrode EL2 (or a second sensor electrode).

[0185] The anode electrode AE ​​and the first electrode EL1 may be disposed on the ninth insulating layer INS9. The anode electrode AE ​​and the first electrode EL1 may be formed of a metal layer made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or an alloy thereof and / or indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc., but are not necessarily limited thereto. The anode electrode AE ​​may be electrically connected to the first bridge pattern BRP1 through a contact hole passing through the ninth insulating layer INS9. The first electrode EL1 may be electrically connected to the second bridge pattern BRP2 through another contact hole passing through the ninth insulating layer INS9.

[0186] The anode electrode AE ​​and the first electrode EL1 may be formed simultaneously or sequentially by patterning using a mask.

[0187] The bank BNK may be a pixel defining layer that defines (or divides) the emission area EMA of the sub-pixel SPX and the light receiving area FXA of the optical sensing pixel PSR. The bank BNK may be an organic layer including an organic material (or substance). The organic material may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0188] In an embodiment, the bank BNK may include a light absorbing material or be coated with a light absorber so that the bank BNK can be used to absorb light introduced from the outside. For example, the bank BNK may include a carbon-based black pigment, but is not necessarily limited thereto. The bank BNK may include an opaque metal with a high light absorptivity, such as chromium (Cr), molybdenum (Mo), an alloy (MoTi) of molybdenum (Mo) and titanium (Ti), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni).

[0189] The bank BNK may include openings corresponding to the emission area EMA and the light receiving area FXA.

[0190] The light emitting layer EML may be disposed on the anode electrode AE. The light emitting layer EML may include an organic light emitting layer. The light emitting layer EML may emit light such as red light, green light, or blue light, depending on an organic material included in the light emitting layer EML, but is not necessarily limited thereto.

[0191] A light receiving layer OPL may be disposed on the first electrode EL1. The light receiving layer OPL may sense the intensity of light by emitting electrons in response to light of a specific wavelength band.

[0192] The light receiving layer OPL may include a low molecular weight organic material (or substance). For example, the light receiving layer OPL may be made of a phthalocyanine compound including copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La) and / or zinc (Zn).

[0193] Alternatively, the low molecular weight organic material included in the light receiving layer OPL may be formed of a double-layer structure including a layer including a phthalocyanine compound and a layer including a C 60 The phthalocyanine compound includes copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La) and / or zinc (Zn), or the phthalocyanine compound and C60 Mixed layers mixed with each other are formed. However, the present disclosure is not necessarily limited to the above-mentioned embodiments. In an embodiment, the light receiving layer OPL may include a polymer organic layer.

[0194] In an embodiment, the light receiving layer OPL can determine the light detection wavelength band of the optical sensing pixel PSR by controlling the selection of the metal component included in the phthalocyanine compound. For example, the phthalocyanine compound including copper can absorb the visible light wavelength in the wavelength band in the range of about 600nm to about 800nm. The phthalocyanine compound including tin can absorb the near-infrared wavelength in the wavelength band in the range of about 800nm ​​to about 1000nm. Therefore, the optical sensing pixel PSR (or optical sensor) capable of detecting the wavelength of the wavelength band desired by the user can be realized by controlling the selection of the metal to be included in the phthalocyanine compound. For example, the light receiving element LRD can be formed to selectively absorb the wavelength of the red light wavelength band, the wavelength of the green light wavelength band, or the wavelength of the blue light wavelength band through the light receiving layer OPL.

[0195] The cathode electrode CE may be disposed on the light emitting layer EML. The second electrode EL2 may be disposed on the light receiving layer OPL. The cathode electrode CE and the second electrode EL2 may be common electrodes integrally formed in the display area DA. The second power voltage VSS may be supplied to the cathode electrode CE and the second electrode EL2.

[0196] The cathode electrode CE and the second electrode EL2 may be formed of a metal layer made of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc. and / or a transparent conductive layer made of ITO, IZO, ZnO, ITZO, etc. In an embodiment, the cathode electrode CE and the second electrode EL2 may be formed of a multilayer structure having two or more layers including a thin metal layer. For example, the common electrode may be formed of a three-layer structure of ITO / Ag / ITO.

[0197] A thin film encapsulation layer TFE may be formed on surfaces of the cathode electrode CE and the second electrode EL2 .

[0198] The thin film encapsulation layer TFE may be formed of a single layer or multiple layers. The thin film encapsulation layer TFE may include a plurality of insulating layers covering the light emitting element LED and the light receiving element LRD. For example, the thin film encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the thin film encapsulation layer TFE may have a structure formed by alternately stacking inorganic layers and organic layers.

[0199] The color filter layer CFL may be disposed on the thin film encapsulation layer TFE. The color filter layer CFL may include a light blocking pattern and a color filter. The light blocking pattern may be disposed in a non-emission area NEA surrounding an emission area EMA of a sub-pixel SPX and a light receiving area FXA of an optical sensing pixel PSR. A color filter may be disposed in the emission area EMA and the light receiving area FXA. The color filter layer CFL may be used as an anti-reflection layer to block external light reflection.

[0200] The window WD may be disposed on the color filter layer CFL.

[0201] The window WD can protect the display device 1 or the display panel (refer to the Figure 1 The window WD may protect the display device 1 from external impacts and provide an input surface and / or a display surface to the user. The window WD (or cover glass) may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The multilayer structure may be formed by a continuous process or a bonding process using an adhesive layer. The window WD may be fully or partially flexible.

[0202] Fig. 9 is a schematic plan view showing sub-pixels SPX1 to SPX4 and a first optical sensing pixel PSR1 according to an embodiment. Fig.10 It is shown that the Fig. 9 Schematic plan view of the components in the first additional layer FL. Fig.11 It is shown that the Fig. 9 Schematic plan view of the components in the second additional layer SL and the third additional layer TL in FIG. Fig.12 It is shown that the Fig. 9 Schematic plan view of the components in the fourth additional layer FOL. Fig.13 It is shown that the Fig. 9 Schematic plan view of components in the fifth additional layer FIL and the sixth additional layer SIL. Fig.14 It is shown that the Fig. 9 Schematic plan view of the components in the seventh additional layer SEL. Fig.15 It is shown that the Fig. 9 Schematic plan view of the components in the eighth additional layer EIL. Fig.16 It is shown that the Fig. 9 Schematic plan view of the components in the ninth additional layer NIL. Figures 17 to 19 It is along Fig. 9 A schematic cross-sectional view taken along line II'.

[0203] Fig.18 and Fig.19 Shows Fig.17Modifications of the embodiment regarding the arrangement relationship and shape of the twelfth additional line WL12 and the thirteenth additional line WL13.

[0204] exist Figures 9 to 19 , for convenience of explanation, the first subpixel SPX1 , the second subpixel SPX2 , the third subpixel SPX3 , the fourth subpixel SPX4 , and the first optical sensing pixel PSR1 arranged on the same pixel row (or the same horizontal line) are illustrated.

[0205] refer to Figures 1 to 19 , the first sub-pixel SPX1 , the second sub-pixel SPX2 , the third sub-pixel SPX3 , and the fourth sub-pixel SPX4 may be arranged in the first direction DR1 , and the first optical sensing pixel PSR1 may be disposed between the second sub-pixel SPX2 and the third sub-pixel SPX3 .

[0206] Each of the first to fourth subpixels SPX1 to SPX4 may include a pixel circuit PXC. For example, the first subpixel SPX1 may include a first pixel circuit PXC1. The second subpixel SPX2 may include a second pixel circuit PXC2. The third subpixel SPX3 may include a third pixel circuit PXC3. The fourth subpixel SPX4 may include a fourth pixel circuit PXC4.

[0207] The first optical sensing pixel PSR1 may include a sensor circuit SC.

[0208] The first to fourth subpixels SPX1 to SPX4 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a thin film encapsulation layer TFE, a color filter layer CFL, and a window WD. The sensor circuit SC may include a substrate SUB, a pixel circuit layer PCL, a sensor layer SSL, a thin film encapsulation layer TFE, a color filter layer CFL, and a window WD.

[0209] The substrate SUB may include a transparent insulating material allowing light to be transmitted. The substrate SUB may be a rigid substrate or a flexible substrate.

[0210] The first to fourth pixel circuits PXC1 to PXC4 , the sensor circuits SC, and the signal lines may be provided in the pixel circuit layer PCL.

[0211] The light emitting element (reference Figure 6 The “LED” in the display element layer DPL can be provided in the display element layer DPL. The light receiving element (reference Figure 6 The “LRD” in the figure) can be set in the sensor layer SSL.

[0212] The first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, the fourth insulating layer INS4, the fifth insulating layer INS5, the sixth insulating layer INS6, the seventh insulating layer INS7, the eighth insulating layer INS8, and the ninth insulating layer INS9 may be sequentially stacked on the substrate SUB in the third direction DR3.

[0213] One or more conductive layers and one or more semiconductor layers may be disposed on the substrate SUB. For example, the conductive layer may include a first conductive layer CL1 between the substrate SUB and the first insulating layer INS1, a second conductive layer CL2 between the second insulating layer INS2 and the third insulating layer INS3, a third conductive layer CL3 between the third insulating layer INS3 and the fourth insulating layer INS4, a fourth conductive layer CL4 between the fifth insulating layer INS5 and the sixth insulating layer INS6, a fifth conductive layer CL5 between the sixth insulating layer INS6 and the seventh insulating layer INS7, a sixth conductive layer CL6 between the seventh insulating layer INS7 and the eighth insulating layer INS8, and a seventh conductive layer CL7 between the eighth insulating layer INS8 and the ninth insulating layer INS9. The semiconductor layer may include a first semiconductor layer SCL1 formed of polysilicon and located between the first insulating layer INS1 and the second insulating layer INS2, and a second semiconductor layer SCL2 formed of an oxide semiconductor and located between the fourth insulating layer INS4 and the fifth insulating layer INS5. The first conductive layer CL1, the first semiconductor layer SCL1, the second conductive layer CL2, the third conductive layer CL3, the second semiconductor layer SCL2, the fourth conductive layer CL4, the fifth conductive layer CL5, the sixth conductive layer CL6, and the seventh conductive layer CL7 may be sequentially stacked on one surface of the substrate SUB in the third direction DR3. According to the stacking order, the first conductive layer CL1 may correspond to the first additional layer FL, the first semiconductor layer SCL1 may correspond to the second additional layer SL, the second conductive layer CL2 may correspond to the third additional layer TL, the third conductive layer CL3 may correspond to the fourth additional layer FOL, the second semiconductor layer SCL2 may correspond to the fifth additional layer FIL, the fourth conductive layer CL4 may correspond to the sixth additional layer SIL, the fifth conductive layer CL5 may correspond to the seventh additional layer SEL, the sixth conductive layer CL6 may correspond to the eighth additional layer EIL, and the seventh conductive layer CL7 may correspond to the ninth additional layer NIL.

[0214] The signal line may be disposed in a display area where the first sub-pixel SPX1 to the fourth sub-pixel SPX4 and the first optical sensing pixel PSR1 are located (refer to Figure 1 For example, the first to thirteenth additional lines WL1 to WL13, the first to fourth data lines D1 to D4, and the first power line PL1 may be disposed in the display area DA.

[0215] The first additional line WL1 may extend in the first direction DR1 and may correspond to the third additional layer TL (or the second conductive layer CL2). In an embodiment, the first additional line WL1 may correspond to the reference Figure 6 The i-th emission control line Ei described. One area of ​​the first additional line WL1 may be a gate electrode of a fifth transistor T5 of each of the first pixel circuit PXC1 to the fourth pixel circuit PXC4 (hereinafter referred to as a "fifth gate electrode"). In addition, another area of ​​the first additional line WL1 may be a gate electrode of a sixth transistor T6 of each of the first pixel circuit PXC1 to the fourth pixel circuit PXC4 (hereinafter referred to as a "sixth gate electrode").

[0216] The second additional line WL2 may extend in the first direction DR1 and be spaced apart from the first additional line WL1. The second additional line WL2 may correspond to the third additional layer TL (or the second conductive layer CL2). In an embodiment, the second additional line WL2 may correspond to the reference Figure 6 The 1i-th scan line S1i described. One area of ​​the second additional line WL2 may be the gate electrode of the second transistor T2 of each of the first pixel circuit PXC1 to the fourth pixel circuit PXC4 (hereinafter referred to as the "second gate electrode"). In addition, another area of ​​the second additional line WL2 may be the gate electrode of the seventh transistor T7 of each of the first pixel circuit PXC1 to the fourth pixel circuit PXC4 (hereinafter referred to as the "seventh gate electrode"). In addition, another area of ​​the second additional line WL2 may correspond to the gate electrode of the 10a-th transistor T10a of the sensor circuit SC (hereinafter referred to as the "10a-th gate electrode") and the gate electrode of the 10b-th transistor T10b (hereinafter referred to as the "10b-th gate electrode").

[0217] The third additional wire WL3 may extend in the first direction DR1 and may correspond to the fourth additional layer FOL (or the third conductive layer CL3 ). The third additional wire WL3 may be a dummy wire overlapping the sixth additional wire WL6 formed of the sixth additional layer SIL.

[0218] The fourth additional line WL4 may extend in the first direction DR1 and be spaced apart from the third additional line WL3. The fourth additional line WL4 may correspond to the fourth additional layer FOL (or the third conductive layer CL3). The fourth additional line WL4 may be a dummy line overlapping the seventh additional line WL7 formed by the sixth additional layer SIL.

[0219] The fifth additional line WL5 may extend in the first direction DR1 and be spaced apart from the third additional line WL3 and the fourth additional line WL4. The fifth additional line WL5 may correspond to the fourth additional layer FOL (or the third conductive layer CL3). The fifth additional line WL5 may be a dummy line overlapping the eighth additional line WL8 formed by the sixth additional layer SIL.

[0220] The sixth additional wire WL6 may extend in the first direction DR1 and may correspond to the sixth additional layer SIL (or the fourth conductive layer CL4). In an embodiment, the sixth additional wire WL6 may be a reference wire. Figure 6 The reset line RSTL described above is provided with a reset signal RST. An area of ​​the sixth additional line WL6 may be a gate electrode of a ninth transistor T9 of the sensor circuit SC (hereinafter referred to as a "ninth gate electrode"). The sixth additional line WL6 may overlap with the third additional line WL3 and be electrically connected to the third additional line WL3. In this case, the reset signal RST may also be applied to the third additional line WL3.

[0221] The seventh additional line WL7 may extend in the first direction DR1 and be spaced apart from the sixth additional line WL6. The seventh additional line WL7 may correspond to the sixth additional layer SIL (or the fourth conductive layer CL4). In an embodiment, the seventh additional line WL7 may correspond to the reference line SIL. Figure 6 The 4i-th scan line S4i described above is provided with the fourth scan signal GC[i]. A region of the seventh additional line WL7 may be a gate electrode of the third transistor T3 of each of the first pixel circuit PXC1 to the fourth pixel circuit PXC4 (hereinafter referred to as the "third gate electrode"). The seventh additional line WL7 may overlap with the fourth additional line WL4 and be electrically connected to the fourth additional line WL4. In this case, the fourth scan signal GC[i] may also be applied to the fourth additional line WL4.

[0222] The eighth additional line WL8 may extend in the first direction DR1 and may be spaced apart from the sixth additional line WL6 and the seventh additional line WL7. The eighth additional line WL8 may correspond to the sixth additional layer SIL (or the fourth conductive layer CL4). In an embodiment, the eighth additional line WL8 may correspond to the reference Figure 6 The 2i-th scan line S2i described above may be provided with the second scan signal GI[i]. A region of the eighth additional line WL8 may be the gate electrode of the fourth transistor T4 of each of the first pixel circuit PXC1 to the fourth pixel circuit PXC4 (hereinafter referred to as the "fourth gate electrode"). The eighth additional line WL8 may overlap with the fifth additional line WL5 and be electrically connected to the fifth additional line WL5. In this case, the second scan signal GI[i] may also be applied to the fifth additional line WL5.

[0223] The ninth additional line WL9 may extend in the first direction DR1 and correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). In an embodiment, the ninth additional line WL9 may correspond to the reference Figure 6 The fourth power line PL4 is described. The ninth additional line WL9 may be supplied with the reset voltage VRST. The ninth additional line WL9 may be electrically connected to the twelfth additional line WL12 formed of the eighth additional layer EIL.

[0224] The tenth additional line WL10 may extend in the first direction DR1 and be spaced apart from the ninth additional line WL9. The tenth additional line WL10 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). In an embodiment, the tenth additional line WL10 may correspond to the reference Figure 6 The third power line PL3 described. The tenth additional line WL10 may be supplied with the second initialization power voltage Vint2. The tenth additional line WL10 may be electrically connected to the first semiconductor pattern SCP1 formed of the second additional layer SL of the seventh transistor T7. The tenth additional line WL10 may be electrically connected to the second semiconductor pattern SCP2 formed of the second additional layer SL of the eighth transistor T8.

[0225] The eleventh additional line WL11 may extend in the first direction DR1 and be spaced apart from the ninth additional line WL9 and the tenth additional line WL10. The eleventh additional line WL11 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). In an embodiment, the eleventh additional line WL11 may correspond to the reference Figure 6 The second power line PL2 is described. The eleventh additional line WL11 may be supplied with the first initialization power voltage Vint1. The eleventh additional line WL11 may be electrically connected to the third semiconductor pattern SCP3 formed of the fifth additional layer FIL of the fourth transistor T4.

[0226] The twelfth additional line WL12 may extend in the second direction DR2 and correspond to the eighth additional layer EIL (or the sixth conductive layer CL6). The twelfth additional line WL12 may be electrically connected to the ninth additional line WL9 by passing through the corresponding first through hole VIH1 of the seventh insulating layer INS7. In this case, the reset voltage VRST may be applied to the twelfth additional line WL12. In an embodiment, the ninth additional line WL9 may be a horizontal power line of the fourth power line PL4. The twelfth additional line WL12 may be a vertical power line of the fourth power line PL4. The fourth power line PL4 may have a mesh structure due to the ninth additional line WL9 and the twelfth additional line WL12 electrically connected to each other. In addition, the twelfth additional line WL12 may be electrically connected to the eighth conductive pattern CP8 by passing through another first through hole VIH1 of the seventh insulating layer INS7.

[0227] The eighth conductive pattern CP8 may be formed by the seventh additional layer SEL (or the fifth conductive layer CL5) and electrically connected to the twelfth additional wire WL12 through the corresponding first through hole VIH1. In addition, the eighth conductive pattern CP8 may be electrically connected to the fourth semiconductor pattern SCP4 formed by the fifth additional layer FIL of the ninth transistor T9 by passing through the corresponding second contact portion CNT2 of the sixth insulating layer INS6 and the fifth insulating layer INS5. In an embodiment, the twelfth additional wire WL12 formed by the eighth additional layer EIL may be electrically connected to the fourth semiconductor pattern SCP4 formed by the fifth additional layer FIL of the ninth transistor T9 through the eighth conductive pattern CP8 formed by the seventh additional layer SEL.

[0228] The thirteenth additional wire WL13 may extend in the second direction DR2 and correspond to the ninth additional layer NIL (or the seventh conductive layer CL7). In an embodiment, the thirteenth additional wire WL13 may correspond to the reference Figure 6 The kth readout line RXk (hereinafter referred to as “readout line”) is described. In an embodiment, the thirteenth additional line WL13 may be electrically connected to the third connection pattern CNP3 by passing through a corresponding second via VIH2 of the eighth insulating layer INS8.

[0229] The third connection pattern CNP3 may correspond to the eighth additional layer EIL (or the sixth conductive layer CL6). The first end of the third connection pattern CNP3 may be electrically connected to the thirteenth additional wire WL13 formed in a different layer (or formed by the ninth additional layer NIL) through the corresponding second through hole VIH2. The second end of the third connection pattern CNP3 may be electrically connected to the seventh conductive pattern CP7 through the corresponding first through hole VIH1 passing through the seventh insulating layer INS7.

[0230] The seventh conductive pattern CP7 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The first end of the seventh conductive pattern CP7 may be electrically connected to the third connection pattern CNP3 formed in a different layer (or formed by the eighth additional layer EIL) through the corresponding first through hole VIH1. The second end of the seventh conductive pattern CP7 may be electrically connected to the second semiconductor pattern SCP2 formed by the second additional layer SL of the tenth transistor T10 by passing through the corresponding first contact portion CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0231] In an embodiment, the thirteenth additional wire WL13 formed of the ninth additional layer NIL may be electrically connected to the second semiconductor pattern SCP2 formed of the second additional layer SL of the tenth transistor T10 through both the third connection pattern CNP3 formed of the eighth additional layer EIL and the seventh conductive pattern CP7 formed of the seventh additional layer SEL.

[0232] The first data line D1 may extend in the second direction DR2 and correspond to the eighth additional layer EIL (or the sixth conductive layer CL6). The first data line D1 may be a reference Figure 6 The j-th data line Dj is described. The first data line D1 may be electrically connected to the first semiconductor pattern SCP1 of the second transistor T2 of the first pixel circuit PXC1.

[0233] The second data line D2 may extend in the second direction DR2 and be spaced apart from the first data line D1 and the twelfth additional line WL12. The second data line D2 may correspond to the eighth additional layer EIL (or the sixth conductive layer CL6). The second data line D2 may be a reference line. Figure 6 The second data line D2 may be electrically connected to the first semiconductor pattern SCP1 of the second transistor T2 of the second pixel circuit PXC2.

[0234] The third data line D3 may extend in the second direction DR2 and be spaced apart from the twelfth additional line WL12 and the first and second data lines D1 and D2. The third data line D3 may correspond to the eighth additional layer EIL (or the sixth conductive layer CL6). The third data line D3 may be a reference line. Figure 6 The third data line D3 may be electrically connected to the first semiconductor pattern SCP1 of the second transistor T2 of the third pixel circuit PXC3.

[0235] The fourth data line D4 may extend in the second direction DR2 and be spaced apart from the twelfth additional line WL12 and the first, second, and third data lines D1, D2, and D3. The fourth data line D4 may correspond to the eighth additional layer EIL (or the sixth conductive layer CL6). The fourth data line D4 may be a reference Figure 6 The j-th data line Dj is described. The fourth data line D4 may be electrically connected to the first semiconductor pattern SCP1 of the second transistor T2 of the fourth pixel circuit PXC4.

[0236] The first power line PL1 may extend in the second direction DR2 and be spaced apart from the twelfth additional line WL12 and the first to fourth data lines D1 to D4. The first power line PL1 may correspond to the eighth additional layer EIL (or the sixth conductive layer CL6). The first power line PL1 may be a reference line. Figure 6The first power line PL1 is described. The first power line PL1 may be supplied with a first power voltage VDD. The first sub-pixel SPX1 and the second sub-pixel SPX2 may share one first power line PL1. The third sub-pixel SPX3 and the fourth sub-pixel SPX4 may share one first power line PL1. However, the present disclosure is not necessarily limited to the above examples.

[0237] In each of the first to fourth sub-pixels SPX1 to SPX4 , the first power line PL1 may be electrically connected to the first conductive pattern CP1 formed of the seventh additional layer SEL by passing through a corresponding first through hole VIH1 of the seventh insulating layer INS7 .

[0238] The first conductive pattern CP1 may be formed by the seventh additional layer SEL and electrically connected to the first power line PL1 through the corresponding first through hole VIH1. In addition, the first conductive pattern CP1 may be electrically connected to the first semiconductor pattern SCP1 of the fifth transistor T5 of each pixel circuit PXC by passing through the corresponding first contact portion CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. In an embodiment, the first power line PL1 formed by the eighth additional layer EIL may be electrically connected to the first semiconductor pattern SCP1 formed by the second additional layer SL of the fifth transistor T5 through the first conductive pattern CP1 formed by the seventh additional layer SEL.

[0239] The first to second to third data lines D1 , D2 , D3 , D4 , and the first power line PL1 may be formed by the same process, include the same material, and be disposed in the same layer as the twelfth additional line WL12 .

[0240] The first pixel circuit PXC1, the second pixel circuit PXC2, the third pixel circuit PXC3 and the fourth pixel circuit PXC4 may have substantially similar or identical structures. For example, the first pixel circuit PXC1 and the second pixel circuit PXC2 located on the left side of the sensor circuit SC and the third pixel circuit PXC3 and the fourth pixel circuit PXC4 located on the right side of the sensor circuit SC may be symmetrical to each other. For example, the first pixel circuit PXC1 and the third pixel circuit PXC3 may be symmetrical to each other. The second pixel circuit PXC2 and the fourth pixel circuit PXC4 may be symmetrical to each other. In an embodiment, the first pixel circuit PXC1 and the second pixel circuit PXC2 may form a mirror symmetry with respect to a specific line RL extending in the second direction DR2. The third pixel circuit PXC3 and the fourth pixel circuit PXC4 may form a mirror symmetry with respect to a specific line RL extending in the second direction DR2. However, the present disclosure is not necessarily limited to the above examples.

[0241] Hereinafter, for purposes of explanation, the following description will focus on the first pixel circuit PXC1, and to the extent an element is not described in detail with respect to this figure, it will be understood that the element is at least similar to corresponding elements already described elsewhere within the present disclosure.

[0242] The first pixel circuit PXC1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a storage capacitor Cst.

[0243] The first transistor T1 may include a first active pattern ACT1 and a first gate electrode GE1.

[0244] The first active pattern ACT1 may be a region of the first semiconductor pattern SCP1 overlapping the first gate electrode GE1. The first semiconductor pattern SCP1 may correspond to the second additional layer SL (or the first semiconductor layer SCL1). The first active pattern ACT1 may be a channel region of the first transistor T1.

[0245] For example, the channel region may be an undoped semiconductor pattern without impurities and may be an intrinsic semiconductor. Other regions of the semiconductor pattern except the channel region may be a semiconductor pattern doped with impurities.

[0246] One region of the first semiconductor pattern SCP1 connected to a first side of the first active pattern ACT1 (or the channel region) (e.g., a left side of the first active pattern ACT1 in a plan view) without overlapping the first gate electrode GE1 may be a first contact region. One region of the first semiconductor pattern SCP1 connected to a second side of the first active pattern ACT1 (e.g., a right side of the first active pattern ACT1 in a plan view) without overlapping the first gate electrode GE1 may be a second contact region. The first contact region and the second contact region may extend from the first active pattern ACT1 (or the channel region) in opposite directions. The first contact region and the second contact region may face each other in the first direction DR1 with the first active pattern ACT1 interposed therebetween.

[0247] The first contact region may be connected to a first side of the first active pattern ACT1 and to the first semiconductor pattern SCP1 of the second transistor T2 and the first semiconductor pattern SCP1 of the fifth transistor T5. The second contact region may be connected to a second side of the first active pattern ACT1 and to the first semiconductor pattern SCP1 of the sixth transistor T6.

[0248] The first gate electrode GE1 may overlap the first active pattern ACT1 and correspond to the third additional layer TL (or the second conductive layer CL2). The first gate electrode GE1 may be an island-shaped conductive pattern. The first gate electrode GE1 may be electrically connected to the third transistor T3 and the fourth transistor T4 through the third conductive pattern CP3.

[0249] The third conductive pattern CP3 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The first end of the third conductive pattern CP3 may be electrically connected to the first gate electrode GE1 by sequentially passing through the corresponding first contact portion CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. The second end of the third conductive pattern CP3 may be electrically connected to a region of the third semiconductor pattern SCP3 shared by the third transistor T3 and the fourth transistor T4 by sequentially passing through the corresponding second contact portion CNT2 of the sixth insulating layer INS6 and the fifth insulating layer INS5.

[0250] In an implementation, the first gate electrode GE1 may overlap the bottom metal pattern BML.

[0251] The bottom metal pattern BML may correspond to the first additional layer FL (or the first conductive layer CL1). In a plan view, the bottom metal pattern BML may overlap with the first transistor T1 (or the lower electrode LE, the upper electrode UE). The bottom metal pattern BML may shield the first transistor T1 (or the lower electrode LE, the upper electrode UE) from below. A constant voltage (e.g., a first power voltage VDD) may be applied to the bottom metal pattern BML, but the present disclosure is not necessarily limited thereto. The bottom metal pattern BML may extend in a first direction DR1 and a second direction DR2 based on the first transistor T1. The bottom metal pattern BML may have a mesh structure throughout the entire display area DA.

[0252] The second transistor T2 may include a second active pattern ACT2 and a second gate electrode.

[0253] The second active pattern ACT2 may be a region of the first semiconductor pattern SCP1 overlapping the second additional line WL2. The first semiconductor pattern SCP1 may correspond to the second additional layer SL (or the first semiconductor layer SCL1). The second active pattern ACT2 may be a channel region of the second transistor T2.

[0254] A region of the first semiconductor pattern SCP1 connected to a first side of the second active pattern ACT2 (e.g., a lower side of the second active pattern ACT2 in a plan view) without overlapping the second additional line WL2 may be a first contact region. A region of the first semiconductor pattern SCP1 connected to a second side of the second active pattern ACT2 (e.g., an upper side of the second active pattern ACT2 in a plan view) without overlapping the second additional line WL2 may be a second contact region.

[0255] The first contact region may be connected to a first side of the second active pattern ACT2 and electrically connected to the fifth conductive pattern CP5. The second contact region may be connected to a second side of the second active pattern ACT2 and connected to a first contact region of the first transistor T1.

[0256] The fifth conductive pattern CP5 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The fifth conductive pattern CP5 may be electrically connected to the first semiconductor pattern SCP1 corresponding to the first contact region of the second transistor T2 by passing through the corresponding first contact portions CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0257] The second gate electrode may be a region of the second additional line WL2 overlapping the second active pattern ACT2 .

[0258] The third transistor T3 may include a third active pattern ACT3 and a third gate electrode.

[0259] The third active pattern ACT3 may be a region of the third semiconductor pattern SCP3 overlapping the seventh additional line WL7 and forming a channel region of the third transistor T3. The third semiconductor pattern SCP3 may correspond to the fifth additional layer FIL (or the second semiconductor layer SCL2).

[0260] A region of the third semiconductor pattern SCP3 connected to a first side of the third active pattern ACT3 (e.g., an upper side of the third active pattern ACT3 in a plan view) without overlapping the seventh additional line WL7 may be a first contact region. A region of the third semiconductor pattern SCP3 connected to a second side of the third active pattern ACT3 (e.g., a lower side of the third active pattern ACT3 in a plan view) without overlapping the seventh additional line WL7 may be a second contact region.

[0261] The first contact region may be connected to a first side of the third active pattern ACT3 and electrically connected to the first transistor T1 and the sixth transistor T6 through the fourth conductive pattern CP4. The second contact region may be connected to a second side of the third active pattern ACT3 and connected to the third semiconductor pattern SCP3 of the fourth transistor T4.

[0262] The fourth conductive pattern CP4 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The first end of the fourth conductive pattern CP4 may be electrically connected to the first contact region of the third transistor T3 by passing through the corresponding second contact portion CNT2 of the sixth insulating layer INS6 and the fifth insulating layer INS5. The second end of the fourth conductive pattern CP4 may be electrically connected to a region of the first semiconductor pattern SCP1 shared by the first transistor T1 and the sixth transistor T6 by passing through the corresponding first contact portion CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0263] The third gate electrode may be a region of the seventh additional line WL7 overlapping the third active pattern ACT3 .

[0264] The fourth transistor T4 may include a fourth active pattern ACT4 and a fourth gate electrode.

[0265] The fourth active pattern ACT4 may be a region of the third semiconductor pattern SCP3 overlapping the eighth additional line WL8 and forming a channel region of the fourth transistor T4. The third semiconductor pattern SCP3 may correspond to the fifth additional layer FIL (or the second semiconductor layer SCL2).

[0266] A region of the third semiconductor pattern SCP3 connected to a first side of the fourth active pattern ACT4 (e.g., an upper side of the fourth active pattern ACT4 in a plan view) without overlapping the eighth additional line WL8 may be a first contact region. A region of the third semiconductor pattern SCP3 connected to a second side of the fourth active pattern ACT4 (e.g., a lower side of the fourth active pattern ACT4 in a plan view) without overlapping the eighth additional line WL8 may be a second contact region.

[0267] The first contact region may be connected to a first side of the fourth active pattern ACT4 and to the third semiconductor pattern SCP3 of the third transistor T3. The second contact region may be connected to a second side of the fourth active pattern ACT4 and electrically connected to an eleventh additional line WL11 formed of the seventh additional layer SEL through a corresponding second contact portion CNT2 passing through the sixth insulating layer INS6 and the fifth insulating layer INS5.

[0268] The fourth gate electrode may be a region of the eighth additional line WL8 overlapping the fourth active pattern ACT4 .

[0269] The fifth transistor T5 may include a fifth active pattern ACT5 and a fifth gate electrode.

[0270] The fifth active pattern ACT5 may be one region of the first semiconductor pattern SCP1 overlapping the first additional line WL1 and forming a channel region of the fifth transistor T5. The first semiconductor pattern SCP1 may correspond to the second additional layer SL (or the first semiconductor layer SCL1).

[0271] One region of the first semiconductor pattern SCP1 connected to a first side of the fifth active pattern ACT5 (e.g., an upper side of the fifth active pattern ACT5 in a plan view) without overlapping the first additional line WL1 may be a first contact region. One region of the first semiconductor pattern SCP1 connected to a second side of the fifth active pattern ACT5 (e.g., a lower side of the fifth active pattern ACT5 in a plan view) without overlapping the first additional line WL1 may be a second contact region.

[0272] The first contact region may be connected to a first side of the fifth active pattern ACT5 and electrically connected to the first conductive pattern CP1 through the corresponding first contact portion CNT1. The second contact region may be connected to a second side of the fifth active pattern ACT5 and connected to the first semiconductor pattern SCP1 of each of the first and second transistors T1 and T2.

[0273] The first conductive pattern CP1 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The first end of the first conductive pattern CP1 may be electrically connected to the first contact region of the fifth transistor T5 through the corresponding first contact portion CNT1. The second end of the first conductive pattern CP1 may be electrically connected to the upper electrode UE through the corresponding first contact portion CNT1 passing through the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4.

[0274] The fifth gate electrode may be a region of the first additional line WL1 overlapping the fifth active pattern ACT5 .

[0275] The sixth transistor T6 may include a sixth active pattern ACT6 and a sixth gate electrode.

[0276] The sixth active pattern ACT6 may be one region of the first semiconductor pattern SCP1 overlapping the first additional line WL1 and forming a channel region of the sixth transistor T6. The first semiconductor pattern SCP1 may correspond to the second additional layer SL (or the first semiconductor layer SCL1).

[0277] A region of the first semiconductor pattern SCP1 connected to a first side of the sixth active pattern ACT6 (e.g., an upper side of the sixth active pattern ACT6 in a plan view) without overlapping the first additional line WL1 may be a first contact region. A region of the first semiconductor pattern SCP1 connected to a second side of the sixth active pattern ACT6 (e.g., a lower side of the sixth active pattern ACT6 in a plan view) without overlapping the first additional line WL1 may be a second contact region.

[0278] The first contact region may be connected to the first side of the sixth active pattern ACT6 and each of the first semiconductor patterns SCP1 of the seventh transistor T7. The second contact region may be connected to the second side of the sixth active pattern ACT6 and each of the first semiconductor patterns SCP1 of the first transistor T1. In addition, the second contact region may be electrically connected to the second conductive pattern CP2 through the corresponding first contact portion CNT1.

[0279] The second conductive pattern CP2 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The second conductive pattern CP2 may be electrically connected to the second contact region of the sixth transistor T6 by passing through the corresponding first contact portion CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. In addition, the second conductive pattern CP2 may be electrically connected to the first connection pattern CNP1 formed by the eighth additional layer EIL (or the sixth conductive layer CL6) through the corresponding first through hole VIH1.

[0280] The first end of the first connection pattern CNP1 may be electrically connected to the second conductive pattern CP2 by passing through the corresponding first through hole VIH1 of the seventh insulating layer INS7. The second end of the first connection pattern CNP1 may be electrically connected to the anode electrode by passing through the corresponding second through hole VIH2 of the eighth insulating layer INS8. The anode electrode may be a reference electrode. Figure 7 Described anode electrode AE.

[0281] The sixth gate electrode may be a region of the first additional line WL1 overlapping the sixth active pattern ACT6 .

[0282] The seventh transistor T7 may include a seventh active pattern ACT7 and a seventh gate electrode.

[0283] The seventh active pattern ACT7 may be a region of the first semiconductor pattern SCP1 overlapping the second additional line WL2. The first semiconductor pattern SCP1 may correspond to the second additional layer SL (or the first semiconductor layer SCL1). The seventh active pattern ACT7 may be a channel region of the seventh transistor T7.

[0284] A region of the first semiconductor pattern SCP1 connected to a first side of the seventh active pattern ACT7 (e.g., a lower side of the seventh active pattern ACT7 in a plan view) without overlapping the second additional line WL2 may be a first contact region. A region of the first semiconductor pattern SCP1 connected to a second side of the seventh active pattern ACT7 (e.g., an upper side of the seventh active pattern ACT7 in a plan view) without overlapping the second additional line WL2 may be a second contact region.

[0285] The first contact region may be connected to a first side of the seventh active pattern ACT7 and to the first semiconductor pattern SCP1 of the sixth transistor T6. The second contact region may be connected to a second side of the seventh active pattern ACT7 and electrically connected to the tenth additional line WL10 by passing through corresponding first contacts CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0286] The seventh gate electrode may be a region of the second additional line WL2 overlapping the seventh active pattern ACT7 .

[0287] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0288] The lower electrode LE may be integrally formed with the first gate electrode GE1. The lower electrode LE may correspond to the third additional layer TL (or the second conductive layer CL2).

[0289] The upper electrode UE may overlap the lower electrode LE and correspond to the fourth additional layer FOL (or the third conductive layer CL3). The upper electrode UE may include an opening OPN formed by removing a portion thereof. The lower electrode LE (or the first gate electrode GE1) may be exposed through the opening OPN. The upper electrode UE may be electrically connected to the first conductive pattern CP1. In an embodiment, the upper electrode UE formed by the fourth additional layer FOL, the first power line PL1 formed by the eighth additional layer EIL, and the first semiconductor pattern SCP1 formed by the second additional layer SL of the fifth transistor T5 may be electrically connected through the first conductive pattern CP1.

[0290] The sensor circuit SC may be located between the second pixel circuit PXC2 and the third pixel circuit PXC3. However, the present disclosure is not necessarily limited to the above example, and the location of the sensor circuit SC may be changed in various ways.

[0291] The sensor circuit SC may include an eighth transistor T8 , a ninth transistor T9 , and a tenth transistor T10 .

[0292] The eighth transistor T8 may include an eighth active pattern ACT8 and an eighth gate electrode GE8.

[0293] The eighth active pattern ACT8 may be a region of the second semiconductor pattern SCP2 overlapping the eighth gate electrode GE8. The second semiconductor pattern SCP2 may correspond to the second additional layer SL (or the first semiconductor layer SCL1). The second semiconductor pattern SCP2 may be spaced apart from the first semiconductor pattern SCP1. The eighth active pattern ACT8 may be a channel region of the eighth transistor T8.

[0294] A region of the second semiconductor pattern SCP2 connected to a first side of the eighth active pattern ACT8 (or the channel region) (e.g., a left side of the eighth active pattern ACT8 in a plan view) without overlapping the eighth gate electrode GE8 may be a first contact region. A region of the second semiconductor pattern SCP2 connected to a second side of the eighth active pattern ACT8 (e.g., a right side of the eighth active pattern ACT8 in a plan view) without overlapping the eighth gate electrode GE8 may be a second contact region.

[0295] The first contact region may be connected to each of the first side of the eighth active pattern ACT8 and the second semiconductor pattern SCP2 of the 10a-th transistor T10a. The second contact region may be connected to the second side of the eighth active pattern ACT8 and electrically connected to the tenth additional wire WL10 through the corresponding first contact portions CNT1 passing through the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0296] The eighth gate electrode GE8 may overlap the eighth active pattern ACT8 and correspond to the third additional layer TL (or the second conductive layer CL2 ). The eighth gate electrode GE8 may be an island-shaped conductive pattern. The eighth gate electrode GE8 may be electrically connected to the ninth transistor T9 through the sixth conductive pattern CP6 .

[0297] The sixth conductive pattern CP6 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The first end of the sixth conductive pattern CP6 may be electrically connected to the eighth gate electrode GE8 by sequentially passing through the corresponding first contact portion CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. The second end of the sixth conductive pattern CP6 may be electrically connected to a region of the fourth semiconductor pattern SCP4 of the ninth transistor T9 by passing through the corresponding second contact portion CNT2 of the sixth insulating layer INS6 and the fifth insulating layer INS5. In addition, the sixth conductive pattern CP6 may be electrically connected to the second connection pattern CNP2 formed by the eighth additional layer EIL (or the sixth conductive layer CL6).

[0298] The second connection patterns CNP2 may be electrically connected to the sixth conductive patterns CP6 through corresponding first vias VIH1 passing through the seventh insulating layer INS7. In addition, the second connection patterns CNP2 may be electrically connected to the bridge patterns BRP formed of the ninth additional layer NIL (or the seventh conductive layer CL7).

[0299] The bridge pattern BRP may be electrically connected to the second connection pattern CNP2 via a corresponding second through hole VIH2 passing through the eighth insulating layer INS8. In addition, the bridge pattern BRP may be electrically connected to the light receiving element of the sensor circuit SC (refer to Figure 6 The first electrode may be a reference electrode. Figure 7 The bridge pattern BRP may be formed by the same process as the thirteenth additional line WL13 , include the same material as the thirteenth additional line WL13 , and may be disposed in the same layer.

[0300] The ninth transistor T9 may include a ninth active pattern ACT9 and a ninth gate electrode.

[0301] The ninth active pattern ACT9 may be a region of the fourth semiconductor pattern SCP4 overlapping the sixth additional line WL6. The fourth semiconductor pattern SCP4 may correspond to the fifth additional layer FIL (or the second semiconductor layer SCL2). The fourth semiconductor pattern SCP4 may be spaced apart from the third semiconductor pattern SCP3. The ninth active pattern ACT9 may be a channel region of the ninth transistor T9.

[0302] A region of the fourth semiconductor pattern SCP4 connected to a first side of the ninth active pattern ACT9 (e.g., a lower side of the ninth active pattern ACT9 in a plan view) without overlapping the sixth additional line WL6 may be a first contact region. A region of the fourth semiconductor pattern SCP4 connected to a second side of the ninth active pattern ACT9 (e.g., an upper side of the ninth active pattern ACT9 in a plan view) without overlapping the sixth additional line WL6 may be a second contact region.

[0303] The first contact region may be connected to a first side of the ninth active pattern ACT9 and electrically connected to the eighth gate electrode GE8 of the eighth transistor T8 through the sixth conductive pattern CP6. The second contact region may be connected to a second side of the ninth active pattern ACT9 and electrically connected to the eighth conductive pattern CP8 through the corresponding second contact portion CNT2.

[0304] The ninth gate electrode may be a region of the sixth additional line WL6 overlapping the ninth active pattern ACT9 .

[0305] The tenth transistor T10 may have a double gate structure in which sub-transistors are connected in series to prevent current leakage. For example, the tenth transistor T10 may include a 10a-th transistor T10a and a 10b-th transistor T10b.

[0306] The 10a-th transistor T10a may include a 10a-th active pattern ACT10a and a 10a-th gate electrode.

[0307] The 10ath active pattern ACT10a may be a region of the second semiconductor pattern SCP2 overlapping the second additional line WL2. The second semiconductor pattern SCP2 may correspond to the second additional layer SL (or the first semiconductor layer SCL1). The 10ath active pattern ACT10a may be a channel region of the 10ath transistor T10a.

[0308] A region of the second semiconductor pattern SCP2 connected to a first side of the 10a-th active pattern ACT10a (e.g., an upper side of the 10a-th active pattern ACT10a in a plan view) without overlapping the second additional line WL2 may be a first contact region. A region of the second semiconductor pattern SCP2 connected to a second side of the 10a-th active pattern ACT10a (e.g., a lower side of the 10a-th active pattern ACT10a in a plan view) without overlapping the second additional line WL2 may be a second contact region.

[0309] The first contact region may be connected to each of the first side of the 10ath active pattern ACT10a and the second semiconductor pattern SCP2 of the eighth transistor T8. The second contact region may be connected to each of the second side of the 10ath active pattern ACT10a and the second semiconductor pattern SCP2 of the 10bth transistor T10b.

[0310] The 10a-th gate electrode may be a region of the second additional line WL2 overlapping the 10a-th active pattern ACT10a.

[0311] The 10b-th transistor T10b may include a 10b-th active pattern ACT10b and a 10b-th gate electrode.

[0312] The 10bth active pattern ACT10b may be a region of the second semiconductor pattern SCP2 overlapping a protrusion protruding from the second additional line WL2 extending in the first direction DR1 in a direction opposite to the second direction DR2. The 10bth active pattern ACT10b may be a channel region of the 10bth transistor T10b.

[0313] A region of the second semiconductor pattern SCP2 connected to a first side of the 10b-th active pattern ACT10b (e.g., a left side of the 10b-th active pattern ACT10b in a plan view) without overlapping with the protrusion of the second additional line WL2 may be a first contact region. A region of the second semiconductor pattern SCP2 connected to a second side of the 10b-th active pattern ACT10b (e.g., a right side of the 10b-th active pattern ACT10b in a plan view) without overlapping with the protrusion of the second additional line WL2 may be a second contact region.

[0314] The first contact region may be connected to each of the first side of the 10bth active pattern ACT10b and the second semiconductor pattern SCP2 of the 10ath transistor T10a. The second contact region may be connected to the second side of the 10bth active pattern ACT10b and electrically connected to the seventh conductive pattern CP7.

[0315] The seventh conductive pattern CP7 may correspond to the seventh additional layer SEL (or the fifth conductive layer CL5). The seventh conductive pattern CP7 may be electrically connected to the second semiconductor pattern SCP2 of the 10b-th transistor T10b by passing through the corresponding first contact portions CNT1 of the sixth insulating layer INS6, the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. The seventh conductive pattern CP7 may be electrically connected to the third connection pattern CNP3 located in the eighth additional layer EIL.

[0316] In the above-mentioned embodiment, the twelfth additional line WL12, the second data line D2, and the third data line D3 formed by the eighth additional layer EIL may be spaced apart from each other on the seventh insulating layer INS7. The twelfth additional line WL12 to which the reset voltage VRST having a constant voltage level is applied may be disposed between the second data line D2 and the third data line D3. The thirteenth additional line WL13 (or the kth readout line RXk) formed by the ninth additional layer NIL on the eighth insulating layer INS8 and disposed in a layer different from the twelfth additional line WL12 and the second data line D2 and the third data line D3 may overlap with the twelfth additional line WL12 in a plan view and a cross-sectional view, but not overlap with the second data line D2 and the third data line D3. In addition, in a plan view, the thirteenth additional line WL13 may not overlap with the first power line PL1.

[0317] According to the above-mentioned embodiment, the thirteenth additional line WL13 corresponding to the k-th readout line RXk and the second data line D2 and the third data line D3 are formed by layers different from each other (or are located on layers different from each other), so that the spacing distance between the thirteenth additional line WL13 and the second data line D2 and the spacing distance between the thirteenth additional line WL13 and the third data line D3 can be ensured. In addition, in the case where the twelfth additional line WL12 formed by the eighth additional layer EIL and located between the second data line D2 and the third data line D3 is arranged below the thirteenth additional line WL13 formed by the ninth additional layer NIL, the twelfth additional line WL12 can be used as a shielding component to reduce or prevent the coupling capacitance from occurring between the second data line D2 and the third data line D3 and the thirteenth additional line WL13. For example, in the case where the twelfth additional line WL12 is used as a shielding component to ensure the spacing distance between the second data line D2 and the third data line D3 and the thirteenth additional line WL13, the following phenomenon can be reduced or prevented: the data signal transmitted to each of the second data line D2 and the third data line D3 (or the sensing signal transmitted to the thirteenth additional line WL13) is affected by the sensing signal transmitted to the thirteenth additional line WL13 (or the data signal transmitted to each of the second data line D2 and the third data line D3). For example, the phenomenon of coupling the thirteenth additional line WL13 (or the kth readout line RXk) with the adjacent data line (for example, each of the second data line D2 and the third data line D3) can be reduced or prevented. Therefore, the noise occurring in the sensing signal applied to the thirteenth additional line WL13 due to the data signal applied to each of the second data line D2 and the third data line D3 can be reduced. In addition, noise occurring in the data signal applied to each of the second data line D2 and the third data line D3 due to the sensing signal applied to the thirteenth additional line WL13 (or the kth readout line RXk) can be reduced. Therefore, the fingerprint sensitivity and fingerprint sensing accuracy in the first optical sensing pixel PSR1 can be increased, thereby further enhancing the reliability of the display device 1.

[0318] In the above-described embodiment, although the case where the twelfth additional line WL12 formed by the eighth additional layer EIL and the thirteenth additional line WL13 formed by the ninth additional layer NIL overlap each other has been illustrated, the present disclosure is not necessarily limited thereto. Fig.18 As shown in , the thirteenth additional line WL13 is positioned closer to the bridge pattern BRP on the eighth insulating layer INS8, and the thirteenth additional line WL13 may not overlap with the twelfth additional line WL12. In this case, the spacing distance between the thirteenth additional line WL13 and the third data line D3 is increased, so that the coupling capacitance occurring between the thirteenth additional line WL13 and the third data line D3 can be more reliably reduced or prevented.

[0319] Furthermore, in an embodiment, if Fig.19 As shown in , the spacing distance between the thirteenth additional line WL13 and the third data line D3 is further increased by reducing the width of the thirteenth additional line WL13 by design. In addition, if the width of the twelfth additional line WL12 overlapping the thirteenth additional line WL13 is increased, the shielding effect of the twelfth additional line WL12 used as a shielding component can be further maximized. Therefore, the coupling capacitance occurring between the thirteenth additional line WL13 and the third data line D3 can be more reliably reduced or prevented.

[0320] Fig. 20 is a schematic plan view showing sub-pixels SPX1 to SPX4 and a first optical sensing pixel PSR1 according to an embodiment. Fig.21 It is shown that the Fig. 20 Schematic plan view of the components in the first additional layer FL. Fig. 22 It is shown that the Fig. 20 Schematic plan view of the components in the second additional layer SL and the third additional layer TL in FIG. Fig.23 It is shown that the Fig. 20 Schematic plan view of the components in the fourth additional layer FOL. Fig.24 It is shown that the Fig. 20 Schematic plan view of components in the fifth additional layer FIL and the sixth additional layer SIL. Fig.25 It is shown that the Fig. 20 Schematic plan view of the components in the seventh additional layer SEL. Fig.26 It is shown that the Fig. 20 Schematic plan view of the components in the eighth additional layer EIL. Fig. 27 It is shown that the Fig. 20 Schematic plan view of the components in the ninth additional layer NIL. Fig.28 It is shown that the Fig. 20 Schematic plan view of components in the second additional layer SL and the ninth additional layer NIL. Fig.29 It is along Fig. 20 A schematic cross-sectional view taken along line II-II'.

[0321] Fig. 20 The implementation method involves Fig. 9 Modifications of the embodiment regarding the position of the sensor circuit SC, etc.

[0322] Figures 20 to 29 The description of the embodiment will focus on the differences from the above-described embodiments, and to the extent an element is not described in detail with respect to this figure, it will be understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0323] refer to Figure 1 as well as Figures 20 to 29 , the first pixel circuit PXC1 of the first subpixel SPX1, the sensor circuit SC of the first optical sensing pixel PSR1, the second pixel circuit PXC2 of the second subpixel SPX2, the third pixel circuit PXC3 of the third subpixel SPX3, and the fourth pixel circuit PXC4 of the fourth subpixel SPX4 may be sequentially arranged in the first direction DR1. In an embodiment, the sensor circuit SC may be located between the first pixel circuit PXC1 and the second pixel circuit PXC2.

[0324] Each of the first to fourth pixel circuits PXC1 to PXC4 may include first to seventh transistors T1 to T7 and a storage capacitor Cst. The sensor circuit SC may include eighth to tenth transistors T8 to T10.

[0325] The signal line can be set in the display area (refer to Figure 1 The signal line may include the first to fourth pixel circuits PXC1 to PXC4 and the sensor circuit SC in a region of the DA in FIG.

[0326] The first to fourth pixel circuits PXC1 to PXC4 and the sensor circuit SC may be disposed in a pixel circuit layer PCL on a substrate SUB.

[0327] The pixel circuit layer PCL may include a first additional layer FL (or a first conductive layer CL1), a second additional layer SL (or a first semiconductor layer SCL1), a third additional layer TL (or a second conductive layer CL2), a fourth additional layer FOL (or a third conductive layer CL3), a fifth additional layer FIL (or a second semiconductor layer SCL2), a sixth additional layer SIL (or a fourth conductive layer CL4), a seventh additional layer SEL (or a fifth conductive layer CL5), an eighth additional layer EIL (or a sixth conductive layer CL6) and a ninth additional layer NIL (or a seventh conductive layer CL7), which are positioned sequentially in a third direction DR3 based on a surface of a substrate SUB.

[0328] The first additional layer FL may include a bottom metal pattern BML. The second additional layer SL may include a first semiconductor pattern SCP1 and a second semiconductor pattern SCP2 spaced apart from each other. The third additional layer TL may include a first additional line WL1, a second additional line WL2, a first gate electrode GE1 (or a lower electrode LE), and an eighth gate electrode GE8. The fourth additional layer FOL may include an upper electrode UE, a third additional line WL3, a fourth additional line WL4, and a fifth additional line WL5 spaced apart from each other. The fifth additional layer FIL may include a third semiconductor pattern SCP3 and a fourth semiconductor pattern SCP4 spaced apart from each other. The sixth additional layer SIL may include a sixth additional line WL6, a seventh additional line WL7, and an eighth additional line WL8 spaced apart from each other. The seventh additional layer SEL may include a ninth additional line WL9, a tenth additional line WL10, an eleventh additional line WL11, and first to eighth conductive patterns CP1 to CP8. The eighth additional layer EIL may include first to fourth data lines D1 to D4, a first power line PL1, and first to fourth connection patterns CNP1 to CNP4 spaced apart from each other. The ninth additional layer NIL may include a twelfth additional line WL12, a thirteenth additional line WL13, and a bridge pattern BRP that are spaced apart from each other.

[0329] In an embodiment, the twelfth additional line WL12 may include a twelfth horizontal line WL12 a and a twelfth vertical line WL12 b .

[0330] The twelfth horizontal line WL12a may extend in the first direction DR1. The twelfth vertical line WL12b may extend in the second direction DR2. The twelfth horizontal line WL12a and the twelfth vertical line WL12b may be formed by the ninth additional layer NIL and may be integrally formed with each other. Since the twelfth horizontal line WL12a and the twelfth vertical line WL12b are integrally formed with each other, the twelfth additional line WL12 may have a mesh structure.

[0331] The twelfth horizontal line WL12a may be electrically connected to the fourth connection pattern CNP4 formed by the eighth additional layer EIL through the corresponding second through hole VIH2. The fourth connection pattern CNP4 may be electrically connected to the twelfth horizontal line WL12a through the second through hole VIH2. In addition, the fourth connection pattern CNP4 may be electrically connected to the ninth additional line WL9 formed by the seventh additional layer SEL through the corresponding first through hole VIH1. In addition, the fourth connection pattern CNP4 may be electrically connected to the eighth conductive pattern CP8 through the corresponding first through hole VIH1. The eighth conductive pattern CP8 may be electrically connected to the fourth semiconductor pattern SCP4 of the ninth transistor T9 of the sensor circuit SC through the corresponding second contact portion CNT2. In an embodiment, the fourth connection pattern CNP4 may electrically connect the ninth additional line WL9, the twelfth additional line WL12, the eighth conductive pattern CP8, and the fourth semiconductor pattern SCP4 of the ninth transistor T9.

[0332] A reset voltage (reference voltage) may be supplied to the ninth additional line WL9 and the twelfth additional line WL12 electrically connected to each other. Figure 6 As described above, when the twelfth additional line WL12 has a mesh structure, the reset voltage can be reliably supplied to the entire area of ​​the display area DA, thereby further enhancing the display device (refer to Figure 1 The reliability of the “1” in .

[0333] The twelfth vertical line WL12b may be disposed between two pixel circuits PXC (or sub-pixels) adjacent to each other. For example, the twelfth vertical line WL12b may be disposed between the second pixel circuit PXC2 (or the second sub-pixel SPX2) and the third pixel circuit PXC3 (or the third sub-pixel SPX3), and between the third pixel circuit PXC3 (or the third sub-pixel SPX3) and the fourth pixel circuit PXC4 (or the fourth sub-pixel SPX4). If the twelfth vertical line WL12b is located between the second pixel circuit PXC2 and the third pixel circuit PXC3, then the twelfth vertical line WL12b may be located between the second data line D2 and the third data line D3, as shown in FIG. Fig. 20 The position of the twelfth vertical line WL12b is not necessarily limited to the above-mentioned embodiment. According to the embodiment, the position of the twelfth vertical line WL12b may be changed in various ways.

[0334] The thirteenth additional line WL13 may be spaced apart from the twelfth additional line WL12 formed of the same layer (or formed by the same process and disposed in the same layer). In an embodiment, the thirteenth additional line WL13 may extend in the second direction DR2 and may correspond to the reference line WL12. Figure 6The kth readout line RXk is described. The thirteenth additional line WL13 may be located in an area of ​​the display area DA where the sensor circuit SC is located, and may be electrically connected to the tenth transistor T10 of the sensor circuit SC through the third connection pattern CNP3 and the seventh conductive pattern CP7.

[0335] If the sensor circuit SC is located between the first pixel circuit PXC1 and the second pixel circuit PXC2, the thirteenth additional line WL13 may also be located between the first pixel circuit PXC1 and the second pixel circuit PXC2. In the case where the thirteenth additional line WL13 corresponding to the kth readout line RXk is located between the first pixel circuit PXC1 and the second pixel circuit PXC2, the spacing distance between the thirteenth additional line WL13 and the first data line D1 electrically connected to the first pixel circuit PXC1 and the spacing distance between the thirteenth additional line WL13 and the second data line D2 electrically connected to the second pixel circuit PXC2 may be further increased. If the spacing distance between the thirteenth additional line WL13 and each of the first data line D1 and the second data line D2 is further increased, the phenomenon that the sensing signal transmitted to the thirteenth additional line WL13 and the data signal transmitted to each of the first data line D1 and the second data line D2 affect each other may be further reduced.

[0336] In the case where the thirteenth additional line WL13 is located between the first pixel circuit PXC1 and the second pixel circuit PXC2, the thirteenth additional line WL13 may overlap with the first power line PL1 shared by the first sub-pixel SPX1 and the second sub-pixel SPX2. In an embodiment, the thirteenth additional line WL13 may be disposed on the first power line PL1 formed by the eighth additional layer EIL with the eighth insulating layer INS8 interposed therebetween, and may overlap with the first power line PL1. If a first power voltage (reference Figure 6 In the embodiment of the present invention, the first power line PL1 (the first power line PL1 of the "VDD" in the figure) can be arranged under the thirteenth additional line WL13 and overlap with the thirteenth additional line WL13, then the first power line PL1 can be used as a shielding component to reduce and prevent the coupling capacitance occurring between the first data line D1 and the second data line D2 and the thirteenth additional line WL13.

[0337] In the case where the first power line PL1 is used as a shielding member to ensure the spacing distance between the thirteenth additional line WL13 and each of the first data line D1 and the second data line D2 (or adjacent data lines), the coupling capacitance occurring between the thirteenth additional line WL13 and each of the first data line D1 and the second data line D2 can be reduced. Therefore, the reliability of the display device 1 can be further enhanced.

[0338] Fig.30is a schematic plan view showing sub-pixels SPX1 to SPX4 and a first optical sensing pixel PSR1 according to an embodiment. Fig.31 It is shown that the Fig.30 Schematic plan view of components in the second additional layer SL and the ninth additional layer NIL. Fig.32 It is along Fig.30 A schematic cross-sectional view taken along line III-III'.

[0339] Fig.30 The implementation method involves Fig. 20 Modifications of the embodiment regarding the position of the twelfth vertical line WL12b, etc.

[0340] Figure 30 to Figure 32 The description of the embodiment will focus on the differences from the above-described embodiment, and to the extent that an element is not described in detail with respect to this figure, it will be understood that the element is at least similar to corresponding elements that have been described elsewhere within the present disclosure.

[0341] refer to Figure 1 and Figure 30 to Figure 32 , the twelfth additional line WL12 may be formed by the ninth additional layer NIL (or the seventh conductive layer CL7), and may include a twelfth horizontal line WL12a extending in the first direction DR1 and a twelfth vertical line WL12b extending in the second direction DR2. The twelfth horizontal line WL12a and the twelfth vertical line WL12b may be integrally formed and electrically connected to each other. Since the twelfth horizontal line WL12a and the twelfth vertical line WL12b are integrally formed with each other, the twelfth additional line WL12 may have a mesh structure.

[0342] The twelfth vertical line WL12b may be arranged at a ratio of one twelfth vertical line WL12b per N sub-pixels (where N is a positive integer). For example, the twelfth vertical line WL12b may be disposed between the third pixel circuit PXC3 (or the third sub-pixel SPX3) and the fourth pixel circuit PXC4 (or the fourth sub-pixel SPX4). However, the present disclosure is not necessarily limited to the above examples. In an embodiment, the twelfth vertical line WL12b may be arranged at a ratio of one twelfth vertical line WL12b per sub-pixel.

[0343] Fig.33 is a schematic block diagram showing an electronic device 1000 according to an embodiment. Fig.34 It is shown Fig.33 The electronic device 1000 is a schematic diagram of an example in which the electronic device 1000 is implemented as a smart phone. Fig.35 It is shown Fig.33 1 is a schematic diagram of an example in which the electronic device 1000 is implemented as a tablet computer.

[0344] refer to Figure 33 to Figure 35 , the electronic device 1000 may include a processor 1010, a storage device 1020, a memory device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 and Figure 2 The electronic device 1000 may also include various ports for communicating with a graphics card, a sound card, a memory card, a USB device or other systems. Fig.34 As shown in , the electronic device 1000 may be implemented as a smart phone. Fig.35 As shown in , the electronic device 1000 can be implemented as a tablet computer. However, the above examples are illustrative, and the electronic device 1000 is not necessarily limited to the above examples. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart board, a smart watch, a navigation device for a vehicle, a computer monitor, a laptop computer, a head-mounted display device, etc.

[0345] The processor 1010 may perform specific calculations or tasks. In an embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. In an embodiment, the processor 1010 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0346] The storage device 1020 may store data required to perform operations of the electronic device 1000. For example, the storage device 1020 may include nonvolatile storage devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and ferroelectric random access memory (FRAM) devices, and / or volatile storage devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, mobile DRAM devices, etc.

[0347] The memory device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0348] The I / O device 1040 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as a speaker and a printer. In an implementation, the display device 1060 may be included in the I / O device 1040 .

[0349] The power supply 1050 may provide power required to perform operations of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0350] The display device 1060 may display an image corresponding to visual information of the electronic device 1000. Here, the display device 1060 may be an organic light emitting diode (OLED) display device or a quantum dot light emitting display device, but is not necessarily limited thereto. The display device 1060 may be connected to other components via a bus or other communication links.

[0351] In an embodiment, the data line and the readout line may be arranged in different layers, so that the spacing distance between the data line and the readout line can be more reliably ensured. A power line configured to receive a voltage having a constant voltage level may be located below the readout line and formed in the same layer as the data line. Therefore, the parasitic capacitance occurring between the data line and the readout line may be reduced. Therefore, a display device and an electronic device having enhanced reliability may be provided.

[0352] The effects of the present disclosure are not necessarily limited to the foregoing, and other various effects are expected herein.

[0353] While various exemplary embodiments have been described above, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope of the present disclosure.

[0354] Therefore, the embodiments disclosed in this specification are for illustrative purposes and do not necessarily limit the technical spirit of the present disclosure.

Claims

1. A display device, comprising: The first sub-pixel, the second sub-pixel and the third sub-pixel are arranged in a first direction and each includes a pixel circuit; an optical sensing pixel including a sensor circuit; a first data line extending in a second direction crossing the first direction and electrically connected to the first sub-pixel; a second data line extending in the second direction and electrically connected to the second sub-pixel; a third data line extending in the second direction and electrically connected to the third sub-pixel; a readout line extending in the second direction and electrically connected to the optical sensing pixel; as well as a first additional line extending in the second direction and electrically connected to the optical sensing pixel and configured to receive a reset voltage, wherein the first additional line is disposed in the same layer as each of the first data line, the second data line and the third data line, and The readout line is disposed in a layer different from a layer of the first data line, the second data line, the third data line and the first additional line.

2. The display device according to claim 1, wherein: The readout line is disposed on the first data line, the second data line, the third data line, and the first additional line.

3. The display device according to claim 1, wherein: The readout line overlaps with the first additional line and is disposed on the first additional line.

4. The display device according to claim 1, wherein: The first additional line is disposed between the second data line and the third data line.

5. The display device according to claim 1, wherein: The optical sensing pixel is disposed between the second sub-pixel and the third sub-pixel.

6. The display device according to claim 1, in, Each of the first sub-pixel, the second sub-pixel, and the third sub-pixel further includes a light emitting element configured to emit light, and The optical sensing pixel further includes a light receiving element configured to output a sensing signal corresponding to the light emitted from the light emitting element.

7. The display device according to claim 6, in, The optical sensing pixel further includes a bridge pattern electrically connected to the light receiving element, and The bridge pattern and the readout line are disposed in the same layer and are spaced apart from each other.

8. The display device according to claim 1, wherein: The first additional line has a width greater than a width of the readout line.

9. The display device according to claim 1, further comprising a second additional line extending in the first direction and electrically connected to the first additional line and configured to receive the reset voltage, in, The first additional line is disposed on the second additional line with an insulating layer interposed between the first additional line and the second additional line.

10. The display device according to claim 1, further comprising a third additional line electrically connected to each of the first sub-pixel, the second sub-pixel and the third sub-pixel and configured to receive a first power voltage, in, The third additional line is disposed in the same layer as each of the first data line, the second data line, the third data line, and the first additional line.

11. The display device according to claim 10, wherein: The readout line does not overlap with the third additional line.

12. The display device according to claim 1, wherein: The sensor circuit comprises: A light receiving element; a first sensor transistor configured to control a current flowing to the readout line in response to a voltage of one electrode of the light receiving element; a second sensor transistor electrically connected between the first sensor transistor and the readout line; and a third sensor transistor electrically connected between the first additional line and the one electrode of the light receiving element and including a gate electrode connected to a reset control line, wherein each of the first sensor transistor and the second sensor transistor comprises a first type semiconductor, and The third sensor transistor includes a second type semiconductor different from the first type semiconductor.

13. The display device according to claim 12, in, Each of the first sensor transistor and the second sensor transistor includes a silicon semiconductor, and Wherein, the third sensor transistor includes an oxide semiconductor.

14. The display device according to claim 1, comprising: substrate; A first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, an eighth insulating layer and a ninth insulating layer are sequentially arranged on the substrate; a first additional layer, disposed between the substrate and the first insulating layer; a second additional layer, disposed between the first insulating layer and the second insulating layer; a third additional layer, disposed between the second insulating layer and the third insulating layer; a fourth additional layer, disposed between the third insulating layer and the fourth insulating layer; a fifth additional layer, disposed between the fourth insulating layer and the fifth insulating layer; a sixth additional layer, disposed between the fifth insulating layer and the sixth insulating layer; a seventh additional layer, disposed between the sixth insulating layer and the seventh insulating layer; an eighth additional layer, disposed between the seventh insulating layer and the eighth insulating layer; as well as a ninth additional layer, disposed between the eighth insulating layer and the ninth insulating layer, The eighth additional layer includes the first additional line, the first data line, the second data line and the third data line, and Wherein, the ninth additional layer includes the readout line.

15. A display device comprising: The first sub-pixel, the second sub-pixel and the third sub-pixel are arranged in a first direction and each includes a pixel circuit; an optical sensing pixel including a sensor circuit; a first data line extending in a second direction crossing the first direction and electrically connected to the first sub-pixel; a second data line extending in the second direction and electrically connected to the second sub-pixel; a third data line extending in the second direction and electrically connected to the third sub-pixel; a readout line extending in the second direction and electrically connected to the optical sensing pixel; a first additional line extending in the second direction and electrically connected to the optical sensing pixel and configured to receive a reset voltage; as well as a second additional line electrically connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel and configured to receive a first power voltage, wherein the second additional line is disposed in the same layer as each of the first data line, the second data line and the third data line, wherein the readout line and the first additional line are arranged in a common layer, and The readout line and the first additional line are arranged in a layer different from a layer of the first data line, the second data line, the third data line and the second additional line.

16. The display device according to claim 15, in, The readout line overlaps the second additional line, and The first additional line is disposed between the second data line and the third data line, and is disposed on the second data line and the third data line.

17. The display device according to claim 15, in, The first additional lines include a horizontal line extending in the first direction and a vertical line extending in the second direction, and Wherein, the horizontal lines and the vertical lines together form a mesh structure.

18. The display device according to claim 17, wherein: The readout line is spaced apart from the horizontal line and the vertical line.

19. The display device according to claim 15, wherein: The optical sensing pixel is disposed between the first sub-pixel and the second sub-pixel.

20. An electronic device, comprising: a processor configured to provide input image data to a display device; as well as the display device being configured to display an image based on the input image data, Wherein, the display device comprises: The first sub-pixel, the second sub-pixel and the third sub-pixel are arranged in a first direction and each includes a pixel circuit; an optical sensing pixel including a sensor circuit; a first data line extending in a second direction intersecting the first direction, and is electrically connected to the first sub-pixel; A second data line extending in the second direction and electrically connected to the a second sub-pixel; A third data line extends in the second direction and is electrically connected to the a third sub-pixel; a readout line extending in the second direction and electrically connected to the optical sensing pixel; and a first additional line extending in the second direction and electrically connected to the optical sensing pixel and configured to receive a reset voltage, wherein the first additional line is disposed in the same layer as each of the first data line, the second data line and the third data line, and The readout line is disposed in a layer different from a layer of the first data line, the second data line, the third data line, and the first additional line.

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