Display panel, display screen and display device

Abstract

The invention relates to a display panel, a display screen and a display device, and relates to the technical field of display. The display panel comprises a plurality of pixel circuit columns, a plurality of first data lines and a plurality of second data lines, wherein each pixel circuit column is provided with one first data line and one second data line; wherein the pixel circuit column comprises a plurality of first pixel circuits and a plurality of second pixel circuits, in the same pixel circuit column, each first pixel circuit is connected with the first data line, each second pixel circuit is connected with the second data line, and layout structures of the first pixel circuits and the second pixel circuits are mirror image structures of each other in the direction of the pixel circuit column; a first connecting point of the first pixel circuit and the first data line is located on the edge, close to the first data line, of the first pixel circuit, and a second connecting point of the second pixel circuit and the second data line is located on the edge, close to the second data line, of the second pixel circuit. By adopting the display panel, crosstalk between the data line and other signal lines can be reduced, and the display performance is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a display screen and a display device. Background Art

[0002] With the continuous development of display technology, the refresh rate of display panels is also increasing. At a high refresh rate, the row scanning time of the pixel circuit in the display panel is shortened, and the threshold compensation time of the pixel circuit is also shortened accordingly.

[0003] In the existing design, in order to increase the threshold compensation time of the pixel circuit, a dual data line driving method can be adopted, that is, the pixel circuits of adjacent rows in the same pixel column are connected to different data lines respectively. However, under this setting method, there is a problem of crosstalk between the data line and other signal lines in the display panel. Summary of the invention

[0004] The embodiments of the present application provide a display panel, a display screen and a display device, which can reduce the mutual crosstalk between data lines and other signal lines in the display panel, thereby improving the display performance.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a plurality of pixel circuit columns, a plurality of first data lines and a plurality of second data lines, wherein the pixel circuit columns are provided with one first data line and one second data line; wherein:

[0006] The pixel circuit column includes a plurality of first pixel circuits and a plurality of second pixel circuits. In the same pixel circuit column, each of the first pixel circuits is connected to the first data line, each of the second pixel circuits is connected to the second data line, and the layout structures of the first pixel circuits and the second pixel circuits are mirror images of each other along the direction of the pixel circuit column.

[0007] A first connection point between the first pixel circuit and the first data line is located at an edge of the first pixel circuit close to the first data line, and a second connection point between the second pixel circuit and the second data line is located at an edge of the second pixel circuit close to the second data line.

[0008] In a second aspect, an embodiment of the present application provides a display screen, comprising a cover plate and a display panel as described above, wherein the cover plate is located on a surface of the display panel in a light emitting direction.

[0009] In a third aspect, an embodiment of the present application provides a display device, which includes the display panel as described above.

[0010] In the display panel, display screen and display device provided by the embodiments of the present application, each pixel circuit column is respectively provided with a first data line and a second data line. In each pixel circuit column, each first pixel circuit is respectively connected to the first data line, and each second pixel circuit is connected to the second data line, and the layout structure of the first pixel circuit and the layout structure of the second pixel circuit are mirror images of each other along the direction of the pixel circuit column. In this case, the first connection point between the first pixel circuit and the first data line can be located at the edge of the first pixel circuit close to the first data line, and the second connection point between the second pixel circuit and the second data line can be located at the edge of the second pixel circuit close to the second data line. Therefore, when the first data line and the second data line are used to drive the same pixel circuit column, that is, when the dual data line (including the first data line and the second data line) driving mode is used, the data line does not need to cross the pixel circuit area to connect to the pixel circuit, that is, there is no need for a cross-line connection between the data line and the pixel circuit, which shortens the connection length between the data line and the pixel circuit, saves space, is conducive to realizing a display panel with a narrow frame and a high pixel density, and reduces the coupling capacitance between the data line and other signal lines in the display panel, thereby improving the problem of mutual crosstalk between the data line and other signal lines, and improving the display effect of the display panel. In addition, in the same pixel circuit column, the layout structure of the first pixel circuit and the second pixel circuit is designed as a mirror structure, which avoids the data line crossing in the pixel circuit area, reduces the total capacitance of the data line, and improves the pixel charging rate, so that the impedance of the display panel fan-out routing can be further increased and the line width can be further compressed, which is beneficial to the narrow bezel design of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a top view structure of a display panel provided in an embodiment of the present application;

[0012] Figure 2 is a schematic diagram of a top view structure of a display panel;

[0013] Figure 3 A schematic diagram of a top view structure of another display panel provided in an embodiment of the present application;

[0014] Figure 4 A schematic diagram of a layout structure of a display panel provided in an embodiment of the present application;

[0015] Figure 5 A schematic diagram of the layout structure of another display panel provided in an embodiment of the present application;

[0016] Figure 6 A schematic diagram of a top view structure of another display panel provided in an embodiment of the present application;

[0017] Figure 7A schematic diagram of a top view structure of another display panel provided in an embodiment of the present application;

[0018] Figure 8 A timing diagram of a control signal provided in an embodiment of the present application;

[0019] Fig. 9 A schematic diagram of a layout structure of another display panel provided in an embodiment of the present application;

[0020] Fig.10 A schematic diagram of a layout structure of another display panel provided in an embodiment of the present application;

[0021] Fig.11 A schematic diagram of the internal structure of a pixel circuit provided in an embodiment of the present application;

[0022] Fig.12 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application;

[0023] Fig.13 A schematic diagram of a layout structure of a semiconductor layer provided in an embodiment of the present application;

[0024] Fig.14 A schematic diagram of a layout structure of a first conductive layer provided in an embodiment of the present application;

[0025] Fig.15 A schematic diagram of a layout structure of a capacitor conductive layer provided in an embodiment of the present application;

[0026] Fig.16 A schematic diagram of a layout structure of a second conductive layer provided in an embodiment of the present application;

[0027] Fig.17 A schematic diagram of a layout structure of a third conductive layer provided in an embodiment of the present application;

[0028] Fig.18 A schematic diagram of the layout structure of another display panel provided in an embodiment of the present application;

[0029] Fig.19 A schematic diagram of another layout structure of a third conductive layer provided in an embodiment of the present application;

[0030] Fig. 20 A schematic diagram of a cross-sectional structure of a display screen provided in an embodiment of the present application;

[0031] Fig.21 A schematic diagram of a top view of another display device provided in an embodiment of the present application.

[0032] Description of reference numerals:

[0033] Pixel circuit column 10, first pixel circuit column 11, second pixel circuit column 12, first pixel circuit 110, second pixel circuit 120, data line 20, first data line 21, first A data line 211, first B data line 212, first data line body 2111, first data signal output node 2112, second data line 22, second A data line 221, second B data line 222, second data line body 2211, second data signal output node 2212, first connection point 31, second connection point 32, gating circuit 40, first gating circuit 41, second gating circuit 42, first switch unit 410, second switch unit 420, third switch unit 430, fourth switch unit 440, control line 50, first control line 51, second control line 52, third control line 53, fourth control line 54, display panel 1100, cover plate 1200, display screen 1000, display device 10000. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0036] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0037] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0038] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present application, a first data line may be referred to as a second data line, and similarly, a second data line may be referred to as a first data line.

[0039] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0040] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0041] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0042] Figure 1 A schematic diagram of a top view of a display panel provided in an embodiment of the present application. Figure 1 In one embodiment, the display panel includes pixel circuits arranged in an array, each pixel circuit column 10 is connected to two data lines 20, and each pixel circuit column 10 writes data signals through the two connected data lines 20, that is, a double data line (DDL) driving method is adopted. In this way, the jump effect caused by the switch of each row of pixel circuits on the same data line 20 can be reduced, and the circuit stability can be improved. At the same time, the delay of the data line 20 signal can be reduced, and the charging efficiency of the pixel circuit can be improved, which is conducive to achieving high-frequency display.

[0043] As described in the background technology section, the display panel in the related art adopts a dual data line driving method, and there is a problem of mutual crosstalk between the data line and other signal lines in the display panel. The inventor found that the reason for the above problem is that since the layout structure of each pixel circuit in the display panel adopts a specific design, the connection points between each pixel circuit of the same pixel circuit column and the two data lines are located on the same side of the pixel circuit. Therefore, for the two data lines located on both sides of the pixel circuit column, at least one of the data lines needs to cross the pixel circuit area to connect with the pixel circuit, that is, the data line and the pixel circuit need to be connected across the line. Therefore, the data line with the cross-line connection is easily coupled by other signal lines in the display panel. Therefore, the data line and other signal lines are prone to mutual crosstalk, thereby affecting the display performance of the display panel. For example, Figure 2 A schematic diagram of a top view structure of a display panel is provided, such as Figure 2 As shown, due to the layout structure of the pixel circuit P, in each pixel circuit P column, the connection points CON between each pixel circuit P and the two data lines DL are all located on the left side of the pixel circuit P. Therefore, the data line DL located on the right side of the pixel circuit P column and the corresponding pixel circuit P need to be connected across the line in the row direction of the pixel circuit P. Therefore, the data line DL located on the right side of the pixel circuit P column is prone to crosstalk with the signal line extending along the row direction of the pixel circuit P in the display panel, thereby affecting the display performance of the display panel.

[0044] Based on the above technical problems, the inventors have found that by designing the pixel circuit layout structure connecting different data lines in the same pixel circuit column as a mirror structure along the direction of the pixel circuit column, the connection point between the data line and the pixel circuit is located at the edge of the pixel circuit close to the data line, which can avoid the cross-line connection between the data line and the pixel circuit, thereby reducing the mutual crosstalk between the data line and other signal lines in the display panel, thereby improving the display performance of the display panel. Based on this, the inventors further studied the technical solution of the embodiment of the present application. Specifically, the display panel provided by the embodiment of the present application includes multiple pixel circuit columns, multiple first data lines and multiple second data lines, and the pixel circuit column is provided with a first data line and a second data line; wherein, the pixel circuit column includes multiple first pixel circuits and multiple second pixel circuits, and in the same pixel circuit column, each first pixel circuit is respectively connected to the first data line, and each second pixel circuit is connected to the second data line, and the layout structure of the first pixel circuit and the second pixel circuit is a mirror structure of each other along the direction of the pixel circuit column; the first connection point between the first pixel circuit and the first data line is located at the edge of the first pixel circuit close to the first data line, and the second connection point between the second pixel circuit and the second data line is located at the edge of the second pixel circuit close to the second data line.

[0045] Since in the same pixel circuit column, the layout structure of the first pixel circuit and the layout structure of the second pixel circuit are mirror images of each other along the direction of the pixel circuit column, the first connection point between the first pixel circuit and the first data line is located at the edge of the first pixel circuit close to the first data line, and the second connection point between the second pixel circuit and the second data line is located at the edge of the second pixel circuit close to the second data line, that is, the connection points between each pixel circuit and the data line are close to the corresponding data line, therefore, there is no need for cross-line connection between the data line and the pixel circuit, therefore, the coupling effect between the data line and other signals can be reduced, thereby avoiding the crosstalk problem caused by cross-line connection, and further improving the display performance of the display panel.

[0046] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] Figure 3 A schematic diagram of a top view of a display panel provided in an embodiment of the present application is shown in FIG. Figure 4 A schematic diagram of a layout structure of a display panel provided in an embodiment of the present application, Figure 5 A schematic diagram of a display panel layout structure provided in an embodiment of the present application. Figures 3 to 5 In one embodiment, a display panel is provided. The display panel includes a plurality of pixel circuit columns, a plurality of first data lines 21 and a plurality of second data lines 22 .

[0048] The pixel circuit column is provided with a first data line 21 and a second data line 22. The first data line 21 and the second data line 22 are respectively used to provide a data signal VData. The first data line 21 and the second data line 22 extend along the pixel circuit column direction Y, respectively, and the first data line 21 and the second data line 22 are respectively arranged along the pixel circuit row direction X. Wherein, Y intersects with X, for example, Y is perpendicular to X. Exemplarily, in the same pixel circuit column, the first data line 21 and the second data line 22 are respectively located on both sides of the pixel circuit column. For example, as Figures 3 to 5 As shown, in the same pixel circuit column, the first data line 21 is located on the left side of the pixel circuit column, and the second data line 22 is located on the right side of the pixel circuit column. It should be noted that the above is only an exemplary description, and the relative position relationship between the first data line 21 and the second data line 22 and the pixel circuit column can also be other layout modes, for example, the first data line 21 is located on the right side of the pixel circuit column, and the second data line 22 is located on the left side of the pixel circuit column. Specifically, a suitable layout mode can be selected according to the actual application scenario, and is not limited here.

[0049] The pixel circuit column includes a plurality of first pixel circuits 110 and a plurality of second pixel circuits 120. In the same pixel circuit column, each first pixel circuit 110 is connected to the first data line 21, and each second pixel circuit 120 is connected to the second data line 22. That is, in the same pixel circuit, the pixel circuit connected to the first data line 21 is the first pixel circuit 110, and the pixel circuit connected to the second data line 22 is the second pixel circuit 120.

[0050] Exemplarily, in the same pixel circuit column, the first pixel circuit 110 and the second pixel circuit 120 are alternately arranged, that is, the first pixel circuit 110 and the second pixel circuit 120 are arranged alternately along the pixel circuit column direction. For example, in the same pixel circuit column, the pixel circuits located in odd rows are the first pixel circuits 110 and are connected to the first data line 21, and the pixel circuits located in even rows are the second pixel circuits 120 and are connected to the second data line 22; or the pixel circuits located in odd rows are the second pixel circuits 120 and are connected to the second data line 22, and the pixel circuits located in even rows are the first pixel circuits 110 and are connected to the first data line 21. It should be noted that, in applications, the first pixel circuit 110 and the second pixel circuit 120 in the same pixel circuit column may not be arranged alternately. For example, multiple first pixel circuits 110 are arranged adjacent to and continuously, and multiple second pixel circuits 120 are arranged adjacent to and continuously, and the multiple first pixel circuits 110 arranged continuously and the multiple second pixel circuits 120 arranged continuously are arranged alternately along the direction of the pixel circuit column. The above are all exemplary descriptions. In applications, the appropriate layout method can be selected for the arrangement of the first pixel circuit 110 and the second pixel circuit 120 according to actual needs, and no limitation is made here.

[0051] The positions of the first pixel circuit 110 and the second pixel circuit 120 in different pixel circuit columns may be the same or different. For example, in each pixel circuit column, the pixel circuits located in odd rows are the first pixel circuits 110 and are connected to the first data line 21, and the pixel circuits located in even rows are the second pixel circuits 120 and are connected to the second data line 22. For another example, in two adjacent pixel circuit columns, the pixel circuits located in odd rows in one pixel circuit column are the first pixel circuits 110 and are connected to the first data line 21, and the pixel circuits located in even rows are the second pixel circuits 120 and are connected to the second data line 22, and the pixel circuits located in odd rows in the other pixel circuit column are the second pixel circuits 120 and are connected to the second data line 22, and the pixel circuits located in even rows are the first pixel circuits 110 and are connected to the first data line 21. It should be noted that the above is only an exemplary description, and the arrangement of pixel circuits in the pixel circuit column may also adopt a combination of the above methods. In applications, the arrangement of pixel circuits in each pixel circuit column in the display panel can be selected according to the actual scenario and is not excessively limited here.

[0052] The layout structure of the first pixel circuit 110 and the layout structure of the second pixel circuit 120 are mirror images of each other along the direction of the pixel circuit column. That is, in the same pixel circuit row, the layout structure of the first pixel circuit 110 and the layout structure of the second pixel circuit 120 are symmetrically arranged along the direction of the pixel circuit column. Moreover, in the same pixel circuit column, the layout structure of the first pixel circuit 110 and the layout structure of the second pixel circuit 120 are symmetrical along the direction of the pixel circuit column.

[0053] The connection point between the first pixel circuit 110 and the first data line 21 is a first connection point 31, and the first connection point 31 is located at the edge of the first pixel circuit 110 close to the first data line 21. The connection point between the second pixel circuit 120 and the second data line 22 is a second connection point 32, and the second connection point 32 is located at the edge of the second pixel circuit 120 close to the second data line 22. For example, Figures 3 to 5 As shown, the first connection point 31 is located at the left edge of the first pixel circuit 110 close to the first data line 21, and the second connection point 32 is located at the right edge of the second pixel circuit 120 close to the second data line 22. It should be noted that the above is only an exemplary description, and in applications, the specific positions of the first connection point 31 and the second connection point 32 can be determined according to factors such as the relative position relationship between the first data line 21 and the second data line 22 and the pixel circuit column, the arrangement of the pixel circuit column, etc., and no excessive limitations are made here.

[0054] It can be understood that the first connection point 31 is located at the edge of the first pixel circuit 110 close to the first data line 21, and the second connection point 32 is located at the edge of the second pixel circuit 120 close to the second data line 22. Therefore, there is no need for a cross-line connection between the first data line 21 and the first pixel circuit 110, and there is no need for a cross-line connection between the second data line 22 and the second pixel circuit 120. That is, there is no need for a cross-line connection between the data line 20 and the corresponding pixel circuit. That is, the data line 20, that is, the connection point is located at the edge of the pixel circuit close to the correspondingly connected data line 20.

[0055] Exemplarily, the first connection point 31 and the second connection point 32 are mirror connection points of each other along the direction of the pixel circuit column. That is, the first connection point 31 and the second connection point 32 are symmetrical. Among them, in the same pixel circuit column, the first connection point 31 and the second connection point 32 are symmetrical along the pixel circuit column. And, in the same pixel circuit row, the first connection point 31 and the second connection point 32 are symmetrically arranged along the direction of the pixel circuit column.

[0056] In the above-mentioned display panel, each pixel circuit column is respectively provided with a first data line 21 and a second data line 22. In each pixel circuit column, each first pixel circuit 110 is respectively connected to the first data line 21, and each second pixel circuit 120 is connected to the second data line 22. The layout structure of the first pixel circuit 110 and the layout structure of the second pixel circuit 120 are mirror images of each other along the direction of the pixel circuit column. In this case, the first connection point 31 between the first pixel circuit 110 and the first data line 21 can be located at the edge of the first pixel circuit 110 close to the first data line 21, and the second connection point 32 between the second pixel circuit 120 and the second data line 22 can be located at the edge of the first pixel circuit 110 close to the first data line 21, and the second connection point 32 between the second pixel circuit 120 and the second data line 22 can be located at the edge of the first pixel circuit 110 close to the first data line 21. The second pixel circuit 120 is close to the edge of the second data line 22, so that when the first data line 21 and the second data line 22 are used to drive the same pixel circuit column, that is, when the dual data line 20 (including the first data line 21 and the second data line 22) is used for driving, the data line 20 does not need to cross the pixel circuit area to connect with the pixel circuit, that is, there is no need for a cross-line connection between the data line 20 and the pixel circuit, which saves space, is beneficial to a display panel with a high pixel density, and reduces the coupling between the data line 20 and other signal lines in the display panel, thereby improving the problem of crosstalk between the data line 20 and other signal lines, thereby improving the display effect of the display panel. In addition, in the same pixel circuit column, the layout structure of the first pixel circuit 110 and the second pixel circuit 120 is designed as a mirror structure, which avoids the data line 20 from crossing the line in the pixel circuit area, reduces the total capacitance of the data line 20, and improves the pixel charging rate, so that the impedance of the fan-out wiring of the display panel can be further increased, and the line width can be further compressed, which is beneficial to the narrow frame design of the display panel.

[0057] Figure 6A schematic diagram of a top view of a display panel provided in an embodiment of the present application. Figure 6 As shown, in one embodiment, the display panel further includes a gating circuit 40. Exemplarily, the gating circuit 40 includes a multiplexer (Demux).

[0058] The first data line 21 and the second data line 22 connected to at least one pixel circuit column are connected to the data signal terminal Data_in via the gating circuit 40. The input terminal of the gating circuit 40 is connected to the data signal terminal Data_in, and the multiple output terminals of the gating circuit 40 are respectively connected to the first data line 21 and the second data line 22 connected to at least one pixel circuit column.

[0059] Each gating circuit 40 is respectively connected to at least one pixel circuit column, that is, each gating circuit 40 can be connected to one or more pixel circuit columns. The pixel circuit columns corresponding to each gating circuit 40 are different from each other, and the data signal terminals Data_in connected to each gating circuit 40 are different from each other. For example, each gating circuit 40 is respectively connected to a pixel circuit column, that is, the first data line 21 and the second data line 22 of a pixel circuit column are connected to the data signal terminal Data_in through the gating circuit 40, that is, the number ratio of the data signal terminal Data_in connected by the gating circuit 40 to the data line 20 is 1:2, which can be recorded as DDL+Demux1:2. For another example, each gating circuit 40 is respectively connected to two adjacent pixel circuit columns, that is, the first data line 21 and the second data line 22 of the two pixel circuit columns are respectively connected to the data signal terminal Data_in through the gating circuit 40, that is, the number ratio of the data signal terminal Data_in connected by the gating circuit 40 to the data line 20 is 1:4, which can be recorded as DDL+Demux1:4. In applications, the connection mode between the first data line 21 and the second data line 22 connected to the pixel circuit column by the selection circuit 40 can be selected according to the actual scenario. The ratio of the number of data signal terminals Data_in connected to the selection circuit 40 and the data lines 20 is 1:n, where n is an even number greater than or equal to 2, that is, DDL+Demux1:n, which is not limited here.

[0060] The data signal terminal Data_in is used to provide a data signal VData. The gating circuit 40 is used to transmit the data signal VData provided by the data signal terminal Data_in to the first data line 21 and the second data line 22 connected to the gating circuit 40 in a time-sharing manner. That is, the gating circuit 40 is used to conduct the paths between the data signal terminal Data_in and the first data line 21 and the second data line 22 in a time-sharing manner, so as to transmit the data signal VData to the first data line 21 and the second data line 22 in a time-sharing manner.

[0061] It should be noted that the number of the gating circuits 40 and the number of the first data lines 21 and the second data lines 22 connected to the gating circuits 40 can be determined according to the actual application scenario. For example, the display panel includes N pixel circuit columns, and each gating circuit 40 is connected to the first data line 21 and the second data line 22 of a pixel circuit column, that is, n=2, then the number of the gating circuits 40 is N. In the application, other methods can also be used. For example, when n=4, the number of the gating circuits 40 is N / 2, etc., which is not excessively limited here.

[0062] In the above-mentioned display panel, the first data line 21 and the second data line 22 connected to at least one pixel circuit column are connected to the data signal terminal Data_in via the selection circuit 40, and the data signal VData provided by the data signal terminal Data_in is transmitted to the first data line 21 and the second data line 22 connected to the selection circuit 40 in a time-sharing manner through the selection circuit 40. In this way, multiple data lines 20 share the same data signal terminal Data_in through the selection circuit 40, which can reduce the number of data signal terminals Data_in, and help to achieve a display panel with a narrow frame and a high pixel density; and can reduce the jump effect caused by the switching of each row of pixel circuits on the same data line 20, thereby improving the circuit stability; in addition, the delay of the data line 20 signal can be reduced, thereby improving the charging efficiency of the pixel circuit, and helping to achieve high-frequency display.

[0063] Figure 7 A schematic diagram of a top view of a display panel provided in an embodiment of the present application. Figure 7 As shown, in one embodiment, the plurality of pixel circuit columns include a plurality of first pixel circuit columns 11 and a plurality of second pixel circuit columns 12. The first pixel circuit columns 11 and the second pixel circuit columns 12 are alternately arranged along the pixel circuit row direction, that is, the first pixel circuit columns 11 and the second pixel circuit columns 12 are alternately arranged along the pixel circuit row direction.

[0064] The four data lines 20 connected to the first pixel circuit column 11 and the second pixel circuit column 12 are connected to the data signal terminal Data_in via the gating circuit 40, wherein the four data lines 20 refer to the first data line 21 and the second data line 22 connected to the first pixel circuit column 11, and the first data line 21 and the second data line 22 connected to the second pixel circuit column 12. The input end of the gating circuit 40 is connected to the data signal terminal Data_in, and the four output ends of the gating circuit 40 are respectively connected to the first data line 21 and the second data line 22 connected to the first pixel circuit column 11, and the first data line 21 and the second data line 22 of the second pixel circuit column 12. The four data lines 20 connected to each gating circuit 40 are different from each other, that is, the first pixel circuit column 11 and the second pixel circuit column 12 connected to each gating circuit 40 are different from each other. Exemplarily, the first pixel circuit column 11 and the second pixel circuit column 12 corresponding to the same gating circuit 40 are adjacent in the pixel circuit row direction.

[0065] The gating circuit 40 is used to transmit the data signal VData provided by the data signal terminal Data_in to the four data lines 20 connected to the gating circuit 40 in a time-sharing manner. That is, the gating circuit 40 is used to conduct the first data line 21 and the second data line 22 of the first pixel circuit column 11 and the first data line 21 and the second data line 22 of the second pixel circuit column 12 in a time-sharing manner, respectively, to the paths between the data signal terminal Data_in, so as to transmit the data signal VData to the first data line 21 and the second data line 22 of the first pixel circuit column 11 and the first data line 21 and the second data line 22 of the second pixel circuit column 12 in a time-sharing manner.

[0066] In the above-mentioned display panel, the four data lines 20 connected to the first pixel circuit column 11 and the second pixel circuit column 12 are connected to the data signal terminal Data_in via the selection circuit 40, and the data signal VData provided by the data signal terminal Data_in is transmitted to the four data lines 20 connected to the selection circuit 40 in a time-sharing manner through the selection circuit 40, so that the four data lines 20 share one data signal terminal Data_in. Compared with the method of not multiplexing the data signal terminal Data_in and two data lines 20 sharing one data signal terminal Data_in, the number of data signal terminals Data_in is significantly reduced, which helps to further realize a display panel with a narrow frame and a high pixel density; and, the jump effect caused by the switching of each row of pixel circuits on the same data line 20 can be further reduced, thereby further improving the circuit stability; in addition, the delay of the data line 20 signal can be further reduced, thereby further improving the charging efficiency of the pixel circuit, which helps to achieve high-frequency display.

[0067] Figure 8 A timing diagram of a display panel provided in an embodiment of the present application, Fig. 9A schematic diagram of a display panel layout structure provided in an embodiment of the present application. Figures 7 to 9 As shown, in one embodiment, the plurality of first data lines 21 include a plurality of first A data lines 211 and a plurality of first B data lines 212. The plurality of second data lines 22 include a plurality of second A data lines 221 and a plurality of second B data lines 222. The first A data lines 211 and the second A data lines 221 are respectively connected to the same first pixel circuit column 11, and the first B data lines 212 and the second B data lines 222 are respectively connected to the same second pixel circuit column 12. The gating circuit 40 includes a first switch unit 410, a second switch unit 420, a third switch unit 430 and a fourth switch unit 440.

[0068] Exemplarily, the number of the first data lines 21 and the second data lines 22 is the same, wherein the number of the first A data lines 211 and the first B data lines 212 is the same, and the number of the second A data lines 221 and the second B data lines 222 is the same. For example, taking the display panel including N pixel circuit columns as an example, the display panel includes N / 4 gating circuits 40, N first data lines 21 and N second data lines 22, wherein the N / 4 gating circuits 40 include N switch units, the N first data lines 21 include N / 2 first A data lines 211 and N / 2 first B data lines 212, and the N second data lines 22 include N / 2 second A data lines 221 and N / 2 second B data lines 222. The switch unit is a general term for the first switch unit 410, the second switch unit 420, the third switch unit 430 and the fourth switch unit 440.

[0069] Exemplarily, the first A data line 211 and the second B data line 222 are symmetrically arranged, and the second A data line 221 and the first B data line 212 are symmetrically arranged. That is, among the four data lines 20 connected to the same gating circuit 40, the first A data line 211 and the first B data line 212 are symmetrically arranged along the second central axis, and the second A data line 221 and the first B data line 212 are symmetrically arranged along the second central axis, wherein the second central axis is the central axis between the first pixel circuit column 11 and the second pixel circuit column 12 connected to the four data lines 20.

[0070] Exemplarily, the first A data line 211, the second A data line 221, the first B data line 212, and the second B data line 222 are alternately arranged along the pixel circuit row direction. Exemplarily, the first A data line 211 and the second A data line 221 are respectively located on both sides of the first pixel circuit column 11, the first B data line 212 and the second B data line 222 are respectively located on both sides of the second pixel circuit column 12, and the second A data line 221 and the first B data line 212 are adjacent.

[0071] It should be noted that the first A data line 211, the second A data line 221, the first B data line 212 and the second B data line 222 may also be arranged in other ways along the row direction of the pixel circuit. For example, the second A data line 221, the first A data line 211, the second B data line 222 and the first B data line 212 are alternately arranged along the row direction of the pixel circuit; for another example, the first A data line 211, the second A data line 221, the second B data line 222 and the first B data line 212 are alternately arranged along the row direction of the pixel circuit; for another example, the second A data line 221, the first A data line 211, the first B data line 212 and the second B data line 222 are alternately arranged along the row direction of the pixel circuit; in application, the appropriate arrangement method can be selected according to the actual scenario, and no excessive restrictions are made here.

[0072] Exemplarily, each gating circuit 40 is connected to two adjacent first pixel circuit columns 11 and second pixel circuit columns 12. Exemplarily, among the four data lines 20 connected to the same gating circuit 40, the first pixel circuit 110 in the first pixel circuit column 11 is connected to the first A data line 211, the second pixel circuit 120 in the first pixel circuit column 11 is connected to the second A data line 221, the first pixel circuit 110 in the second pixel circuit column 12 is connected to the first B data line 212, and the second pixel circuit 120 in the second pixel circuit column 12 is connected to the second B data line 222.

[0073] Exemplarily, in the same first pixel circuit column 11, the connection point between the first pixel circuit 110 and the first A data line 211 is the first A connection point, and the first A connection point is located at the edge of the first pixel circuit 110 close to the first A data line 211; the connection point between the second pixel circuit 120 and the second A data line 221 is the second A connection point, and the second A connection point is close to the edge of the second pixel circuit 120 close to the second A data line 221. Exemplarily, the first A connection point and the second A connection point are mirror connection points of each other along the pixel circuit column direction.

[0074] Exemplarily, in the same second pixel circuit column 12, the connection point between the first pixel circuit 110 and the first B data line 212 is the first B connection point, and the first B connection point is located at the edge of the first pixel circuit 110 close to the first B data line 212; the connection point between the second pixel circuit 120 and the second B data line 222 is the second B connection point, and the second B connection point is located at the edge of the second pixel circuit 120 close to the second B data line 222. Exemplarily, the first B connection point and the second B connection point are mirror connection points of each other along the pixel circuit column direction.

[0075] For example, Figure 7 and Fig. 9As shown, among the four data lines 20 connected to the same gating circuit 40, the first A data line 211, the second A data line 221, the first B data line 212 and the second B data line 222 are alternately arranged along the pixel circuit row direction, and the first A data line 211 is located on the left side of the first pixel circuit column 11, the first A data line 211 is connected to each first pixel circuit 110 in the first pixel circuit column 11, and the first A connection point is located at the left edge of the first pixel circuit 110 close to the first A data line 211; the second A data line 221 is located on the right side of the first pixel circuit column 11, the second A data line 221 is connected to each second pixel circuit 120 in the first pixel circuit column 11 0 is connected, and the second A connection point is located at the right edge of the second pixel circuit 120 close to the second A data line 221; the first B data line 212 is located on the left side of the second pixel circuit column 12, the first B data line 212 is connected to each first pixel circuit 110 in the second pixel circuit column 12, and the first B connection point is located at the left edge of the first pixel circuit 110 close to the first B data line 212; the second B data line 222 is located on the right side of the second pixel circuit column 12, the second B data line 222 is connected to each second pixel circuit 120 in the second pixel circuit column 12, and the second B connection point is located at the right edge of the second pixel circuit 120 close to the second B data line 222.

[0076] Among them, the first ends of the first switch unit 410, the second switch unit 420, the third switch unit 430 and the fourth switch unit 440 are respectively connected to the data signal end Data_in. The control ends of the first switch unit 410, the second switch unit 420, the third switch unit 430 and the fourth switch unit 440 are respectively used to receive different control signals. The enable pulses of the control signals received by the control ends of the first switch unit 410, the second switch unit 420, the third switch unit 430 and the fourth switch unit 440 do not overlap with each other. That is, the time periods in which the first switch unit 410, the second switch unit 420, the third switch unit 430 and the fourth switch unit 440 are in the on state do not overlap with each other.

[0077] The second end of the first switch unit 410 is connected to the first A data line 211. The first switch unit 410 is used to select and conduct the path between the data signal terminal Data_in and the first A data line 211 under the control of the control signal received at the control end of the first switch unit 410; the first switch unit 410 is used to be turned on in response to the enable pulse of the control signal received at the control end of the first switch unit 410, so as to transmit the data signal VData provided by the data signal terminal Data_in to the first A data line 211.

[0078] The second end of the second switch unit 420 is connected to the second A data line 221. The second switch unit 420 is used to select and conduct the path between the data signal terminal Data_in and the second A data line 221 under the control of the control signal received at the control end of the second switch unit 420; the second switch unit 420 is used to be turned on in response to the enable pulse of the control signal received at the control end of the second switch unit 420, so as to transmit the data signal VData provided by the data signal terminal Data_in to the second A data line 221.

[0079] The second end of the third switch unit 430 is connected to the first B data line 212. The third switch unit 430 is used to select and conduct the path between the data signal terminal Data_in and the first B data line 212 under the control of the control signal received at the control end of the third switch unit 430; the third switch unit 430 is used to be turned on in response to the enable pulse of the control signal received at the control end of the third switch unit 430, so as to transmit the data signal VData provided by the data signal terminal Data_in to the first B data line 212.

[0080] The second end of the fourth switch unit 440 is connected to the second B data line 222. The fourth switch unit 440 is used to select and conduct the path between the data signal terminal Data_in and the second B data line 222 under the control of the control signal received by the control end of the fourth switch unit 440; the fourth switch unit 440 is used to be turned on in response to the enable pulse of the control signal received by the control end of the fourth switch unit 440, so as to transmit the data signal VData provided by the data signal terminal Data_in to the second B data line 222.

[0081] Exemplarily, the display panel further includes four control lines 50, which are respectively connected to the first switch unit 410, the second switch unit 420, the third switch unit 430 and the fourth switch unit 440, and the four control lines 50 are respectively used to provide different control signals. Exemplarily, the four control lines 50 include a first control line 51, a second control line 52, a third control line 53 and a fourth control line 54. Among them, the first control line 51 is connected to the control end of the first switch unit 410, and the first control line 51 is used to provide the first control signal MUX1; the second control line 52 is connected to the control end of the second switch unit 420, and the second control line 52 is used to provide the second control signal MUX2; the third control line 53 is connected to the control end of the third switch unit 430, and the third control line 53 is used to provide the third control signal MUX3; the fourth control line 54 is connected to the control end of the fourth switch unit 440, and the fourth control line 54 is used to provide the fourth control signal MUX4. The enable pulses of the first control signal MUX1 , the second control signal MUX2 , the third control signal MUX3 and the fourth control signal MUX4 do not overlap with each other.

[0082] Exemplarily, the first switching unit 410 includes a first transistor, a first electrode of the first transistor is connected to the data signal terminal Data_in, a second electrode of the first transistor is connected to the first A data line 211, and a gate of the first transistor is connected to the first control line 51. The first transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the first A data line 211 in response to an enable pulse of the first control signal MUX1 provided by the first control line 51.

[0083] Exemplarily, the second switching unit 420 includes a second transistor, the second electrode of the second transistor is connected to the data signal terminal Data_in, the second electrode of the second transistor is connected to the second A data line 221, the gate of the second transistor is connected to the second control line 52, and the second transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the second A data line 221 in response to the enable pulse of the second control signal MUX2 provided by the second control line 52.

[0084] Exemplarily, the third switch unit 430 includes a third transistor, a third electrode of the third transistor is connected to the data signal terminal Data_in, a second electrode of the third transistor is connected to the first B data line 212, and a gate of the third transistor is connected to the third control line 53. The third transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the first B data line 212 in response to an enable pulse of the third control signal MUX3 provided by the third control line 53.

[0085] Exemplarily, the fourth switch unit 440 includes a fourth transistor, a fourth electrode of the fourth transistor is connected to the data signal terminal Data_in, a second electrode of the fourth transistor is connected to the second B data line 222, and a gate of the fourth transistor is connected to the fourth control line 54. The fourth transistor is used to transmit the data signal VData provided by the data signal terminal Data_in to the second B data line 222 in response to an enable pulse of the fourth control signal MUX4 provided by the fourth control line 54.

[0086] Exemplarily, for the first transistor, the second transistor, the third transistor and the fourth transistor, their quantity can be one or more respectively, their conductivity type can be a P-type transistor or an N-type transistor, and their process type can be a MOS (Metal-Oxide-Semiconductor) transistor or a TFT (Thin Film Transistor). The quantity and type of each transistor can be selected according to the actual scenario, and no excessive restrictions are made here.

[0087] It should be noted that the above description is based on the example of the selection circuit 40 connecting four data lines 20. In the application, the number of switch units in the selection circuit 40 can be set accordingly according to the number of data lines 20 connected to the selection circuit 40, and the switch unit can be one or more switch devices (such as transistors), which are not excessively limited here.

[0088] In the above display panel, each gating circuit 40 includes four switch units, namely, a first switch unit 410, a second switch unit 420, a third switch unit 430 and a fourth switch unit 440, and the data signal terminal Data_in is respectively connected to four data lines 20 through the four switch units, namely, the first A data line 211 and the second A data line 221 connected to the first pixel circuit column 11, and the first B data line 212 and the second B data line 222 connected to the second pixel circuit column 12, so that the four data lines 20 can share one data signal terminal Data_in, which can reduce the number of data signal terminals Data_in, provide technical support for charging the pixel circuit using dual data lines 20, help improve the charging efficiency of the pixel circuit, so as to improve the display performance of the display panel, and facilitate high-frequency display. In addition, there is no need for cross-line connection between each data line 20 and the pixel circuit, which saves space, is beneficial to display panels with high pixel density, improves the problem of crosstalk between the data line 20 and other signal lines, and improves the display effect of the display panel. In addition, the total capacitance of the data line 20 is reduced, and the pixel charging rate is improved, so that the impedance of the fan-out line can be further increased and the line width can be further compressed, which is beneficial to the narrow frame design of the display panel.

[0089] Please continue reading Figure 7 In one embodiment, in the first pixel circuit column 11, the first pixel circuit 110 is a pixel circuit for driving a first color pixel, and the second pixel circuit 120 is a pixel circuit for driving a second color pixel. In the second pixel circuit column 12, the first pixel circuit 110 and the second pixel circuit 120 are pixel circuits for driving a third color pixel, respectively. The first color, the second color, and the third color are different. In this way, by driving the pixels to emit light of different colors through the first pixel circuit 110, the second pixel circuit 120, and the third pixel circuit, the display panel can perform color display to meet the display requirements.

[0090] Please continue reading Figure 7In one embodiment, the first color pixel is a red pixel, the second color pixel is a blue pixel, and the third color pixel is a green pixel. In another embodiment, the first color pixel is a blue pixel, the second color pixel is a red pixel, and the third color pixel is a green pixel. That is, in the first pixel circuit column 11, one of the first pixel circuit 110 and the second pixel circuit 120 is a pixel circuit for driving red pixels, and the other is a pixel circuit for driving blue pixels. In the second pixel circuit column 12, the first pixel circuit 110 and the second pixel circuit 120 are pixel circuits for driving green pixels, respectively. In this way, the pixels are driven to emit three colors, namely red, green and blue, through the first pixel circuit 110, the second pixel circuit 120 and the third pixel circuit, so that the display panel can perform color display and meet the display requirements of multiple colors.

[0091] Exemplarily, in the four pixel circuit columns connected to two adjacent gating circuits 40 (for example, the first gating circuit 41 and the second gating circuit 42), the first pixel circuit column 11 and the second pixel circuit column 12 connected to the first gating circuit 41, and the first pixel circuit 110 and the second pixel circuit 120 connected to the second gating circuit 42 are arranged in sequence along the pixel circuit row direction; in the first pixel circuit column 11 connected to the first gating circuit 41, the pixel circuits located in the odd rows are the first pixel circuits 110 and are pixel circuits for driving red pixels, and are connected to the first A data line 211, and the pixel circuits located in the even rows are the second pixel circuits 120 and are pixel circuits for driving blue pixels, and are connected to the second A data line 221; in the second pixel circuit column 12 connected to the first gating circuit 41, each pixel circuit is a pixel circuit for driving green pixels, the pixel circuits located in the odd rows are the second pixel circuits 120 and are connected to the second B data line 222, and the pixel circuits located in the even rows are the first pixel circuits 110 and are connected to the first B data line 212; 2, the pixel circuits in the odd rows are the second pixel circuits 120 and are pixel circuits for driving blue pixels, and are connected to the second A data line 221, and the pixel circuits in the even rows are the first pixel circuits 110 and are pixel circuits for driving red pixels, and are connected to the first A data line 211; in the second pixel circuit column 12 connected by the second selection circuit 42, each pixel circuit is a pixel circuit for driving green pixels, the pixel circuits in the odd rows are the first pixel circuits 110 and are connected to the first B data line 212, and the pixel circuits in the even rows are the second pixel circuits 120 and are connected to the second B data line 222; in the same row, the pixel circuits of the first pixel circuit column 11 connected by the first selection circuit 41 and the pixel circuits of the second pixel circuit column 12 connected by the second selection circuit 42 have the same layout structure; in the same row, the pixel circuits of the second pixel circuit column 12 connected by the first selection circuit 41 and the pixel circuits of the first pixel circuit column 11 connected by the second selection circuit 42 have the same layout structure.

[0092] It should be noted that the above description is only based on the RGB arrangement of multiple pixels on the display panel. In other embodiments, multiple pixels may also be arranged in other ways. In addition, the shape of the light-emitting area of ​​the pixel includes but is not limited to Figure 7 The rectangle shown in FIG. 1 , in other embodiments, the shape of the light emitting area of ​​the pixel may also be designed according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0093] Fig.10 A schematic diagram of a display panel layout structure provided in an embodiment of the present application. Figures 7 to 10As shown, in one embodiment, in the first pixel circuit column 11 and the second pixel circuit column 12 connected to the same gating circuit 40, the layout structures of two adjacent pixel circuits located in the same row are mirrored along the direction of the pixel circuit column, that is, the first pixel circuit column 11 and the second pixel circuit column 12 connected to the same gating circuit 40 are symmetrical along the second central axis, wherein the second central axis is the central axis of the first pixel circuit column 11 and the second pixel circuit column 12. For example, Fig.10 As shown, in the leftmost first pixel circuit column 1111 and the adjacent second pixel circuit column 1212, the layout structure of two adjacent pixel circuits located in the same row is symmetrical along the pixel circuit column direction; in the rightmost second pixel circuit column 1212 and the adjacent first pixel circuit column 1111, the layout structure of two adjacent pixel circuits located in the same row is symmetrical along the pixel circuit column direction.

[0094] In the first pixel circuit column 11 and the second pixel circuit column 12 connected by the same selection circuit 40, the connection points between each pixel circuit in the first pixel circuit column 11 and the data line 20 and the connection points between each pixel circuit in the second pixel circuit column 12 and the data line 20 are mirror-imaged, or symmetrical along the second central axis; specifically, the first A connection point is symmetrical with the second B connection point, and the second A connection point is symmetrical with the first B connection point; wherein the first A connection point is the connection point between the first pixel circuit 110 in the first pixel circuit column 11 and the first A data line 211, the second A connection point is the connection point between the second pixel circuit 120 in the first pixel circuit column 11 and the second A data line 221, the first B connection point is the connection point between the first pixel circuit 110 in the second pixel circuit column 12 and the first B data line 212, and the second B connection point is the connection point between the second pixel circuit 120 in the second pixel circuit column 12 and the second B data line 222.

[0095] In the above-mentioned display panel, in the first pixel circuit column 11 and the second pixel circuit column 12 connected by the same gating circuit 40, the layout structure of two adjacent pixel circuits in the same row is mirrored along the direction of the pixel circuit column, so that the connection points between each pixel circuit and the data line 20 can be respectively located at the edge of the pixel circuit close to the data line 20, thereby avoiding the data line 20 from crossing the pixel circuit area to connect with the pixel circuit, avoiding the cross-line connection between the data line 20 and the pixel circuit, saving space, being beneficial to the display panel with high pixel density, improving the problem of mutual crosstalk between the data line 20 and other signal lines, and improving the display effect of the display panel. In addition, the total capacitance of the data line 20 is reduced, the pixel charging rate is improved, so that the impedance of the fan-out wiring of the display panel can be further increased, and the line width can be further compressed, which is beneficial to the narrow frame design of the display panel.

[0096] For the convenience of description, in the embodiment of the present application, the first pixel circuit 110 and the second pixel circuit 120 are collectively referred to as pixel circuits, and the first data line 21 and the second data line 22 are collectively referred to as data lines 20 . Fig.11 A schematic diagram of the internal structure of a pixel circuit provided in an embodiment of the present application. Fig.11 As shown, in one embodiment, the pixel circuit of the pixel circuit column includes a driving transistor T0, a storage capacitor Cst, a data writing transistor T1 and a threshold compensation transistor T2.

[0097] The driving transistor T0 is used to provide a driving current to the light emitting element D. The first end of the storage capacitor Cst is used to receive the first power signal pvdd. The second end of the storage capacitor Cst is connected to the gate of the driving transistor T0.

[0098] The first electrode of the data writing transistor T1 is connected to the data line 20, the second electrode of the data writing transistor T1 is connected to the first electrode of the driving transistor T0, and the gate of the data writing transistor T1 is used to receive the first scanning signal Scan1. The data writing transistor T1 is used to write the data signal VData provided by the data line 20 to the first electrode of the driving transistor T0 under the control of the first scanning signal Scan1.

[0099] The first electrode of the threshold compensation transistor T2 is respectively connected to the gate of the driving transistor T0 and the second end of the storage capacitor Cst, the second electrode of the threshold compensation transistor T2 is respectively connected to the second electrode of the driving transistor T0, and the gate of the threshold compensation transistor T2 is used to receive the first scanning signal Scan1. The threshold compensation transistor T2 is used to compensate the threshold voltage of the driving transistor T0 to the gate of the driving transistor T0 under the control of the first scanning signal Scan1. Exemplarily, the number of the threshold compensation transistors T2 can be one or more, which is not limited here.

[0100] Exemplarily, the first electrode of the data write transistor T1 in the first pixel circuit 110 is connected to the first data line 21, and the first electrode of the data write transistor T1 in the second pixel circuit 120 is connected to the second data line 22. Exemplarily, taking the selection circuit 40 as an example of the four data lines 20 of the two pixel circuit columns, in the first pixel circuit column 11, the first electrode of the data write transistor T1 in the first pixel circuit 110 is connected to the first A data line 211, and the first electrode of the data write transistor T1 in the second pixel circuit 120 is connected to the second A data line 221; in the second pixel circuit column 12, the first electrode of the data write transistor T1 in the first pixel circuit 110 is connected to the first B data line 212, and the first electrode of the data write transistor T1 in the second pixel circuit 120 is connected to the second B data line 222.

[0101] In the above display panel, the pixel circuit provides a driving current to the light-emitting element D through the driving transistor T0 to drive the light-emitting element D to emit light, and writes the data signal VData provided by the data line 20 to the first electrode of the driving transistor T0 through the data writing transistor T1, and stores the gate potential of the driving transistor T0 through the storage capacitor Cst to keep the light-emitting element D emitting light, and performs threshold compensation on the gate potential of the driving transistor T0 through the threshold compensation transistor T2 to adjust the threshold voltage of the driving transistor T0, thereby realizing the driving of the light-emitting element D by the pixel circuit, thereby realizing the display function of the display panel. In addition, the same pixel circuit column uses the first data line 21 and the second data line 22, i.e., the dual data line 20, to provide the data signal VData, which can improve the charging efficiency of the pixel circuit and help to further improve the display performance.

[0102] Fig.12 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application is shown in FIG. Fig.13 A schematic diagram of a layout structure of a semiconductor layer Poly provided in an embodiment of the present application, Fig.14 A schematic diagram of a layout structure of a first conductive layer M1 provided in an embodiment of the present application, Fig.15 A schematic diagram of the layout structure of a capacitor conductive layer MC provided in an embodiment of the present application, Fig.16 A schematic diagram of a layout structure of a second conductive layer M2 provided in an embodiment of the present application, Fig.17 A schematic diagram of a layout structure of a third conductive layer M3 provided in an embodiment of the present application, Fig.18 A schematic diagram of a layout structure of a display panel provided in an embodiment of the present application, wherein: Fig.18 for Figures 13 to 17 Schematic diagram after stacking.

[0103] Combination Figures 12 to 18 As shown, in one embodiment, the display panel includes a substrate Sub and a semiconductor layer Poly, a first conductive layer M1, a capacitor conductive layer MC, a second conductive layer M2 and a third conductive layer M3 which are sequentially away from the substrate Sub.

[0104] The pixel circuit includes an active layer. The active layer of the pixel circuit is located in the semiconductor layer Poly. The gate of the driving transistor T0, the gate of the data writing transistor T1, the gate of the threshold compensation transistor T2 and the second end of the storage capacitor Cst are respectively located in the first conductive layer M1. The first end of the storage capacitor Cst is located in the capacitor conductive layer MC. The first data line 21 and the second data line 22 are respectively located in the third conductive layer M3.

[0105] The active layer of the pixel circuit includes an active layer of a driving transistor T0, an active layer of a data writing transistor T1, and an active layer of a threshold compensation transistor T2. The first electrode and the second electrode of the driving transistor T0 are respectively connected to the active layer of the driving transistor T0. The first electrode and the second electrode of the data writing transistor T1 are respectively connected to the active layer of the data writing transistor T1. The first electrode and the second electrode of the threshold compensation transistor T2 are respectively connected to the active layer of the threshold compensation transistor T2.

[0106] In the same pixel circuit column, the active layer of the first pixel circuit 110 and the active layer of the second pixel circuit 120 are mirror images of each other along the pixel circuit column direction; that is, the active layer of the first pixel circuit 110 and the active layer of the second pixel circuit 120 are symmetrical along the pixel circuit column direction.

[0107] For example, Fig.13 As shown, in the first pixel circuit column 11 and the second pixel circuit column 12 connected to the gating circuit 40, the active layers of the two adjacent pixel circuits in the same row are mirror-imaged, or symmetrically arranged along the second central axis. Exemplarily, in the same row, the pixel circuits of the first pixel circuit column 11 connected to the first gating circuit 41 and the pixel circuits of the second pixel circuit column 12 connected to the second gating circuit 42 have the same active layers; in the same row, the pixel circuits of the second pixel circuit column 12 connected to the first gating circuit 41 and the pixel circuits of the first pixel circuit column 11 connected to the second gating circuit 42 have the same active layers.

[0108] The above-mentioned display panel is configured such that the active layer of the pixel circuit is set on the semiconductor layer Poly, and the gate of the driving transistor T0, the gate of the data writing transistor T1, the gate of the threshold compensation transistor T2 and the second end of the storage capacitor Cst are respectively set on the first conductive layer M1, and the first end of the storage capacitor Cst is set on the capacitor conductive layer MC, and the first data line 21 and the second data line 22 are respectively set on the third conductive layer M3. That is, by separating different structures in different film layers, it is beneficial to signal routing, reduces interference between signals, and can effectively utilize space, which helps to achieve a narrow frame. In addition, by setting the active layers of the first pixel circuit 110 and the second pixel circuit 120 as mirror film layers along the pixel circuit column direction, the first connection point 31 connected between the first pixel circuit 110 and the first data line 21 through the active layer can be located at the edge of the first pixel circuit 110 close to the first data line 21, and the second connection point 32 connected between the second pixel circuit 120 and the second data line 22 through the active layer can be located at the edge of the second pixel circuit 120 close to the second data line 22, thereby avoiding the data line 20 from crossing the pixel area to connect with the pixel circuit, avoiding the cross-line connection between the data line 20 and the pixel circuit, thereby improving the mutual crosstalk problem between the data line 20 and other signal lines, and thus improving the display performance. It can also reduce the total capacitance of the data line 20, improve the charging efficiency of the pixel circuit, help to further increase the impedance of the fan-out wiring of the display panel, and further compress the line width, which is conducive to the narrow frame design of the display panel.

[0109] Fig.19 A schematic diagram of the layout structure of a data line 20 provided in an embodiment of the present application. Fig.19 In one embodiment, the first data line 21 includes a first data line body 2111 and a plurality of first data signal output nodes 2112. In the same first data line 21, each first data signal output node 2112 is respectively connected to the first data line body 2111. The second data line 22 includes a second data line body 2211 and a plurality of second data signal output nodes 2212. In the same second data line 22, each second data signal output node 2212 is respectively connected to the second data line body 2211.

[0110] Exemplarily, for any pixel circuit column, the number of the first data signal output nodes 2112 of the first data line 21 connected thereto and the second data signal output nodes 2212 of the second data line 22 are the same, and are the same as the number of pixel circuits in the pixel circuit column. It should be noted that the first data line body 2111 and the second data line body 2211 can be respectively linear, the first data signal output node 2112 and the second data signal output node 2212 can be respectively cylindrical, and each body and each node can also be any other suitable shape, which is not limited too much here.

[0111] The first data signal output node 2112 is connected to the first data signal VData input node in the first pixel circuit 110 through the first via hole. The first data signal VData input node is located in the active layer of the first pixel circuit 110, and the first data signal VData input node is located at the edge of the active layer of the first pixel circuit 110 close to the first data line 21. The active layer of the first pixel circuit 110 is connected to the first electrode of the data writing transistor T1 in the first pixel circuit 110, so the first data line 21 is connected to the first electrode of the data writing transistor T1 in the first pixel circuit 110 through the first data signal VData node, the first via hole, the first data signal VData input node and the active layer of the first pixel circuit 110, so that the connection between the first pixel circuit 110 and the first data line 21 is realized. Among them, the first connection point 31 between the first pixel circuit 110 and the first data line 21 can be understood as a connection structure composed of the first data signal output node 2112, the first via hole and the first data signal VData input node.

[0112] The second data signal output node 2212 is connected to the second data signal VData input node in the second pixel circuit 120 through the second via hole. The second data signal VData input node is located in the active layer of the second pixel circuit 120, and the second data signal VData input node is located at the edge of the active layer of the second pixel circuit 120 close to the second data line 22. The active layer of the second pixel circuit 120 is connected to the first electrode of the data writing transistor T1 in the second pixel circuit 120, so that the second data line 22 is connected to the first electrode of the data writing transistor T1 in the second pixel circuit 120 through the second data signal VData node, the second via hole, the second data signal VData input node and the active layer of the second pixel circuit 120, thereby realizing the connection between the second pixel circuit 120 and the second data line 22. The second connection point 32 between the second pixel circuit 120 and the second data line 22 can be understood as a connection structure composed of the second data signal output node 2212, the second via hole and the second data signal VData input node.

[0113] It can be understood that the data line 20 and the active layer of the pixel circuit are located in different film layers. Therefore, the embodiment of the present application connects the data signal VData output node and the data signal VData input node through a via, thereby realizing the connection between the data line 20 and the data writing transistor T1 in the pixel circuit. Among them, the number of first vias is the same as the number of correspondingly connected first pixel circuits 110, and the number of second vias is the same as the number of correspondingly connected second pixel circuits 120. The shapes of the first via and the second via can be cylindrical or any other suitable structure, which can be specifically set according to the actual scenario and is not limited too much here.

[0114] In the above-mentioned display panel, the first data line 21 is connected to the first data signal output node 2112 through the first data line body 2111, and is connected to the first data signal VData input node in the first pixel circuit 110 through the first data signal output node 2112 via the first via hole, and is connected to the active layer of the first pixel circuit 110 through the first data signal VData input node, thereby realizing the connection between the first data line 21 and the first pixel circuit 110, and because the first data signal VData input node is located at the edge of the active layer of the first pixel circuit 110 close to the first data line 21, there is no need for a cross-line connection between the first data line 21 and the first pixel circuit 110, thereby avoiding mutual crosstalk between the first data line 21 and other signal lines, and reducing the total capacitance of the first data line 21; similarly, the second data line 22 is connected to the second data signal output node 2212 through the second data line body 2211, and is connected to the first data signal VData input node through the second data line body 2212. The data signal output node 2212 is connected to the second data signal VData input node in the second pixel circuit 120 through the second via hole, and is connected to the active layer of the second pixel circuit 120 through the second data signal VData input node, thereby realizing the connection between the second data line 22 and the second pixel circuit 120, and since the second data signal VData input node is located at the edge of the active layer of the second pixel circuit 120 close to the second data line 22, there is no need for a cross-line connection between the second data line 22 and the second pixel circuit 120, thereby avoiding mutual crosstalk between the second data line 22 and other signal lines, reducing the total capacitance of the second data line 22, thereby improving the problem of mutual crosstalk between the data line 20 and other signal lines, improving the display effect, reducing the total capacitance of the data line 20, and improving the pixel charging rate, so that the impedance of the fan-out routing of the display panel can be further increased, and the line width can be further compressed, which is beneficial to the narrow frame design of the display panel.

[0115] Please continue reading Fig.19In one embodiment, the first data signal output node 2112 is located on a side of the first data line body 2111 close to the target pixel circuit column, and the second data signal output node 2212 is located on a side of the second data line body 2211 close to the target pixel circuit column, wherein the target pixel circuit column is connected to the first data signal output node 2112 and the second data signal output node 2212 respectively. The target pixel circuit column is any pixel circuit column in the display panel. In this way, the connection length between the data line 20 and the pixel circuit can be shortened as much as possible, the possibility of crosstalk between the data line 20 and other signal lines is greatly reduced, and the total capacitance of the data line 20 is reduced, which is conducive to the design of display panels with narrow borders, high-frequency display and high pixel density.

[0116] Exemplarily, the first data line 21 and the second data line 22 of the same pixel circuit column are respectively located on both sides of the pixel circuit column, wherein each first data signal output node 2112 is respectively located on one side of the first data line body 2111 close to the pixel circuit column, and each second data signal output node 2212 is respectively located on one side of the second data line body 2211 close to the pixel circuit column. Fig.19 As shown, the first data line 21 connected to the same pixel circuit column is located on the left side of the pixel circuit column, and the second data line 22 is located on the right side of the pixel circuit column, wherein the first data signal output node 2112 is located on the right side of the first data line body 2111 close to the pixel circuit column, and the second data signal output node 2212 is located on the left side of the second data line body 2211 close to the pixel circuit column.

[0117] It should be noted that the above is only an exemplary description. In the application, the relative position relationship between the first data signal output node 2112 and the second data signal output node 2212 and the target pixel circuit column can be determined according to the layout of the pixel circuit column, the first data line 21 and the second data line 22 in the display panel, and is not excessively limited here.

[0118] Please continue reading Fig.19 In one embodiment, the first distance d1 between the first data line body 2111 and the first data signal output node 2112 is the same as, or similar to, the second distance d2 between the second data line body 2211 and the second data signal output node 2212. The first distance d1 and the second distance d2 are respectively smaller than the width of the pixel circuit in the row direction of the pixel circuit. It should be noted that due to other factors such as process preparation accuracy, the first distance d1 and the second distance d2 may be different in the actual manufacturing process, but the error between the first distance d1 and the second distance d2 is less than the set distance threshold, and they can also be regarded as the same. Combined with Figure 2As shown, in the display panel of the related art, among the two data lines 20 connected to the same pixel circuit column, the distance between the main body of one data line 20 and the data signal VData output node connected thereto is greater than the width of the pixel circuit in the pixel circuit row direction.

[0119] Combined with the above comparison, it can be seen that the display panel provided by the embodiment of the present application shortens the distance between the data signal VData output node and the main body of the data line 20, avoids the main body of the data line 20 crossing the pixel circuit to connect with the corresponding data signal VData output node, that is, avoids the cross-line connection between the data line 20 and the pixel circuit, saves space, is conducive to narrow frame and high pixel density display panel, and reduces the coupling capacitance between the data line 20 and other signal lines in the display panel, improves the problem of mutual crosstalk between the data line 20 and other signal lines, and improves the display effect of the display panel. In addition, the total capacitance of the data line 20 is also reduced, the pixel charging rate is improved, so that the impedance of the display panel fan-out line can be further increased, and the line width can be further compressed, which is conducive to the narrow frame design of the display panel.

[0120] Please continue reading Figures 11 to 19 In one embodiment, the pixel circuit further includes a first initialization transistor T3, a second initialization transistor T4, a first light emission control transistor T5 and a second light emission control transistor T6.

[0121] The first electrode of the first initialization transistor T3 is used to receive the first initialization signal Vref1. The second electrode of the first initialization transistor T3 is respectively connected to the gate of the driving transistor T0, the second end of the storage capacitor Cst and the first electrode of the threshold compensation transistor T2. The gate of the first initialization transistor T3 is used to receive the second scan signal Scan2. The first initialization transistor T3 is used to initialize the gate potential of the driving transistor T0 using the first initialization signal Vref1 under the control of the second scan signal Scan2. Among them, the first electrode and the second electrode of the first initialization transistor T3 are respectively connected to the active layer of the first initialization transistor T3, the active layer of the first initialization transistor T3 is located in the semiconductor layer Poly, and the gate of the first initialization transistor T3 is located in the first conductive layer M1. The number of the first initialization transistors T3 can be one or more, and the appropriate number can be selected according to the actual scenario, which is not limited here.

[0122] The first electrode of the second initialization transistor T4 is used to receive the second initialization signal Vref2. The second electrode of the second initialization transistor T4 is connected to the anode of the light-emitting element D. The gate of the second initialization transistor T4 is used to receive the first scan signal Scan1. The second initialization transistor T4 is used to initialize the anode potential of the light-emitting element D using the second initialization signal Vref2 under the control of the first scan signal Scan1. The first electrode and the second electrode of the second initialization transistor T4 are respectively connected to the active layer of the second initialization transistor T4, the active layer of the second initialization transistor T4 is located in the semiconductor layer Poly, and the gate of the second initialization transistor T4 is located in the first conductive layer M1.

[0123] The first electrode of the first light-emitting control transistor T5 is used to receive the first power supply signal pvdd. The first electrode of the first light-emitting control transistor T5 is connected to the first end of the storage capacitor Cst. The second electrode of the first light-emitting control transistor T5 is respectively connected to the first electrode of the driving transistor T0 and the first electrode of the data writing transistor T1. The gate of the first light-emitting control transistor T5 is used to receive the light-emitting control signal Emit. The first light-emitting control transistor T5 is used to control the light-emitting element D to emit light under the control of the light-emitting control signal Emit. Among them, the first electrode and the second electrode of the first light-emitting control transistor T5 are respectively connected to the active layer of the first light-emitting control transistor T5, the active layer of the first light-emitting control transistor T5 is located in the semiconductor layer Poly, and the gate of the first light-emitting control transistor T5 is located in the first conductive layer M1.

[0124] The first electrode of the second light emitting control transistor T6 is respectively connected to the second electrode of the driving transistor T0 and the second electrode of the threshold compensation transistor T2. The second electrode of the second light emitting control transistor T6 is respectively connected to the anode of the light emitting element D and the second electrode of the second initialization transistor T4. The gate of the second light emitting control transistor T6 is used to receive the light emitting control signal Emit. The second light emitting control transistor T6 is used to control the light emitting element D to emit light under the control of the light emitting control signal Emit. The first electrode and the second electrode of the second light emitting control transistor T6 are respectively connected to the active layer of the second light emitting control transistor T6, the active layer of the second light emitting control transistor T6 is located in the semiconductor layer Poly, and the gate of the second light emitting control transistor T6 is located in the first conductive layer M1.

[0125] The cathode of the light emitting element D is used to receive the second power signal pvss. The light emitting element D is used to emit light under the action of the driving current. Wherein, the first power signal pvdd and the second power signal pvss are different.

[0126] Each transistor in the pixel circuit may be a low temperature polycrystalline silicon (LTPS) thin film transistor Tx, or a low temperature polycrystalline oxide (LTPO) thin film transistor Ty, specifically, indium gallium zinc oxide (IGZO). For example, Fig.11 In the pixel circuit shown, the threshold compensation transistor T2 and the first initialization transistor T3 may be LTPO thin film transistors Ty, and other transistors may be LTPS thin film transistors Tx.

[0127] It should be noted that the pixel circuit provided above is a 7T1C structure. In applications, the pixel circuit may be of other structural types, such as 8T1C, 9T1C, etc. The appropriate type may be selected according to the actual scenario, and no further limitations are made here.

[0128] The display panel further includes a first power signal line PVDD, a first scan signal line S1, a second scan signal line S2, a first initialization signal line V1, a second initialization signal line V2, and a light emission control signal line EM.

[0129] The first power signal line PVDD is used to output the first power signal pvdd. The first power signal line PVDD is located in the second conductive layer M2. The first power signal line PVDD is connected to the first end of the storage capacitor Cst and the active layer of the first light-emitting control transistor T5, respectively. The active layer of the first light-emitting control transistor T5 is connected to the first electrode of the first light-emitting control transistor T5, so that the first power signal line PVDD is connected to the first electrode of the first light-emitting control transistor T5 through the active layer of the first light-emitting control transistor T5, so as to provide the first power signal pvdd to the first electrode of the first light-emitting control transistor T5. Exemplarily, the first power signal line PVDD extends along the column direction of the pixel circuit and is arranged along the row direction of the pixel circuit.

[0130] The first scan signal line S1 is used to output the first scan signal Scan1. The first scan signal line S1 is located in the first conductive layer M1. The first scan signal line S1 is respectively connected to the gate of the data writing transistor T1, the gate of the threshold compensation transistor T2, and the gate of the second initialization transistor T4, thereby providing the first scan signal Scan1 to the gate of the data writing transistor T1, the gate of the threshold compensation transistor T2, and the gate of the second initialization transistor T4. Exemplarily, the first scan signal line S1 is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0131] The second scan signal line S2 is used to output a second scan signal Scan2. The second scan signal line S2 is located in the first conductive layer M1. The second scan signal line S2 is connected to the gate of the first initialization transistor T3, thereby providing the second scan signal Scan2 to the gate of the first initialization transistor T3. Exemplarily, the second scan signal line S2 is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0132] The first initialization signal line V1 is used to output the first initialization signal Vref1. The first initialization signal line V1 is located in the capacitor conductive layer MC. The first initialization signal line V1 is connected to the active layer of the first initialization transistor T3, so that the first initialization signal line V1 is connected to the first electrode of the first initialization transistor T3 through the active layer of the first initialization transistor T3, thereby providing the first initialization signal Vref1 to the first electrode of the first initialization transistor T3. Exemplarily, the first initialization signal line V1 is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0133] The second initialization signal line V2 is used to output the second initialization signal Vref2. The second initialization signal line V2 is located in the capacitor conductive layer MC. The second initialization signal line V2 is connected to the active layer of the second initialization transistor T4, so that the second initialization signal line V2 is connected to the first electrode of the second initialization transistor T4 through the active layer of the second initialization transistor T4, thereby providing the second initialization signal Vref2 to the first electrode of the second initialization transistor T4. Exemplarily, the second initialization signal line V2 is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0134] The light emitting control signal line EM is used to output the light emitting control signal Emit. The light emitting control signal line EM is located in the first conductive layer M1. The light emitting control signal line EM is connected to the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6 respectively. Exemplarily, the light emitting control signal line EM is arranged along the column direction of the pixel circuit and extends along the row direction of the pixel circuit.

[0135] It should be noted that the above is only an exemplary description. In applications, the display panel can be provided with signal lines corresponding to the signal requirements of the pixel circuit, and this is not limited here.

[0136] The above-mentioned display panel, by further providing the pixel circuit with a first initialization transistor T3, a second initialization transistor T4, a first light-emitting control transistor T5 and a second light-emitting control transistor T6, and correspondingly providing the first power signal line PVDD, the first scanning signal line S1, the second scanning signal line S2, the first initialization signal line V1, the second initialization signal line V2 and the light-emitting control signal line EM in the display panel, enables the display panel to drive the light-emitting element D to emit light through the pixel circuit of the 7T1C structure, thereby providing technical support for the display function of the display panel and improving the display performance compared with the pixel circuit of the 2T1C structure and the like in the related technology.

[0137] Based on the same application concept, the embodiment of the present application also provides a display screen. Fig. 20 A schematic diagram of the cross-sectional structure of a display screen 1000 provided in an embodiment of the present application is shown in FIG. Fig. 20 As shown, the display screen 1000 includes a cover plate 1200 and a display panel 1100 in any of the above embodiments. The cover plate 1200 is located on the surface of the display panel 1100 in the light emitting direction, that is, the cover plate 1200 is located on the light emitting side of the display panel 1100. Therefore, the display screen 1000 also has the beneficial effects of the display panel 1100 in the above embodiments, and the similarities can be understood by referring to the above explanation of the display panel 1100, which will not be repeated below.

[0138] Based on the same application concept, an embodiment of the present application also provides a display device. Fig.21 A schematic diagram of a top view of a display device provided in an embodiment of the present application is shown in FIG. Fig.21 As shown, the display device 10000 includes the display screen 1000 in any of the above embodiments. Fig.21 As shown, the display device 10000 includes a display screen 1000, and the display screen 1000 includes a cover plate 1200 and a display panel 1100 in any of the above embodiments. Therefore, the display device 10000 also has the beneficial effects of the display panel 1100 in the above embodiments, and the similarities can be understood by referring to the above explanation of the display panel 1100, which will not be repeated below.

[0139] The display device provided in the embodiment of the present application can be Fig.21 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0140] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: include: A plurality of pixel circuit columns, a plurality of first data lines and a plurality of second data lines, wherein the pixel circuit column is provided with one first data line and one second data line; wherein, The pixel circuit column includes a plurality of first pixel circuits and a plurality of second pixel circuits. In the same pixel circuit column, each of the first pixel circuits is connected to the first data line, each of the second pixel circuits is connected to the second data line, and the layout structures of the first pixel circuits and the second pixel circuits are mirror images of each other along the direction of the pixel circuit column. A first connection point between the first pixel circuit and the first data line is located at an edge of the first pixel circuit close to the first data line, and a second connection point between the second pixel circuit and the second data line is located at an edge of the second pixel circuit close to the second data line.

2. The display panel according to claim 1, characterized in that: The display panel also includes a gating circuit, and the first data line and the second data line connected to at least one pixel circuit column are connected to a data signal terminal via the gating circuit. The gating circuit is used to transmit the data signal provided by the data signal terminal to the first data line and the second data line connected to the gating circuit in a time-sharing manner.

3. The display panel according to claim 2, characterized in that: The plurality of pixel circuit columns include a plurality of first pixel circuit columns and a plurality of second pixel circuit columns, and the first pixel circuit columns and the second pixel circuit columns are alternately arranged; The four data lines connected to the first pixel circuit column and the second pixel circuit column are connected to the data signal end via the gating circuit, and the gating circuit is used to transmit the data signal provided by the data signal end to the four data lines connected to the gating circuit in a time-sharing manner.

4. The display panel according to claim 3, characterized in that: The plurality of first data lines include a plurality of first A data lines and a plurality of first B data lines, and the plurality of second data lines include a plurality of second A data lines and a plurality of second B data lines; the gating circuit includes a first switch unit, a second switch unit, a third switch unit and a fourth switch unit; The first A data line and the second A data line are respectively connected to the same first pixel circuit column, and the first B data line and the second B data line are respectively connected to the same second pixel circuit column; The first ends of the first switch unit, the second switch unit, the third switch unit and the fourth switch unit are respectively connected to the data signal end, the second end of the first switch unit is connected to the first A data line, the second end of the second switch unit is connected to the second A data line, the second end of the third switch unit is connected to the first B data line, and the second end of the fourth switch unit is connected to the second B data line, and the control ends of the first switch unit, the second switch unit, the third switch unit and the fourth switch unit are respectively used to receive different control signals.

5. The display panel according to claim 3, characterized in that: The plurality of first data lines include a plurality of first A data lines and a plurality of first B data lines, and the plurality of second data lines include a plurality of second A data lines and a plurality of second B data lines; The first A data line and the second A data line are respectively connected to the same first pixel circuit column, and the first B data line and the second B data line are respectively connected to the same second pixel circuit column; wherein, The first A data line and the second B data line are symmetrically arranged, and the second A data line and the first B data line are symmetrically arranged.

6. The display panel according to claim 3, characterized in that: In the first pixel circuit column, the first pixel circuit is a pixel circuit for driving a first color pixel, and the second pixel circuit is a pixel circuit for driving a second color pixel; In the second pixel circuit column, the first pixel circuit and the second pixel circuit are pixel circuits for driving third color pixels respectively.

7. The display panel according to claim 6, characterized in that: The first color pixel is a red pixel, the second color pixel is a blue pixel, and the third color pixel is a green pixel.

8. The display panel according to claim 3, characterized in that: In the first pixel circuit column and the second pixel circuit column connected to the same gating circuit, the layout structures of two adjacent pixel circuits located in the same row are mirror-imaged along the direction of the pixel circuit column.

9. The display panel according to any one of claims 1 to 8, characterized in that: The pixel circuit of the pixel circuit column comprises: A driving transistor, used for providing a driving current to the light emitting element; A storage capacitor, wherein a first end of the storage capacitor is used to receive a first power supply signal, and a second end of the storage capacitor is connected to the gate of the driving transistor; a data writing transistor, wherein a first electrode of the data writing transistor is connected to the data line, a second electrode of the data writing transistor is connected to the first electrode of the driving transistor, and a gate of the data writing transistor is used to receive a first scanning signal; A threshold compensation transistor, wherein the first electrode of the threshold compensation transistor is respectively connected to the gate of the driving transistor and the second end of the storage capacitor, the second electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor, and the gate of the threshold compensation transistor is used to receive the first scanning signal.

10. The display panel according to claim 9, characterized in that: The display panel includes a substrate and a semiconductor layer, a first conductive layer, a capacitor conductive layer, a second conductive layer and a third conductive layer which are sequentially away from the substrate; wherein, The pixel circuit comprises an active layer, the active layer of the pixel circuit is located in the semiconductor layer, the gate of the driving transistor, the gate of the data writing transistor, the gate of the threshold compensation transistor and the second end of the storage capacitor are respectively located in the first conductive layer, the first end of the storage capacitor is located in the capacitor conductive layer, and the first data line and the second data line are respectively located in the third conductive layer; In the same pixel circuit column, the active layer of the first pixel circuit and the active layer of the second pixel circuit are mirror images of each other along the direction of the pixel circuit column.

11. The display panel according to claim 10, characterized in that: The first data line includes a connected first data line body and a plurality of first data signal output nodes, and the second data line includes a connected second data line body and a plurality of second data signal output nodes; The first data signal output node is connected to a first data signal input node in the first pixel circuit through a first via hole, and the first data signal input node is located at an edge of the active layer of the first pixel circuit close to the first data line; The second data signal output node is connected to a second data signal input node in the second pixel circuit through a second via hole, and the second data signal input node is located at an edge of the active layer of the second pixel circuit close to the second data line.

12. The display panel according to claim 11, characterized in that: The first data signal output node is located on a side of the first data line body close to the target pixel circuit column, and the second data signal output node is located on a side of the second data line body close to the target pixel circuit column, wherein the target pixel circuit column is connected to the first data signal output node and the second data signal output node respectively.

13. The display panel according to claim 11, characterized in that: A first distance between the first data line body and the first data signal output node is the same as a second distance between the second data line body and the second data signal output node.

14. The display panel according to claim 10, characterized in that: The display panel further includes a first power signal line, a first scan signal line, a second scan signal line, a first initialization signal line, a second initialization signal line and a light emission control signal line; the pixel circuit further includes a first initialization transistor, a second initialization transistor, a first light emission control transistor and a second light emission control transistor; wherein, The first power signal line is used to output the first power signal, the first power signal line is located in the second conductive layer, and the first power signal line is connected to the first end of the storage capacitor; The first scanning signal line is used to output the first scanning signal, the first scanning signal line is located in the first conductive layer, and the first scanning signal line is respectively connected to the gate of the data writing transistor, the gate of the threshold compensation transistor, and the gate of the second initialization transistor; The second scanning signal line is used to output a second scanning signal, the second scanning signal line is located in the first conductive layer, and the second scanning signal line is connected to the gate of the first initialization transistor; The first initialization signal line is used to output a first initialization signal, the first initialization signal line is located in the capacitor conductive layer, and the first initialization signal line is connected to the active layer of the first initialization transistor; The second initialization signal line is used to output a second initialization signal; the second initialization signal line is located in the capacitor conductive layer, and the second initialization signal line is connected to the active layer of the second initialization transistor; The light-emitting control signal line is used to output a light-emitting control signal; the light-emitting control signal line is located in the first conductive layer, and the light-emitting control signal line is respectively connected to the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor; The first electrode of the first initialization transistor is used to receive the first initialization signal, the second electrode of the first initialization transistor is connected to the gate of the driving transistor, and the gate of the first initialization transistor is used to receive the second scanning signal; The first electrode of the second initialization transistor is used to receive the second initialization signal, the second electrode of the second initialization transistor is connected to the anode of the light-emitting element, and the gate of the second initialization transistor is used to receive the first scanning signal; The first electrode of the first light emitting control transistor is used to receive the first power supply signal, the second electrode of the first light emitting control transistor is connected to the first electrode of the driving transistor, and the gate of the first light emitting control transistor is used to receive the light emitting control signal; The first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, the second electrode of the second light-emitting control transistor is connected to the anode of the light-emitting element, and the gate of the second light-emitting control transistor is used to receive the light-emitting control signal; wherein, The gates of the first initialization transistor, the second initialization transistor, the first light emission control transistor and the second light emission control transistor are respectively located in the first conductive layer.

15. A display screen, characterized in that: It comprises a cover plate and the display panel according to any one of claims 1 to 14, wherein the cover plate is located on a surface of the display panel in a light emitting direction.

16. A display device, characterized in that: Comprising the display screen as claimed in claim 15.

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