Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises at least two display subareas, the at least two display subareas comprise a first display subarea and a second display subarea, and the first display subarea and the second display subarea are adjacent in the direction perpendicular to a data line; the at least two display partitions respectively comprise a plurality of pixel circuit groups; the display panel further comprises a first scanning circuit, a plurality of first scanning lines and a plurality of first gating circuits. The first scanning circuits are correspondingly and electrically connected with the first scanning lines through the first gating circuits, and the first scanning lines are connected with the corresponding pixel circuit groups; the first gating circuit is used for gating or turning off the first scanning line and the first scanning circuit, and is also used for transmitting a turn-off level signal to the first scanning line. According to the invention, partitioned multi-frequency display of the transverse region can be realized.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) and flat display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream of display devices. However, current display panels cannot achieve multi-frequency display in horizontal areas. Summary of the invention

[0003] The present invention provides a display panel and a display device, which can realize partitioned multi-frequency display in a horizontal area.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising at least two display partitions, wherein the at least two display partitions include a first display partition and a second display partition, and the first display partition and the second display partition are adjacent to each other in a direction perpendicular to a data line; the at least two display partitions respectively include a plurality of pixel circuit groups; the display panel also includes a first scanning circuit, a plurality of first scanning lines and a plurality of first gating circuits; the first scanning circuit is electrically connected to the first scanning line through the first gating circuit, and the first scanning line is connected to the corresponding pixel circuit group; the first gating circuit is used to turn on or off the first scanning line and the first scanning circuit, and is also used to transmit an off-level signal to the first scanning line.

[0005] In a second aspect, an embodiment of the present invention provides a display device, including the display panel provided by any embodiment of the present invention.

[0006] The display panel provided by the embodiment of the present invention includes a plurality of first gating circuits, which are respectively connected to the first scanning circuit and the first scanning line. The first input end of the first gating circuit receives the scanning signal output by the first scanning circuit, and the second input end is connected to the off-level signal. By responding to the signal on the gating signal line, the first gating circuit can determine the connection state between the first scanning circuit and the first scanning line. When the first gating circuit is turned on, the scanning signal is transmitted to the pixel circuit, prompting the pixel switch state to change; when the first gating circuit is turned off, the scanning signal is blocked, or the shift register cannot generate the scanning signal, and the pixel circuit cannot receive the scanning signal. In different display partitions, the gating signals received by the first gating circuit are different, thereby realizing differentiated control of the transmission of scanning signals in different partitions. For example, at certain moments, the first gating circuit of the first display partition is turned off, and the pixel circuit of the partition does not receive the scanning signal, while the first gating circuit of the second display partition is turned on, and its pixel circuit normally receives the scanning signal, so that the refresh frequency of the two partitions is different. Each display partition includes a plurality of pixel circuit groups, and the pixel circuits in the pixel circuit group control the display state of the pixel according to the scanning signal transmitted by the first scanning line. Due to the control of the first gating circuit on the transmission of the scanning signal, the pixel circuits of different partitions receive the scanning signal at different frequencies. When the first gating circuit of the first display partition is turned off during a specific period of time, the pixel circuit of the partition cannot receive the scanning signal and does not perform data writing operations; while the first gating circuit of the second display partition is in the on state, its pixel circuit can normally receive the scanning signal and write data, ultimately making different display partitions present different refresh frequencies, realizing partition multi-frequency display in the horizontal area.

[0007] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0010] Figure 2 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0011] Figure 3is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0012] Figure 4 is a waveform diagram of a signal transmitted on a first selection signal line and a second selection signal line provided by an embodiment of the present invention;

[0013] Figure 5 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 6 is a structural schematic diagram of a second gating circuit provided by an embodiment of the present invention;

[0015] Figure 7 is a structural schematic diagram of another second gating circuit provided by an embodiment of the present invention;

[0016] Figure 8 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0017] Fig. 9 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0018] Fig.10 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0021] As described in the background technology, the existing display panel cannot realize the partitioned multi-frequency display in the horizontal area. The inventors have found that the reason for the above problem is that the display panel often adopts the method of longitudinal partitioned multi-frequency to reduce the power consumption of the screen body, usually by controlling the output of the gate drive (GIP) circuit integrated in the control panel, so that the frequency output of the GIP circuit in different areas is inconsistent, so as to achieve inconsistent refresh rates at different positions of the screen body, but according to this principle, it is impossible to effectively realize the partitioned multi-frequency of the horizontal area.

[0022] In order to solve the above technical problem, an embodiment of the present invention provides a display panel. Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 1 As shown, the display panel includes at least two display partitions, the at least two display partitions include a first display partition AA1 and a second display partition AA2, and the first display partition AA1 and the second display partition AA2 are adjacent to each other along a direction X perpendicular to the data line. The at least two display partitions respectively include a plurality of pixel circuit groups 10; the display panel also includes a first scanning circuit 11, a plurality of first scanning lines GL1, and a plurality of first gating circuits 12.

[0023] The first scanning circuit 11 is electrically connected to the first scanning line GL1 through the first gating circuit 12, and the first scanning line GL1 is connected to the corresponding pixel circuit group 10; the first gating circuit 12 is used to turn on or off the first scanning line GL1 and the first scanning circuit 11, and is also used to transmit the shutdown level signal VGH to the first scanning line GL1.

[0024] Specifically, the pixel circuit group 10 includes a plurality of columns of pixel circuits PX, and the pixel circuits PX may have the structure of any existing pixel driving circuit. The first scanning circuit 11 may include a plurality of cascaded shift registers 111, and each stage of the shift register 111 may be connected to a first scanning line GL1 through a corresponding first gating circuit 12, and the first scanning line GL is connected to a functional module in one or more columns of the pixel circuits PX, for example, a functional module in the pixel circuit PX for controlling the gate of the driving transistor for initialization.

[0025] The first scanning circuit 11 is used to output a first scanning signal according to at least an input signal and a clock signal, and the first scanning signal is transmitted to the first scanning line GL1 through the first gating circuit 12. The first scanning line GL1 is used to transmit the first scanning signal generated by the first scanning circuit 11 to the pixel circuit group 10, so as to control the switching state of the pixel and realize the row-by-row display of the image. Exemplarily, when the display panel includes multiple rows of pixel circuits PX, multiple shift registers in each first scanning circuit 11 are cascaded. Multiple cascaded shift registers 111 respectively provide the first scanning signal to at least one column of pixel circuits PX through the corresponding first gating circuit 12. Among them, the input signal of the first-stage shift register 111 may include the input signal provided by the driving chip to the start signal line STV, and the input signal of the other-stage shift registers 111 may be the scanning signal output by the previous-stage shift register 111.

[0026] The first scanning signal output by the first scanning circuit 11 may include an effective level and an ineffective level, wherein the effective level is a level for controlling the conduction of a functional module in the pixel circuit, and the ineffective level is a level for controlling the shutoff of a functional module in the pixel circuit. The effective level may be a high level, and the ineffective level may be a low level; or, the effective level may be a low level, and the ineffective level may be a high level. The embodiments of the present invention are all described by taking the ineffective level as a high level and the effective level as a low level as an example. Optionally, the ineffective level is the same as the shutoff level signal VGH.

[0027] The first gating circuit 12 includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first gating circuit 12 is connected to the output terminal of the first scanning circuit 11 to receive the first scanning signal output by the first scanning circuit 11. The second input terminal of the first gating circuit 12 is connected to the off-level signal VGH. When the first input terminal of the first gating circuit 12 is connected to the output terminal, the first scanning signal is transmitted to the corresponding first scanning line GL1 through the output terminal of the first gating circuit 12. When the second input terminal of the first gating circuit 12 is connected to the output terminal, the off-level signal VGH is transmitted to the corresponding first scanning line GL1 through the output terminal of the first gating circuit 12. The off-level signal VGH is the cut-off potential of the functional module connected to the first scanning signal in the pixel circuit. The functional module is, for example, a functional module that controls the data voltage writing process of the gate of the driving transistor in the pixel circuit. When realizing the multi-frequency display of the horizontal area partition, the first gating circuits 12 of different display partitions work according to the signal on the gating signal line. When it is necessary to stop the pixel writing data voltage of a certain partition to achieve different refresh frequencies, the first selection circuit 12 transmits the off-level signal VGH to the first scan line GL1. This operation cuts off the transmission of the first scan signal, so that the pixel circuit of the corresponding partition cannot receive the first scan signal and does not write data, thereby generating a difference in refresh frequency with other partitions, and realizing partition multi-frequency display. In addition, during the switching process of the connection state between the first scan circuit 11 and the first scan line GL1, there may be residual first scan signals. If these residual signals are not processed, they may interfere with the normal operation of the pixel circuit, resulting in noise, ghosting and other problems in the display. Transmitting the off-level signal VGH to the first scan line GL1 can effectively cover the possible residual first scan signal, so that the level on the first scan line GL1 is in a certain off state. In this way, the residual scan signal can be avoided from false triggering of the pixel circuit, the clarity and stability of the displayed picture can be ensured, and the overall performance of the display panel can be improved.

[0028] The first scanning circuit 11 is electrically connected to the first scanning line GL1 through the first gating circuit 12. The first gating circuit 12 is responsible for gating or shutting off the first scanning line GL1 and the first scanning circuit 11, and transmitting the shutoff level signal VGH. When the first input end of the first gating circuit 12 is connected to its output end, the first scanning signal can be transmitted to the pixel circuit PX to control the switching state of the pixel; when the first input end of the first gating circuit 12 is disconnected from its output end, the first scanning signal is blocked or the pixel circuit PX cannot receive the first scanning signal. In this way, the first gating circuits 12 of different display partitions can realize differentiated control of the transmission of the first scanning signal according to the different gating signals, thereby making the refresh frequencies of different display partitions different.

[0029] Each display partition includes a plurality of pixel circuit groups 10, and the pixel circuits PX in the pixel circuit groups control the display state of the pixels according to the first scan signal transmitted by the first scan line GL1. Due to the control of the first scan signal by the first gating circuit 12, the pixel circuits PX in different partitions receive the first scan signal at different frequencies, thereby achieving different refresh frequencies. For example, when the first gating circuit 12 of the first display partition AA1 is turned off at certain moments, the pixel circuit PX of the first display partition AA1 cannot receive the first scan signal and does not write data, while the first gating circuit 12 of the second display partition AA2 is turned on, and its pixel circuit PX normally receives the first scan signal and writes data, so that the refresh frequencies of the first display partition AA1 and the second display partition differ.

[0030] The display panel provided by the embodiment of the present invention includes a plurality of first gating circuits, which are respectively connected to the first scanning circuit and the first scanning line. The first input end of the first gating circuit receives the first scanning signal output by the first scanning circuit, and the second input end is connected to the off-level signal. The first gating circuit is responsible for gating or shutting off the first scanning line and the first scanning circuit, and transmitting the off-level signal. When the first input end of the first gating circuit is connected to its output end, the first scanning signal is transmitted to the pixel circuit, causing the pixel switch state to change; when the first input end of the first gating circuit is disconnected from its output end, the first scanning signal is blocked, and the pixel circuit cannot receive the first scanning signal. In different display partitions, the gating signals received by the first gating circuit are different, thereby realizing differentiated control of the transmission of scanning signals in different partitions. For example, at certain moments, the first gating circuit of the first display partition is turned off, and the pixel circuit of the partition does not receive the first scanning signal, while the first gating circuit of the second display partition is turned on, and its pixel circuit normally receives the first scanning signal, so that the refresh frequencies of the two partitions are different. Each display partition includes multiple pixel circuit groups, and the pixel circuits in the pixel circuit group control the display state of the pixel according to the first scanning signal transmitted by the first scanning line. Due to the control of the first selection circuit on the transmission of the first scanning signal, the pixel circuits in different partitions receive the first scanning signal at different frequencies. When the first input end and the output end of the first selection circuit of the first display partition are turned off during a specific period of time, the pixel circuit of the partition cannot receive the first scanning signal and does not perform data writing operations; while the first input end and the output end of the first selection circuit of the second display partition are in a conducting state, and its pixel circuit can normally receive the scanning signal and write data, which ultimately makes different display partitions present different refresh frequencies, realizing partition multi-frequency display in the horizontal area.

[0031] Optionally, continue to refer to Figure 1The display panel further includes a plurality of clock signal lines and a driving chip, wherein the driving chip is connected to the first scanning circuit 11 through the clock signal lines to output a clock signal to the first scanning circuit. The driving chip can input clock signals to at least two clock signal lines, and the clock signal lines can transmit the clock signals to the first scanning circuit 11. Figure 1 The example shows that the multiple clock signal lines may include a first clock signal line CK1 and a second clock signal line CK2, which is not limited in any way. The first clock signal line CK1 may be set to provide a first clock signal to an odd-numbered shift register, and a second clock signal to an even-numbered shift register. The second clock signal line CK2 may be set to provide a second clock signal to an odd-numbered shift register, and a first clock signal to an even-numbered shift register.

[0032] Optionally, continue to refer to Figure 1 The display panel also includes a plurality of selection signal lines SE1, the selection signal lines SE1 are correspondingly connected to the first selection circuit 12, the first selection circuit 12 is used to switch on or off the first scanning line 12 and the first scanning circuit 11 according to the signal on the selection signal line SE1, and is also used to transmit the shutdown level signal VGH to the first scanning line GL1 according to the signal on the selection signal line SE1.

[0033] Specifically, the first selection circuit 12 can determine the connection state between the first scanning line GL1 and the first scanning circuit 11 according to the signal state on the selection signal line SE1. When the signal on the selection signal line SE1 controls the first input end of the first selection circuit 12 to be turned on with its output end, and controls the second input end of the first selection circuit 12 to be turned off with its output end, the first selection circuit 12 selects the first scanning line GL1 and the first scanning circuit 11. At this time, the first scanning signal output by the first scanning circuit 11 is transmitted to the first scanning line GL1 through the first selection circuit 12, and then transmitted to the corresponding pixel circuit group 10, to control the switching state of the pixel, and realize the line-by-line display of the image. Conversely, when the signal on the selection signal line SE1 controls the first input end of the first selection circuit 12 to be turned off with its output end, and controls the second input end of the first selection circuit 12 to be turned on with its output end, the first selection circuit 12 will transmit the connected off-level signal VGH to the first scanning line GL1. The shutdown level signal VGH is the cutoff potential of the relevant functional modules in the pixel circuit. Transmitting it to the first scanning line GL1 can cut off the corresponding functional modules in the pixel circuit, ensure that the pixel circuit is in a stable non-working state, avoid false triggering due to factors such as residual signals, and ensure the accuracy and stability of the display state of the display panel.

[0034] Figure 2 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 2As shown, optionally, the gate signal line SE1 includes a first gate signal line SE11 and a second gate signal line SE12.

[0035] The first gating circuit 12 includes a first gating unit 121 and a second gating unit 122, wherein the control end of the first gating unit 121 is connected to the first gating signal line SE11, the first end of the first gating unit 121 is connected to the first scanning circuit 11, and the second end of the first gating unit 121 is connected to the first scanning line GL1, and is used to switch the first scanning line GL1 and the first scanning circuit 11 on or off according to the signal on the first gating signal line SE11.

[0036] The control end of the second selection unit 122 is connected to the second selection signal line SE12, the first end of the second selection unit 122 is connected to the first scanning line GL1, and the second end of the second selection unit 122 is connected to the shutdown level signal VGH, which is used to transmit the shutdown level signal VGH to the first scanning signal line GL1 according to the signal on the second selection signal line SE12.

[0037] In at least one frame of the display period of the display panel, the signals transmitted on the first selection signal line SE11 and the second selection signal line SE12 in the first display partition AA1 are different from the signals transmitted on the first selection signal line SE11 and the second selection signal line SE12 in the second display partition AA2.

[0038] Specifically, the signal on the first selection signal line SE11 determines the on or off state of the first selection unit 121. When the signal on the first selection signal line SE11 is at an effective level, the first selection unit 121 connects the first scanning circuit 11 and the first scanning line GL1, so that the first scanning signal generated by the first scanning circuit 11 can be transmitted to the first scanning line GL1, providing a control signal for the pixel circuit group to realize the row-by-row display of the image.

[0039] The signal on the second selection signal line SE12 controls the working state of the second selection unit 122. When the signal on the first selection signal line SE11 is at an invalid level, the second selection unit 122 is turned on, and the off-level signal VGH is transmitted to the first scanning line GL1, so that the relevant functional modules in the pixel circuit are turned off, ensuring that the pixel circuit is in a stable non-working state, and avoiding false triggering caused by residual signals.

[0040] In a display period of a display panel, the signals transmitted on the first selection signal line SE11 and the second selection signal line SE12 of the first display partition AA1 and the second display partition AA2 are different. This signal difference makes the working state of the first selection circuit 12 of the two partitions different. At a certain moment, the first selection unit 121 of the first display partition AA1 may be turned off due to the signal of the first selection signal line SE11, and the pixel of the partition is stopped from writing the data voltage; while the first selection unit 121 of the second display partition AA2 remains turned on due to the different signals and continues to write data, thereby achieving different refresh frequencies of the two partitions to meet the display requirements of different scenes. In this implementation, the selection signal line and the selection unit are subdivided, and the first selection unit 121 and the second selection unit 122 are controlled respectively by different selection signal lines, thereby improving the control accuracy of the connection between the first scanning circuit 11 and the first scanning line GL1 and the turn-off level signal VGH. Differentiated signal control of different partitions can more accurately control the working state of each partition, reduce signal interference, enhance the stability of the display panel, improve display quality, and reduce the occurrence of display problems such as noise and ghosting.

[0041] Optionally, the first selection signal line SE11 in each display partition is connected to the first selection units 121 of all rows. This means that the signal transmitted by the first selection signal line SE11 can simultaneously control the working state of the first selection units 121 of all rows. When the signal on the first selection signal line SE11 changes, the first selection units 121 of all rows will synchronously turn on or off the first scanning circuit 11 and the first scanning line GL1 according to the signal, thereby determining whether the first scanning signal can be transmitted to each pixel circuit group.

[0042] Optionally, the second selection signal line SE12 in each display partition is connected to the second selection unit 122 of all rows. The signal transmitted by the second selection signal line SE12 can simultaneously control the second selection units 122 of all rows, determine whether to transmit the shutdown level signal VGH to the first scan line GL1, and then control the cut-off state of the relevant functional modules in the pixel circuit. By connecting the first selection signal line SE11 to the first selection unit 121 of all rows, it can be ensured that the pixel circuits of all rows in the same display partition remain synchronized when receiving the first scan signal. When displaying an image, there will be no problems such as asynchronous display and misalignment of different rows in the same partition, ensuring the consistency and stability of the display of the entire partition. The connection between the second selection signal line SE12 and the second selection unit 122 of all rows also makes the pixel circuits of all rows consistent in the control of the shutdown state, avoiding display defects caused by untimely or abnormal shutdown of some rows.

[0043] As a preferred embodiment provided by the embodiment of the present invention, Figure 3FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 3 As shown, optionally, the first selection unit 121 includes a first transistor T1, the gate of the first transistor T1 serves as the gate of the first selection unit 121, the first electrode of the first transistor T1 serves as the first end of the first selection unit 121, and the second electrode of the first transistor T1 serves as the second end of the first selection unit 121.

[0044] Specifically, when the signal transmitted by the first selection signal line SE11 causes the gate voltage of the first transistor T1 to reach the conduction threshold, the first transistor T1 is turned on. At this time, a conductive path is formed between the first electrode (connected to the first scanning circuit 11) and the second electrode (connected to the first scanning line GL1) of the first transistor T1, and the first scanning signal generated by the first scanning circuit 11 can be transmitted to the first scanning line GL1 through the first transistor T1, providing a control signal for the pixel circuit group 10 to realize the line-by-line display of the image. When the gate voltage is lower than the conduction threshold, the first transistor T1 is turned off, cutting off the connection between the first scanning circuit 11 and the first scanning line GL1, and preventing the transmission of the scanning signal.

[0045] Optionally, the second selection unit 122 includes a second transistor T2, the gate of the second transistor T2 serves as the control end of the second selection unit 122, the first electrode of the second transistor T2 serves as the first end of the second selection unit 122, and the second electrode of the second transistor T2 serves as the second end of the second selection unit 122.

[0046] Specifically, when the signal transmitted by the second selection signal line SE12 makes the gate voltage of the second transistor T2 meet the conduction condition, the second transistor T2 is turned on. The first electrode of the second transistor T2 is connected to the first scanning line GL1, and the second electrode is connected to the off-level signal VGH. When turned on, the off-level signal VGH is transmitted to the first scanning line GL1 through the second transistor T2, so that the relevant functional modules in the pixel circuit are turned off, avoiding false triggering caused by residual signals, and ensuring that the pixel circuit is in a stable non-working state. When the gate voltage does not meet the conduction condition, the second transistor T2 is turned off, and the transmission of the off-level signal VGH is stopped.

[0047] Figure 4 is a waveform diagram of a signal transmitted on a first selection signal line and a second selection signal line provided by an embodiment of the present invention. Figure 4 Exemplarily, the signal on the first selection signal line SE11 is the first selection signal E1, and the signal on the second selection signal line SE12 is the second selection signal E2. In the same phase, the first selection signal E1 and the second selection signal E2 have opposite levels.

[0048] refer to Figure 3 and Figure 4In the first stage P1, that is, when the first selection signal E1 is at an invalid level (such as a high level) and the second selection signal E2 is at an effective level (such as a low level), the first transistor T1 is turned off, the second transistor T2 is turned on, and the off-level signal VGH is transmitted to the first scan line GL1; in the second stage P2, that is, when the first selection signal E1 is at a low level and the second selection signal E2 is at a high level, the first transistor T1 is turned on, the first scanning circuit 11 is connected to the first scanning line GL1, and the scanning signal is transmitted. At this time, the second transistor T2 is turned off, preventing the off-level signal VGH from being transmitted to the first scanning line GL1. This setting of opposite levels ensures that at any time, the first scanning line GL1 either transmits the scanning signal or is in a stable state under the control of the off-level signal VGH, avoiding confusion caused by the simultaneous appearance of the two signals. If the levels of the two are not opposite, the first transistor T1 and the second transistor T2 may be turned on or turned off at the same time, causing a conflict between the scanning signal and the off-level signal VGH, or the first scanning line GL1 cannot obtain the required signal in time, affecting the normal operation of the pixel circuit, resulting in abnormal display.

[0049] Optionally, continue to refer to Figure 2 and Figure 3 , the refresh frequency of the first display partition AA1 is a first refresh frequency, the refresh frequency of the second display partition AA2 is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.

[0050] In the first frame, the signal on the first selection signal line SE11 in the first display partition AA1 and the second display partition AA2 is at a valid level, and the signal on the second selection signal line SE12 in the first display partition AA1 and the second display partition AA2 is at an invalid level, so that the sub-pixels in the first display partition AA1 and the second display partition AA2 are both written with data voltages.

[0051] In the second frame, the signal on the first selection signal line SE11 in the first display partition AA1 is at an invalid level, and the signal on the second selection signal line SE12 is at a valid level; the signal on the first selection signal line SE11 in the second display partition AA2 is at a valid level, and the signal on the second selection signal line SE12 is at an invalid level, so that the data voltage is not written to the sub-pixels in the first display partition AA1, and the data voltage is written to the sub-pixels in the second display partition AA2.

[0052] Specifically, the display cycle of the display panel includes a plurality of display frames, and the first frame and the second frame are any two frames. In the first frame, the signal on the first selection signal line SE11 of the two partitions is at a valid level, and the signal on the second selection signal line SE12 is at an invalid level. At this time, the first transistor T1 in the first selection unit 121 is turned on, the first scanning circuit 11 is connected to the first scanning line GL1, and the first scanning signal is transmitted to the pixel circuit group. At the same time, the second transistor T2 in the second selection unit 122 is turned off, and the off-level signal VGH cannot be transmitted to the first scanning line GL1. This enables the sub-pixels in the first display partition AA1 and the second display partition AA2 to write data voltages, preparing for subsequent display.

[0053] In the second frame, the first selection signal line SE11 of the first display partition AA1 becomes an invalid level, and the second selection signal line SE12 becomes an effective level, causing the first transistor T1 to be turned off, the second transistor T2 to be turned on, the scanning signal to be cut off, the shutdown level signal VGH transmission, and the sub-pixel in the partition does not write the data voltage; while the second display partition AA2 maintains the first selection signal line SE11 valid and the second selection signal line SE12 invalid, and the sub-pixel continues to write the data voltage. In this way, by setting the selection signals of the two frames, the sub-pixels in different partitions are controlled to write data at different times. Since the first display partition AA1 does not write the data voltage in the second frame, the second display partition AA2 writes normally. In one display cycle, the number of times the second display partition AA2 writes the data voltage is relatively more. The refresh frequency is related to the number of data writes per unit time. The more the number of writes, the higher the refresh frequency. Therefore, by using the differentiated setting of the two partition selection signals in the first frame and the second frame, the refresh frequency of the second display partition AA2 is higher than that of the first display partition AA1, and the partition multi-frequency display of the horizontal area of ​​the display panel is achieved to meet the display refresh rate requirements of different scenes.

[0054] Figure 5 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 5 The display panel also includes a second scanning circuit 13, a plurality of second scanning lines GL2 and a plurality of second gating circuits 14; the second scanning circuit 13 is electrically connected to the second scanning line GL2 via the second gating circuit 14, and the second scanning line GL2 is connected to the corresponding pixel circuit group 10; the second gating circuit 14 is used to switch on or off the second scanning line GL2 and the second scanning circuit 13, and is also used to transmit the shutdown level signal VGH to the second scanning line GL2.

[0055] Specifically, the second scanning circuit 13 is used to output a second scanning signal at least according to the input signal and the clock signal, and the second scanning signal is transmitted to the second scanning line GL2 through the second gating circuit 14. The second scanning line GL2 is used to transmit the second scanning signal generated by the second scanning circuit 13 to the pixel circuit group 10, so as to control the switching state of the pixel and realize the row-by-row display of the image. Exemplarily, when the display panel includes multiple rows of pixel circuits PX, multiple first shift registers 131 in each second scanning circuit 13 are cascaded. Multiple cascaded first shift registers 131 respectively provide a second scanning signal to at least one column of pixel circuits PX through the corresponding second gating circuit 14. Among them, the input signal of the first shift register 131 of the first stage may include the input signal provided by the driving chip to the first start signal line STV1, and the input signal of the first shift register 131 of other stages may be the second scanning signal output by the first shift register 131 of the previous stage. Among them, the structures of the shift register 111 and the first shift register 131 may be the same or different, and the embodiment of the present invention is not limited to this.

[0056] The first scanning signal output by the second scanning circuit 13 may include an effective level and an ineffective level, wherein the effective level is a level for controlling the conduction of a functional module in the pixel circuit, and the ineffective level is a level for controlling the shutoff of a functional module in the pixel circuit. For example, the level for controlling the shutoff of the initialization module in the pixel circuit PX. The effective level may be a high level, and the ineffective level may be a low level; or, the effective level may be a low level, and the ineffective level may be a high level. The embodiments of the present invention are all described by taking the ineffective level as a high level and the effective level as a low level as an example. Optionally, the ineffective level is the same as the shutoff level signal VGH.

[0057] The second gating circuit 14 includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the second gating circuit 14 is connected to the output terminal of the second scanning circuit 13 to receive the second scanning signal output by the second scanning circuit 13. The second input terminal of the second gating circuit 14 is connected to the shutdown level signal VGH. When the first input terminal of the second gating circuit 14 is connected to the output terminal and the second input terminal of the second gating circuit 14 is disconnected from the output terminal, the second scanning signal is transmitted to the corresponding second scanning line GL2 through the output terminal of the second gating circuit 12. The second scanning signal generated by the second scanning circuit 13 can reach the pixel circuit group 10 through the second scanning line GL2, thereby participating in the control of the pixel, for example, playing a role in the initialization operation of the pixel circuit.

[0058] When the second input terminal and the output terminal of the first gating circuit 12 are connected, and the first input terminal and the output terminal of the second gating circuit 14 are disconnected, the shutdown level signal VGH is transmitted to the corresponding second scanning line GL2 through the output terminal of the second gating circuit 14. The shutdown level signal VGH can turn off the functional modules in the pixel circuit (such as the initialization module), ensure that the pixel circuit is in a stable state, avoid pixel mis-triggering due to abnormal signals, and ensure the stability and accuracy of the displayed image.

[0059] Optionally, continue to refer to Figure 5 The display panel also includes a plurality of selection signal lines SE1, which are connected to the second selection circuit 14 accordingly. The second selection circuit 14 is used to switch on or off the second scanning line GL2 and the second scanning circuit 14 according to the signal on the selection signal line SE1, and is also used to transmit the off-level signal to the second scanning line GL2 according to the signal on the selection signal line SE1.

[0060] Figure 6 is a schematic diagram of the structure of a second gating circuit provided by an embodiment of the present invention. Figure 6 Optionally, the gate signal line SE1 includes a first gate signal line SE11 and a second gate signal line SE12.

[0061] The second gating circuit 14 includes a third gating unit 141 and a fourth gating unit 142, the control end of the third gating unit 141 is connected to the first gating signal line SE11, the first end of the third gating unit 141 is connected to the second scanning circuit 13, and the second end of the third gating unit 142 is connected to the second scanning line GL2, and is used to turn on or off the second scanning line GL2 and the second scanning circuit 13 according to the signal on the first gating signal line SE1.

[0062] The control end of the fourth selection unit 142 is connected to the second selection signal line SE12, the first end of the fourth selection unit 142 is connected to the second scan line GL2, and the second end of the fourth selection unit 142 is connected to the shutdown level signal VGH, which is used to transmit the shutdown level signal to the second scan line GL2 according to the signal on the second selection signal line SE12.

[0063] Specifically, the signal on the first selection signal line SE11 determines the on or off state of the third selection unit 141. When the signal on the first selection signal line SE11 is at an effective level, the third selection unit 141 connects the first scanning circuit 11 and the second scanning line GL2, so that the first scanning signal generated by the first scanning circuit 11 can be transmitted to the second scanning line GL2, providing a control signal for the pixel circuit group 10 to realize the row-by-row display of the image.

[0064] The signal on the second selection signal line SE12 controls the working state of the fourth selection unit 142. When the signal on the first selection signal line SE11 is at an invalid level, the fourth selection unit 142 is turned on, and the off-level signal VGH is transmitted to the second scanning line GL2, so that the relevant functional modules in the pixel circuit are turned off, ensuring that the pixel circuit is in a stable non-working state, and avoiding false triggering caused by residual signals.

[0065] Optionally, the first selection signal line SE11 in each display partition is connected to the third selection units 141 of all rows. This means that the signal transmitted by the first selection signal line SE11 can simultaneously control the working state of the third selection units 141 of all rows. When the signal on the first selection signal line SE11 changes, the third selection units 141 of all rows will synchronously turn on or off the second scanning circuit 13 and the second scanning line GL2 according to the signal, thereby determining whether the second scanning signal can be transmitted to each pixel circuit group.

[0066] Optionally, the second selection signal line SE12 in each display partition is connected to the fourth selection unit 142 of all rows. The second selection signal line SE12 is connected to the fourth selection unit 142 of all rows, which means that in the same display partition, the pixel circuits of all rows can maintain synchronization when receiving the shutdown level signal VGH. When the second selection signal line SE12 transmits a signal to turn on the fourth selection unit 142, the second scan lines GL2 of all rows will simultaneously access the shutdown level signal VGH, so that the relevant functional modules in each pixel circuit are synchronously cut off. In this way, the display inconsistency problem caused by the untimely or abnormal shutdown of some rows can be avoided, and the picture of the entire display partition is guaranteed to be stable and flicker-free, thereby improving the display quality. When displaying a static picture, the unified shutdown control can ensure that all pixels are in a stable state to prevent noise or other display defects.

[0067] As a preferred embodiment provided by the embodiment of the present invention, Figure 7 is a schematic diagram of the structure of another second gating circuit provided by an embodiment of the present invention. Figure 7 Optionally, the third selection unit 141 includes a third transistor T3, the gate of the third transistor T3 serves as the gate of the third selection unit 141, the first electrode of the third transistor T3 serves as the first end of the third selection unit 141, and the second electrode of the third transistor T3 serves as the second end of the third selection unit 141.

[0068] Specifically, when the signal transmitted by the first selection signal line SE11 causes the gate voltage of the third transistor T3 to reach the conduction threshold, the third transistor T3 is turned on. At this time, a conductive path is formed between the first electrode (connected to the second scanning circuit 13) and the second electrode (connected to the second scanning line GL2) of the third transistor T3, and the second scanning signal generated by the second scanning circuit 13 can be transmitted to the second scanning line GL2 through the third transistor T3, providing a control signal for the pixel circuit group 10 to realize the line-by-line display of the image. When the gate voltage is lower than the conduction threshold, the third transistor T3 is turned off, cutting off the connection between the second scanning circuit 13 and the second scanning line GL2, and preventing the transmission of the scanning signal.

[0069] Optionally, the fourth selection unit 142 includes a fourth transistor T4, the gate of the fourth transistor T4 serves as the control end of the fourth selection unit 142, the first electrode of the fourth transistor T4 serves as the first end of the fourth selection unit 142, and the second electrode of the fourth transistor T4 serves as the second end of the fourth selection unit 142.

[0070] Specifically, when the signal transmitted by the second selection signal line SE12 makes the gate voltage of the fourth transistor T4 meet the conduction condition, the fourth transistor T4 is turned on. The first electrode of the fourth transistor T4 is connected to the second scan line GL2, and the second electrode is connected to the off-level signal VGH. When turned on, the off-level signal VGH is transmitted to the second scan line GL2 through the fourth transistor T4, so that the relevant functional modules in the pixel circuit are turned off, avoiding false triggering caused by residual signals, and ensuring that the pixel circuit is in a stable non-working state. When the gate voltage does not meet the conduction condition, the fourth transistor T4 is turned off, and the transmission of the off-level signal VGH is stopped.

[0071] Figure 8 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 8 Optionally, the pixel circuit includes a driving module 110 , a data writing module 120 and a threshold compensation module 130 .

[0072] The data writing module 120 is electrically connected between the first end of the driving module 110 and the data line Data, and is used to write the data voltage provided by the data line to the control end of the driving module according to the signal on the first scanning line GL1.

[0073] The threshold compensation module 130 is connected between the second terminal and the control terminal of the driving module 110 , and is used to perform threshold compensation on the driving module 110 according to the signal on the first scan line GL2 .

[0074] Specifically, in the data writing and threshold compensation stage, the signal on the first scan line GL1 controls the data writing module 120 and the threshold compensation module 130 to be turned on, so that the data voltage on the data line Data can be written to the control end of the driving module 110 through the data writing module 120, the driving module 110 and the threshold compensation module 130 in sequence, so that the voltage at the control end of the driving module 110 is related to both the data voltage and the threshold voltage of the driving module 110.

[0075] Optionally, the pixel circuit also includes a first initialization module 140, which is connected between the control end of the driving module 110 and the first initialization voltage line Vref1, and is used to write the first initialization voltage provided by the first initialization voltage line Vref1 to the control end of the driving module 110 according to the signal on the second scanning line GL2.

[0076] Optionally, the pixel circuit also includes a light-emitting module 150 and a light-emitting control module 160. The light-emitting control module 160, the driving module 110 and the light-emitting module 150 are connected between a first power line VDD and a second power line VSS. The light-emitting control module 160 is used to control the light-emitting module to emit light according to a driving current output by the driving module 110 according to a signal on the light-emitting control signal line EM.

[0077] Optionally, the light-emitting control module 160 includes a first light-emitting control module 161 and a second light-emitting control module 162, the first light-emitting control module 161 is connected between the first end of the driving module 110 and the first power line VDD, the second light-emitting control module 162 is connected between the second end of the driving module 110 and the first end of the light-emitting module 150, and the second end of the light-emitting module 160 is electrically connected to the second power line VSS.

[0078] Optionally, the pixel circuit also includes a second initialization module 170, which is connected between the control end of the driving module 110 and the first initialization voltage line Vref1, and is used to write the second initialization voltage provided by the second initialization voltage line Vref2 to the first end of the light-emitting module 150 according to the signal on the third scanning line GL3.

[0079] Optionally, the pixel circuit further includes a storage module 180 , which is connected between the control terminal of the driving module 110 and the first power line VDD and is used to store the voltage of the control terminal of the driving module 110 .

[0080] Fig. 9 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Fig. 9 The light emitting module 150 includes a light emitting element D1 , an anode of the light emitting element D1 serves as a first end of the light emitting module 150 , and a cathode of the light emitting element D1 serves as a second end of the light emitting module 150 .

[0081] The driving module 110 may include a driving transistor DTFT, which may be, for example, an NMOS transistor or a PMOS transistor, and a gate, a first electrode, and a second electrode of the driving transistor DTFT may respectively serve as a control terminal, a first terminal, and a second terminal of the driving module 110. The driving module 110 may generate a driving current according to a voltage between its control terminal and the first terminal, and the light-emitting element D1 emits light in response to the driving current.

[0082] The data writing module 120 includes a data writing transistor M1, for example, the data writing transistor M1 is an NMOS transistor or a PMOS transistor, the first electrode of the data writing transistor M1 is connected to the first end of the driving module 110, the second electrode of the data writing transistor M1 is connected to the data line Data, and the gate of the data writing transistor M1 is connected to the first scanning line GL1.

[0083] The threshold compensation module 130 includes a threshold compensation transistor M2, which is an NMOS transistor. The gate of the threshold compensation transistor M2 is connected to the first scan line GL1, the first electrode of the threshold compensation transistor M2 is connected to the second end of the driving module 110, and the second electrode of the threshold compensation transistor M2 is connected to the control end of the driving module 110.

[0084] Optionally, the first initialization module 140 includes a first initialization transistor M3, which is an NMOS transistor. The first electrode of the first initialization transistor M3 is connected to the control end of the driving module 110, the second electrode of the first initialization transistor M3 is connected to the first initialization voltage line Vref1, and the gate of the first initialization transistor M3 is connected to the second scan line GL3.

[0085] Optionally, the first light emission control module 161 includes a first light emission control transistor M4, which is a PMOS transistor or an NMOS transistor, a first electrode of the first light emission control transistor M4 is connected to the first end of the driving module 110, a second electrode of the first light emission control transistor M4 is connected to the first power line VDD, and a gate of the first light emission control transistor M4 is connected to the light emission control signal line EM. The first light emission control transistor M4 can be an NMOS transistor or a PMOS transistor.

[0086] Optionally, the second light emitting control module 190 includes a second light emitting control transistor M5, which is a PMOS transistor or an NMOS transistor, a first electrode of the second light emitting control transistor M5 is connected to the second end of the driving module 110, a second electrode of the second light emitting control transistor M5 is connected to the anode of the light emitting element D1, and a gate of the second light emitting control transistor M5 is connected to the light emitting control signal line EM. The second light emitting control transistor M5 can be an NMOS transistor or a PMOS transistor.

[0087] Optionally, the second initialization module 170 includes a second initialization transistor M6, a gate of the second initialization transistor M6 is connected to the third scan line GL3, a first electrode of the second initialization transistor M6 is connected to the second initialization voltage line Vref2, and a second electrode of the second initialization transistor T5 is connected to the anode of the light emitting element D1. The second initialization transistor M6 can be an NMOS transistor or a PMOS transistor.

[0088] Optionally, the storage module 180 includes a storage capacitor Cst, a first electrode of the storage capacitor Cst is connected to the first power line VDD so that the first electrode of the storage capacitor Cst is connected to the first power voltage, and a second electrode of the storage capacitor Cst is connected to the control end of the driving module 110.

[0089] Fig.10 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Fig.10 The drive timing shown is applicable to drive Fig. 9 The pixel circuit shown in the figure works. Fig. 9 and Fig.10 , the working principle of the pixel circuit provided by the embodiment of the present invention is described. Exemplarily, the working process of the pixel circuit in a display frame at least includes a first initialization stage P1, a data writing and threshold compensation stage P2, a second initialization stage P3 and a light emitting stage P4. After the end of the i-1th display frame, the i-th display frame is entered. i is an integer greater than or equal to 2.

[0090] In the first initialization phase P1 of the i-th display frame, the first initialization module 140 is turned on, the threshold compensation module 130, the data writing module 120, the second initialization module 170, the first light emission control module 161 and the second light emission control module 162 are turned off. That is, the first initialization transistor M3 is turned on, and the data writing transistor M1, the threshold compensation transistor M2, the second initialization transistor M6, the first light emission control transistor M4 and the second light emission control transistor M5 are turned off. The first initialization voltage transmitted by the first initialization voltage line Vref1 is written into the gate of the driving transistor DTFT through the first initialization transistor M3, the gate voltage of the driving transistor DTFT is reset to the first initialization voltage, and the driving transistor DTFT is controlled to be turned on.

[0091] In the data writing and threshold compensation phase P2 of the i-th display frame, the data writing module 120 and the threshold compensation module 130 are turned on, and the first initialization module 140, the second initialization module 170, the first light emitting control module 161 and the second light emitting control module 162 are turned off. That is, the threshold compensation transistor M2 and the data writing transistor M1 are turned on, and the first initialization transistor M3, the second initialization transistor M6, the first light emitting control transistor M4 and the second light emitting control transistor M5 are turned off. The data voltage transmitted by the data line Data is sequentially written into the gate of the driving transistor DTFT through the data writing transistor M1, the driving transistor DTFT and the threshold compensation transistor M2, so that the gate voltage of the driving transistor DTFT is related to both the data voltage and the threshold voltage of the driving transistor DTFT, and the gate voltage of the driving transistor DTFT is stored through the storage capacitor Cst.

[0092] In the light-emitting phase P3 of the i-th display frame, the second initialization module 170 is turned on, and the threshold compensation module 130, the data writing module 120, the first initialization module 140, the first light-emitting control module 161 and the second light-emitting control module 162 are turned off. That is, the second initialization transistor M6 is turned on, and the threshold compensation transistor M2, the data writing transistor M1, the first initialization transistor M3, the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned off. The second initialization voltage transmitted by the second initialization voltage line Vref2 is written into the anode of the light-emitting element D1 through the second initialization transistor M6. The second initialization voltage transmitted by the third initialization voltage line Vref3 is written into the first electrode of the driving transistor DTFT through the third initialization transistor M5.

[0093] In the light-emitting stage P4 of the i-th display frame, the driving module 110, the first light-emitting control module 161 and the second light-emitting control module 162 are turned on, and the threshold compensation module 130, the data writing module 120, the first initialization module 140 and the second initialization module 170 are turned off. That is to say, the first light-emitting control transistor M4, the second light-emitting control transistor M5 and the driving transistor DTFT are turned on, and the threshold compensation transistor M2, the data writing transistor M1, the first initialization transistor M3 and the second initialization transistor M6 are turned off. The driving transistor DTFT generates a driving current according to its own gate voltage, thereby driving the light-emitting element D1 to emit light with a corresponding brightness. In the light-emitting stage P4, since the gate voltage of the driving transistor DTFT is related to the data voltage and the threshold voltage of the driving transistor DTFT, it is helpful to compensate for the influence of the threshold voltage of the driving transistor DTFT on the driving current, thereby improving the display uniformity of the light-emitting stage.

[0094] Based on the same inventive concept, the present invention also provides a display device, including a display panel provided by any embodiment of the present invention. It can be understood that the display device provided by the embodiment of the present invention can be a display device with a display function such as a mobile phone, a wearable product, a computer, a television, a car display device, etc., and the present invention does not impose specific restrictions on this. The display device provided by the embodiment of the present invention has the beneficial effects of the display panel provided by the embodiment of the present invention. For details, please refer to the specific description of the display in the above embodiments, and the embodiments of the present invention will not be repeated here.

[0095] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: At least two display partitions are included, wherein the at least two display partitions include a first display partition and a second display partition, and the first display partition and the second display partition are adjacent to each other along a direction perpendicular to the data line; At least two of the display subareas respectively include a plurality of pixel circuit groups; the display panel further includes a first scanning circuit, a plurality of first scanning lines and a plurality of first gating circuits; The first scanning circuit is electrically connected to the first scanning line through the first gating circuit, and the first scanning line is connected to the corresponding pixel circuit group; the first gating circuit is used to turn on or off the first scanning line and the first scanning circuit, and is also used to transmit a shutdown level signal to the first scanning line.

2. The display panel according to claim 1, characterized in that: The display panel further includes a plurality of gate signal lines, the gate signal lines are correspondingly connected to the first gate circuit, the first gate circuit is used to gate or shut down the first scan line and the first scan circuit according to the signal on the gate signal line, and is also used to transmit the shut-off level signal to the first scan line according to the signal on the gate signal line; Preferably, the strobe signal line includes a first strobe signal line and a second strobe signal line; The first gating circuit comprises a first gating unit and a second gating unit, wherein a control end of the first gating unit is connected to the first gating signal line, a first end of the first gating unit is connected to the first scanning circuit, and a second end of the first gating unit is connected to the first scanning line, and is used to switch on or off the first scanning line and the first scanning circuit according to a signal on the first gating signal line; The control end of the second gating unit is connected to the second gating signal line, the first end of the second gating unit is connected to the first scanning line, and the second end of the second gating unit is connected to the off-level signal, so as to transmit the off-level signal to the first scanning signal line according to the signal on the second gating signal line; wherein, in at least one frame of a display period of the display panel, the signals transmitted on the first selection signal line and the second selection signal line in the first display partition are different from the signals transmitted on the first selection signal line and the second selection signal line in the second display partition; Preferably, the first gating signal line in each of the display partitions is connected to the first gating units of all rows; Preferably, the second gating signal line in each of the display partitions is connected to the second gating units of all rows.

3. The display panel according to claim 2, characterized in that: The first gating unit includes a first transistor, a gate of the first transistor serves as the gate of the first gating unit, a first electrode of the first transistor serves as a first end of the first gating unit, and a second electrode of the first transistor serves as a second end of the first gating unit; Preferably, the second gating unit comprises a second transistor, the gate of the second transistor serves as the control terminal of the second gating unit, the first electrode of the second transistor serves as the first terminal of the second gating unit, and the second electrode of the second transistor serves as the second terminal of the second gating unit; Preferably, the signal on the first selection signal line is a first selection signal, and the signal on the second selection signal line is a second selection signal. In the same phase, the levels of the first selection signal and the second selection signal are opposite.

4. The display panel according to claim 2, characterized in that: The refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency; In a first frame, the signal on the first selection signal line in the first display partition and the second display partition is at a valid level, and the signal on the second selection signal line in the first display partition and the second display partition is at an invalid level, so that the sub-pixels in the first display partition and the second display partition are both written with data voltages; In the second frame, the signal on the first selection signal line in the first display partition is the invalid level, the signal on the second selection signal line is the valid level, the signal on the first selection signal line in the second display partition is the valid level, and the signal on the second selection signal line is the invalid level, so that the sub-pixels in the first display partition are not written with data voltage, and the sub-pixels in the second display partition are written with data voltage.

5. The display panel according to claim 1, characterized in that: The display panel also includes a second scanning circuit, a plurality of second scanning lines and a plurality of second gating circuits; the second scanning circuit is electrically connected to the second scanning line through the second gating circuit, and the second scanning line is connected to the corresponding pixel circuit group; the second gating circuit is used to turn on or off the second scanning line and the second scanning circuit, and is also used to transmit a shutdown level signal to the second scanning line.

6. The display panel according to claim 5, characterized in that: The display panel further includes a plurality of gate signal lines, the gate signal lines are correspondingly connected to the second gate circuit, the second gate circuit is used to gate or shut down the second scan line and the second scan circuit according to the signal on the gate signal line, and is also used to transmit the shut-off level signal to the second scan line according to the signal on the gate signal line; Preferably, the strobe signal line includes a first strobe signal line and a second strobe signal line; The second gating circuit comprises a third gating unit and a fourth gating unit, wherein a control end of the third gating unit is connected to the first gating signal line, a first end of the third gating unit is connected to the second scanning circuit, and a second end of the third gating unit is connected to the second scanning line, and is used to switch on or off the second scanning line and the second scanning circuit according to a signal on the first gating signal line; The control end of the fourth gating unit is connected to the second gating signal line, the first end of the fourth gating unit is connected to the second scan line, and the second end of the fourth gating unit is connected to the off-level signal, so as to transmit the off-level signal to the second scan line according to the signal on the second gating signal line; Preferably, the first gating signal line in each of the display partitions is connected to the third gating units of all rows; Preferably, the second gating signal line in each of the display partitions is connected to the fourth gating units of all rows.

7. The display panel according to claim 6, characterized in that: The third gating unit comprises a third transistor, a gate of the third transistor serves as the gate of the third gating unit, a first electrode of the third transistor serves as the first end of the third gating unit, and a second electrode of the third transistor serves as the second end of the third gating unit; Preferably, the fourth gating unit comprises a fourth transistor, the gate of the fourth transistor serves as the control terminal of the fourth gating unit, the first electrode of the fourth transistor serves as the first terminal of the fourth gating unit, and the second electrode of the fourth transistor serves as the second terminal of the fourth gating unit; Preferably, when the third transistor is turned on, the fourth transistor is turned off; or when the third transistor is turned off, the fourth transistor is turned on.

8. The display panel according to claim 1, characterized in that: The pixel circuit group includes a plurality of columns of pixel circuits, and the pixel circuit includes a driving module, a data writing module and a threshold compensation module; The data writing module is electrically connected between the first end of the driving module and the data line, and is used to write the data voltage provided by the data line to the control end of the driving module according to the signal on the first scanning line; The threshold compensation module is connected between the second end of the driving module and the control end, and is used to perform threshold compensation on the driving module according to the signal on the first scanning line.

9. The display panel according to claim 8, characterized in that: The pixel circuit further includes a first initialization module, which is connected between the control terminal of the driving module and the first initialization voltage line and is used to write the first initialization voltage provided by the first initialization voltage line to the control terminal of the driving module according to the signal on the second scanning line; Preferably, the pixel circuit further comprises a light emitting module and a light emitting control module, wherein the light emitting control module, the driving module and the light emitting module are connected between a first power line and a second power line, and the light emitting control module is used to control the light emitting module to emit light according to a driving current output by the driving module according to a signal on a light emitting control signal line; Preferably, the pixel circuit further comprises a second initialization module, which is connected between the control terminal of the driving module and the first initialization voltage line, and is used to write a second initialization voltage provided by the second initialization voltage line to the first terminal of the light-emitting module according to a signal on the third scanning line; Preferably, the pixel circuit further comprises a storage module, wherein the storage module is connected between the control end of the driving module and the first power line and is used for storing the voltage of the control end of the driving module.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

Images