Display device

Abstract

A display device is disclosed, the display device comprising a substrate, a circuit layer and an element layer. The circuit layer comprises: a light-emitting pixel driver; a data line; a demultiplexing circuit, which outputs a data signal of the data line based on a data multiplexing signal supplied from a display driving circuit; and a data transmission line, which is electrically connected between the display driving circuit and the demultiplexing circuit, and transmits the data multiplexing signals of the demultiplexing circuit respectively. The data transmission line comprises: a first data transmission line, which is electrically connected to a first demultiplexing circuit adjacent to an edge of the substrate in a first direction; and a second data transmission line, which is electrically connected to a second demultiplexing circuit, and the second demultiplexing circuit is spaced farther from the edge of the substrate in the first direction than the first demultiplexing circuit. The second data transmission line is electrically connected to a path compensation capacitor in a sub-area.

Description

Technical Field

[0001] An aspect of some embodiments of the present disclosure relates to a display device. Background Art

[0002] With the development of information society, more and more demands are put forward for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro-light-emitting display device including a micro-light-emitting element.

[0004] Organic light-emitting display devices use light-emitting elements each including a light-emitting layer made of an organic light-emitting material to display images. As described above, organic light-emitting display devices use self-luminous elements to realize image display, and therefore can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

[0005] One surface of the display device may be a display surface including a display area in which an image is displayed and a non-display area as a periphery of the display area. An emission area emitting light having corresponding brightness and color may be arranged in the display area.

[0006] The above information disclosed in this background section is only for enhancement of understanding of the background technology and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the invention

[0007] As display devices become higher resolution or larger, the number of data lines may increase, and the difference in the length of the transmission path between the display driving circuit and the data line may increase. As a result, distorted or delayed data signals may be supplied to the data line having a relatively long transmission path among the data lines, resulting in a reduction in display quality due to brightness deviation.

[0008] In view of the above circumstances, aspects of the present disclosure provide a display device that can relatively improve display quality by reducing brightness deviation caused by a length difference of a transmission path between a display driving circuit and a data line.

[0009] According to some embodiments of the present disclosure, a display device includes: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer. According to some embodiments, the substrate includes: a main area including a display area in which an emission area is arranged and a non-display area around the display area; and a sub-area protruding from one side of the main area. According to some embodiments, the element layer includes light-emitting elements respectively in the emission area. According to some embodiments, the circuit layer includes: light-emitting pixel drivers, respectively electrically connected to the light-emitting elements, and arranged in a first direction and a second direction; data lines, extending in the second direction, and transmitting data signals to the light-emitting pixel drivers; a demultiplexing circuit, in the non-display area, and outputting data signals of the data lines based on data multiplexing signals supplied from a display driving circuit; and data transmission lines, electrically connected between the display driving circuit and the demultiplexing circuit, and transmitting data multiplexing signals of the demultiplexing circuit, respectively. According to some embodiments, the data transmission lines include: a first data transmission line, electrically connected to a first demultiplexing circuit adjacent to an edge of the substrate in the first direction; and a second data transmission line, electrically connected to a second demultiplexing circuit, the second demultiplexing circuit being spaced farther from the edge of the substrate than the first demultiplexing circuit in the first direction. According to some embodiments, the second data transmission line is electrically connected to a path compensation capacitor in the sub-region.

[0010] According to some embodiments, the data line includes: a first data line electrically connected to a demultiplexing output line of a first demultiplexing circuit; and a second data line electrically connected to a demultiplexing output line of a second demultiplexing circuit. According to some embodiments, the circuit layer further includes: a first detour auxiliary line extending in the second direction, paired with one of the second data lines, and electrically connected to the first data transmission line; a second detour auxiliary line extending in the first direction and electrically connected to the first detour auxiliary line; a third detour auxiliary line extending in the second direction, paired with one of the first data lines, and electrically connected to the second detour auxiliary line; and an input auxiliary line in a non-display area and electrically connected between the third detour auxiliary line and the first demultiplexing circuit. According to some embodiments, the second data transmission line is directly electrically connected to the second demultiplexing circuit.

[0011] According to some embodiments, the sub-region includes: a bending region, which is transformed into a bending shape; a first sub-region, between the main region and one side of the bending region; and a second sub-region, connected to the other side of the bending region. According to some embodiments, the display driving circuit is in the second sub-region. According to some embodiments, the circuit layer also includes a power pad line extending from a portion of the signal pads in the second sub-region to the bending region. According to some embodiments, each of the data transmission lines includes: a data output line, which is in the second sub-region and extends from the display driving circuit to the bending region; a data bending line, which is in the bending region and is electrically connected to the data output line; and a data input line, which is in the first sub-region and the non-display region and is electrically connected to the data bending line. According to some embodiments, the path compensation capacitor is electrically connected to the data output line of the second data transmission line.

[0012] According to some embodiments, the data transmission line further comprises: a third data transmission line electrically connected to a third demultiplexing circuit, the third demultiplexing circuit being spaced further from an edge of the substrate in the first direction than the second demultiplexing circuit. According to some embodiments, the data output line of the second data transmission line is electrically connected to the first path compensation capacitor. According to some embodiments, the data output line of the third data transmission line is electrically connected to a second path compensation capacitor, the second path compensation capacitor having a capacitance greater than that of the first path compensation capacitor and being in the sub-region.

[0013] According to some embodiments, the circuit layer further comprises: a compensation capacitor electrode in the second sub-region and electrically connected to the data output line of the second data transmission line. According to some embodiments, the path compensation capacitor is provided by an overlapping region between the power pad line and each of the compensation capacitor electrode and the data output line of the second data transmission line.

[0014] According to some embodiments, the circuit layer includes: a first semiconductor layer on a substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a first source-drain conductive layer on the first interlayer insulating layer; and a first planarization layer covering the first source-drain conductive layer. According to some embodiments, the first source-drain conductive layer includes a data output line for each of the data transmission lines.

[0015] According to some embodiments, the first gate conductive layer includes a power pad line. According to some embodiments, the second gate conductive layer includes a compensation capacitor electrode. According to some embodiments, the compensation capacitor electrode is electrically connected to a data output line of the second data transmission line through at least one capacitor auxiliary contact hole penetrating the first interlayer insulating layer.

[0016] According to some embodiments, the first gate conductive layer includes a compensation capacitor electrode. According to some embodiments, the second gate conductive layer includes a power pad line. According to some embodiments, the compensation capacitor electrode is electrically connected to a data output line of the second data transmission line through at least one capacitor auxiliary contact hole penetrating the second gate insulating layer and the first interlayer insulating layer.

[0017] According to some embodiments, the circuit layer further includes: a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer on the third gate insulating layer; and a second interlayer insulating layer covering the third gate conductive layer. According to some embodiments, the first source-drain conductive layer is on the second interlayer insulating layer.

[0018] According to some embodiments, the compensation capacitor electrode includes a first capacitor allocation electrode and a second capacitor allocation electrode in different conductive layers. According to some embodiments, the first gate conductive layer includes the first capacitor allocation electrode. According to some embodiments, the second gate conductive layer includes a power pad line. According to some embodiments, the third gate conductive layer includes the second capacitor allocation electrode. According to some embodiments, the first capacitor allocation electrode is electrically connected to the data output line of the second data transmission line through at least one first capacitor auxiliary contact hole penetrating the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, and the second gate insulating layer. According to some embodiments, the second capacitor allocation electrode is electrically connected to the data output line of the second data transmission line through at least one second capacitor auxiliary contact hole penetrating the second interlayer insulating layer.

[0019] According to some embodiments, the power pad line includes a first pad distribution line and a second pad distribution line in different conductive layers. According to some embodiments, the first gate conductive layer includes the first pad distribution line. According to some embodiments, the second gate conductive layer includes a compensation capacitor electrode. According to some embodiments, the third gate conductive layer includes a second pad distribution line. According to some embodiments, the compensation capacitor electrode is electrically connected to the data output line of the second data transmission line through at least one capacitor auxiliary contact hole penetrating the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer.

[0020] According to some embodiments, the power pad line includes: a first power pad line transmitting a first power; and a second power pad line transmitting a second power. According to some embodiments, the first power and the second power are provided for driving a light emitting element.

[0021] According to some embodiments, each of the demultiplexing circuits includes a demultiplexing transistor electrically connected between one of the data transmission lines and two or more of the data lines. According to some embodiments, the demultiplexing transistor includes: a first demultiplexing transistor turned on by a first demultiplexing control signal; and a second demultiplexing transistor turned on by a second demultiplexing control signal.

[0022] According to some embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer. According to some embodiments, the substrate comprises: a main area including a display area in which an emission area is arranged and a non-display area around the display area; and a sub-area protruding from one side of the main area. According to some embodiments, the element layer comprises light-emitting elements respectively in the emission area. According to some embodiments, the circuit layer comprises: light-emitting pixel drivers, respectively electrically connected to the light-emitting elements, and arranged in a first direction and a second direction; data lines, extending in the second direction, and transmitting data signals to the light-emitting pixel drivers; a demultiplexing circuit, in the non-display area, and outputting data signals of the data lines based on data multiplexing signals supplied from the display driving circuit; and data transmission lines, electrically connected between the display driving circuit and the demultiplexing circuit, and transmitting data multiplexing signals of the demultiplexing circuit respectively. According to some embodiments, the demultiplexing circuit comprises: a first demultiplexing circuit, adjacent to an edge of the substrate in the first direction; and a second demultiplexing circuit, spaced farther from the edge of the substrate than the first demultiplexing circuit in the first direction. According to some embodiments, the data transmission line includes: a first data transmission line that transmits a data multiplexing signal of a first demultiplexing circuit; and a second data transmission line that transmits a data multiplexing signal of a second demultiplexing circuit. According to some embodiments, the first data transmission line is electrically connected to the first demultiplexing circuit through a bypass line in the display area and an input auxiliary line in the non-display area. According to some embodiments, the second data transmission line is directly electrically connected to the second demultiplexing circuit and is electrically connected to a path compensation capacitor in the sub-area.

[0023] According to some embodiments, the sub-region includes: a bending region, which is transformed into a bending shape; a first sub-region, between the main region and one side of the bending region; and a second sub-region, which is connected to the other side of the bending region. According to some embodiments, the display driving circuit is in the second sub-region. According to some embodiments, the circuit layer also includes: a power pad line, which extends from a portion of the signal pads in the second sub-region to the bending region. Each of the data transmission lines includes: a data output line, which is in the second sub-region and extends from the display driving circuit to the bending region; a data bending line, which is in the bending region and is electrically connected to the data output line; and a data input line, which is in the first sub-region and the non-display region and is electrically connected to the data bending line. According to some embodiments, the path compensation capacitor is electrically connected to the data output line of the second data transmission line.

[0024] According to some embodiments, the demultiplexing circuit further comprises a third demultiplexing circuit, and the third demultiplexing circuit is spaced farther from the edge of the substrate in the first direction than the second demultiplexing circuit. According to some embodiments, the data transmission line further comprises a third data transmission line that transmits a data multiplexing signal of the third demultiplexing circuit. According to some embodiments, the circuit layer further comprises: a first compensation capacitor electrode, in the second sub-region, overlapping with the power pad line and electrically connected to the data output line of the second data transmission line; and a second compensation capacitor electrode, in the second sub-region, overlapping with the power pad line and electrically connected to the data output line of the third data transmission line. According to some embodiments, the overlapping area between the second compensation capacitor electrode and the power pad line has a width greater than a width of the overlapping area between the first compensation capacitor electrode and the power pad line.

[0025] According to some embodiments, the path compensation capacitor is provided by an overlapping area between the power pad line and each of the data output line of the second data transmission line and the compensation capacitor electrode electrically connected to the data output line of the second data transmission line. According to some embodiments, the circuit layer includes: a first semiconductor layer on a substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a first source-drain conductive layer on the first interlayer insulating layer; and a first planarization layer covering the first source-drain conductive layer. According to some embodiments, the first source-drain conductive layer includes a data output line of each of the data transmission lines. According to some embodiments, one of the first gate conductive layer and the second gate conductive layer includes a power pad line. According to some embodiments, the other of the first gate conductive layer and the second gate conductive layer includes a compensation capacitor electrode.

[0026] According to some embodiments, the path compensation capacitor is provided by an overlapping area between the power pad line and each of the data output line of the second data transmission line and the compensation capacitor electrode electrically connected to the data output line of the second data transmission line. According to some embodiments, the circuit layer includes: a first semiconductor layer on a substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; a first interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer on the third gate insulating layer; a second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer on the second interlayer insulating layer; and a first planarizing layer covering the first source-drain conductive layer. According to some embodiments, the first source-drain conductive layer includes the data output line of each of the data transmission lines.

[0027] According to some embodiments, the compensation capacitor electrode comprises a first capacitor allocation electrode and a second capacitor allocation electrode in different conductive layers. According to some embodiments, the first gate conductive layer comprises the first capacitor allocation electrode. According to some embodiments, the second gate conductive layer comprises the power pad line. According to some embodiments, the third gate conductive layer comprises the second capacitor allocation electrode.

[0028] According to some embodiments, the power pad line includes a first pad distribution line and a second pad distribution line in different conductive layers. According to some embodiments, the first gate conductive layer includes the first pad distribution line. According to some embodiments, the second gate conductive layer includes the compensation capacitor electrode. According to some embodiments, the third gate conductive layer includes the second pad distribution line.

[0029] According to some embodiments, the display device may include a substrate, a circuit layer, and an element layer. According to some embodiments, the circuit layer may include: a light-emitting pixel driver, electrically connected to the light-emitting elements, respectively, and arranged in a first direction and a second direction; a data line, extending in the second direction, and outputting a data signal to the light-emitting pixel driver; a demultiplexing circuit, outputting a data signal of the data line based on a data multiplexing signal supplied from a display driving circuit; and a data transmission line, electrically connected between the display driving circuit and the demultiplexing circuit. According to some embodiments, the data transmission line may include: a first data transmission line, electrically connected to a first demultiplexing circuit adjacent to an edge of the substrate in the first direction; and a second data transmission line, transmitting a data multiplexing signal of a second demultiplexing circuit, the second demultiplexing circuit being spaced farther from the edge of the substrate in the first direction than the first demultiplexing circuit. According to some embodiments, the second data transmission line may be electrically connected to a path compensation capacitor.

[0030] That is, because the second demultiplexing circuit is located closer to the display driving circuit than the first demultiplexing circuit, the second data transmission line may have a shorter length than the first data transmission line.

[0031] According to some embodiments, the substrate may include: a main region including a display region in which the emission region is arranged and a non-display region around the display region; and a sub region protruding from one side of the main region.

[0032] According to some embodiments, the demultiplexing circuit may be in the non-display area, and the display driving circuit may be in the sub-area.

[0033] According to some embodiments, the first data transmission line may be electrically connected to the first demultiplexing circuit through a detour line in the display area and an input auxiliary line in the non-display area.

[0034] Therefore, due to the detour line and the input auxiliary line, a difference in length of a transmission path electrically connecting the display driving circuit to the first demultiplexing circuit and the second demultiplexing circuit may increase.

[0035] However, according to some embodiments, the second data transmission line may be electrically connected to the path compensation capacitor so that the brightness deviation caused by the length difference of the transmission path can be compensated. Therefore, the display quality of the display device can be relatively improved.

[0036] However, the characteristics of the embodiments of the present disclosure are not limited to the above-mentioned characteristics, and various other effects are included therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by describing aspects of some embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which: Figure 1 is a perspective view showing a display device according to some embodiments; Figure 2 is a diagram showing some embodiments of the present invention. Figure 1 A plan view of a display device; Figure 3 According to some embodiments, Figure 2 A cross-sectional view taken along line AA'; Figure 4 is a diagram showing some embodiments of the present invention. Figure 2 a layout diagram of part B; Figure 5 is a diagram showing some embodiments of the present invention. Figure 4 An equivalent circuit diagram of a light-emitting pixel driver; Figure 6 is a diagram showing some embodiments of the present invention. Figure 5 A cross-sectional view of the first transistor, the sixth transistor and the light emitting element shown in ; Figure 7 is a diagram showing some embodiments of the present invention. Figure 3 A plan view of the base; Figure 8 is a diagram showing some embodiments of the present invention. Figure 7 a layout diagram of part C; Fig. 9 According to some embodiments, Figure 8 A cross-sectional view taken along line D-D'; Fig.10 is a diagram showing some embodiments of the present invention. Figure 8 An equivalent circuit diagram of a transmission path between a display driving circuit and a first demultiplexing circuit; Fig.11 is a diagram showing some embodiments of the present invention. Figure 8An equivalent circuit diagram of a transmission path between a display driving circuit and a second demultiplexing circuit; Fig.12 is a diagram showing some embodiments of the present invention. Figure 8 a plan view of section E; Fig.13 According to some embodiments, Fig.12 A cross-sectional view taken along line G-G'; Fig.14 is a diagram showing some embodiments of the present invention. Figure 8 a plan view of section F; Fig.15 is a diagram showing some embodiments of the present invention. Figure 8 a plan view of section E; Fig.16 According to some embodiments, Fig.15 A cross-sectional view taken along line G-G'; Fig.17 is a diagram showing some embodiments of the present invention. Figure 4 An equivalent circuit diagram of a light-emitting pixel driver; Fig.18 is a diagram showing some embodiments of the present invention. Fig.17 A cross-sectional view of a first transistor, a second transistor, a fourth transistor, a sixth transistor and a light emitting element; Fig.19 is a diagram showing some embodiments of the present invention. Figure 7 a layout diagram of part C; Fig. 20 is a diagram showing some embodiments of the present invention. Fig.19 A plan view of a portion H of; Fig.21 According to some embodiments, Fig. 20 A cross-sectional view taken along line II'; Fig. 22 is a diagram showing some embodiments of the present invention. Fig.19 a plan view of part H of ; and Fig.23 According to some embodiments, Fig. 22 A cross-sectional view taken along line II'. DETAILED DESCRIPTION

[0038] Aspects of some embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout the present disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0039] Some of parts not related to the description may not be provided in order to describe the embodiments of the present disclosure.

[0040] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0041] In addition, the phrase "in a plan view" means when the target portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-section intercepted by vertically cutting the target portion is viewed from the side. The term "overlapping with..." or "overlapping" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlapping with..." can include layers, stacks, facing or facing, extending on, covering or partially covering, or any other suitable terms as will be appreciated and understood by those of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separate" or "biased" or "deviation" and any other suitable equivalents that will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, but still facing each other.

[0042] For ease of description, spatially relative terms such as "below", "under", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or assembly and another element or assembly as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are also intended to encompass different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned "below" or "below" another device may be placed "above" the other device. Therefore, the illustrative term "below" may include both lower and upper positions. The device may also be oriented in other directions, so spatially relative terms may be interpreted differently depending on the orientation.

[0043] When an element is referred to as being "connected" or "coupled" to another element, the element may be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms "comprises," "having," "including," and / or variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0044] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate their description and explanation. For example, when discussing a "first element" in the description, the "first element" may be referred to as a "second element" or a "third element," and the "second element" and "third element" may be named in a similar manner without departing from the spirit and scope of the present disclosure herein.

[0045] As used herein, the term "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements being discussed and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0046] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purpose of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or a disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for the purpose of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0047] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0048] Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view showing a display device according to some embodiments. Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'.

[0050] Reference Figure 1 and Figure 2 The display device 100 is a device for displaying a moving image (e.g., a video image) or a still image (e.g., a static image). The display device 100 can be used as a display screen for various medium and large electronic devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0051] The display device 100 may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micro or nano light-emitting diode (LED). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the embodiments according to the present disclosure are not limited thereto, and may be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

[0052] The display device 100 may be formed to be flat, but is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device 100 may be formed to be flexible so that it can be bent, folded, or rolled.

[0053] like Figure 1 , Figure 2 and Figure 3 As shown in , the display device 100 includes a substrate 110 .

[0054] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 and a sub area SBA protruding from one side of the main area MA.

[0055] like Figure 2 As shown in , the main area MA may include a display area DA located at most of its center and a non-display area NDA located around the display area DA (eg, in the periphery of the display area DA or outside the display area DA footprint).

[0056] In a plan view, the display area DA may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 crossing the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 meet may be rounded to have a curvature (e.g., a set or predetermined curvature) or may be right angles. The planar shape of the display area DA is not limited to a rectangular shape and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

[0057] The non-display area NDA may be located at an edge of the main area MA to surround the display area DA.

[0058] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA to one side in the second direction DR2.

[0059] Since a portion of the sub-area SBA is transformed into a bent shape, another portion of the sub-area SBA may be located on the rear surface of the display device 100 .

[0060] Figure 2 and Figure 3 The display device 100 is shown with a portion of the sub-area SBA in a bent state.

[0061] Reference Figure 3 According to some embodiments, the display device 100 includes a substrate 110 , a circuit layer 120 located on the substrate 110 , and a component layer 130 located on the circuit layer 120 .

[0062] The display device 100 according to some embodiments may further include an encapsulation layer 140 located on the element layer 130 and a touch sensor layer 150 located on the encapsulation layer 140 .

[0063] In addition, the display device 100 according to some embodiments may further include a polarization layer 160 on the touch sensor layer 150 to reduce reflection of external light.

[0064] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be formed of polyimide. The substrate 110 may be a flexible substrate that may be bent, folded, or rolled.

[0065] Alternatively, the substrate 110 may be formed of an insulating material such as glass.

[0066] The substrate 110 may include a main area MA and a sub area SBA. The main area MA may include a display area DA and a non-display area NDA.

[0067] Figure 4 It is shown Figure 2 Layout diagram of part B.

[0068] Reference Figure 4 According to some embodiments, the display area DA of the display device 100 may include the emission areas EA. In addition, the display area DA may further include a non-emission area located in a gap between the emission areas EA.

[0069] The light emitting pixel drivers EPD respectively corresponding to the emission areas EA may be arranged in parallel with each other in the first direction DR1 and the second direction DR2 in the display area DA. The light emitting pixel drivers EPD may be respectively electrically connected to the light emitting elements LE (see FIG. 1 ) of the element layer 130 respectively located in the emission areas EA. Figure 5 and Figure 6 ).

[0070] The emission area EA may have a rhombus shape or a rectangular shape in a plan view. However, this is only an example, and the planar shape of the emission area EA is not limited to Figure 4 That is, in a plan view, the emission area EA may have a polygonal shape such as a square, a pentagon, a hexagon, etc., or may have a circular or elliptical shape including edges of a curved line.

[0071] The emission area EA may include a first emission area EA1 that emits light of a first color in a band (e.g., a set or predetermined band), a second emission area EA2 that emits light of a second color in a band lower than the band of the first color, and a third emission area EA3 that emits light of a third color in a band lower than the band of the second color.

[0072] For example, the first color may be red having a wavelength of approximately 600 nm to 750 nm. The second color may be green having a wavelength of approximately 480 nm to 560 nm. The third color may be blue having a wavelength of approximately 370 nm to 460 nm.

[0073] The first emission regions EA1 and the third emission regions EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0074] The second emission regions EA2 may be arranged side by side in at least one of the first direction DR1 and the second direction DR2.

[0075] In addition, the second emission region EA2 may be adjacent to the first emission region EA1 and the third emission region EA3 in oblique directions DR4 and DR5 crossing the first direction DR1 and the second direction DR2 .

[0076] The pixel PX displaying its own brightness and color may be provided by the first emission area EA1 , the second emission area EA2 , and the third emission area EA3 adjacent to each other among the emission areas EA.

[0077] In other words, the pixel PX may be a basic unit for displaying various colors including white at brightness (eg, set or predetermined brightness).

[0078] Each of the pixels PX may include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other. Therefore, each of the pixels PX may display various colors by mixing the light emitted from the first emission area EA1, the second emission area EA2, and the third emission area EA3 adjacent to each other.

[0079] Figure 5 is a diagram showing some embodiments of the present invention. Figure 4 Equivalent circuit diagram of the light-emitting pixel driver.

[0080] Reference Figure 5 , one of the light emitting elements LE of the element layer 130 may be electrically connected between one of the light emitting pixel drivers EPD of the circuit layer 120 and the second power ELVSS.

[0081] That is, the anode electrode 131 (see Figure 6 ) can be electrically connected to the light emitting pixel driver EPD, and the cathode electrode 134 of the light emitting element LE (see Figure 6 ) may be applied with a second power ELVSS lower than the first power ELVDD.

[0082] The capacitor Cel connected in parallel with the light emitting element LE refers to a parasitic capacitance between the anode electrode 131 and the cathode electrode 134 .

[0083] The circuit layer 120 may further include a first power line VDL for transmitting the first power ELVDD and an initialization power line VIL for transmitting the initialization voltage VINT.

[0084] The circuit layer 120 may further include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, an emission control line ECL for transmitting an emission control signal EC, and a gate control line GCL for transmitting a gate control signal GC.

[0085] One light emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving the light emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1 , and at least one pixel capacitor PC1 .

[0086] The first transistor T1 is connected in series with the light emitting element LE between the first power ELVDD and the second power ELVSS.

[0087] That is, the first electrode (eg, source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through the fifth transistor T5. In addition, the second electrode (eg, drain electrode) of the first transistor T1 may be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor T6.

[0088] The first electrode of the first transistor T1 may be electrically connected to the data line DL through the second transistor T2 .

[0089] The gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the pixel capacitor PC1. That is, the pixel capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0090] Therefore, the potential of the gate electrode of the first transistor T1 may be maintained by the first power ELVDD of the first power line VDL.

[0091] When the data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2 , a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 may correspond to a voltage difference between the first power ELVDD and the data signal Vdata.

[0092] In this case, when a voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (ie, a gate-source voltage difference) becomes equal to or greater than a threshold voltage, the first transistor T1 may be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0093] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light emitting element LE between the first power line VDL and the second power line VSL. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as a driving current of the light emitting element LE.

[0094] Therefore, the light emitting element LE may emit light having brightness corresponding to the data signal Vdata.

[0095] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0096] The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by the scan write signal GW of the scan write line GWL.

[0097] The third transistor T3 may include a plurality of sub-transistors connected in series. For example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32. In this way, the potential of the gate electrode of the first transistor T1 can be prevented from changing due to leakage current through the cut-off third transistor T3.

[0098] The fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the initialization power line VIL. The fourth transistor T4 may be turned on by a scan initialization signal GI of the scan initialization line GIL.

[0099] The fourth transistor T4 may include a plurality of sub-transistors connected in series. For example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42. In this way, the potential of the gate electrode of the first transistor T1 can be prevented from changing due to leakage current through the cut-off fourth transistor T4.

[0100] The fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0101] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode 131 of the light emitting element LE.

[0102] The fifth transistor T5 and the sixth transistor T6 may be turned on by the emission control signal EC of the emission control line ECL.

[0103] The seventh transistor T7 may be electrically connected between the anode electrode 131 of the light emitting element LE and the initialization power line VIL. The seventh transistor T7 may be turned on by a gate control signal GC of the gate control line GCL.

[0104] like Figure 5 As shown in , the first transistor T1 to the seventh transistor T7 can be set as a P-type MOSFET. However, this is only an example, and some of the first transistor T1 to the seventh transistor T7 can be set as an N-type MOSFET. That is, according to other embodiments, the third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 can be set as an N-type MOSFET.

[0105] Figure 6 It is shown Figure 5 A cross-sectional view of a first transistor, a sixth transistor and a light emitting element shown in FIG.

[0106] Reference Figure 6 According to some embodiments, the display device 100 may include a substrate 110 , a circuit layer 120 on the substrate 110 , an element layer 130 on the circuit layer 120 , an encapsulation layer 140 on the element layer 130 , and a touch sensor layer 150 on the encapsulation layer 140 .

[0107] In addition, the display device 100 according to some embodiments may further include a polarization layer 160 located on the touch sensor layer 150 .

[0108] According to some embodiments, the touch sensor layer 150 may be located on a touch buffer layer covering the encapsulation layer 140 .

[0109] The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may include polyimide.

[0110] like Figure 6 As shown in, according to some embodiments, the circuit layer 120 may include: a first semiconductor layer CH1, S1, D1, CH6, S6 and D6, located on the substrate 110; a first gate insulating layer 122, covering the first semiconductor layer; a first gate conductive layer G1 and G6, located on the first gate insulating layer 122; a second gate insulating layer 123, covering the first gate conductive layer; a second gate conductive layer CAE, located on the second gate insulating layer 123; a first interlayer insulating layer 124, covering the second gate conductive layer; a first source-drain conductive layer ANDE1, located on the first interlayer insulating layer 124; a first planarizing layer 125, covering the first source-drain conductive layer; a second source-drain conductive layer ANDE2, located on the first planarizing layer 125; and a second planarizing layer 126, covering the second source-drain conductive layer.

[0111] According to some embodiments, the circuit layer 120 may further include a buffer layer 121 covering the substrate 110. In this case, the first semiconductor layer may be located on the buffer layer 121.

[0112] The circuit layer 120 may include light-emitting pixel drivers EPD electrically connected to the light-emitting elements LE located in the emission area EA, respectively, and wiring for transmitting various signals and voltages to the light-emitting pixel drivers EPD. The light-emitting pixel driver EPD may include a first transistor T1 and two or more of transistors T2 to T7 electrically connected to the first transistor T1.

[0113] According to some embodiments, the first transistor T1 may include a channel portion CH1, a source portion S1 and a drain portion D1 in a first semiconductor layer on a substrate 110, and a gate electrode G1 in a first gate conductive layer on a first gate insulating layer 122 covering the first semiconductor layer. The source portion S1 and the drain portion D1 may be connected to both ends of the channel portion CH1. The source portion S1 and the drain portion D1 may be doped at a higher concentration than the channel portion CH1. The gate electrode G1 may overlap the channel portion CH1.

[0114] Similarly, the sixth transistor T6 may include a channel portion CH6 , a source portion S6 and a drain portion D6 in the first semiconductor layer on the substrate 110 , and a gate electrode G6 in the first gate conductive layer on the first gate insulating layer 122 covering the first semiconductor layer.

[0115] According to some embodiments, the second to fifth transistors T2 to T5 and the seventh transistor T7 have substantially the same structure as the first transistor T1 and the sixth transistor T6 , and thus some redundant descriptions may be omitted below.

[0116] The pixel capacitor PC1 may be disposed as an overlapped region between the gate electrode G1 of the first transistor T1 and the pixel capacitor electrode CAE. The pixel capacitor electrode CAE may be located on the second gate conductive layer on the second gate insulating layer 123 covering the first gate conductive layer.

[0117] The anode electrode 131 of the element layer 130 may be electrically connected to the drain portion D6 of the sixth transistor T6 through the first anode connection electrode ANDE1 and the second anode connection electrode ANDE2 .

[0118] The first anode connection electrode ANDE1 may be located on the first source-drain conductive layer on the first interlayer insulating layer 124 covering the second gate conductive layer. The first anode connection electrode ANDE1 may be electrically connected to the drain portion D6 of the sixth transistor T6 through a first anode contact hole ANCT1 penetrating the first interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0119] The second anode connection electrode ANDE2 may be on the second source-drain conductive layer on the first planarization layer 125 covering the first source-drain conductive layer. The second anode connection electrode ANDE2 may be electrically connected to the first anode connection electrode ANDE1 through a second anode contact hole ANCT2 penetrating the first planarization layer 125.

[0120] The element layer 130 may include light emitting elements LE located on the second planarization layer 126 and corresponding to the emission areas EA, respectively.

[0121] Each of the light emitting elements LE may include an anode electrode 131 and a cathode electrode 134 facing each other, and a light emitting layer 133 between the anode electrode 131 and the cathode electrode 134 .

[0122] Optionally, each of the light emitting elements LE may further include a first common layer 135 located between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 located between the light emitting layer 133 and the cathode electrode 134 .

[0123] That is, the element layer 130 may include anode electrodes 131 respectively corresponding to the emission areas EA, pixel defining layers 132 corresponding to the non-emission areas NEA and covering the edges of the anode electrodes 131, light-emitting layers 133 respectively located on the anode electrodes 131, and cathode electrodes 134 located on the light-emitting layers 133 and the pixel defining layers 132.

[0124] The anode electrode 131 may be located in each of the emission areas EA, and may be electrically connected to one light emitting pixel driver EPD of the circuit layer 120. The anode electrode 131 may be referred to as a pixel electrode.

[0125] The anode electrode 131 may be electrically connected to the second anode connection electrode ANDE2 through a third anode contact hole ANCT3 penetrating the second planarization layer 126 .

[0126] The light emitting layer 133 may be formed of an organic light emitting material that converts electron-hole pairs into light.

[0127] The encapsulation layer 140 may be located on the circuit layer 120 and cover the element layer 130 .

[0128] The encapsulation layer 140 may include: a first encapsulation layer 141, which is located on the component layer 130 and is made of an inorganic insulating material; a second encapsulation layer 142, which is located on the first encapsulation layer 141, overlaps with the component layer 130, and is made of an organic insulating material; and a third encapsulation layer 143, which is located on the first encapsulation layer 141, covers the second encapsulation layer 142, and is made of an inorganic insulating material.

[0129] Figure 7 is a diagram showing some embodiments of the present invention. Figure 3 A plan view of the base.

[0130] Reference Figure 7 , the substrate 110 of the display device 100 according to some embodiments includes a main area MA corresponding to a display surface, and a sub area SBA protruding from one side of the main area MA.

[0131] The main area MA may include a display area DA located at most of the center, and a non-display area NDA located at the periphery to surround the display area DA.

[0132] The display area DA may include a detour area DEA located at one side adjacent to the sub area SBA, and a general area GA located in a remaining area except the detour area DEA.

[0133] The detour area DEA may include: a detour middle area MDDA, located at the center in the first direction DR1; a first detour side area SDA1, parallel to the detour middle area MDDA in the first direction DR1 and in contact with the non-display area NDA; and a second detour side area SDA2, located between the detour middle area MDDA and the first detour side area SDA1.

[0134] The first detour side area SDA1 may be positioned adjacent to a bending corner of the substrate 110 compared to the detour middle area MDDA and the second detour side area SDA2 .

[0135] The first and second detour side areas SDA1 and SDA2 may be located between the detour middle area MDDA and the non-display area NDA at both sides of the detour middle area MDDA in the first direction DR1 .

[0136] The general area GA may include: a general middle area GMA, a bypass middle area MDDA connected to the bypass area DEA in the second direction DR2; a first general side area GSA1, a first bypass side area SDA1 connected to the bypass area DEA in the second direction DR2; and a second general side area GSA2, a second bypass side area SDA2 connected to the bypass area DEA in the second direction DR2.

[0137] The non-display area NDA may include a gate driving circuit area GDRA where a gate driving circuit is located.

[0138] The gate driving circuit area GDRA may be located in a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1.

[0139] The gate driving circuit of the gate driving circuit area GDRA may sequentially transmit the gate signal to the gate line. Here, the gate line may include a transmission scanning write signal GW (see Figure 5 ) scan write line GWL (see Figure 5 ), transmission scanning initialization signal GI (see Figure 5 ) of the scan initialization line GIL (see Figure 5 ), transmission gate control signal GC (see Figure 5 ) of the gate control line GCL (see Figure 5 ), transmission bias control signal GB (see Figure 5 ) of the bias control line GBL (see Figure 5 ), and transmit the emission control signal EC (see Figure 5 ) of the emission control line ECL (see Figure 5 ).

[0140] The sub-region SBA may include a bent region BA transformed into a bent shape, a first sub-region SB1 between one side of the bent region BA and the main region MA, and a second sub-region SB2 connected to the other side of the bent region BA.

[0141] When the bent area BA is transformed into a bent shape, the second sub-area SB2 is located under the substrate 110 and overlaps the main area MA.

[0142] The display driving circuit 200 may be located in the second sub-region SB2 .

[0143] bonded to the circuit board 300 (see Figure 1 ) may be located at one edge of the second sub-region SB2.

[0144] Figure 8 is a diagram showing some embodiments of the present invention. Figure 7 Layout diagram of part C. Fig. 9 It is along Figure 8 A cross-sectional view taken along line D-D'. Fig.10 It is shown Figure 8 An equivalent circuit diagram of a transmission path between a display driving circuit and a first demultiplexing circuit. Fig.11 It is shown Figure 8 An equivalent circuit diagram of a transmission path between a display driving circuit and a second demultiplexing circuit.

[0145] Reference Figure 8 According to some embodiments, the circuit layer 120 of the display device 100 may include: a light-emitting pixel driver EPD arranged in the first direction DR1 and the second direction DR2 and electrically connected to the light-emitting elements LE of the element layer 130; a data line DL extending in the second direction DR2 and transmitting a data signal Vdata (see Figure 5 ) is transmitted to the light-emitting pixel driver EPD; a demultiplexing circuit DMC is located in the non-display area NDA, and outputs a data signal Vdata of the data line DL based on the data multiplexing signal supplied from the display driving circuit 200; and a data transmission line DSPL is electrically connected between the display driving circuit 200 and the demultiplexing circuit DMC, and transmits the data multiplexing signal of the demultiplexing circuit DMC, respectively.

[0146] The demultiplexing circuit DMC may include a first demultiplexing circuit DMC1 located adjacent to an edge of the substrate 110 in the first direction DR1 and a second demultiplexing circuit DMC2 spaced farther from the edge of the substrate 110 than the first demultiplexing circuit DMC1 in the first direction DR1.

[0147] The data lines DL may include a first data line DL1 in a first detour side area SDA1 adjacent to an edge of the substrate 110 in the first direction DR1 and a second data line DL2 in a second detour side area SDA2 between the first detour side area SDA1 and the detour middle area MDDA.

[0148] The first data line DL1 may be electrically connected to an output terminal (eg, a demultiplexing output line) of the first demultiplexing circuit DMC1 .

[0149] The second data line DL2 may be electrically connected to an output terminal (eg, a demultiplexing output line) of the second demultiplexing circuit DMC2 .

[0150] The data transmission line DSPL may include: a first data transmission line DSPL1, which transmits a data multiplexing signal of the first demultiplexing circuit DMC1 and is electrically connected to an input terminal of the first demultiplexing circuit DMC1; and a second data transmission line DSPL2, which transmits a data multiplexing signal of the second demultiplexing circuit DMC2 and is electrically connected to an input terminal of the second demultiplexing circuit DMC2.

[0151] The data transmission line DSPL may extend to a portion of the non-display area NDA between the sub-area SBA and the second detour side area SDA2 and the detour middle area MDDA.

[0152] That is, the first data transmission line DSPL1 transmitting the data multiplexing signal of the first demultiplexing circuit DMC1 may extend to the second detour side area SDA2 instead of extending to the first demultiplexing circuit DMC1 adjacent to the first detour side area SDA1.

[0153] Therefore, the first data transmission line DSPL1 may be located adjacent to the second demultiplexing circuit DMC2 .

[0154] As an example, one first data transmission line DSPL1 may extend between two adjacent second demultiplexing circuits DMC2 .

[0155] In addition, the first data transmission line DSPL1 may be electrically connected to the input terminal of the first demultiplexing circuit DMC1 through the detour auxiliary line TASL located in the display area DA and the input auxiliary line IPAL located in the non-display area NDA.

[0156] On the other hand, the second data transmission line DSPL2 may be directly electrically connected to the second demultiplexing circuit DMC2.

[0157] The detour auxiliary line TASL may include: a first detour auxiliary line TASL1, extending in the second direction DR2, paired with one of the second data lines DL2 connected to the second demultiplexing circuit DMC2, and electrically connected to the first data transmission line DSPL1; a second detour auxiliary line TASL2, extending in the first direction DR1, and electrically connected to the first detour auxiliary line TASL1; and a third detour auxiliary line TASL3, extending in the second direction DR2, paired with one of the first data lines DL1 connected to the first demultiplexing circuit DMC1, and electrically connected to the second detour auxiliary line TASL2.

[0158] The input auxiliary line IPAL may electrically connect the third detour auxiliary line TASL3 to the input terminal of the first demultiplexing circuit DMC1 .

[0159] The first detour auxiliary line TASL1 may extend in the second direction DR2 between the first data transmission line DSPL1 and the second detour auxiliary line TASL2 .

[0160] Since the first detour auxiliary line TASL1 is paired with one of the second data lines DL2 electrically connected to the output terminal of the second demultiplexing circuit DMC2 , the first data transmission line DSPL1 may be positioned adjacent to the second demultiplexing circuit DMC2 .

[0161] The second detour auxiliary line TASL2 may extend in the first direction DR1 between the first detour auxiliary line TASL1 and the third detour auxiliary line TASL3 .

[0162] The third detour auxiliary line TASL3 may extend in the second direction DR2 between the second detour auxiliary line TASL2 and the input auxiliary line IPAL.

[0163] According to some embodiments, the circuit layer 120 may further include first auxiliary lines ASL1 extending in the first direction DR1 , and second auxiliary lines ASL2 extending in the second direction DR2 and respectively paired with the data lines DL.

[0164] The first auxiliary lines ASL1 may overlap the light emitting pixel driver EPD of the display area DA. That is, the number of the first auxiliary lines ASL1 may be the number of columns each including the emission areas EA arranged in the first direction DR1.

[0165] The data lines DL and the second auxiliary lines ASL2 may be alternately arranged one by one in the first direction DR1.

[0166] The second auxiliary line ASL2 may include a first detour auxiliary line TASL1 and a third detour auxiliary line TASL3 extending in the second direction DR2 among the detour auxiliary lines TASL.

[0167] The first auxiliary line ASL1 may include a second detour auxiliary line TASL2 extending in the first direction DR1 among the detour auxiliary lines TASL.

[0168] In addition, in order to reduce the visibility of each of the first, second and third detour auxiliary lines TASL1, TASL2 and TASL3, the first auxiliary line ASL1 may further include a power assist horizontal line VASHL and the second auxiliary line ASL2 may further include a power assist vertical line VASVL.

[0169] The power-assist horizontal line VASHL and the power-assist vertical line VASVL may transmit at least one of the first power ELVDD, the second power ELVSS, and the initialization voltage VINT. As an example, the power-assist horizontal line VASHL and the power-assist vertical line VASVL may transmit the second power ELVSS. In another example, some of the power-assist horizontal lines VASHL and some of the power-assist vertical lines VASVL may transmit the second power ELVSS, and other of the power-assist horizontal lines VASHL and other of the power-assist vertical lines VASVL may transmit the initialization voltage VINT.

[0170] Reference Figure 8 and Fig. 9 , the data lines DL and the second auxiliary lines ASL2 (TASL1 , TASL3 , and VASVL) may be located on the first planarization layer 125 covering the first auxiliary lines ASL1 (TASL2 and VASHL).

[0171] As an example, the first auxiliary line ASL1 may be located in a first source-drain conductive layer on the first interlayer insulating layer 124 , and the data line DL and the second auxiliary line ASL2 may be located in a second source-drain conductive layer on the first planarization layer 125 covering the first source-drain conductive layer.

[0172] The second detour auxiliary line TASL2 may be electrically connected to each of the first and third detour auxiliary lines TASL1 and TASL3 through a connection hole penetrating the first planarization layer 125 .

[0173] According to some embodiments, the data transmission line DSPL and the input auxiliary line IPAL may be located in the first gate conductive layer on the first gate insulating layer 122 or in the second gate conductive layer on the second gate insulating layer 123 .

[0174] like Figure 8As shown in , according to some embodiments, the demultiplexing circuit DMC may further include a third demultiplexing circuit DMC3 spaced farther from the edge of the substrate 110 in the first direction DR1 than the second demultiplexing circuit DMC2 .

[0175] The data transmission line DSPL may further include a third data transmission line DSPL3 transmitting a data multiplexing signal of the third demultiplexing circuit DMC3 and electrically connected to an input terminal of the third demultiplexing circuit DMC3 .

[0176] The data lines DL may further include a third data line DL3 located in the detour middle area MDDA.

[0177] The third data line DL3 may be electrically connected to an output terminal of the third demultiplexing circuit DMC3 .

[0178] According to some embodiments, the data transmission lines DSPL1, DSPL2 and DSPL3 may include: data output lines DOPL1, DOPL2 and DOPL3, which are located in the second sub-area SB2 and extend from the display driving circuit 200 to the bending area BA; data bending lines DBDL1, DBDL2 and DBDL3, which are located in the bending area BA and are electrically connected to the data output lines DOPL1, DOPL2 and DOPL3; and data input lines DIPL1, DIPL2 and DIPL3, which are located in the first sub-area SB1 and the non-display area NDA and are electrically connected to the data bending lines DBDL1, DBDL2 and DBDL3, respectively.

[0179] The data input line DIPL1 of the first data transmission line DSPL1 may be electrically connected to the first detour auxiliary line TASL1 .

[0180] The data input line DIPL2 of the second data transmission line DSPL2 may be electrically connected to the input terminal of the second demultiplexing circuit DMC2 , and the data input line DIPL3 of the third data transmission line DSPL3 may be electrically connected to the input terminal of the third demultiplexing circuit DMC3 .

[0181] According to some embodiments, the circuit layer 120 may further include a signal pad SPD (see Figure 7 ) extends to the power pad lines VDPDL and VSPDL of the bending area BA from a portion of the signal pad SPD transmitting the first power ELVDD and the second power ELVSS.

[0182] The power pad lines VDPDL and VSPDL may include a first power pad line VDPDL for transmitting the first power ELVDD and a second power pad line VSPDL for transmitting the second power ELVSS.

[0183] In addition, the circuit layer 120 may further include: power bending lines VDBDL and VSBDL, which are located in the bending area BA and are electrically connected to the power pad lines VDPDL and VSPDL; and power supply lines VDSPL and VSSPL, which are located in the non-display area NDA and the first sub-area SB1 and are electrically connected to the power bending lines VDBDL and VSBDL.

[0184] The power bending lines VDBDL and VSBDL may include a first power bending line VDBDL electrically connected to the first power pad line VDPDL, and a second power bending line VSBDL electrically connected to the second power pad line VSPDL.

[0185] The power lines VDSPL and VSSPL may include a first power line VDSPL electrically connected to the first power bending line VDBDL, and a second power line VSSPL electrically connected to the second power bending line VSBDL.

[0186] According to some embodiments, the data transmission line DSPL may extend only to a portion of the non-display area NDA between the sub-area SBA and the second detour side area SDA2 and the detour middle area MDDA.

[0187] That is, the second data transmission line DSPL2 may extend to the second demultiplexing circuit DMC2 , and the third data transmission line DSPL3 may extend to the third demultiplexing circuit DMC3 .

[0188] In addition, the first data transmission line DSPL1 may extend to the first detour auxiliary line TASL1 paired with the second data line DL2 of the second detour side area SDA2 instead of extending to the first demultiplexing circuit DMC1.

[0189] In this manner, the extension length of the data transmission line DSPL may be reduced, which may be advantageous in reducing the width of the non-display area NDA.

[0190] However, since the first data transmission line DSPL1 is electrically connected to the first demultiplexing circuit DMC1 through the detour auxiliary line TASL and the input auxiliary line IPAL, the transmission path between the first demultiplexing circuit DMC1 and the display driving circuit 200 includes the detour auxiliary line TASL and the input auxiliary line IPAL in addition to the first data transmission line DSPL1.

[0191] On the other hand, since the second data transmission line DSPL2 is directly electrically connected to the second demultiplexing circuit DMC2 , the transmission path between the second demultiplexing circuit DMC2 and the display driving circuit 200 includes only the second data transmission line DSPL2 .

[0192] That is, the transmission path between the second demultiplexing circuit DMC2 and the display driving circuit 200 has a shorter length than the transmission path between the first demultiplexing circuit DMC1 and the display driving circuit 200. Therefore, as the difference in the length of the transmission path between the demultiplexing circuit DMC and the display driving circuit 200 increases, the deviation of the data signal Vdata transmitted to the data line DL increases, thereby causing a brightness deviation.

[0193] To prevent this, according to some embodiments, the second data transmission line DSPL2 may be electrically connected to the path compensation capacitor Ccmp (see Fig.11 ).

[0194] Reference Fig.10 and Fig.11 , each of the demultiplexing circuits DMC may include two or more demultiplexing transistors TDM1 and TDM2 electrically connected between the display driving circuit 200 and the two or more data lines DL, respectively.

[0195] In each of the demultiplexing circuits DMC, two or more demultiplexing transistors TDM1 and TDM2 may be turned on in different periods so that a data multiplexing signal supplied from the display driving circuit 200 may be time-divided by the demultiplexing circuit DMC and supplied as data signals to two or more data lines DL.

[0196] As an example, each of the demultiplexing circuits DMC may include a first demultiplexing transistor TDM1 turned on by a first demultiplexing control signal SCS1 , and a second demultiplexing transistor TDM2 turned on by a second demultiplexing control signal SCS2 .

[0197] According to some embodiments, the input terminal of the first demultiplexing circuit DMC1 may be electrically connected to the first data transmission line DSPL1 through the bypass auxiliary line TASL and the input auxiliary line IPAL.

[0198] Therefore, if Fig.10 As shown in FIG. 1 , the capacitance of the transmission path between the first demultiplexing circuit DMC1 and the display driving circuit 200 may include a capacitance Cs due to the first data transmission line DSPL1 and a capacitance Ct due to the detour auxiliary line TASL and the input auxiliary line IPAL.

[0199] Meanwhile, an input terminal of the second demultiplexing circuit DMC2 may be directly electrically connected to the second data transmission line DSPL2 .

[0200] If the capacitance of the transmission path between the second demultiplexing circuit DMC2 and the display driving circuit 200 only includes the capacitance Cs caused by the second data transmission line DSPL2, the deviation of signal distortion caused by the transmission path between the demultiplexing circuit DMC and the display driving circuit 200 will increase, resulting in large brightness deviation.

[0201] However, if Fig.11 As shown in , according to some embodiments, the second data transmission line DSPL2 is electrically connected to the path compensation capacitor Ccmp.

[0202] In this way, because the capacitance of the transmission path between the second demultiplexing circuit DMC2 and the display driving circuit 200 includes the capacitance of the path compensation capacitor Ccmp in addition to the capacitance Cs caused by the second data transmission line DSPL2, the capacitance of the transmission path between the second demultiplexing circuit DMC2 and the display driving circuit 200 can be compensated to be approximately the capacitance of the transmission path between the first demultiplexing circuit DMC1 and the display driving circuit 200.

[0203] Therefore, a deviation of signal distortion caused by a transmission path between the demultiplexing circuit DMC and the display driving circuit 200 may become smaller, and thus a brightness deviation may be reduced.

[0204] According to some embodiments, the path compensation capacitor Ccmp may be located in the second sub-region SB2 of the sub-region SBA In this manner, an increase in the width of the non-display area NDA due to the placement of the path compensation capacitor Ccmp may be prevented.

[0205] In the following, reference is made to Figures 12 to 16 , the path compensation capacitor Ccmp according to each embodiment will be described.

[0206] exist Figures 12 to 16 In the present invention, for simplicity of description, the case where the power pad line is the first power pad line VDPDL will be described by way of example. However, this is only an example, and the power pad line may be any wiring to which a constant voltage (such as the first power ELVDD, the second power ELVSS, and the initialization voltage VINT) is applied and located in the second sub-region SB2.

[0207] Fig.12 is a diagram showing some embodiments of the present invention. Figure 8 Floor plan of Section E. Fig.13 It is along Fig.12 A cross-sectional view taken along line G-G'.

[0208] Reference Fig.12The circuit layer 120 according to some embodiments may further include a compensation capacitor electrode CCE located in the second sub-region SB2 and electrically connected to the data output line DOPL2 of the second data transmission line DSPL2.

[0209] The compensation capacitor electrode CCE may be electrically connected to the data output line DOPL2 of the second data transmission line DSPL2 through at least one capacitor auxiliary contact hole CACT.

[0210] The first power pad line VDPDL may overlap the compensation capacitor electrode CCE and the second data transmission line DSPL2. Therefore, the path compensation capacitor Ccmp may be provided by an overlapping area between the first power pad line VDPDL and each of the data output line DOPL2 of the compensation capacitor electrode CCE and the second data transmission line DSPL2.

[0211] As an example, the compensation capacitor electrode CCE electrically connected to the data output line DOPL2 of the second data transmission line DSPL2 may be positioned with a first width CW1 and a first length CL1.

[0212] The capacitance of the path compensation capacitor Ccmp may correspond to the width of an overlapping region between the compensation capacitor electrode CCE and the first power pad line VDPDL.

[0213] like Fig.13 As shown in , according to some embodiments, the data output line DOPL2 of the second data transmission line DSPL2 may be located in the first source-drain conductive layer on the first interlayer insulating layer 124 .

[0214] That is, the first source-drain conductive layer on the first interlayer insulating layer 124 may include the data output lines DOPL1 , DOPL2 , and DOPL3 of the data transmission line DSPL.

[0215] In addition, the first gate conductive layer on the first gate insulating layer 122 may include a first power pad line VDPDL.

[0216] The second gate conductive layer on the second gate insulating layer 123 may include a compensation capacitor electrode CCE.

[0217] In this case, the capacitor auxiliary contact hole CACT for electrical connection between the data output line DOPL2 of the second data transmission line DSPL2 and the compensation capacitor electrode CCE may penetrate the first interlayer insulating layer 124 .

[0218] Fig.14 is a diagram showing some embodiments of the present invention. Figure 8 Floor plan of Section F.

[0219] As previously in Figure 8 As shown in FIG. 1 , the third data transmission line DSPL3 transmitting the data multiplexed signal of the third demultiplexing circuit DMC3 electrically connected to the third data line DL3 detouring the middle area MDDA is directly electrically connected to the input terminal of the third demultiplexing circuit DMC3 .

[0220] Therefore, according to some embodiments, in order to reduce a deviation of signal distortion caused by a transmission path between the display driving circuit 200 and the demultiplexing circuit DMC, the third data transmission line DSPL3 may be electrically connected to the path compensation capacitor Ccmp.

[0221] Reference Fig.14 , the path compensation capacitor Ccmp electrically connected to the third data transmission line DSPL3 and Fig.12 and Fig.13 The path compensation capacitor Ccmp electrically connected to the second data transmission line DSPL2 shown in FIG. 1 is substantially the same except that the data output line DOPL3 electrically connected to the third data transmission line DSPL3 is located with a second width CW2 and a second length CL2. Therefore, some redundant descriptions may be omitted below.

[0222] According to some embodiments, the third demultiplexing circuit DMC3 is spaced farther from the edge of the substrate 110 in the first direction DR1 than the second demultiplexing circuit DMC2. In other words, the third demultiplexing circuit DMC3 is positioned closer to the display driving circuit 200 than the second demultiplexing circuit DMC2, so that the extension length of the third data transmission line DSPL3 may be shorter than the extension length of the second data transmission line DSPL2.

[0223] As a result, the capacitance of the transmission path between the third demultiplexing circuit DMC3 and the display driving circuit 200 may be smaller than the capacitance of the transmission path between the second demultiplexing circuit DMC2 and the display driving circuit 200 .

[0224] To compensate for this, according to some embodiments, when the data output line DOPL2 of the second data transmission line DSPL2 is electrically connected to the first path compensation capacitor, the data output line DOPL3 of the third data transmission line DSPL3 can be electrically connected to a second path compensation capacitor having a capacitance greater than that of the first path compensation capacitor.

[0225] like Fig.12 As shown in FIG. 1 , the compensation capacitor electrode CCE of the first path compensation capacitor electrically connected to the data output line DOPL2 of the second data transmission line DSPL2 may be positioned with a first width CW1 and a first length CL1 .

[0226] On the other hand, Fig.14As shown in FIG. 1 , the compensation capacitor electrode CCE of the second path compensation capacitor electrically connected to the data output line DOPL3 of the third data transmission line DSPL3 may be positioned with a second width CW2 and a second length CL2 .

[0227] The second width CW2 may be greater than or equal to the first width CW1.

[0228] The second length CL2 may be greater than or equal to the first length CL1 .

[0229] Furthermore, although not separately shown, according to some embodiments, as the length of the transmission path between the display driving circuit 200 and the demultiplexing circuit DMC is shorter, a path compensation capacitor Ccmp of greater capacitance may be electrically connected to the data transmission line DSPL.

[0230] In this manner, due to the path compensation capacitor Ccmp, it is possible to prevent a deviation in signal distortion caused by the transmission path between the display driving circuit 200 and the demultiplexing circuit DMC from occurring.

[0231] At the same time, according to Fig.12 , Fig.13 and Fig.14 In some embodiments shown in , the compensation capacitor electrode CCE is located in the second gate conductive layer on the second gate insulating layer 123, and the first power pad line VDPDL is located in the first gate conductive layer on the first gate insulating layer 122. However, this is only an example, and according to some embodiments, any modification may be made as long as the compensation capacitor electrode CCE, the first power pad line VDPDL, and the data output lines DOPL1, DOPL2, and DOPL3 are located in different conductive layers. That is, the compensation capacitor electrode CCE may be located in one of the first gate conductive layer and the second gate conductive layer, and the first power pad line VDPDL may be located in the other of the first gate conductive layer and the second gate conductive layer. In other words, the compensation capacitor electrode CCE may be located in the first gate conductive layer on the first gate insulating layer 122, and the first power pad line VDPDL may be located in the second gate conductive layer on the second gate insulating layer 123.

[0232] Fig.15 is a diagram showing some embodiments of the present invention. Figure 8 Floor plan of Section E. Fig.16 It is along Fig.15 A cross-sectional view taken along line G-G'.

[0233] like Fig.15 and Fig.16 The display device 100 according to some embodiments shown in FIG. Figures 1 to 14The display device 100 of the embodiment shown in FIG. 1 is substantially the same except that the compensation capacitor electrode CCE is located in the first gate conductive layer on the first gate insulating layer 122, and the first power pad line VDPDL is located in the second gate conductive layer on the second gate insulating layer 123. Therefore, some redundant descriptions may be omitted below.

[0234] Meanwhile, as described above, some of the transistors in each of the light emitting pixel drivers EPD may be set as N-type MOSFETs, and the other of the transistors in each of the light emitting pixel drivers EPD may be set as P-type MOSFETs.

[0235] Fig.17 It is shown that according to other embodiments Figure 4 Equivalent circuit diagram of the light-emitting pixel driver.

[0236] Reference Fig.17 According to other embodiments, the light emitting pixel driver EPD and Figure 5 The light emitting pixel driver EPD of the embodiment shown in is substantially the same except that it further includes an eighth transistor T8 electrically connected between the first electrode of the first transistor T1 and a bias line VBL for transmitting a bias voltage VBS, and the third transistor T3 and the fourth transistor T4 are configured as N-type MOSFETs. Therefore, some redundant descriptions may be omitted below.

[0237] The second transistor T2 and the third transistor T3 are turned on by different signals. Specifically, the second transistor T2 may be turned on by the scan write signal GW of the scan write line GWL, and the third transistor T3 may be turned on by the gate control signal GC of the gate control line GCL.

[0238] The fourth transistor T4 may be electrically connected between the gate electrode of the first transistor T1 and a gate initialization voltage line VGIL for transmitting a gate initialization voltage VGINT.

[0239] The fourth transistor T4 may be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0240] The seventh transistor T7 may be electrically connected between the anode electrode 131 of the light emitting element LE and an anode initialization voltage line VAIL for transmitting an anode initialization voltage VAINT.

[0241] The seventh transistor T7 may be turned on by the bias control signal GB of the bias control line GBL.

[0242] The eighth transistor T8 may be turned on by the bias control signal GB of the bias control line GBL. Through the turned-on eighth transistor T8, the potential of the first electrode of the first transistor T1 may be maintained at the bias voltage VBS.

[0243] Fig.18 It is shown Fig.17 A cross-sectional view of a first transistor, a second transistor, a fourth transistor, a sixth transistor and a light-emitting element.

[0244] Reference Fig.18 According to other embodiments, the circuit layer 120 of the display device 100 and Figure 6 The circuit layer 120 of the embodiment shown in FIG. 1 is substantially the same, except that it further includes: a second semiconductor layer CH4, S4 and D4 located on the first interlayer insulating layer 124; a third gate insulating layer 127 covering the second semiconductor layer; a third gate conductive layer G4 located on the third gate insulating layer 127; and a second interlayer insulating layer 128 covering the third gate conductive layer, and a first source-drain conductive layer located on the second interlayer insulating layer 128. Therefore, some redundant descriptions may be omitted below.

[0245] According to other embodiments, in order to be set to a type different from the first transistor T1, the second transistor T2 and the sixth transistor T6, the fourth transistor T4 may include a channel portion CH4, a source portion S4 and a drain portion D4 in the second semiconductor layer located on the first interlayer insulating layer 124, and a gate electrode G4 in the third gate conductive layer located on the third gate insulating layer 127.

[0246] The first source-drain conductive layer on the second interlayer insulating layer 128 may further include a gate initialization voltage line VGIL, a gate connection electrode GCNE, and a data connection electrode DCE.

[0247] The gate initialization voltage line VGIL may be electrically connected to the source portion S4 of the fourth transistor T4 through the initialization connection hole VICH.

[0248] The gate connection electrode GCNE may be electrically connected to the drain portion D4 of the fourth transistor T4 through the first gate connection hole GCH1 , and may be electrically connected to the gate electrode G1 of the first transistor T1 through the second gate connection hole GCH2 .

[0249] The second source-drain conductive layer on the first planarization layer 125 may include the data line DL.

[0250] The data line DL may be electrically connected to the data connection electrode DCE through the data connection hole DCH.

[0251] The data connection electrode DCE may be electrically connected to the source portion S2 of the second transistor T2 through the data auxiliary connection hole DCAH. The second transistor T2 may include a channel portion CH2, a source portion S2, and a drain portion D2 in a first semiconductor layer on the substrate 110, and a gate electrode G2 in a first gate conductive layer on a first gate insulating layer 122 covering the first semiconductor layer.

[0252] According to other embodiments, the circuit layer 120 may further include a first light blocking layer LB1 located on the substrate 110 and overlapping with the channel portion CH1 of the first transistor T1, and a second light blocking layer LB2 located in the second gate conductive layer on the second gate insulating layer 123 and overlapping with the channel portion CH4 of the fourth transistor T4.

[0253] Fig.19 It is shown that according to other embodiments Figure 7 Layout diagram of part C.

[0254] Reference Fig.19 According to other embodiments, the display device 100 and Figure 8 The display device of the embodiment shown in FIG. 1 is substantially the same, except that the data lines DL and the second auxiliary lines ASL2 are alternately arranged in pairs in the first direction DR1, and two first data transmission lines DSPL1 extend between two adjacent second demultiplexing circuits DMC2. Therefore, some redundant descriptions may be omitted below.

[0255] Fig. 20 is a diagram showing some embodiments of the present invention. Fig.19 Plan view of section H. Fig.21 It is along Fig. 20 A cross-sectional view taken along line II'.

[0256] According to Fig. 20 and Fig.21 In some embodiments shown in FIG. 1 , the compensation capacitor electrode CCE may include a first capacitor sharing electrode CCPE1 and a second capacitor sharing electrode CCPE2 located in different conductive layers.

[0257] The first capacitor distribution electrode CCPE1 may be located in the first gate conductive layer on the first gate insulating layer 122 and may be electrically connected to the data output line DOPL2 of the second data transmission line DSPL2 through at least one first capacitor auxiliary contact hole CACT1. The at least one first capacitor auxiliary contact hole CACT1 may penetrate the second interlayer insulating layer 128, the third gate insulating layer 127, the first interlayer insulating layer 124, and the second gate insulating layer 123.

[0258] The second capacitor sharing electrode CCPE2 may be located in the third gate conductive layer on the third gate insulating layer 127 and may be electrically connected to the data output line DOPL2 of the second data transmission line DSPL2 through at least one second capacitor auxiliary contact hole CACT2. The at least one second capacitor auxiliary contact hole CACT2 may penetrate the second interlayer insulating layer 128.

[0259] The first power pad line VDPDL may be located in the second gate conductive layer on the second gate insulating layer 123 .

[0260] Therefore, the path compensation capacitor Ccmp may be provided by the overlapping area between the first capacitor sharing electrode CCPE1 and the first power pad line VDPDL and the overlapping area between the second capacitor sharing electrode CCPE2 and the first power pad line VDPDL. Therefore, it may become easy to provide a larger capacity path compensation capacitor Ccmp.

[0261] Fig. 22 is a diagram showing some embodiments of the present invention. Fig.19 Plan view of section H. Fig.23 It is along Fig. 22 A cross-sectional view taken along line II'.

[0262] According to Fig. 22 and Fig.23 In some embodiments shown in , the first power pad line VDPDL may include a first pad distribution line PDPL1 and a second pad distribution line PDPL2 located in different conductive layers.

[0263] The first pad distribution line PDPL1 may be located in the first gate conductive layer on the first gate insulating layer 122 .

[0264] The second pad distribution line PDPL2 may be located in the third gate conductive layer on the third gate insulating layer 127 .

[0265] The second pad distribution line PDPL2 may be electrically connected to the first pad distribution line PDPL1 through a power assist connection hole VCT. The power assist connection hole VCT may penetrate the third gate insulating layer 127, the first interlayer insulating layer 124, and the second gate insulating layer 123.

[0266] The compensation capacitor electrode CCE may be located in the second gate conductive layer on the second gate insulating layer 123 .

[0267] Therefore, the path compensation capacitor Ccmp can be provided by the overlapping area between the first pad distribution line PDPL1 and the compensation capacitor electrode CCE, the overlapping area between the second pad distribution line PDPL2 and the compensation capacitor electrode CCE, and the overlapping area between the second pad distribution line PDPL2 and the data output line DOPL2 of the second data transmission line DSPL2.

[0268] Therefore, it may become easier to provide a path compensation capacitor Ccmp of a larger capacity.

[0269] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the appended claims and their equivalents.

Claims

1. A display device, comprising: substrate; a circuit layer on the substrate; as well as A component layer, on the circuit layer, The substrate includes: a main area including a display area in which an emission area is arranged and a non-display area around the display area; and a sub-area protruding from one side of the main area. The element layer includes light emitting elements respectively in the emission regions, and The circuit layer includes: light-emitting pixel drivers electrically connected to the light-emitting elements, respectively, and arranged in a first direction and a second direction; data lines extending in the second direction and transmitting data signals to the light-emitting pixel drivers; a demultiplexing circuit in the non-display area and configured to output the data signals of the data lines based on a data multiplexing signal supplied from a display driving circuit; and data transmission lines electrically connected between the display driving circuit and the demultiplexing circuit and configured to transmit the data multiplexing signals of the demultiplexing circuit, respectively. The data transmission line comprises: a first data transmission line electrically connected to a first demultiplexing circuit adjacent to an edge of the substrate in the first direction; and a second data transmission line electrically connected to a second demultiplexing circuit, the second demultiplexing circuit being spaced farther from the edge of the substrate in the first direction than the first demultiplexing circuit. Wherein, the second data transmission line is electrically connected to the path compensation capacitor in the sub-region.

2. The display device according to claim 1, wherein: The data line comprises: a first data line electrically connected to a demultiplexed output line of the first demultiplexing circuit; and a second data line electrically connected to a demultiplexed output line of the second demultiplexing circuit, The circuit layer further includes: a first detour auxiliary line extending in the second direction, paired with one of the second data lines, and electrically connected to the first data transmission line; a second detour auxiliary line extending in the first direction, and electrically connected to the first detour auxiliary line; a third detour auxiliary line extending in the second direction, paired with one of the first data lines, and electrically connected to the second detour auxiliary line; and an input auxiliary line in the non-display area, and electrically connected between the third detour auxiliary line and the first demultiplexing circuit, and The second data transmission line is directly electrically connected to the second demultiplexing circuit.

3. The display device according to claim 2, wherein: The sub-regions include: a curved region having a curved shape; a first sub-region between the main region and one side of the curved region; and a second sub-region connected to the other side of the curved region. The display driving circuit is in the second sub-area, The circuit layer further includes: a power pad line extending from a portion of the signal pads in the second sub-area to the bending area, and Each of the data transmission lines includes: a data output line in the second sub-area and extending from the display driving circuit to the bending area; a data bending line in the bending area and electrically connected to the data output line; and a data input line in the first sub-area and the non-display area and electrically connected to the data bending line. Wherein, the path compensation capacitor is electrically connected to the data output line of the second data transmission line.

4. The display device according to claim 3, wherein: The data transmission line further includes: a third data transmission line electrically connected to a third demultiplexing circuit, the third demultiplexing circuit being spaced farther from the edge of the substrate in the first direction than the second demultiplexing circuit, The data output line of the second data transmission line is electrically connected to a first path compensation capacitor, and The data output line of the third data transmission line is electrically connected to a second path compensation capacitor having a capacitance greater than that of the first path compensation capacitor and in the sub-region.

5. The display device according to claim 3, wherein: The circuit layer further includes: a compensation capacitor electrode in the second sub-region and electrically connected to the data output line of the second data transmission line, and The path compensation capacitor is provided by an overlapping region between the power pad line and each of the compensation capacitor electrode and the data output line of the second data transmission line.

6. The display device according to claim 5, wherein: The circuit layer comprises: a first semiconductor layer on the substrate; a first gate insulating layer, covering the first semiconductor layer; a first gate conductive layer, on the first gate insulating layer; a second gate insulating layer, covering the first gate conductive layer; a second gate conductive layer, on the second gate insulating layer; a first interlayer insulating layer, covering the second gate conductive layer; a first source-drain conductive layer on the first interlayer insulating layer; and a first planarization layer, covering the first source-drain conductive layer, Wherein, the first source-drain conductive layer includes the data output line of each of the data transmission lines.

7. The display device according to claim 6, wherein: The first gate conductive layer includes the power pad line, The second gate conductive layer includes the compensation capacitor electrode, and The compensation capacitor electrode is electrically connected to the data output line of the second data transmission line through at least one capacitor auxiliary contact hole penetrating the first interlayer insulating layer.

8. The display device according to claim 6, wherein: The first gate conductive layer includes the compensation capacitor electrode, The second gate conductive layer includes the power pad line, and The compensation capacitor electrode is electrically connected to the data output line of the second data transmission line through at least one capacitor auxiliary contact hole penetrating the second gate insulating layer and the first interlayer insulating layer.

9. The display device according to claim 6, wherein: The circuit layer also includes: a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer, covering the second semiconductor layer; a third gate conductive layer, on the third gate insulating layer; and a second interlayer insulating layer covering the third gate conductive layer, Wherein, the first source-drain conductive layer is on the second interlayer insulating layer.

10. The display device according to claim 9, wherein: The compensation capacitor electrodes include a first capacitor distribution electrode and a second capacitor distribution electrode in different conductive layers, The first gate conductive layer includes the first capacitor allocation electrode, The second gate conductive layer includes the power pad line, The third gate conductive layer includes the second capacitor allocation electrode, The first capacitor distribution electrode is electrically connected to the data output line of the second data transmission line through at least one first capacitor auxiliary contact hole penetrating the second interlayer insulating layer, the third gate insulating layer, the first interlayer insulating layer, and the second gate insulating layer, and The second capacitance sharing electrode is electrically connected to the data output line of the second data transmission line through at least one second capacitor auxiliary contact hole penetrating the second interlayer insulating layer.

11. The display device according to claim 9, wherein: The power pad lines include a first pad distribution line and a second pad distribution line in different conductive layers, The first gate conductive layer includes the first pad distribution line, The second gate conductive layer includes the compensation capacitor electrode, The third gate conductive layer includes the second pad distribution line, and The compensation capacitor electrode is electrically connected to the data output line of the second data transmission line through at least one capacitor auxiliary contact hole penetrating the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer.

12. The display device according to claim 3, wherein: The power pad line includes: A first power pad configured to transmit a first power; and a second power pad line configured to transmit a second power, The first power and the second power are configured to drive the light emitting element.

13. The display device according to claim 1, wherein: Each of the demultiplexing circuits includes a demultiplexing transistor electrically connected between one of the data transmission lines and two or more of the data lines, and The demultiplexing transistor comprises: a first demultiplexing transistor configured to be turned on by a first demultiplexing control signal; and The second demultiplexing transistor is configured to be turned on by a second demultiplexing control signal.

14. A display device, comprising: substrate; a circuit layer on the substrate; as well as A component layer, on the circuit layer, The substrate includes: a main area including a display area in which an emission area is arranged and a non-display area around the display area; and a sub-area protruding from one side of the main area. The element layer includes light emitting elements respectively in the emission regions, and The circuit layer includes: light-emitting pixel drivers electrically connected to the light-emitting elements, respectively, and arranged in a first direction and a second direction; data lines extending in the second direction and configured to transmit data signals to the light-emitting pixel drivers; a demultiplexing circuit in the non-display area and configured to output the data signals of the data lines based on a data multiplexing signal supplied from a display driving circuit; and data transmission lines electrically connected between the display driving circuit and the demultiplexing circuit and configured to transmit the data multiplexing signals of the demultiplexing circuit, respectively. The demultiplexing circuit includes: a first demultiplexing circuit adjacent to an edge of the substrate in the first direction; and a second demultiplexing circuit spaced farther from the edge of the substrate than the first demultiplexing circuit in the first direction. The data transmission line includes: a first data transmission line configured to transmit a data multiplexing signal of the first demultiplexing circuit; and a second data transmission line configured to transmit a data multiplexing signal of the second demultiplexing circuit. The first data transmission line is electrically connected to the first demultiplexing circuit through a bypass line in the display area and an input auxiliary line in the non-display area, and The second data transmission line is directly electrically connected to the second demultiplexing circuit and is electrically connected to a path compensation capacitor in the sub-region.

15. The display device according to claim 14, wherein: The sub-regions include: a curved region having a curved shape; a first sub-region between the main region and one side of the curved region; and a second sub-region connected to the other side of the curved region. The display driving circuit is in the second sub-area, The circuit layer further includes: a power pad line extending from a portion of the signal pads in the second sub-area to the bending area, and Each of the data transmission lines includes: a data output line in the second sub-area and extending from the display driving circuit to the bending area; a data bending line in the bending area and electrically connected to the data output line; and a data input line in the first sub-area and the non-display area and electrically connected to the data bending line. Wherein, the path compensation capacitor is electrically connected to the data output line of the second data transmission line.

16. The display device according to claim 15, wherein: The demultiplexing circuit further comprises a third demultiplexing circuit spaced further from the edge of the substrate in the first direction than the second demultiplexing circuit, and The data transmission line further includes: a third data transmission line, transmitting the data multiplexing signal of the third demultiplexing circuit, The circuit layer further includes: a first compensation capacitor electrode, in the second sub-region, overlapping the power pad line and electrically connected to the data output line of the second data transmission line; and a second compensation capacitor electrode, in the second sub-region, overlapping the power pad line and electrically connected to the data output line of the third data transmission line, Wherein, an overlapping area between the second compensation capacitor electrode and the power pad line has a width greater than a width of an overlapping area between the first compensation capacitor electrode and the power pad line.

17. The display device according to claim 15, wherein: The path compensation capacitor is provided by an overlapping area between the power pad line and each of the data output line of the second data transmission line and a compensation capacitor electrode electrically connected to the data output line of the second data transmission line, and The circuit layer comprises: a first semiconductor layer on the substrate; a first gate insulating layer, covering the first semiconductor layer; a first gate conductive layer, on the first gate insulating layer; a second gate insulating layer, covering the first gate conductive layer; a second gate conductive layer, on the second gate insulating layer; a first interlayer insulating layer, covering the second gate conductive layer; a first source-drain conductive layer on the first interlayer insulating layer; and a first planarization layer, covering the first source-drain conductive layer, wherein the first source-drain conductive layer includes the data output line of each of the data transmission lines, One of the first gate conductive layer and the second gate conductive layer includes the power pad line, and The other of the first gate conductive layer and the second gate conductive layer includes the compensation capacitor electrode.

18. The display device according to claim 15, wherein: The path compensation capacitor is provided by an overlapping area between the power pad line and each of the data output line of the second data transmission line and a compensation capacitor electrode electrically connected to the data output line of the second data transmission line, and The circuit layer comprises: a first semiconductor layer on the substrate; a first gate insulating layer, covering the first semiconductor layer; a first gate conductive layer, on the first gate insulating layer; a second gate insulating layer, covering the first gate conductive layer; a second gate conductive layer, on the second gate insulating layer; a first interlayer insulating layer, covering the second gate conductive layer; a second semiconductor layer on the first interlayer insulating layer; a third gate insulating layer, covering the second semiconductor layer; a third gate conductive layer, on the third gate insulating layer; A second interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer on the second interlayer insulating layer; and a first planarization layer, covering the first source-drain conductive layer, Wherein, the first source-drain conductive layer includes the data output line of each of the data transmission lines.

19. The display device according to claim 18, wherein: The compensation capacitor electrodes include a first capacitor distribution electrode and a second capacitor distribution electrode in different conductive layers, The first gate conductive layer includes the first capacitor allocation electrode, The second gate conductive layer includes the power pad line, and The third gate conductive layer includes the second capacitor sharing electrode.

20. The display device according to claim 18, wherein: The power pad lines include a first pad distribution line and a second pad distribution line in different conductive layers, The first gate conductive layer includes the first pad distribution line, The second gate conductive layer includes the compensation capacitor electrode, and The third gate conductive layer includes the second pad distribution line.

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