Multi-protocol interface universal controller and display device

Abstract

The invention discloses a multi-protocol interface universal controller and a display device. The multi-protocol interface universal controller comprises an input / output interface used for connecting a backlight driving chip; the timer is used for outputting a direct memory access request signal during timing triggering; the direct memory access controller is used for being connected with an upper computer through the peripheral interface and further connected with the timer, the direct memory access controller is connected with the input and output interface, and the direct memory access controller is used for receiving data output by the upper computer through the peripheral interface; the processor is used for converting the data output by the upper computer into bit data; and the direct memory access controller is also used for outputting the bit data output by the processor to the input / output interface when receiving the direct memory access request signal so as to output the bit data to the backlight driving chip. The technical scheme of the invention aims to solve the problem of long time consumption when a multi-protocol interface universal controller carries out data transmission with different types of backlight driving chips.

Description

Technical Field

[0001] The present invention relates to the field of controllers, and in particular to a multi-protocol interface universal controller and a display device. Background Art

[0002] With the continuous evolution of Mini LED backlight technology, the general interface protocol has been gradually replaced, and the communication protocol between the controller and the backlight driver chip has evolved into a three-wire, two-wire or even single-wire serial protocol. The interface protocols of various backlight driver solutions are different and cannot be compatible with the general interface protocol. In addition, there is no unified standard transmission protocol at the current stage. This has led to the fact that the general controller that previously served as the controller can no longer be applied to such driver chips. Therefore, a controller adapted to the driver chip has been introduced, which is generally called a backlight control (BCON) chip. The combination of the two means that a backlight driver chip needs to be bound to a dedicated BCON chip. For different types of backlight driver chips, the forced bundling mode is not flexible and is not conducive to the standardization and modularization of general devices and software.

[0003] When a general controller is used in conjunction with the bit-banging mode of the input and output pins, when there are more serial data partitions, that is, when there is a lot of serial data, the data transmission takes a long time, which will cause data cross-frame problems. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a multi-protocol interface universal controller and a display device to solve the problem that the universal controller takes a long time to transmit data with different types of backlight driver chips.

[0005] The technical solution of the present invention is as follows:

[0006] A multi-protocol interface universal controller, comprising:

[0007] Input and output interface, used to connect the backlight driver chip;

[0008] A timer, used for outputting a direct memory access request signal when the timing is triggered;

[0009] A direct memory access controller, used to connect to the host computer through the peripheral interface, and also connected to the timer, the direct memory access controller is connected to the input and output interface, and the direct memory access controller is used to receive data output by the host computer through the peripheral interface;

[0010] A processor, used for converting data output by the host computer into bit data;

[0011] The direct memory access controller is further configured to output the bit data output by the processor to the input / output interface when receiving the direct memory access request signal, so as to output the bit data to the backlight driving chip.

[0012] Optionally, the multi-protocol interface universal controller further includes:

[0013] A memory is connected to the direct memory access controller and also connected to the processor. The memory is used to store the bit data output by the direct memory access controller and transfer the bit data to the interface register through the data bus so as to output it to the backlight driver chip through the input and output interface; the direct memory access controller is also used to store the data output by the host computer in the memory.

[0014] Optionally, the memory includes:

[0015] a first buffer connected to the direct memory access controller and also connected to the processor 50, the first buffer being used to store the bit data output by the processor 50, the first buffer being used to determine the source and target addresses of the bit data through the direct memory access controller;

[0016] The second buffer is connected to the direct memory access controller, and the second buffer is used to store data output by the direct memory access controller.

[0017] Optionally, the multi-protocol interface universal controller further includes:

[0018] A main control register, the main control register is used to control the working mode of the multi-protocol interface universal controller;

[0019] An interrupt enable register, wherein the interrupt enable register is used to control the interrupt enable state of the multi-protocol interface universal controller.

[0020] Optionally, the multi-protocol interface universal controller further includes:

[0021] A channel control register, wherein the channel control register is used to control a hardware double buffer of the direct memory access controller.

[0022] Optionally, the multi-protocol interface universal controller further includes:

[0023] A port input status register, the port input status register is used to read the input status of the input and output interface;

[0024] A port output control register, wherein the port output control register is used to control the output state of the input and output interface.

[0025] Optionally, the direct memory access controller includes:

[0026] a first access controller, the first access controller being connected to the input / output interface, the first access controller being used to output the bit data output by the processor to the backlight driver chip through the input / output interface, and the first access controller being used to read data of the backlight driver chip through the input / output interface;

[0027] The second access controller is used to connect to the host computer through the peripheral interface, and the second access controller is used to receive data output by the host computer through the peripheral interface.

[0028] Optionally, the direct memory access controller includes:

[0029] a first access controller, the first access controller being connected to the input-output interface, and the first access controller being used to output the bit data output by the processor to the backlight driving chip through the input-output interface;

[0030] a second access controller, the second access controller being connected to the input-output interface, and the second access controller being used to read data of a backlight driver chip through the input-output interface;

[0031] The third access controller is used to connect to the host computer through the peripheral interface, and the third access controller is used to receive data output by the host computer through the peripheral interface.

[0032] The present invention further provides a display device, comprising a backlight driver chip and the multi-protocol interface universal controller as described above, wherein the backlight driver chip is connected to an input / output interface in the multi-protocol interface universal controller.

[0033] Optionally, the display device further includes:

[0034] The LED array is connected to the backlight driving chip, and the backlight driving chip is used to drive the LED array to work according to the bit data output by the multi-protocol interface universal controller.

[0035] The technical solution of the present invention forms a multi-protocol interface universal controller through an input / output interface, a timer and a direct memory access controller, wherein the input / output interface can be connected to a backlight driver chip; the timer can output a direct memory access request signal when the timing is triggered; the direct memory access controller is used to connect to a host computer through a peripheral interface, the direct memory access controller is connected to the input / output interface and the timer, the processor converts the data output by the host computer into bit data, and the direct memory access controller can output the bit data to the backlight driver chip through the input / output interface when receiving the direct memory access request signal output by the timer. In this way, the present solution reduces the time for data bitization by converting the output data into bit data before outputting, thereby reducing the data transmission time between the multi-protocol interface universal controller and the backlight driver chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0037] Figure 1 It is a functional module diagram of an embodiment of a multi-protocol interface universal controller of the present invention.

[0038] Figure 2 It is a timing diagram of the port bit operation register in the multi-protocol interface universal controller of the present invention.

[0039] Figure 3 It is a schematic diagram of the software state machine of the backlight driver chip in the display device of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] In the embodiments and the scope of the patent application, unless the text specifically defines the article, "a", "an", "the" and "the" may also include plural forms. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0042] It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, the "connection" or "coupling" used herein can include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0043] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as herein.

[0044] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0045] With the continuous evolution of Mini LED backlight technology, the general interface protocol has been gradually replaced, and the communication protocol between the controller and the backlight driver chip has evolved into a three-wire, two-wire or even single-wire serial protocol. The interface protocols of various backlight driver solutions are different and cannot be compatible with the general interface protocol. In addition, there is no unified standard transmission protocol at the current stage. This has led to the fact that the general controller that previously served as the controller can no longer be applied to such driver chips. Therefore, a controller adapted to the driver chip has been introduced, which is generally called a backlight control (BCON) chip. The combination of the two means that a backlight driver chip needs to be bound to a dedicated BCON chip. For different types of backlight driver chips, the forced bundling mode is not flexible and is not conducive to the standardization and modularization of general devices and software.

[0046] When a general controller is used in conjunction with the bit-banging mode of the input and output pins, when there are more serial data partitions, that is, when there is a lot of serial data, the data transmission takes a long time, which will cause data cross-frame problems.

[0047] In order to solve the above problems, the present invention proposes a multi-protocol interface universal controller.

[0048] Reference Figure 1 In one embodiment, the multi-protocol interface universal controller includes:

[0049] Input and output interface 10, used to connect to the backlight driver chip;

[0050] Timer 20, used for outputting a direct memory access request signal when the timing is triggered;

[0051] A direct memory access controller 30, which is used to connect to the host computer through the peripheral interface and is also connected to the timer. The direct memory access controller 30 is connected to the input and output interface 10. The direct memory access controller 30 is used to receive data output by the host computer through the peripheral interface;

[0052] The processor 50 is used to convert the data output by the host computer into bit data;

[0053] The direct memory access controller 30 is further configured to output the bit data output by the processor 50 to the input / output interface 10 upon receiving the direct memory access request signal, so as to output the bit data to the backlight driving chip.

[0054] In this embodiment, the input / output interface 10 can be a general purpose input / output interface 10 (General Purpose Input / Output, GPIO for short) in the controller. The multi-protocol interface general controller can interact with different backlight driver chips through the input / output interface 10 for digital signals. The input / output interface 10 can be configured as an input or output mode, allowing the multi-protocol interface general controller to read the output signal of the backlight driver chip or send a signal to the backlight driver chip. The timer 20 can output a direct memory access request signal to the direct memory access controller 30 when the timing is triggered, and the counting frequency of the timer 20 can be set according to the actual situation and user needs. When the count reaches the preset counting frequency, the timer 20 can output a direct memory access request signal. The direct memory access (DMA) controller is a hardware component that can realize efficient data transmission; and the direct memory access controller 30 used in this embodiment can include two, one direct memory access controller 30 can be connected to the host computer through a peripheral interface, such as through an SPI (Serial Peripheral Interface) or USB (Universal Serial Bus) interface, so that the host computer can directly exchange data with the multi-protocol interface general controller, which is specifically used for data reception of the host computer; the other direct memory access controller 30 is used to output the bit data output by the processor 50 to the input and output interface 10 when receiving the direct memory access request signal, and then output to the backlight driver chip. After the processor 50 converts the data output by the host computer into a bit form, the direct memory access controller 30 can output the bit data to the backlight driver chip through the input and output interface 10 when receiving the direct memory access request signal, so that the burden of the multi-protocol interface general controller in the data handling process can be reduced. Specifically, DMA can be configured first, the source address (data in the memory), the target address (GPIO register), and the size of the transmission (the amount of data); and then DMA is started. At this point, the DMA controller will start reading data from memory and write them to the GPIO registers. When the DMA transfer is complete, the DMA controller will usually generate an interrupt, indicating that the transfer has ended. At this point, you can choose to perform further operations, such as updating the data in memory, or starting a new DMA transfer. During the DMA transfer process, the processor in the multi-protocol interface general controller can handle other tasks without having to wait for the data to be written to the GPIO. This improves the parallelism and efficiency of the system. This can improve the overall performance of the system, thereby reducing the data transmission time between the multi-protocol interface general controller and the backlight driver chip.

[0055] It should be noted that, in this embodiment, the basic hardware requirements for a multi-protocol interface general controller that can realize the above functions are a built-in direct memory access controller 30, supporting a timer 20 to trigger a DMA transfer request, and the DMA controller can access the bus where the controller's GPIO-related registers are located; further, other hardware such as registers or memory 40 can be added to the multi-protocol interface general controller according to actual conditions and specific user needs.

[0056] The technical solution of the present invention forms a multi-protocol interface universal controller through an input / output interface 10, a timer 20 and a direct memory access controller 30, wherein the input / output interface 10 can be connected to a backlight driver chip; the timer 20 can output a direct memory access request signal when the timing is triggered; the direct memory access controller 30 is used to connect to a host computer through a peripheral interface, the direct memory access controller 30 is connected to the input / output interface 10 and the timer 20, the processor 50 converts the data output by the host computer into bit data, and the direct memory access controller 30 can output the bit data to the backlight driver chip through the input / output interface 10 when receiving the direct memory access request signal output by the timer 20. In this way, the present solution reduces the data transmission time between the multi-protocol interface universal controller and the backlight driver chip by converting the output data into bit data and then outputting it, and by reducing the time for bitization of the data.

[0057] Reference Figure 1 In one embodiment, the multi-protocol interface universal controller further includes:

[0058] The memory 40 is connected to the direct memory access controller 30 and also connected to the processor 50. The memory 40 is used to store the bit data output by the processor 50 and transfer the bit data to the interface register through the data bus so as to output it to the backlight driver chip through the input and output interface 10; the direct memory access controller 30 is also used to store the data output by the host computer into the memory 40.

[0059] In this embodiment, the memory 40 may be a static random access memory 40 (Static Random-Access Memory, SRAM for short). In this embodiment, the execution efficiency of the program is improved by exchanging space for time. Time refers to the time required for program execution, which is usually related to factors such as the complexity of the algorithm, the number of loops, and function calls. Space refers to the memory required when the program is running (such as SRAM, Flash, etc.), including variables, arrays, buffers, etc. In some cases, increasing memory usage (space) can reduce the amount of calculation (time), such as through pre-calculation, caching, lookup table and other technologies. Conversely, reducing memory usage may lead to more calculations, thereby increasing execution time. Therefore, in this embodiment, by setting the memory 40 to store the bit data output by the processor 50 and the data output by the host computer, the calculation time can be reduced, thereby improving the execution efficiency of the program; the interface register is a register connected to the input and output interface 10.

[0060] Furthermore, in one embodiment, the memory 40 includes:

[0061] a first buffer connected to the direct memory access controller 30 and also connected to the processor 50, the first buffer being used to store the bit data output by the processor 50, the first buffer being used to determine the source and target addresses of the bit data through the direct memory access controller 30;

[0062] The second buffer is connected to the direct memory access controller 30, and the second buffer is used to store the data output by the direct memory access controller. In this embodiment, the memory 40 can be composed of a first buffer and a second buffer, and the bit data output by the processor 50 can be stored through the first buffer, and the first buffer can determine the source and target addresses of the bit data through the direct memory access controller 30, so that the direct memory access controller 30 can transfer the bit data from the address where the first buffer is located to the address where the interface register is located through the bus. And the direct memory access controller 30 can store the received data output by the host computer through the second buffer. Setting the first buffer and the second buffer can isolate the data and reduce the risk of interference between the data, and different types of data are stored in different buffers, which can reduce access delay and improve overall performance.

[0063] In one embodiment, the multi-protocol interface universal controller further includes:

[0064] A main control register, the main control register is used to control the working mode of the multi-protocol interface universal controller;

[0065] An interrupt enable register, wherein the interrupt enable register is used to control the interrupt enable state of the multi-protocol interface universal controller.

[0066] In this embodiment, a main control register and an interrupt enable register may also be set in the multi-protocol interface universal controller, and the control register may be used to configure various operation modes and functions of the multi-protocol interface universal controller. For example, it may be used to enable or disable specific peripherals, set operating modes (such as low power mode, normal mode, etc.), and configure clock sources, etc. The bits of the control register usually correspond to different functions or peripherals, and the user may achieve the desired configuration by setting or clearing these bits. The interrupt enable register may be used to control which interrupt sources are enabled. By setting the corresponding bits, a specific interrupt may be enabled or disabled. When a certain interrupt source is enabled and an interrupt occurs, the microcontroller will suspend the current execution process and execute the interrupt service program instead. The main control register and the interrupt enable register set in this embodiment may make the functions of the multi-protocol interface universal controller more complete. It should be noted that because the frequency of the update event of the timer 20 is relatively high, equal to twice the main clock frequency of the transmission protocol, at the MHz level, interrupts are generally not enabled without special requirements.

[0067] In one embodiment, the multi-protocol interface universal controller further includes:

[0068] A channel control register, wherein the channel control register is used to control the hardware double buffer of the direct memory access controller 30 .

[0069] In this embodiment, a channel control register can also be set in the multi-protocol interface universal controller. In the multi-protocol interface universal controller, the setting of the DMA hardware double buffer usually involves configuring the DMA main control register and the channel control register. The specific steps and register names may vary depending on the architecture of the multi-protocol interface universal controller. In a reference embodiment, the steps for opening the DMA hardware double buffer are as follows: first select the DMA channel to be used, and configure its source address, destination address and transfer size. Then set the double buffer mode. In the control register of the DMA channel, there is usually a bit for enabling the double buffer mode, and the bit is set to 1. Configure the buffer address: Set the addresses of the two buffers, which is usually done by setting two registers, one for the main buffer and one for the secondary buffer. Start DMA transfer: After the configuration is completed, start the DMA transfer. Usually there is a start bit that needs to be set. The optional function is interrupt configuration. If an interrupt needs to be triggered when the DMA transfer is completed, the corresponding interrupt enable bit can also be configured. In this way, by setting the automatic switching of the double buffer, the performance of the multi-protocol interface universal controller can be further improved.

[0070] In one embodiment, the multi-protocol interface universal controller further includes:

[0071] A port input status register, the port input status register is used to read the input status of the input / output interface 10;

[0072] The port output control register is used to control the output state of the input / output interface 10 .

[0073] In the present embodiment, a port input status register and a port output control register may also be set in the multi-protocol interface universal controller, and the port input status register may be used to read the input status of each pin of the multi-protocol interface universal controller. It reflects the level status of the external signal on the pin. By reading this register, the program can obtain the status of the external device (such as a switch, a sensor, etc.) connected to the pin. The port output control register may control the output status of each pin of the microcontroller. By setting or clearing the bit in the register, the pin may be controlled to output a high level or a low level. The port output control register is usually used in conjunction with the port input status register to implement the switching of the input and output functions.

[0074] It should be noted that in order not to affect other pins under the same port, it is more flexible to replace the port output control register with the port bit operation register for separate control (writing 1 to set or reset the bit, and writing 0 has no effect). The requirement for the protocol hardware pin assignment is to try to be located under the same GPIO port, so that the corresponding register can be written or read at one time. The DMA transfer completion interrupt needs to be enabled to configure the data for the next transmission. Because the hardware double buffer has been enabled, after the DMA transfer is completed, when the multi-protocol interface general controller enters the interrupt, the hardware has automatically transmitted the next data under the drive of timer 20, so the next data is calculated in the interrupt.

[0075] It is understandable that the above registers are not shown in the drawings, and the connection relationship of the registers in actual applications can be set according to actual conditions and user requirements.

[0076] In one embodiment, the direct memory access controller 30 includes:

[0077] a first access controller, the first access controller being connected to the input-output interface 10, the first access controller being used to output the bit data output by the processor 50 to the backlight driver chip through the input-output interface 10, and the first access controller being used to read data of the backlight driver chip through the input-output interface 10;

[0078] The second access controller is used to connect to the host computer through the peripheral interface, and the second access controller is used to receive data output by the host computer through the peripheral interface. In this embodiment, for a multi-protocol interface universal controller with its own clock and low timing requirements, the direct memory access controller 30 between the multi-protocol interface universal controller and the backlight driver chip can be composed of a first access controller, and the time-division multiplexing of data reading and writing can be completed through the first access controller, and the second access controller is used to receive data output by the host computer through the peripheral interface.

[0079] In another embodiment, the direct memory access controller 30 includes:

[0080] A first access controller, the first access controller is connected to the input-output interface 10, and the first access controller is used to output the bit data output by the processor to the backlight driving chip through the input-output interface 10;

[0081] A second access controller, the second access controller is connected to the input-output interface 10, and the second access controller is used to read data of the backlight driver chip through the input-output interface 10;

[0082] The third access controller is used to connect to the host computer through the peripheral interface, and the third access controller is used to receive data output by the host computer through the peripheral interface. In this embodiment, for a multi-protocol interface universal controller without a clock and with high timing requirements, it is necessary to set a first access controller and a second access controller to respectively complete the reading and writing of data, which can further improve the overall performance of the system, especially in a multi-tasking or multi-threaded environment; and reduce the delay in the data transmission process, and can also enable the multi-protocol interface universal controller to process more data per unit time, thereby improving the overall system throughput, and the third access controller is used to receive data output by the host computer through the peripheral interface.

[0083] It should be noted that the structure of the direct memory access controller 30 is related to the type of multi-protocol interface universal controller. For the scheme where the clock of the chip digital logic part and the clock driving the PWM are used together, the entire clock cannot be stopped, otherwise the backlight will go out. Therefore, it is necessary to set a first access controller and a second access controller to read and write data respectively. If the digital protocol part and the clock controlling the PWM are separated, and the backlight will not go out when the protocol has no clock, then only one first access controller can be set, and the reading and writing of data can be time-division multiplexed.

[0084] In order to better illustrate the concept of the technical solution of the present invention, combined with the above embodiments and Figures 1 to 3 The working principle of this solution is explained as follows:

[0085] First, set the DMA transfer parameters, and the mode is memory to peripherals. When data needs to be read from the backlight driver chip, according to the timing requirements of different backlight driver chip protocols, another DMA controller may need to be configured for read operations. During the read operation, the DMA mode is peripheral to memory. This solution only describes the write operation in detail. To improve the data throughput, you can enable the DMA transfer loop mode, half-full or full-full interrupts, and set up double buffers. Half-full or full-full interrupts are two interrupts, and one interrupt is usually selected according to actual needs. If the hardware supports automatic switching of double buffers, the performance can be further improved. Therefore, set the channel control register on the multi-protocol interface general controller to enable the DMA hardware double buffer. The address of the peripheral is the GPIO level control register address of the multi-protocol interface general controller. On the multi-protocol interface general controller, the read operation register is the port input status register; the write operation register is the port output control register. In order not to affect other pins under the same port, the write operation register can be selected as the port bit operation register for separate control, which will be more flexible (writing 1 to set or reset the bit, and writing 0 has no effect). The requirement for the protocol hardware pin assignment is to place them under the same GPIO port as much as possible, so that the corresponding registers can be written or read at one time. The DMA transfer completion interrupt needs to be enabled to configure the data for the next transmission. Because the hardware double buffer has been enabled, after the DMA transfer is completed, when the multi-protocol interface general controller enters the interrupt, the hardware has automatically transmitted the next data under the drive of timer 20, so the next data is calculated in the interrupt.

[0086] by Figure 2 Taking the timing diagram of the port bit operation register as an example, it is explained how to construct DMA IO transmission data. In actual application, the amount of data contained in a DMA transmission needs to be adjusted according to the timing requirements of the backlight driver chip and the memory 40 resources in the multi-protocol interface general controller; it should be noted that Figure 2 The timing diagram of the port bit operation register in the figure is only a reference example diagram and does not represent all the timing diagrams in actual applications.

[0087] First, it is necessary to clearly write 1 to the upper 16 bits and lower 16 bits of the multi-protocol interface general controller port bit operation register to reset or set the corresponding GPIO Pin, and writing 0 has no effect, so the most basic DCLK can be generated. Figure 2 In the example, the count of the rising edge of the DCLK clock is set to DLCK_CNT, then the clock rises or falls, and the rising edge count GPIO_POS_TG_CNT can be expressed as:

[0088] GPIO_POS_TG_CNT=2*DCLK_CNT-1;

[0089] The falling edge count GPIO_NEG_TG_CNT can be expressed as:

[0090] GPIO_NEG_TG_CNT=2*DCLK_CNT;

[0091] The low level at the start of DCLK is preset to GPIO_NEG_TG_CNT=0.

[0092] Separately counting the rising and falling edges can accurately control the edge trigger polarity of the DCLK clock to meet the data setup and hold time requirements. Other clocks or data latches can also be set to align the DCLK edge and count requirements, but it will cause the generated data clock to drop to half the frequency of the timer 20 update event. If the GPIO Pin corresponding to DCLK is Pin_5, then the data to be written to the register on the falling edge of the clock is NCLK_DATA=(1<<(16+5)), and the data to be written to the register on the rising and falling edges of the clock is PCLK_DATA=(1<<5). After the timer 20 triggers two DMA transfers, these two 32-bit data are combined into a level-continuous flip signal containing a DCLK falling edge and a rising edge on the hardware pin Pin_5.

[0093] After weighing the size of a DMA data transfer, the port bit operation register data size corresponding to DCLK can be determined as:

[0094] {[NCLK_DATA, PCLK_DATA], [NCLK_DATA, PCLK_DATA], [NCLK_DATA, PCLK_DATA]...};

[0095] Here, because the data is valid at the rising edge of the clock, the first data is NCLK_DATA, which makes it easy to write the first data at the same time.

[0096] Because the clock rising and falling edge counts are distinguished, the data required by various hardware pins can be easily integrated at different locations. Other data can be easily integrated into NCLK_DATA and PCLK_DATA through bit operation "OR" operation on this basis. This operation is defined as data bitization, that is, the data output by the host computer is converted into bit form as mentioned in the above embodiment. The read operation is similar, one of the DMA controllers is used to generate the clock. Depending on the MCU hardware situation, another slave timer may need to be used. The master timer that provides the write operation can be used to synchronously trigger another DMA to transfer the data of the port input status register to the memory to achieve full-duplex read and write operations.

[0097] It is understandable that a frame of data is sent from the host computer, received by the multi-protocol interface universal controller, and serialized and processed according to the physical arrangement of the lights, and then the data is bit-coded and stored in the memory, and then the DMA moves the data to the port bit operation register. The longest time is the DMA moving the bit data, that is, the brightness or register data is written into the backlight driver chip. By adjusting the length of the DMA data and the frequency of the main timer update event, the DMA transfer completion interrupt frequency can be adjusted. While meeting the requirement of not transmitting brightness data across frames, the load rate of the processor in the multi-protocol interface universal controller can also be maintained at an acceptable level. Data bitization is a flexible process, which is mainly related to the main frequency of the multi-protocol interface universal controller. For commonly used encoding methods such as 4B / 5B, CRC check, etc., the soft coding performance is better at the main frequency of tens of megahertz or even hundreds of megahertz of the multi-protocol interface universal controller, and it can also be directly supported by hardware. Therefore, this solution can basically realize the simulation of various drive protocols through data bitization.

[0098] Data bitization can be optimized by combining software and hardware. Usually, on a 32-bit platform, writing a 32-bit data to the driver chip requires 32 DCLK rising edges and 64 DCLK level flips, that is, timer 20 needs 64 update events to trigger DMA to move 64 32-bit data from memory to the port bit operation register. The optimization is that 32-bit data does not necessarily have continuous adjacent high and low changes, and the port bit operation register does not require the corresponding Pin value to be updated every time the DMA moves data, so you can find the place where 01 or 10 switches in the 32-bit data, and ignore the continuous 00 or 11. For example, combined with hardware, using low-level assembly instructions such as CLZ (Count Leading Zeros) and RBIT (Reverse the bit order in a 32-bit word) and data bit operations can better implement this function, which will not be discussed here.

[0099] Furthermore, it is also feasible to expand multiple groups of hardware protocol interfaces. Writing the 32-bit data of the port bit operation register of the same port once can update up to 16 hardware pins at the same time without causing performance loss. Writing different port bit operation registers can expand more hardware interfaces.

[0100] The present invention also provides a display device.

[0101] In one embodiment, the display device includes a backlight driver chip and the multi-protocol interface universal controller as described above, and the backlight driver chip is connected to the input and output interface 10 in the multi-protocol interface universal controller. Through the multi-protocol interface universal controller in this solution, different types of backlight driver chips can be adapted, and the bitization of the host computer data in the multi-protocol interface universal controller can be determined according to the backlight driver chip model in actual application. It can be understood that since the above-mentioned multi-protocol interface universal controller is used in the display device of the present invention, the embodiment of the display device of the present invention includes all the technical solutions of all the embodiments of the above-mentioned multi-protocol interface universal controller, and the technical effects achieved are exactly the same, which will not be repeated here. The interrupt main function is a simple state machine, which is applied to the backlight driver chip. The specific process can be referred to. Figure 3 Software state machine.

[0102] In one embodiment, the display device further includes:

[0103] The LED array is connected to the backlight driving chip, and the backlight driving chip is used to drive the LED array to work according to the bit data output by the multi-protocol interface universal controller.

[0104] In this embodiment, the backlight driver chip can receive bit data from the multi-protocol interface universal controller, which usually contains information about LED brightness, switch status and dimming mode. The backlight driver chip will parse the data to determine how to drive the LED array to work.

[0105] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A multi-protocol interface universal controller, characterized in that: include: Input and output interface, used to connect the backlight driver chip; A timer, used for outputting a direct memory access request signal when the timing is triggered; A direct memory access controller, used to connect to the host computer through the peripheral interface, and also connected to the timer, the direct memory access controller is connected to the input and output interface, and the direct memory access controller is used to receive data output by the host computer through the peripheral interface; A processor, used for converting data output by the host computer into bit data; The direct memory access controller is further configured to output the bit data output by the processor to the input-output interface when receiving the direct memory access request signal, so as to output the bit data to the backlight driving chip.

2. The multi-protocol interface universal controller according to claim 1, characterized in that: Also includes: A memory connected to the direct memory access controller and also connected to the processor, the memory being used to store the bit data output by the direct memory access controller and transfer the bit data to an interface register via a data bus so as to be output to a backlight driver chip via the input / output interface; The direct memory access controller is also used to store data output by the host computer into the memory.

3. The multi-protocol interface universal controller according to claim 2, characterized in that: The memory comprises: a first buffer connected to the direct memory access controller and also connected to the processor, the first buffer being used to store bit data output by the processor, and the first buffer being used to determine source and target addresses of the bit data through the direct memory access controller; The second buffer is connected to the direct memory access controller, and the second buffer is used to store data output by the direct memory access controller.

4. The multi-protocol interface universal controller according to claim 1, characterized in that: Also includes: A main control register, the main control register is used to control the working mode of the multi-protocol interface universal controller; An interrupt enable register, wherein the interrupt enable register is used to control the interrupt enable state of the multi-protocol interface universal controller.

5. The multi-protocol interface universal controller according to claim 1, characterized in that: Also includes: A channel control register, wherein the channel control register is used to control a hardware double buffer of the direct memory access controller.

6. The multi-protocol interface universal controller according to claim 1, characterized in that: Also includes: A port input status register, the port input status register is used to read the input status of the input and output interface; A port output control register, wherein the port output control register is used to control the output state of the input and output interface.

7. The multi-protocol interface universal controller according to claim 1, characterized in that: The direct memory access controller comprises: a first access controller, the first access controller being connected to the input / output interface, the first access controller being used to output the bit data output by the processor to the backlight driver chip through the input / output interface, and the first access controller being used to read data of the backlight driver chip through the input / output interface; The second access controller is used to connect to the host computer through the peripheral interface, and the second access controller is used to receive data output by the host computer through the peripheral interface.

8. The multi-protocol interface universal controller according to claim 1, characterized in that: The direct memory access controller comprises: a first access controller, the first access controller being connected to the input-output interface, and the first access controller being used to output the bit data output by the processor to the backlight driving chip through the input-output interface; a second access controller, the second access controller being connected to the input-output interface, and the second access controller being used to read data of a backlight driver chip through the input-output interface; The third access controller is used to connect to the host computer through the peripheral interface, and the third access controller is used to receive data output by the host computer through the peripheral interface.

9. A display device, characterized in that: It comprises a backlight driving chip and a multi-protocol interface universal controller as claimed in any one of claims 1 to 8, wherein the backlight driving chip is connected to an input and output interface in the multi-protocol interface universal controller.

10. The display device according to claim 9, characterized in that Also includes: The LED array is connected to the backlight driving chip, and the backlight driving chip is used to drive the LED array to work according to the bit data output by the multi-protocol interface universal controller.

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