Semiconductor device with timing control circuit

Abstract

The invention relates to a semiconductor device having a timing control circuit. An example apparatus includes a data bus including a first portion having a timing domain controlled based on a first timing signal, and further including a second portion having a timing domain controlled based on a second timing signal; and a data transfer circuit coupled to the data bus, the data transfer circuit including a data driver between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver. The timing control circuit includes a variable delay that adds a delay amount to a first control signal to generate a second control signal. The data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus in response to the second control signal.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a timing control circuit. Background Art

[0002] Semiconductor memory devices such as DRAM (Dynamic Random Access Memory) perform operations in synchronization with a clock signal supplied from the outside. However, write data supplied from the outside at the time of a write operation is supplied in synchronization with a data strobe signal rather than a clock signal. Therefore, it may be preferable that the write data has timing in a timing domain controlled based on a clock signal inside the semiconductor memory device. Summary of the invention

[0003] In one aspect, the present disclosure relates to a device comprising: a data bus, which includes a first portion having a timing domain controlled based on a first timing signal, and further includes a second portion having a timing domain controlled based on a second timing signal; and a data transfer circuit coupled to the data bus, the data transfer circuit including a data driver located between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver; wherein the timing control circuit includes adding a delay amount to a first control signal to produce a variable delay of a second control signal; and wherein the data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus in response to the second control signal.

[0004] On the other hand, the present disclosure relates to a device comprising: a memory cell array; a data bus configured to transfer write data to the memory cell array; a data transfer circuit configured to transfer the write data to the data bus; and a timing control circuit configured to activate the data transfer circuit after a first delay time that has passed after a timing signal is activated according to a first operating mode, and to activate the data transfer circuit after a second delay time that is different from the first delay time that has passed after the timing signal is activated according to a second operating mode.

[0005] On the other hand, the present disclosure relates to a device comprising: a memory cell array; a control logic circuit configured to generate a first timing signal based on a clock signal in a data write operation; a variable delay circuit configured to generate a second timing signal by delaying the first timing signal; a data bus configured to transmit write data to the memory cell array; and a data transmission circuit configured to transmit the write data to the data bus in response to the second timing signal, wherein the delay amount of the variable delay circuit when the clock signal has a first frequency is shorter than the delay amount of the variable delay circuit when the clock signal has a second frequency lower than the first frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure;

[0007] Figure 2 A circuit diagram for a transmission circuit;

[0008] Figure 3A An example of a circuit diagram for a timing control circuit;

[0009] Figure 3B is another example of a circuit diagram of a timing control circuit; and

[0010] Figure 4 is a timing chart for explaining the operation of the transmission circuit. DETAILED DESCRIPTION

[0011] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show specific aspects and various embodiments of the present disclosure by way of illustration. The detailed description provides sufficient details to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, because some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0012] Figure 1 1 is a block diagram showing the configuration of a semiconductor device 10 according to an embodiment of the present disclosure. Figure 1 The semiconductor device 10 shown in FIG. 1 is a DRAM and has a memory cell array 21 including a plurality of memory cells. The semiconductor device 10 has a command address terminal 31, a clock terminal 32, a data terminal 33, and a data strobe terminal 34. A command address signal CA and a clock signal CK are input from the outside to the command address terminal 31 and the clock terminal 32, respectively. The command address signal CA and the clock signal CK are supplied to a control logic circuit 22.

[0013] When the command address signal CA indicates a read operation, the control logic circuit 22 performs an operation of reading data from a specified address in the memory cell array 21. The read data that has been read from the memory cell array 21 is output to the outside from the data terminal 33 via the read amplifier 231 included in the amplifier circuit 23, the parallel / serial conversion circuit 24, and the I / O circuit 25. The operation of the read amplifier 231 is performed synchronously with the read clock signal RCLK supplied from the control logic circuit 22. The timing domain of the read clock signal RCLK is controlled based on the clock signal CK. The amplifier circuit 23 is coupled to the parallel / serial conversion circuit 24 through a plurality of read / write buses RWBS. A plurality of read data supplied in parallel through the read / write bus RWBS is converted into serial data by the parallel / serial conversion circuit 24. The I / O circuit 25 includes an output buffer circuit 251. Therefore, at the time of the read operation, a plurality of read data are serially output from the data terminal 33.

[0014] When the command address signal CA indicates a write operation, the control logic circuit 22 performs an operation of writing write data input from the outside to the data terminal 33. At the time of the write operation, a plurality of write data supplied serially to the data terminal 33 is supplied to the serial / parallel conversion circuit 26 via the I / O circuit 25. The serial / parallel conversion circuit 26 converts the serial plurality of write data into parallel data. The write data converted into parallel data is supplied to the read / write bus RWBS via the transmission circuit 27. The write data transmitted to the read / write bus RWBS is written to a specified address in the memory cell array 21 via the write amplifier 232 included in the amplifier circuit 23. The operation of the write amplifier 232 is performed synchronously with the write clock signal WCLK supplied from the control logic circuit 22. The timing domain of the write clock signal WCLK is controlled based on the clock signal CK.

[0015] The I / O circuit 25 includes an input receiver circuit 252. The input receiver circuit 252 captures write data input to the data terminal 33 in synchronization with the data strobe signal DQS. Therefore, the serial write data input to the serial / parallel conversion circuit 26 and the parallel write data output from the serial / parallel conversion circuit 26 are synchronized with the data strobe signal DQS. The transmission circuit 27 transmits the parallel write data output from the serial / parallel conversion circuit 26 to the read / write bus RWBS.

[0016] Figure 2 is a circuit diagram of the transmission circuit 27. Figure 2 Only the circuit corresponding to one bit of the parallel write data WD is shown. Figure 2, the transmission circuit 27 includes a trigger circuit 271 that latches the write data WD (DQS) output from the serial / parallel conversion circuit 26 in synchronization with the timing signal DWS2, and a timing control circuit 272 that generates the timing signal DWS2 based on the timing signal DWS1. The trigger circuit 271 can be replaced by a through latch circuit or a tri-state buffer.

[0017] The write data WD (DQS) is synchronized with the data strobe signal DQS. When the command address signal CA indicates a write operation, the timing signal DWS1 is output from the control logic circuit 22 at a predetermined timing of the timing domain controlled based on the clock signal CK. The timing control circuit 272 receives the timing signal DWS1 and delays the timing signal DWS1 to generate the timing signal DWS2. The delay amount of the timing control circuit 272 (i.e., the time elapsed after the timing signal DWS1 is activated until the timing signal DWS2 is activated) can be changed according to the mode signal MR13. The mode signal MR13 is a signal set in the mode register 221 included in the control logic circuit 22, and indirectly indicates the frequency of the clock signal CK. The timing control circuit 272 increases the delay amount as the frequency of the clock signal CK indicated by the mode signal MR13 is lower, and reduces the delay amount as the frequency of the clock signal CK indicated by the mode signal MR13 is higher. Therefore, as the frequency of the clock signal CK indicated by the mode signal MR13 is lower, the timing at which the flip-flop circuit 271 latches the write data WD (DQS) is later, and as the frequency of the clock signal CK indicated by the mode signal MR13 is higher, the timing at which the flip-flop circuit 271 latches the write data WD (DQS) is earlier. The write data WD (CK) latched by the flip-flop circuit 271 is output to the read / write bus RWBS. As a result, the write data WD (CK) is output to the read / write bus RWBS in the timing domain of the clock signal CK. As described above, the transfer circuit 27 is used to convert the write data WD (DQS) in the timing domain of the data strobe signal DQS into the write data WD (CK) in the timing domain of the clock signal CK.

[0018] Figure 3A is an example of a circuit diagram of the timing control circuit 272. Figure 3AThe timing control circuit 272 of the example shown in FIG. 2 includes two delay circuits 41 and 42 that receive a timing signal DWS1, and a multiplexer 40 that selects one of the outputs of the delay circuits 41 and 42. The timing signal DWS1 is commonly supplied to the delay circuits 41 and 42. The delay amounts of the delay circuits 41 and 42 are different from each other. Therefore, the time elapsed until the timing signal DWS2 is output from the delay circuits 41 and 42 after the timing signal DWS1 is activated is different from each other. For example, the delay amount of the delay circuit 42 is shorter than the delay amount of the delay circuit 41. The timing signal DWS2 output from the delay circuits 41 and 42 is supplied to the multiplexer 40. The multiplexer 40 selects one of the timing signals DWS2 output from the delay circuits 41 and 42 according to the mode signal MR13. For example, when the frequency of the clock signal CK indicated by the mode signal MR13 is lower than a predetermined frequency, the multiplexer 40 selects the timing signal DWS2 output from the delay circuit 41, and when the frequency of the clock signal CK indicated by the mode signal MR13 is higher than a predetermined frequency, the multiplexer 40 selects the timing signal DWS2 output from the delay circuit 42.

[0019] Figure 3B FIG. 2 is another example of a circuit diagram of the timing control circuit 272. Figure 3B The timing control circuit 272 of the example shown in FIG. 2 includes n delay circuits 41 to 4n that receive a timing signal DWS1 and a multiplexer 40 that selects one of the outputs of the delay circuits 41 to 4n. The timing signal DWS1 is commonly supplied to the delay circuits 41 to 4n. The delay amounts of the delay circuits 41 to 4n are different from each other. For example, the delay amount of the delay circuit 42 is shorter than the delay amount of the delay circuit 41, and the delay amount of the delay circuit 43 is shorter than the delay amount of the delay circuit 42. Therefore, the time that elapses after the timing signal DWS1 is activated until the timing signal DWS2 is output from the delay circuits 41 to 4n is different from each other. As described above, by using a large number of delay circuits 41 to 4n, the time that elapses after the timing signal DWS1 is activated until the timing signal DWS2 is activated can be adjusted more finely. For example, when the frequency of the clock signal CK indicated by the mode signal MR13 is within a first range, the multiplexer 40 selects the timing signal DWS2 output from the delay circuit 41, when the frequency of the clock signal CK indicated by the mode signal MR13 is within a second range higher than the first range, the multiplexer 40 selects the timing signal DWS2 output from the delay circuit 42, and when the frequency of the clock signal CK indicated by the mode signal MR13 is within a third range higher than the second range, the multiplexer 40 selects the timing signal DWS2 output from the delay circuit 43.

[0020] A write equalization operation is performed on the semiconductor device 10 during the manufacturing stage. When the write equalization operation is performed, the timing of the clock signal CK and the data strobe signal DQS is ideally matched. In some instances, the timing may be referred to as a timing domain. However, the specification allows a certain range of deviations of the data strobe signal DQS from the clock signal CK after the write equalization operation. Specifically, the specifications tDQSS and tDQSoffset are defined, and the total value of tDQSS and tDQSoffset is the range in which the data strobe signal DQS can deviate from the clock signal CK. The absolute values ​​of tDQSS and tDQSoffset are proportional to the period tCK of the clock signal CK. When tCK=0.25ns (nanoseconds) and the write preamble is 4tCK as an example, tDQSS=±0.625tCK and tDQSoffset=±0.5tCK. When tCK=1.01ns and the write preamble is 2tCK as another example, tDQSS=±0.375tCK and tDQSoffset=±0.5tCK. As described above, since the absolute values ​​of tDQSS and tDQSoffset are proportional to the period tCK of the clock signal CK, the absolute value of the timing difference between the timing signal DWS2 having the timing of the timing domain controlled based on the clock signal CK and the write data WD (DQS) synchronized with the data strobe signal DQS increases as the period tCK of the clock signal CK is longer. Therefore, when the period tCK of the clock signal CK is set to the maximum value (tCKmax), the absolute value of the timing difference between the timing signal DWS2 and the write data WD (DQS) is the largest. Therefore, the activation timing of the timing signal DWS2 is adjusted by the timing control circuit 272 so that the write data WD (DQS) can be captured by the trigger circuit 271, even when the timing difference between the timing signal DWS2 and the write data WD (DQS) is the largest.

[0021] Figure 4 2 is a timing chart for explaining the operation of the transfer circuit 27. Figure 4 The valid window for writing data WD (DQS) when the cycle tCK of the clock signal CK is the longest (tCKmax) and the valid window for writing data WD (DQS) when the cycle tCK of the clock signal CK is the shortest (tCKmin) are shown.

[0022] like Figure 4As shown in FIG. 1 , when the timing signal DWS1 is activated at time t10, the timing signal DWS2 is activated at time t12 when the period tCK of the clock signal CK is the longest (tCKmax), and the timing signal DWS2 is activated at time t11 earlier than time t12 when the period tCK of the clock signal CK is the shortest (tCKmin). This is achieved, for example, by selecting the timing signal DWS2 at the time tCK of the clock signal CK when the period tCK is the longest (tCKmax). Figure 3A The delay circuit 41 shown in FIG. 1 is selected when the period tCK of the clock signal CK is the shortest (tCKmin). Figure 3A It is implemented by the delay circuit 42 shown in FIG.

[0023] In the case where the cycle tCK of the clock signal CK is the longest (tCKmax), the setting tolerance tS@tCKmax of the timing signal DWS2 is defined by the period from the start timing of the valid window of the write data WD (DQS) when tDQSS+tDQSoffset is the largest to the activation timing of the timing signal DWS2. In the case where the cycle tCK of the clock signal CK is the longest (tCKmax), the holding tolerance tH@tCKmax of the timing signal DWS2 is defined by the period from the activation timing of the timing signal DWS2 to the end timing of the valid window of the write data WD (DQS) when tDQSS+tDQSoffset is the smallest. As described above, since the valid window of the write data WD (DQS) is large in the case where the cycle tCK of the clock signal CK is the longest (tCKmax), even when the long setting tolerance tS@tCKmax of the timing signal DWS2 is set, a sufficient holding tolerance tH@tCKmax of the timing signal DWS2 can be provided.

[0024] Even when the timing signal DWS2 is activated at time t12 in the case where the cycle tCK of the clock signal CK is the shortest (tCKmin), a sufficient setting margin tS@tCKmin(t12) of the timing signal DWS2 is provided. This is because the period from the activation of the timing signal DWS1 until the start timing of the valid window of the write data WD (DQS) in the case where tDQSS+tDQSoffset is zero (tDQSS+tDQSoffset=Nom) does not depend on the cycle tCK of the clock signal CK. On the contrary, the length of the valid window of the write data WD (DQS) itself is proportional to the cycle tCK of the clock signal CK. Therefore, if the timing signal DWS2 is activated at time t12 in the case where the cycle tCK of the clock signal CK is the shortest (tCKmin), the holding margin tH@tCKmin(t12) of the timing signal DWS2 becomes quite insufficient. However, in the present embodiment, since the timing signal DWS2 is activated at time t11 earlier than time t12 when the cycle tCK of the clock signal CK is the shortest (tCKmin), a sufficient holding margin tH@tCKmin(t11) of the timing signal DWS2 can be provided, as shown in FIG. Figure 4 As shown in .

[0025] When the timing signal DWS2 is activated at time t11 earlier than time t12, the setting tolerance tS@tCKmin(t11) of the timing signal DWS2 is reduced. However, since the absolute values ​​of tDQSS and tDQSoffset are proportional to the period tCK of the clock signal CK, the difference between the start timing of the valid window of the write data WD (DQS) when tDQSS + tDQSoffset is zero (tDQSS + tDQSoffset = Nom) and the start timing of the valid window of the write data WD (DQS) when tDQSS + tDQSoffset is maximum (tDQSS + tDQSoffset = Max) is smaller as the period tCK of the clock signal CK is shorter. Therefore, when the period tCK of the clock signal CK is shortest (tCKmin), the write data WD (DQS) can be accurately latched even when tDQSS + tDQSoffset is maximum (tDQSS + tDQSoffset = Max).

[0026] Although various embodiments have been disclosed in the context of specific preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or use embodiments and their obvious variations and equivalents. In addition, based on the present disclosure, other modifications within the scope of the present disclosure will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be performed and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined with each other or replace each other to form different modes of the disclosed embodiments. Therefore, it is desired that the scope of at least some of the present disclosure should not be limited by the specific disclosed embodiments described above.

Claims

1. A device comprising: a data bus comprising a first portion having a timing domain controlled based on a first timing signal, and further comprising a second portion having a timing domain controlled based on a second timing signal; and a data transfer circuit coupled to the data bus, the data transfer circuit comprising a data driver located between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver; wherein the timing control circuit includes a variable delay that adds a delay amount to the first control signal to produce a second control signal; and Wherein the data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus in response to the second control signal. 2 . The apparatus of claim 1 , wherein a delay amount of the timing control circuit is changed based on a frequency of the first timing signal.

3. The apparatus of claim 2, wherein the second timing signal has the same frequency as the first timing signal.

4. The apparatus according to claim 1, further comprising: a data terminal to which write data is supplied from the outside; and an input receiver circuit configured to capture the write data on the data terminal, wherein the data bus is configured to transmit the write data output from the input receiver circuit. 5 . The apparatus of claim 4 , wherein the input receiver circuit is configured to capture the write data in response to the second timing signal. 6 . The apparatus according to claim 5 , wherein the second timing signal is a data strobe signal supplied from the outside. The apparatus according to claim 6 , wherein the first timing signal is a clock signal supplied from the outside.

8. The apparatus of claim 7, further comprising: a memory cell array; and a write amplifier circuit configured to store the write data on the first portion of the data bus to the memory cell array in response to a write timing signal, Wherein a timing domain of the write timing signal is controlled based on the first timing signal.

9. The apparatus according to claim 1, wherein the delay amount of the timing control circuit is controlled based on a first internal signal.

10. The device according to claim 9, wherein the timing control circuit includes a plurality of delay circuits having different delay amounts from each other, and One of the plurality of delay circuits is selected based on the first internal signal.

11. The apparatus of claim 9, further comprising a mode register circuit configured to store the first internal signal.

12. The apparatus of claim 11, wherein the first internal signal is related to a frequency of the first timing signal.

13. An apparatus comprising: a memory cell array; a data bus configured to transmit write data to the memory cell array; a data transfer circuit configured to transfer the write data to the data bus; and A timing control circuit is configured to activate the data transmission circuit after a first delay time that has passed after a timing signal is activated according to a first operation mode, and to activate the data transmission circuit after a second delay time that is different from the first delay time that has passed after the timing signal is activated according to a second operation mode.

14. The apparatus of claim 13, further comprising a mode register circuit configured to select one of a plurality of operating modes including the first operating mode and the second operating mode.

15. The apparatus according to claim 13, wherein a timing domain of the timing signal is controlled based on a clock signal supplied from the outside.

16. The device according to claim 15, wherein the first operation mode is selected when the clock signal has a first frequency, and The second operation mode is selected when the clock signal has a second frequency different from the first frequency.

17. The device according to claim 16, wherein the first frequency is higher than the second frequency, and The first delay time is shorter than the second delay time.

18. An apparatus comprising: a memory cell array; a control logic circuit configured to generate a first timing signal based on the clock signal in a data writing operation; a variable delay circuit configured to generate a second timing signal by delaying the first timing signal; a data bus configured to transmit write data to the memory cell array; and a data transfer circuit configured to transfer the write data to the data bus in response to the second timing signal, Wherein a delay amount of the variable delay circuit when the clock signal has a first frequency is shorter than a delay amount of the variable delay circuit when the clock signal has a second frequency lower than the first frequency.

19. The apparatus of claim 18, wherein a delay amount of the variable delay circuit when the clock signal has the second frequency is shorter than a delay amount of the variable delay circuit when the clock signal has a third frequency lower than the second frequency.

20. The apparatus of claim 18, further comprising a mode register circuit configured to store a mode signal related to a frequency of the clock signal, The delay amount of the variable delay circuit is changed based on the mode signal.

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