Semiconductor memory device with signal command / address inversion

Abstract

The invention relates to a semiconductor memory device with signal command / address inversion. Methods, systems, and apparatus are disclosed for a semiconductor memory device (e.g., dynamic random access memory (DRAM)) that includes a command / address inversion (CAI) input signal that indicates whether a command / address input to the memory device is inverted. A memory controller, a register clock driver (RCD), or other component coupled to the memory device can generate the CAI input signal, and the component can generate the CAI input signal differently for different memory devices to which the component is coupled. As described herein, the component may dynamically generate the CAI input signal based on a value of the command / address input in order to reduce power consumption of the memory device while maintaining signal integrity.

Description

Technical Field

[0001] The present disclosure relates generally to a memory device, and more particularly, to a memory device that inverts command / address inputs based on a dynamic command / address inversion signal. Background Art

[0002] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices can be volatile or non-volatile and can be of various types, such as magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), and the like. Information is stored in various types of RAM by charging memory cells so that they assume different states. Improvements to RAM memory devices can generally include increasing memory cell density, increasing read / write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Summary of the Invention

[0003] In one aspect, the present disclosure provides a memory module comprising: a plurality of memory devices; a command / address (CA) input; and a dynamic command / address inversion (CAI) control circuit, the dynamic CAI control circuit configured to: evaluate the CA input; generate a CA output based on the evaluation of the CA input, wherein the CA output includes a value of the CA input or an inverted value of the CA input; generate a CAI output, wherein the CAI output indicates whether the CA output includes the inverted value of the CA input; and transmit the CA output and the CAI output to the plurality of memory devices.

[0004] In another aspect, the present disclosure provides a memory module comprising: a first plurality of memory devices; a second plurality of memory devices; a command / address (CA) input; a first command / address inversion (CAI) input; and a second CAI input; wherein the memory module is configured to: generate a first CA output comprising a value of the CA input or an inverted value of the CA input based on the first CAI input; generate a second CA output comprising the value of the CA input or the inverted value of the CA input based on the second CAI input; transmit the first CA output to the first plurality of memory devices; and transmit the second CA output to the second plurality of memory devices.

[0005] In another aspect, the present disclosure provides a method comprising: receiving, at a memory controller, a request from a host device coupled to the memory controller; generating, in response to the received request, a command / address (CA) value characterizing the request, wherein the CA value comprises a plurality of bits; determining a number of CA value bits having a binary 0 value; generating a CA output based on the determination, wherein the CA output comprises the CA value or an inverted CA value; and transmitting the CA output to a memory module coupled to the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 The description schematically illustrates a simplified block diagram of a memory device in accordance with embodiments of the present technology.

[0008] Figure 2 A dual in-line memory module (DIMM) is schematically illustrated with logic to control command / address bus inversion in accordance with an embodiment of the present technology.

[0009] Figure 3 A DIMM according to an embodiment of the present technology is schematically illustrated.

[0010] Figure 4 is a simplified block diagram schematically illustrating a dynamic command / address inversion (CAI) control circuit in accordance with an embodiment of the present technology.

[0011] Figure 5 is a flow chart illustrating a process for performing dynamic CAI according to an embodiment of the present technology.

[0012] Figure 6 is a block diagram of an example computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] Disclosed are methods, systems, and apparatus for semiconductor memory devices, such as dynamic random access memory (DRAM), that include a command / address inversion (CAI) input signal that indicates whether command / address inputs to the memory device are inverted. The CAI input signal can be generated by a memory controller, a registered clock driver (RCD), or other component coupled to the memory device, and the component can generate the CAI input signal differently for different memory devices to which the component is coupled. As described herein, the component can generate the CAI input signal based on the value of the command / address input to reduce power consumption of the memory device while maintaining signal integrity.

[0014] In systems with electronic devices operating at high frequencies, impedance mismatches on interconnects (e.g., between an electronic device transmitting a signal through the interconnect and an electronic device receiving the signal through the interconnect) can negatively impact signal integrity. That is, the signal, as received by a receiving electronic device through the interconnect, may be distorted. Consequently, electronic devices often "terminate" high-speed interconnects (e.g., at or within the receiving electronic device) to match the impedance of the transmitting electronic device, thereby improving signal integrity. Resistors and / or transistors (collectively, "resistors") with known on-resistance can be used to terminate high-speed interconnects, and different combinations of resistors with different resistances can be used depending on the impedance of the transmitting electronic device.

[0015] Memory devices such as DRAM typically use on-die termination (ODT), in which the termination resistor is located within the memory device itself. More specifically, a memory device may use a VDD-based ODT, in which one node of the termination resistor is coupled to VDD (e.g., a positive supply voltage) and the other node of the termination resistor is coupled to the terminated signal line. In addition, ODT consumes different amounts of power depending on the type of ODT used and the value of the terminated signal. Specifically, for a VDD-based ODT, more power is consumed when the terminated signal has a logic value of 0 (e.g., VSS) because this creates a path from VDD to VSS (through the termination resistor) through which current can flow. In contrast, for a VDD-based ODT, relatively less power is consumed when the terminated signal has a logic value of 1 (e.g., VDD). That is, when terminating a multi-bit bus for a VDD-based ODT, the worst-case scenario with respect to the described power consumption is when the bus is all zeros. It will be appreciated that for other types of ODT (e.g., VSS-based ODT), the situation may be reversed. Additionally, the amount of power that may be dissipated by the ODT circuit may be significant.

[0016] Memory devices, such as DRAM, typically include command / address (CA) inputs that provide command and / or address information for operations to be performed by the memory device. Typically, a memory device has multiple CA inputs that form a multi-bit CA bus input. For example, memory devices compliant with certain versions of the Double Data Rate (DDR) SDRAM standard (e.g., DDR5) may have 14-bit CA bus inputs (e.g., CA[13:0]). It will be appreciated that other memory devices may have wider CA bus inputs (formed by more bits) or narrower CA bus inputs (formed by fewer bits). Furthermore, multiple memory devices on a memory module (e.g., a dual in-line memory module, or DIMM) may need to perform the same operation simultaneously, and therefore, multiple memory devices on a memory module may be coupled to the same CA bus (or, as described below, a logical equivalent) of the memory module. Furthermore, the memory device may support configurable ODT for the CA bus. That is, the CA bus ODT may be disabled, enabled, and / or enabled with different resistances, depending on the impedance of the electronics (e.g., a memory controller) transmitting over the CA bus.

[0017] It has been observed that the values ​​on the CA bus are effectively randomly distributed (e.g., in typical use, there is no discernible pattern of 1s and 0s on a multi-bit CA bus) because the CA inputs depend on the commands and addresses sent by the host and / or memory controller. Therefore, to mitigate potential worst-case power consumption when CA bus ODT is enabled (e.g., the host issues many commands / addresses with a high number of 0s), conventional memory devices (e.g., DDR5 memory devices) and / or conventional memory modules (e.g., DDR5 DIMMs) may utilize a mitigation technique based on static configuration inversion of the CA inputs. Specifically, in the conventional mitigation technique, half of the memory devices on the memory module statically receive inverted CA values ​​(i.e., each bit of the CA bus is inverted from the value sent by the host and / or memory controller) via a first CA bus and are statically configured to invert the received CA values ​​before using them (e.g., decoding commands and / or addresses based on the CA values). Furthermore, in the conventional mitigation technique, the other half of the memory devices on the memory module statically receive "true" (i.e., non-inverted) CA values ​​via a second CA bus and are statically configured not to invert the received CA values ​​before using them. By driving the true CA value to half of the memory devices on a memory module via one bus and driving the inverted CA value to the other half of the memory devices on the memory module via another bus, on average, the number of CA bits on the memory module driven with a value of 0 should be reduced (e.g., halved). Thus, conventional mitigation techniques utilized by conventional memory devices and / or conventional memory modules reduce the average power consumption caused by CA bus ODT. Conventional mitigation techniques can be considered "static" because the use of true and inverted CA values ​​is fixed at design time (e.g., by the design of the memory module). For example, a conventional DDR5 DIMM may be designed to drive true CA values ​​(e.g., values ​​received from a memory controller and / or host) to half of the DDR5 memory devices on the DIMM via one CA bus and to drive inverted CA values ​​to the other half of the DDR5 memory devices on the DIMM via another CA bus. Additionally, each conventional DDR5 memory device may receive a conventional CAI input that indicates whether the corresponding CA bus input is inverted, where the CAI input has a fixed value (e.g., tied to a logic 1 or a logic 0 by the design of the DIMM).

[0018] As memory device speeds increase (e.g., with the adoption of DDR6 memory modules and memory devices), achieving the signal integrity required to support these speeds can become increasingly challenging. One known approach to improving signal integrity, and therefore supporting faster device speeds, is to use a lower resistance for the ODT. However, reducing the resistance of the ODT increases the power consumed because the current consumed by the termination resistor is inversely proportional to the resistance of the termination resistor (e.g., as the resistance decreases, the current increases). Therefore, conventional mitigation techniques that reduce power by statically driving an inverted CA value to half of the memory devices on a memory module and a true CA value to the other half of the memory devices may not be sufficient. Therefore, it would be advantageous to be able to further reduce the power consumption due to the ODT as the ODT resistance decreases.

[0019] Thus, a memory system (e.g., a memory controller, memory module, and / or memory device) with dynamic CAI is described herein. Like conventional memory systems, a memory system with dynamic CAI utilizes inverted values ​​on the CA bus, and associated signaling, to reduce power consumption caused by ODT. However, unlike conventional memory systems where the use of inverted values ​​on the CA bus is fixed (e.g., based on the design of conventional memory modules), a memory system with dynamic CAI can determine whether to utilize inverted values ​​on the CA bus during operation, depending on the true CA value used for each operation. As described herein, a memory system with dynamic CAI can receive a CA value associated with an operation to be performed by the memory system (e.g., as part of a host request), evaluate the number of 1s and 0s in the CA value (e.g., on bus CA[13:0], how many bits contain 1s and how many contain 0s), and determine whether to use the CA value from the host (e.g., the true CA value) or the inverted value (e.g., the inverted CA value) to send to the memory device. The determination of whether to use the true CA value or the inverted CA value to send to the memory device can be based on which is more advantageous from a power perspective for the type of ODT being used. For VDD-based ODT (where sending 1s is advantageous), the memory system may send an inverted CA value when there are more 0s than 1s in the true CA value (e.g., 8 bits have a value of 0 in a 14-bit CA value), and may otherwise send the true CA value (e.g., 7 or fewer bits have a value of 0 in a 14-bit CA value). In doing so, a memory system with dynamic CAI advantageously transmits values ​​over the CA bus with a preferred bit balance (e.g., more 1s than 0s when using VDD-based ODT), thereby improving power efficiency.

[0020] In various embodiments of a memory system with dynamic CAI, various system components (e.g., a memory controller coupled to the host, and / or memory module components such as an RCD) that are part of the communication path from the host to the memory devices may be responsible for evaluating the true CA value generated by the host and transmitting the true CA value or the inverted CA value, as well as associated signaling. For example, the memory controller may receive the true CA value (e.g., from the host) and transmit the true CA value or the inverted CA value to the memory modules of the memory system via one or more CA buses. As another example, the RCD of each memory module may receive the true CA value (e.g., from the memory controller) and transmit the true CA value or the inverted CA value to the memory devices of the memory module via one or more CA buses of the memory module. As described herein, memory system components (e.g., the memory controller and / or the RCD) may include dynamic CAI control circuitry that evaluates the true CA value, generates the inverted CA value, and transmits the true CA value or the inverted CA value (e.g., to the memory modules in the system and / or the memory devices on the memory modules). The dynamic CAI control circuitry may additionally generate and transmit a CAI signal that may be used by the memory device to determine whether a received CA value is a true CA value (and may be decoded as is) or an inverted CA value (and should be inverted before decoding). It will be appreciated that, in contrast to conventional systems in which the CAI input of each memory device is tied to a set value depending on the design of the memory module, the CAI signal received by the memory devices in a memory system with dynamic CAI is a dynamic signal that may change with each memory system operation.

[0021] In some embodiments, a memory system with dynamic CAI can support different modes that change the behavior of whether true CA values ​​or inverted CA values ​​are driven through the CA bus. For example, in a first mode, the system can statically drive true CA values ​​or inverted CA values ​​through various CA buses (e.g., operating similarly to a conventional memory system). As another example, in a second mode, the system can dynamically drive true CA values ​​or inverted CA values ​​through the CA bus depending on the true CA value (e.g., as described above). As described herein, the dynamic CAI control circuit can drive the CA bus and / or CAI signal differently depending on the mode of the memory system. In some embodiments, different memory devices can receive different true and / or inverted CA values ​​according to different modes.

[0022] In some embodiments, the CAI signal associated with an operation (e.g., a request from a host) may be fixed for one or more clock cycles and then regenerated for the next operation. For example, some operations are associated with 2-cycle commands, where some of the operation's information is transmitted over the command / address bus in the first cycle, and other information for the operation is transmitted over the command / address bus in the second (e.g., next) cycle. In some embodiments, the CAI signal generated based on the value of the command / address bus during the first cycle of the 2-cycle command will maintain the same value (e.g., inverted or non-inverted) for the second cycle of the 2-cycle command (even though the command / address value may change in the second cycle). Similarly, in some embodiments, the CAI signal associated with an operation is adjusted to account for 2N mode, which enables the system to provide more setup and hold on the command / address bus. In 2N mode, the second half of the command associated with an operation may be received at a later cycle (e.g., two cycles after the first half of the command, rather than one cycle after the first half of the command), and the CAI signal may be maintained accordingly until the next operation.

[0023] Figure 1 The description schematically illustrates a simplified block diagram of a memory device 100 according to an embodiment of the present technology. The memory device 100 may include an array of memory cells, such as a memory array 150. The memory array 150 may include a plurality of memory banks (e.g., Figure 1 In the example of FIG, memory banks 0 to 15 are provided, and each memory bank may include a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. Selection of a word line WL may be performed by a row decoder 140, and selection of a bit line BL may be performed by a column decoder 145. Sense amplifiers (SAMPs) may be provided for corresponding bit lines BL and connected to at least one corresponding local input / output (I / O) line pair (LIOT / B), which in turn may be coupled to at least one corresponding main IO line pair (MIOT / B) via transfer gates (TGs) that may function as switches.

[0024] The memory device 100 may employ a plurality of external terminals including command and address terminals coupled to a command bus and an address bus to receive a command signal CMD and an address signal ADDR, respectively. Figure 1While embodiments of a memory device are described with separate command and address terminals coupled to a command bus and an address bus, it will be appreciated that embodiments of the memory device may employ command / address terminals coupled to a shared command / address bus to receive a command / address signal CA. The memory device may also include a command / address inversion terminal for receiving a command / address inversion signal CAI. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI (for a data bus inversion function), and DMI (for a data mask inversion function), power supply terminals VDD, VSS, VDDQ, and VSSQ, and on-die termination terminals ODT.

[0025] The command signal and the address signal (or in some embodiments, the command / address signal) may be received by the address / command input circuit 105, which may perform certain processing on the signals before the signals are provided to other circuits / components of the memory device 100. For example, the address / command input circuit may include a CA inversion circuit 175 that provides the received command signal and the address signal to other circuits / components of the memory device, or alternatively provides an inverted command signal and an inverted address signal to the other circuits / components. The CA inversion circuit may determine whether to provide the received signal or the inverted signal based on the signal CAI provided by the command / address inversion terminal. For example, a value of 1 on the CAI signal may cause the CA inversion circuit to provide the inverted signal, and a value of 0 on the CAI signal may cause the CA inversion circuit to provide the received signal. As Figure 1 As illustrated in , the CA inversion circuit can include a two-to-one (2:1) multiplexer, with one multiplexer input coupled to the received command and address signals, another multiplexer input coupled to the inverted command and address signals (e.g., generated by the CA inversion circuit), a multiplexer select coupled to the CAI signal, and a multiplexer output coupled to the output of the address / command input circuit (e.g., to be provided to other circuits / components of the memory device). It will be appreciated that in embodiments of a memory device in which the command / address signal is provided by a command / address terminal (e.g., in place of or in addition to separate command and address signals), the command / address signal can be processed by the address / command input circuit and the CA inversion circuit in the same manner as described above with respect to the command and address signals.

[0026] The command and address terminals may be supplied with address signals and bank address signals from the outside. The address signals and bank address signals supplied to the address terminals may be transmitted to the address decoder 110 via the address / command input circuit 105. As described above, the address / command input circuit may invert the address signals and bank address signals supplied from the external terminals before transmitting them to the address decoder. The address decoder 110 may receive the address signals and supply a decoded row address signal (XADD) to the row decoder 140 and a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive the bank address portion of the ADDR input and supply a decoded bank address signal (BADD) and provide the bank address signals to both the row decoder 140 and the column decoder 145.

[0027] The command and address terminals may be supplied with a command signal CMD, an address signal ADDR, and a chip select signal CS from a memory controller. The command signal may represent various memory commands from the memory controller (e.g., including access commands, which may include read commands and write commands). The select signal CS may be used to select the memory device 100 to respond to the command and address provided to the command and address terminals. When the active CS signal is provided to the memory device 100, the command and address may be decoded and the memory operation may be performed. The command signal CMD may be provided to the command decoder 115 as an internal command signal ICMD via the address / command input circuit 105. As described above, the address / command input circuit may invert the command signal CMD supplied from the external terminal before providing it to the command decoder as the internal command signal ICMD. The command decoder 115 may include a circuit for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., a row command signal for selecting a word line and a column command signal for selecting a bit line). The internal command signal may also include output and input activation commands, such as a clock command CMDCK ( Figure 1 not shown).

[0028] In some embodiments, command decoder 115 may further include one or more registers for tracking various counts or values, such as a count of refresh commands received by memory device 100 or self-refresh operations performed by memory device 100. In some embodiments, a subset of the registers may be referred to as mode registers and configured to store user-defined variables to provide flexibility in executing various functions, features, and modes.

[0029] When a read command is issued to a memory bank with an open row and a column address is provided in time as part of the read command, read data can be read from the memory cells in memory array 150 specified by the row address (which may have been provided as part of an activate command identifying the open row) and the column address. The read command can be received by command decoder 115, which can provide an internal command to IO circuit 160 so that the read data can be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier (RW AMP) 155 and IO circuit 160 according to the RDQS clock signal. The read data can be provided at a time defined by read latency information (RL) programmable in memory device 100 (for example, in a mode register). The read latency information RL can be defined based on clock cycles of the CK clock signal. For example, the read latency information RL can be the number of clock cycles of the CK clock signal after the read command is received by memory device 100 when the associated read data is provided.

[0030] When a write command is issued to a memory bank with an open row and a column address is provided in time as part of the write command, write data may be supplied to data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by command decoder 115, which may provide an internal command to IO circuit 160 so that the write data may be received by a data receiver in IO circuit 160 and supplied to memory array 150 via IO circuit 160 and read / write amplifier 155. The write data may be written to the memory cells specified by the row and column addresses. The write data may be supplied to the data terminals at a time defined by write latency information (WL). The write latency information (WL) may be programmed in memory device 100 (for example, in a mode register). The write latency information (WL) may be defined based on clock cycles of the CK clock signal. For example, the write latency information (WL) may be the number of clock cycles of the CK signal after the write command is received by memory device 100 when the associated write data is received.

[0031] The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to an internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0032] The power supply terminal may also be supplied with a power supply potential VDDQ. Power supply potential VDDQ may be supplied to IO circuit 160 along with power supply potential VSS. In an embodiment of the present technology, power supply potential VDDQ may be the same potential as power supply potential VDD. In another embodiment of the present technology, power supply potential VDDQ may be a different potential from power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for IO circuit 160 so that power supply noise generated by IO circuit 160 does not propagate to other circuit blocks.

[0033] The on-die termination terminal may be supplied with an on-die termination signal ODT. The on-die termination signal ODT may be supplied to the IO circuit 160 to instruct the memory device 100 to enter an on-die termination mode (e.g., to provide one of a predetermined number of impedance levels at one or more of the other terminals of the memory device 100).

[0034] An external clock signal and a complementary external clock signal can be supplied to the clock terminal and the data clock terminal. External clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. The CK and CKF clock signals can be complementary, and the WCK and WCKF clock signals can also be complementary. The complementary clock signals can have opposite clock levels and transition between opposite clock levels simultaneously. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high clock level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0035] The input buffer included in the clock input circuit 120 can receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer can receive the CK and CKF clock signals and the WCK and WCKF clock signals. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase and frequency controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from the command decoder 115. For example, the internal clock circuit 130 may include a clock path ( CK_CLOCK_P_LOCK_CLOCK_STOP ... Figure 1(not shown). Internal clock circuit 130 may further provide an IO clock signal. The IO clock signal may be supplied to IO circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies, allowing data to be output from and input to memory device 100 at different data rates. When high memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to timing generator 135, and thus various internal clock signals may be generated.

[0036] Figure 2 A dual in-line memory module (DIMM) 200 is schematically illustrated with logic to control command / address bus inversion according to an embodiment of the present technology. The DIMM 200 includes a plurality of DRAMs 220 (e.g., memory devices, memory dies, memory chips, memory packages, or the like). For example, one or more of the DRAMs 220 may be Figure 1 2. Memory device 100 is illustrated in FIG. DIMM 200 includes an edge connector 202 along the edge of a substrate 201 (e.g., a printed circuit board (PCB) or the like) of DIMM 200 for connecting a data bus 204 and a service bus 206 (illustrated in bold) to a host device (e.g., via a memory controller). Data bus 204 connects DRAM 220 to edge connector 202 and receives and transmits data signals from and to a connected host during memory access operations (e.g., reads and writes). Service bus 206 includes electrical connections configured to communicate information associated with data communicated via data bus 204. For example, service bus 206 may include a command / address bus. The command / address bus may include information used by DIMM 200 to perform memory access operations and other operations, including command information and address information.

[0037] DIMM 200 may further include control circuitry, such as RCD 210. RCD 210 may include circuitry configured to receive a command / address bus from service bus 206 and may generate one or more DRAM-side command / address buses for DRAM 220. RCD 210 may present a predictable electrical load to the host device and / or memory controller (e.g., for matching impedance, reactance, capacitance, etc.) and may redrive the DRAM-side command / address bus to DRAM 220, which helps achieve higher density and increase signal integrity. RCD 210 may also buffer the command / address bus provided by the host and then transmit the buffered signal as a DRAM-side command / address bus to DRAM 220. In other words, DIMM 200 may be a registered DIMM (RDIMM) and / or a load-reduced DIMM (LRDIMM).

[0038] The circuitry of RCD 210 may include dynamic CAI control circuitry 225. Dynamic CAI control circuitry 225 may be configured to evaluate command / address signals on a command / address bus (e.g., received from a host device and / or memory controller via service bus 206) and determine whether to transmit the received command / address signal or invert the command / address signal on one or more DRAM-side command / address buses of DRAM 220. As described herein, the dynamic CAI control circuitry may make this determination based on the number of ones and / or zeros in the received command / address signal and / or the type of ODT used by DIMM 200. For example, if the DIMM uses VDD-based ODT, then if there are more zeros than ones in the received command / address signal, the dynamic CAI control circuitry may transmit an inverted command / address signal. As another example, if the DIMM uses VSS-based ODT, then if there are more ones than zeros in the received command / address signal, the dynamic CAI control circuitry may transmit an inverted command / address signal. The determination made by the dynamic CAI control circuitry may be further based on mode information stored in the CAI mode register 230. For example, if the CAI mode register indicates a first mode, the dynamic CAI control circuitry may transmit true or inverted command / address signals based on the counts of 1s and 0s described above. As another example, if the CAI mode register indicates a second mode, the dynamic CAI control circuitry may transmit true command / address signals or inverted command / address signals to different DRAMs in a fixed manner when the second mode is active. The dynamic CAI control circuitry may also generate one or more CAI signals that indicate whether a set of corresponding command / address signals has been inverted. As described herein, each DRAM may include circuitry that determines, based on the received CAI signals, whether to use (e.g., decode) the received command / address signals as is, or whether to invert the received signals (e.g., to logically undo the inversion performed by the RCD).

[0039] RCD 210 may transmit command / address signals to DRAM 220 via one or more DRAM-side command / address buses. It will be appreciated that it may be advantageous for DIMM 200 to include multiple command / address buses over which different command / address signals from the RCD are transmitted to the DRAMs, to enable inverted command / address signals to be transmitted to some DRAMs and non-inverted command / address signals to be transmitted to other DRAMs (e.g., in the second mode described above). For example, Figure 2As illustrated in FIG, a DIMM may include DRAM-side command / address buses CA Left 235 and CA Right 240, which serve the left and right DRAMs of the DIMM, respectively. Similarly, a DIMM may include CAI Left 245 and CAI Right 250, which indicate whether the corresponding DRAM-side command / address bus contains inverted command / address signals. Thus, in FIG. Figure 2 In the embodiment described in , the RCD can transmit inverted or non-inverted command / address signals to the left DRAM of the DIMM and independently transmit inverted or non-inverted command / address signals to the right DRAM of the DIMM. Although in some examples, the RCD will transmit the same (e.g., inverted or non-inverted) command / address signals over the left and right command / address buses (e.g., when whether to invert is based on the number of 1s and 0s in the command / address signal received from the host), in other examples, the RCD will transmit inverted or non-inverted signals over different buses (e.g., in a mode where inversion or non-inverting is fixedly configured for different DRAMs, such as in conventional DIMMs).

[0040] although Figure 2 While an embodiment of a DIMM 200 is described with two DRAM-side command / address buses (e.g., CA Left 235 and CA Right 240) and corresponding CAI signals (e.g., CAI Left 245 and CAI Right 250), it will be appreciated that in embodiments, a DIMM may include fewer or more DRAM-side command / address buses and corresponding signaling. For example, in some embodiments, the DIMM includes a single command / address bus and CAI signal generated by the RCD 210 and transmitted to all DRAMs 220 on the DIMM. In some embodiments, the DIMM includes four DRAM-side command / address buses and signals. For example, a DIMM may include two rows of DRAMs 220 and four DRAM-side command / address buses and CAI signals corresponding to the top left, top right, bottom left, and bottom right DRAMs. It will be appreciated that the DRAM-side command / address buses and CAI signals may be associated with other DRAM arrangements. For example, in a DIMM with two rows of DRAMs, a first DRAM-side command / address bus may be associated with all top DRAMs, and a second DRAM-side command / address bus may be associated with all bottom DRAMs. Similarly, the DRAMs on the front and back sides of substrate 201 may be associated with the same or different DRAM-side command / address buses.

[0041] Figure 3 A DIMM 300 according to an embodiment of the present technology is schematically illustrated. The DIMM 300 includes a plurality of DRAMs 320 (eg, memory devices, memory dies, memory chips, memory packages, or the like). For example, one or more of the DRAMs 320 may be Figure 13. Memory device 100 illustrated in FIG. DIMM 300 includes an edge connector 302 along the edge of a substrate 301 (e.g., a PCB or the like) of DIMM 300 for connecting a data bus 304 and a service bus 306 (illustrated in bold) to a host device (e.g., via a memory controller). Data bus 304 connects DRAM 320 to edge connector 302 and receives and transmits data signals from and to the connected host during memory access operations (e.g., reads and writes). Service bus 306 connects DRAM 320 to edge connector 302 and includes electrical connections configured to communicate information associated with data communicated via data bus 304. For example, service bus 306 may include a command / address bus. The command / address bus may include information used by DIMM 300 to perform memory access operations and other operations, including command information and address information. As another example, the service bus 306 may include a command / address inversion signal that indicates whether the command / address bus contains true information or whether the bus contains information in an inverted form. In some embodiments, the service bus 306 is driven by a memory controller coupled to the DIMM 300, where the memory controller determines whether to send true or inverted information of the command / address bus portion of the service bus. The memory controller may drive the command / address inversion signal accordingly. As described herein, each DRAM may include circuitry that determines, based on the received command / address inversion signal, whether to use (e.g., decode) the received command / address bus as is or whether to invert the received bus (e.g., to logically undo an inversion performed by the memory controller).

[0042] although Figure 3While an embodiment of a DIMM 300 is described with a single service bus 306, it will be appreciated that other embodiments of the DIMM 300 may include multiple service buses (e.g., a first service bus 306-1, a second service bus 306-2, etc.), each with its own command / address bus and / or command / address inversion signal driven by the host and / or memory controller. Alternatively, an embodiment of the DIMM 300 may include multiple command / address buses and / or command / address inversion signals (e.g., received via the edge connector 302), each driven by the host and / or memory controller, while the DIMM includes only a single service bus 306 corresponding to the rest of the service bus. In embodiments of the DIMM 300 with multiple command / address buses and / or command / address inversion signals, different DRAMs 320 may be driven by different pairs of buses and signals. For example, the left DRAM 320 can be driven by a first command / address bus and a first command / address inversion signal, and the right DRAM 320 can be driven by a second command / address bus and a second command / address inversion signal. Different command / address buses and command / address inversion signals can be driven independently of each other by the host and / or memory controller, such that, for example, some DRAMs receive an inverted command / address bus and some receive a non-inverted command / address bus (e.g., in a mode where the system is configured to operate similarly to a conventional system). In some embodiments, the DIMM receives multiple command / address inversion signals from the host and / or memory controller, along with one command / address bus. In such embodiments, circuitry (not shown) on the DIMM generates an inverted command / address bus and transmits the received command / address bus and the generated inverted command / address bus to different DRAMs corresponding to the multiple received command / address inversion signals.

[0043] Figure 4 is a simplified block diagram schematically illustrating a dynamic CAI control circuit 400 according to an embodiment of the present technology. As described herein, the CAI control circuit 400 can be configured to determine whether a command / address value generated by a host as part of a request to perform an operation in a memory system should be transmitted to a memory device of the memory system in an inverted form. In some embodiments, the CAI control circuit 400 can be implemented within a memory controller coupled to the host, within a memory module of the memory system (e.g., an RCD or other logic of each memory module), or within other memory system components that are part of a communication path from the host to the memory devices.

[0044] The CAI control circuit 400 receives as input the CA bus 405 over which the "real" command / address values ​​(e.g., values ​​generated by the host associated with the memory operation) are transmitted. Figure 4An embodiment of the CAI control circuit 400 is described in which the input CA bus 405 is 14 bits (eg, CA[13:0]), but it will be appreciated that in embodiments the input CA bus may be wider (eg, more bits) or narrower (eg, fewer bits).

[0045] The CAI control circuit 400 uses one or more inverters 415 to generate an inverted CA bus 410 from the input CA bus 405. In some embodiments of the CAI control circuit 400, the inverters 415 perform a bit-by-bit operation, where each bit of the input CA bus 405 is inverted to generate the inverted CA bus 410. The CAI control circuit 400 then transmits the value of the input CA bus 405 or the inverted CA bus 410 via an output CA bus 420 (using a multiplexer 417). As described herein, the output CA bus 420 can be coupled to one or more memory devices of a memory system. For example, in embodiments where the CAI control circuit is implemented in an RCD or other logic of a memory module, the output CA bus 420 can be transmitted to one or more memory devices on the memory module.

[0046] To determine whether to transmit a true or inverted CA value via the output CA bus 420 (eg, to generate a control signal for the multiplexer 417 ), the CAI control circuit 400 may be configured to count the number of ones or zeros in the true CA value on the input CA bus 405 . Figure 4An embodiment of a CAI control circuit 400 configured to count the number of zeros in a true CA value (e.g., using a zero-counting circuit 425) is described, but it will be appreciated that additional and / or other evaluations may be performed. For example, an embodiment of the CAI control circuit 400 may count the number of ones. The CAI control circuit 400 may also be configured to receive as input a CAI pattern 430 that indicates a configuration mode for the memory system. For example, a first value on the CAI pattern 430 may indicate that an inverted CA value should be transmitted based on the number of ones and / or zeros in the true CA value, and a second value on the CAI pattern 430 may indicate whether the use of the inverted CA value is fixed. The CAI pattern 430 may be received, for example, from a mode register. The CAI control circuit 400 may include control logic 432 that evaluates the results of the zero-counting circuit 425 and the CAI pattern 430 to determine operation. For example, the control logic 432 can be configured to generate an output that will cause the multiplexer 417 to select the inverted CA bus 410 when the true CA value has more zeros than ones and dynamic CAI is enabled. The control logic 432 output can also drive the output CAI 435 of the CAI control circuit 400. As described herein, the output CAI 435 can be transmitted to one or more memory devices to indicate whether the corresponding output CA bus 420 has an inverted value (and therefore should be inverted as part of or prior to a decode operation of the memory device).

[0047] The CAI control circuit 400 may further include one or more state-saving components (e.g., flip-flops, not shown) for maintaining the output CAI 435 for multiple cycles. The CAI control circuit 400 may be configured to update the flip-flops with the new output of the control logic 432, or to preserve the current stored value (e.g., for at least one additional clock cycle) based on the control logic 432 or other logic of the CAI control circuit. For example, the CAI control circuit 400 may be configured to preserve the output CAI 435 for an additional cycle if the CAI control circuit detects that the input CA bus 405 has a value indicating a multi-cycle command (e.g., a 2-cycle command). As another example, the CAI control circuit 400 may be configured to preserve the output CAI 435 for an additional cycle based on whether the input CA bus 405 has a value indicating a multi-cycle command and whether the memory system is operating in 2N mode. That is, in both 1N and 2N modes, the first half of the command is sampled on the clock edge during which chip select is active (e.g., the rising or falling edge of the clock). In 1N mode, the second half of the command is sampled on the next rising or falling clock edge. In 2N mode, the second half of the command is sampled two clocks after the first half. Thus, the CAI control circuit 400 can save the value of the output CAI 435 for one extra cycle (e.g., a 2-cycle command in 1N mode), two extra cycles (e.g., a 2-cycle command in 2N mode), and so on.

[0048] Figure 5 is a flow chart illustrating a process 500 for performing dynamic CAI according to an embodiment of the present technology. Aspects of the process 500 may be, for example, Figure 2 DIMM 200, consisting of Figure 4 The dynamic CAI control circuit 400 is executed by the memory controller, or a combination thereof.

[0049] Process 500 begins at decision block 505, where the process determines whether dynamic CAI is enabled. This determination can be based, for example, on a mode register or other configuration information of the memory system. If, at decision block 505, the process determines that dynamic CAI is enabled, processing continues to block 510. Otherwise, the process ends.

[0050] At block 510, the process evaluates a command / address value. The command / address value may, for example, be received from a host and characterize a memory operation to be performed in accordance with the host request. The evaluation may include, for example, evaluating the number of 1s and / or 0s in a binary representation of the command / address value.

[0051] At decision block 515, the process determines whether to invert the command / address value. This determination may be based, for example, on the number of ones and / or zeros in the binary representation of the command / address value. For example, if there are more zeros than ones in the binary representation of the command / address value, decision block 515 may determine to invert the command / address value. If decision block 515 determines to invert the command / address value, processing continues to block 520. Otherwise, processing continues to block 525.

[0052] At block 520, the process transmits the inverted command / address value, for example, to a memory device of the memory system. The process may also transmit a signal indicating that the transmitted command / address value is an inverted value. The process then ends. Otherwise, at block 525, the process transmits the (non-inverted) command / address value to the memory device of the memory system. The process then ends.

[0053] Figure 6 An example machine is illustrated as a computer system 600 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0054] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0055] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 618, which communicate with each other via a bus 630. According to one aspect of the present disclosure, the main memory 604 can dynamically perform inversion of command / address information received from, for example, the processing device 602.

[0056] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communicating over a network 620.

[0057] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functionality described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media.

[0058] Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine, which instructions cause the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0059] The devices discussed herein, including memory devices, can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0060] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0061] As used herein, "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of..." or "one or more of...") in the claims, including the claims, indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0062] As used herein, the terms "vertical," "lateral," "upper," "lower," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "topmost" may refer to a feature that is located closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / under, up / down, and left / right may be interchanged depending on the orientation.

[0063] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, embodiments from two or more of the methods may be combined.

[0064] It will be appreciated from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and instructive description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it will be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may also be within the scope of the present technology.

Claims

1. A memory module, comprising: a plurality of memory devices; Command / address CA input; and A dynamic command / address inversion (CAI) control circuit, wherein the dynamic CAI control circuit is configured to: evaluating the CA input; generating a CA output based on the evaluation of the CA input, wherein the CA output comprises the value of the CA input or an inverse value of the CA input; generating a CAI output, wherein the CAI output indicates whether the CA output includes the inverted value of the CA input; and The CA output and the CAI output are transmitted to the plurality of memory devices.

2. The memory module of claim 1, wherein the CA input comprises a plurality of bits, and wherein the evaluation of the CA input comprises determining a number of CA input bits having a binary 0 value.

3. The memory module of claim 2, wherein the CA input is 14 bits. 4 . The memory module of claim 2 , wherein the evaluation of the CA input further comprises determining whether more than half of the CA input bits have a binary 0 value.

5. The memory module of claim 1, wherein the memory module further comprises a mode register configured to store a CAI mode, and wherein generating the CA output is further based on the CAI mode.

6. The memory module of claim 5, wherein the memory module further comprises a second plurality of memory devices, and wherein the CAI control circuit is further configured to: Determining that the CAI mode corresponds to a fixed mode; generating a second CA output, wherein the second CA output comprises the inverted value of the CA input; generating a second CAI output, wherein the second CAI output indicates an inverted value; and The second CA output and the second CAI output are transmitted to the second plurality of memory devices.

7. The memory module of claim 6 wherein the CA output comprises the value of the CA input and wherein the CAI output indicates a non-inverted value.

8. The memory module of claim 1, wherein at least one of the plurality of memory devices is configured to perform an operation according to an inversion of the CA output based on the CAI output.

9. The memory module of claim 1, wherein the memory module further comprises a clock input, and wherein the CAI control circuit is further configured to: determining whether the value of the CA input indicates a 2-cycle command; and If it is determined that the value of the CA input indicates a 2-cycle command, then the CAI output is maintained until a first rising edge of the clock input.

10. The memory module of claim 9, wherein the CAI control circuit is further configured to: determining whether the memory module is configured to operate in 2N mode; and If it is determined that the value of the CA input indicates a 2-cycle command and the memory module is configured to operate in the 2N mode, the CAI output is maintained until a second rising edge of the clock input.

11. A memory module, comprising: a first plurality of memory devices; a second plurality of memory devices; Command / address CA input; First command / address inversion CAI input; and Second CAI input; The memory module is configured to: generating a first CA output comprising a value of the CA input or an inverse value of the CA input based on the first CAI input; generating a second CA output comprising the value of the CA input or the inverse value of the CA input based on the second CAI input; transmitting the first CA output to the first plurality of memory devices; and The second CA output is transmitted to the second plurality of memory devices.

12. The memory module of claim 11, wherein the CA input is 14 bits.

13. A method comprising: receiving, at a memory controller, a request from a host device coupled to the memory controller; generating a command / address C / A value characterizing the request in response to the received request, wherein the CA value comprises a plurality of bits; determining the number of CA value bits having a binary 0 value; generating a CA output based on the determining, wherein the CA output comprises the CA value or an inverted CA value; and The CA output is transmitted to a memory module coupled to the memory controller.

14. The method of claim 13, wherein the CA output comprises the inverted CA value when it is determined that more CA value bits have a binary 0 value than CA value bits have a binary 1 value.

15. The method of claim 13, wherein the CA output comprises the inverted CA value when it is determined that more CA value bits have a binary 1 value than CA value bits have a binary 0 value.

16. The method of claim 13, further comprising: generating a CAI output indicating whether the CA output is based on the CA value or the inverted CA value; and The CAI output is transmitted to the memory module coupled to the memory controller.

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